Mercurial > repos > blastem
annotate backend_x86.c @ 1110:d1eed3b1121c
Fix a couple of timing regressions in Z80 core
author | Michael Pavone <pavone@retrodev.com> |
---|---|
date | Wed, 14 Dec 2016 23:27:42 -0800 |
parents | 4bc27caa6e20 |
children | fe8c79f82c22 |
rev | line source |
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567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1 #include "backend.h" |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2 #include "gen_x86.h" |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
3 |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
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4 void cycles(cpu_options *opts, uint32_t num) |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
5 { |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
6 if (opts->limit < 0) { |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
7 sub_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
8 } else { |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
9 add_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D); |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
10 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
11 } |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
12 |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
13 void check_cycles_int(cpu_options *opts, uint32_t address) |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
14 { |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
15 code_info *code = &opts->code; |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
diff
changeset
|
16 uint8_t cc; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
17 if (opts->limit < 0) { |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
diff
changeset
|
18 cmp_ir(code, 1, opts->cycles, SZ_D); |
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
diff
changeset
|
19 cc = CC_NS; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
20 } else { |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
21 cmp_rr(code, opts->cycles, opts->limit, SZ_D); |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
diff
changeset
|
22 cc = CC_A; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
23 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
24 code_ptr jmp_off = code->cur+1; |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
diff
changeset
|
25 jcc(code, cc, jmp_off+1); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
26 mov_ir(code, address, opts->scratch1, SZ_D); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
27 call(code, opts->handle_cycle_limit_int); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
28 *jmp_off = code->cur - (jmp_off+1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
29 } |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
30 |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
31 void check_cycles(cpu_options * opts) |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
32 { |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
33 code_info *code = &opts->code; |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
diff
changeset
|
34 uint8_t cc; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
35 if (opts->limit < 0) { |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
diff
changeset
|
36 cmp_ir(code, 1, opts->cycles, SZ_D); |
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
diff
changeset
|
37 cc = CC_NS; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
38 } else { |
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
39 cmp_rr(code, opts->cycles, opts->limit, SZ_D); |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
diff
changeset
|
40 cc = CC_A; |
1047
6b07af1515b5
Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately.
Michael Pavone <pavone@retrodev.com>
parents:
987
diff
changeset
|
41 } |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
42 check_alloc_code(code, MAX_INST_LEN*2); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
43 code_ptr jmp_off = code->cur+1; |
1109
4bc27caa6e20
Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2
Michael Pavone <pavone@retrodev.com>
parents:
1107
diff
changeset
|
44 jcc(code, cc, jmp_off+1); |
567
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
45 call(code, opts->handle_cycle_limit); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
46 *jmp_off = code->cur - (jmp_off+1); |
8e395210f50f
Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
47 } |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
48 |
697
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
49 void log_address(cpu_options *opts, uint32_t address, char * format) |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
50 { |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
51 code_info *code = &opts->code; |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
52 call(code, opts->save_context); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
53 push_r(code, opts->context_reg); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
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54 mov_rr(code, opts->cycles, RDX, SZ_D); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
55 mov_ir(code, (int64_t)format, RDI, SZ_PTR); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
56 mov_ir(code, address, RSI, SZ_D); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
57 call_args_abi(code, (code_ptr)printf, 3, RDI, RSI, RDX); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
58 pop_r(code, opts->context_reg); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
59 call(code, opts->load_context); |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
60 } |
7f96bd1cb1be
Sync fixes and logging to fix more sync issues
Michael Pavone <pavone@retrodev.com>
parents:
692
diff
changeset
|
61 |
601
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
595
diff
changeset
|
62 void check_code_prologue(code_info *code) |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
595
diff
changeset
|
63 { |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
595
diff
changeset
|
64 check_alloc_code(code, MAX_INST_LEN*4); |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
595
diff
changeset
|
65 } |
f0061e3d2ad9
Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor
Michael Pavone <pavone@retrodev.com>
parents:
595
diff
changeset
|
66 |
593
5ef3fe516da9
Z80 core is sort of working again
Michael Pavone <pavone@retrodev.com>
parents:
590
diff
changeset
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67 code_ptr gen_mem_fun(cpu_options * opts, memmap_chunk const * memmap, uint32_t num_chunks, ftype fun_type, code_ptr *after_inc) |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
68 { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
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69 code_info *code = &opts->code; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
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70 code_ptr start = code->cur; |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
71 check_cycles(opts); |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
72 uint8_t is_write = fun_type == WRITE_16 || fun_type == WRITE_8; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
73 uint8_t adr_reg = is_write ? opts->scratch2 : opts->scratch1; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
74 uint8_t size = (fun_type == READ_16 || fun_type == WRITE_16) ? SZ_W : SZ_B; |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
75 if (size != SZ_B && opts->align_error_mask) { |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
76 test_ir(code, opts->align_error_mask, adr_reg, SZ_D); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
77 jcc(code, CC_NZ, is_write ? opts->handle_align_error_write : opts->handle_align_error_read); |
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
Michael Pavone <pavone@retrodev.com>
parents:
894
diff
changeset
|
78 } |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
79 cycles(opts, opts->bus_cycles); |
590
ea80559c67cb
WIP effort to update z80 core for code gen changes
Michael Pavone <pavone@retrodev.com>
parents:
589
diff
changeset
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80 if (after_inc) { |
ea80559c67cb
WIP effort to update z80 core for code gen changes
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diff
changeset
|
81 *after_inc = code->cur; |
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WIP effort to update z80 core for code gen changes
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589
diff
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82 } |
987
1f09994e92c5
Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing.
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894
diff
changeset
|
83 |
750
59b499f6b24f
Fix handling of address mask in gen_mem_fun
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697
diff
changeset
|
84 if (opts->address_size == SZ_D && opts->address_mask != 0xFFFFFFFF) { |
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Fix handling of address mask in gen_mem_fun
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parents:
697
diff
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85 and_ir(code, opts->address_mask, adr_reg, SZ_D); |
589
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diff
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86 } |
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87 code_ptr lb_jcc = NULL, ub_jcc = NULL; |
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diff
changeset
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88 uint16_t access_flag = is_write ? MMAP_WRITE : MMAP_READ; |
690
fc04781f4d28
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
changeset
|
89 uint32_t ram_flags_off = opts->ram_flags_off; |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
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parents:
1084
diff
changeset
|
90 uint32_t min_address = 0; |
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91 uint32_t max_address = opts->max_address; |
589
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92 for (uint32_t chunk = 0; chunk < num_chunks; chunk++) |
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93 { |
1086
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94 if (memmap[chunk].start > min_address) { |
589
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95 cmp_ir(code, memmap[chunk].start, adr_reg, opts->address_size); |
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96 lb_jcc = code->cur + 1; |
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97 jcc(code, CC_C, code->cur + 2); |
1086
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98 } else { |
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99 min_address = memmap[chunk].end; |
589
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100 } |
1086
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101 if (memmap[chunk].end < max_address) { |
589
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102 cmp_ir(code, memmap[chunk].end, adr_reg, opts->address_size); |
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103 ub_jcc = code->cur + 1; |
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104 jcc(code, CC_NC, code->cur + 2); |
1086
f0a1e0a2263c
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diff
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105 } else { |
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diff
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|
106 max_address = memmap[chunk].start; |
589
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107 } |
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108 |
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109 if (memmap[chunk].mask != opts->address_mask) { |
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110 and_ir(code, memmap[chunk].mask, adr_reg, opts->address_size); |
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111 } |
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112 void * cfun; |
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113 switch (fun_type) |
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114 { |
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115 case READ_16: |
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116 cfun = memmap[chunk].read_16; |
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117 break; |
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118 case READ_8: |
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119 cfun = memmap[chunk].read_8; |
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120 break; |
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121 case WRITE_16: |
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122 cfun = memmap[chunk].write_16; |
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123 break; |
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124 case WRITE_8: |
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125 cfun = memmap[chunk].write_8; |
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126 break; |
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127 default: |
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128 cfun = NULL; |
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129 } |
604
39d7d463ed5b
Get Z80 banked access sort of working again
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601
diff
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130 if(memmap[chunk].flags & access_flag) { |
589
2dde38c1744f
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131 if (memmap[chunk].flags & MMAP_PTR_IDX) { |
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132 if (memmap[chunk].flags & MMAP_FUNC_NULL) { |
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133 cmp_irdisp(code, 0, opts->context_reg, opts->mem_ptr_off + sizeof(void*) * memmap[chunk].ptr_index, SZ_PTR); |
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134 code_ptr not_null = code->cur + 1; |
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135 jcc(code, CC_NZ, code->cur + 2); |
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136 call(code, opts->save_context); |
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137 if (is_write) { |
658
6aa29ac33f1a
Use call_args and call_args_abi inside gen_mem_fun
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620
diff
changeset
|
138 call_args_abi(code, cfun, 3, opts->scratch2, opts->context_reg, opts->scratch1); |
6aa29ac33f1a
Use call_args and call_args_abi inside gen_mem_fun
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diff
changeset
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139 mov_rr(code, RAX, opts->context_reg, SZ_PTR); |
589
2dde38c1744f
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140 } else { |
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141 push_r(code, opts->context_reg); |
658
6aa29ac33f1a
Use call_args and call_args_abi inside gen_mem_fun
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diff
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|
142 call_args_abi(code, cfun, 2, opts->scratch1, opts->context_reg); |
589
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143 pop_r(code, opts->context_reg); |
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144 mov_rr(code, RAX, opts->scratch1, size); |
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145 } |
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146 jmp(code, opts->load_context); |
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147 |
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148 *not_null = code->cur - (not_null + 1); |
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149 } |
604
39d7d463ed5b
Get Z80 banked access sort of working again
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150 if ((opts->byte_swap || memmap[chunk].flags & MMAP_BYTESWAP) && size == SZ_B) { |
589
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151 xor_ir(code, 1, adr_reg, opts->address_size); |
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152 } |
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153 if (opts->address_size != SZ_D) { |
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154 movzx_rr(code, adr_reg, adr_reg, opts->address_size, SZ_D); |
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155 } |
1081
89cc20cf1ad3
Fix handling of MMAP_CODE chunks that also have MMAP_PTR_IDX set
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156 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { |
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157 push_r(code, adr_reg); |
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158 } |
589
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159 add_rdispr(code, opts->context_reg, opts->mem_ptr_off + sizeof(void*) * memmap[chunk].ptr_index, adr_reg, SZ_PTR); |
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160 if (is_write) { |
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161 mov_rrind(code, opts->scratch1, opts->scratch2, size); |
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162 if (memmap[chunk].flags & MMAP_CODE) { |
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163 pop_r(code, adr_reg); |
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164 } |
589
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165 } else { |
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166 mov_rindr(code, opts->scratch1, opts->scratch1, size); |
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167 } |
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168 } else { |
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169 uint8_t tmp_size = size; |
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170 if (size == SZ_B) { |
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171 if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
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172 bt_ir(code, 0, adr_reg, opts->address_size); |
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173 code_ptr good_addr = code->cur + 1; |
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174 jcc(code, (memmap[chunk].flags & MMAP_ONLY_ODD) ? CC_C : CC_NC, code->cur + 2); |
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175 if (!is_write) { |
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176 mov_ir(code, 0xFF, opts->scratch1, SZ_B); |
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177 } |
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178 retn(code); |
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179 *good_addr = code->cur - (good_addr + 1); |
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180 shr_ir(code, 1, adr_reg, opts->address_size); |
604
39d7d463ed5b
Get Z80 banked access sort of working again
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|
181 } else if (opts->byte_swap || memmap[chunk].flags & MMAP_BYTESWAP) { |
589
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182 xor_ir(code, 1, adr_reg, opts->address_size); |
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183 } |
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184 } else if ((memmap[chunk].flags & MMAP_ONLY_ODD) || (memmap[chunk].flags & MMAP_ONLY_EVEN)) { |
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185 tmp_size = SZ_B; |
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186 shr_ir(code, 1, adr_reg, opts->address_size); |
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187 if ((memmap[chunk].flags & MMAP_ONLY_EVEN) && is_write) { |
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188 shr_ir(code, 8, opts->scratch1, SZ_W); |
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189 } |
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190 } |
595
68f86ca4bb32
Add a couple of missing checks for the byte_swap and address_size parameters in gen_mem_fun
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191 if (opts->address_size != SZ_D) { |
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192 movzx_rr(code, adr_reg, adr_reg, opts->address_size, SZ_D); |
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193 } |
589
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194 if ((intptr_t)memmap[chunk].buffer <= 0x7FFFFFFF && (intptr_t)memmap[chunk].buffer >= -2147483648) { |
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195 if (is_write) { |
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196 mov_rrdisp(code, opts->scratch1, opts->scratch2, (intptr_t)memmap[chunk].buffer, tmp_size); |
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197 } else { |
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198 mov_rdispr(code, opts->scratch1, (intptr_t)memmap[chunk].buffer, opts->scratch1, tmp_size); |
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199 } |
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200 } else { |
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201 if (is_write) { |
760
656b1fded67f
Fix self modifying code checks on platforms like OS X on which guest RAM ends up at an address unreachable with a 32-bit displacement
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202 push_r(code, opts->scratch2); |
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203 mov_ir(code, (intptr_t)memmap[chunk].buffer, opts->scratch2, SZ_PTR); |
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204 add_rdispr(code, RSP, 0, opts->scratch2, SZ_PTR); |
589
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205 mov_rrind(code, opts->scratch1, opts->scratch2, tmp_size); |
760
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206 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { |
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207 pop_r(code, opts->scratch2); |
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208 } else { |
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209 add_ir(code, sizeof(void*), RSP, SZ_D); |
894
a7774fc2de4b
Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted.
Michael Pavone <pavone@retrodev.com>
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892
diff
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210 code->stack_off -= sizeof(void *); |
760
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211 } |
589
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212 } else { |
756
e1dc98f7ed9f
Preserve scratch2 when using it as a temporary in memory read functions. This fixes a bunch of issues with the Z80 core and possibly some issues with the 68K core as well
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750
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213 push_r(code, opts->scratch2); |
589
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214 mov_ir(code, (intptr_t)memmap[chunk].buffer, opts->scratch2, SZ_PTR); |
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215 mov_rindexr(code, opts->scratch2, opts->scratch1, 1, opts->scratch1, tmp_size); |
756
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parents:
750
diff
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216 pop_r(code, opts->scratch2); |
589
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217 } |
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218 } |
2dde38c1744f
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219 if (size != tmp_size && !is_write) { |
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diff
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220 if (memmap[chunk].flags & MMAP_ONLY_EVEN) { |
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221 shl_ir(code, 8, opts->scratch1, SZ_W); |
2dde38c1744f
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222 mov_ir(code, 0xFF, opts->scratch1, SZ_B); |
2dde38c1744f
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223 } else { |
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diff
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224 or_ir(code, 0xFF00, opts->scratch1, SZ_W); |
2dde38c1744f
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diff
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225 } |
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diff
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226 } |
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Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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diff
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|
227 } |
2dde38c1744f
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diff
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228 if (is_write && (memmap[chunk].flags & MMAP_CODE)) { |
2dde38c1744f
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diff
changeset
|
229 mov_rr(code, opts->scratch2, opts->scratch1, opts->address_size); |
620
9d6fed6501ba
Fix handling of code writes for Z80 core. This seems to get things close to being back to where they were before the big refactor that broke the Z80 core. Some problems remain. Notably the sound driver in Sonic 2 is still quite broken.
Michael Pavone <pavone@retrodev.com>
parents:
604
diff
changeset
|
230 shr_ir(code, opts->ram_flags_shift, opts->scratch1, opts->address_size); |
690
fc04781f4d28
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
231 bt_rrdisp(code, opts->scratch1, opts->context_reg, ram_flags_off, opts->address_size); |
fc04781f4d28
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
Michael Pavone <pavone@retrodev.com>
parents:
667
diff
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|
232 if (memmap[chunk].mask == opts->address_mask) { |
892
381a3b2f6065
Fix a bug in generating memory access functions when more than one MMAP_CODE region exists
Michael Pavone <pavone@retrodev.com>
parents:
760
diff
changeset
|
233 ram_flags_off += (memmap[chunk].end - memmap[chunk].start) / (1 << opts->ram_flags_shift) / 8; ; |
690
fc04781f4d28
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
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diff
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234 } else { |
892
381a3b2f6065
Fix a bug in generating memory access functions when more than one MMAP_CODE region exists
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parents:
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diff
changeset
|
235 ram_flags_off += (memmap[chunk].mask + 1) / (1 << opts->ram_flags_shift) / 8;; |
690
fc04781f4d28
Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM
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diff
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236 } |
589
2dde38c1744f
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567
diff
changeset
|
237 code_ptr not_code = code->cur + 1; |
2dde38c1744f
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|
238 jcc(code, CC_NC, code->cur + 2); |
1084
193db42e702b
Remove hacky assumption about Genesis memory map in M68K core
Michael Pavone <pavone@retrodev.com>
parents:
1081
diff
changeset
|
239 if (memmap[chunk].mask != opts->address_mask) { |
1107
fc125af5e4f1
Fix to the fix of handling of self modifying code. Was ORing the base address with the wrong register before calling the modified code handler
Michael Pavone <pavone@retrodev.com>
parents:
1086
diff
changeset
|
240 or_ir(code, memmap[chunk].start, opts->scratch2, opts->address_size); |
1084
193db42e702b
Remove hacky assumption about Genesis memory map in M68K core
Michael Pavone <pavone@retrodev.com>
parents:
1081
diff
changeset
|
241 } |
589
2dde38c1744f
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567
diff
changeset
|
242 call(code, opts->save_context); |
658
6aa29ac33f1a
Use call_args and call_args_abi inside gen_mem_fun
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620
diff
changeset
|
243 call_args(code, opts->handle_code_write, 2, opts->scratch2, opts->context_reg); |
589
2dde38c1744f
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parents:
567
diff
changeset
|
244 mov_rr(code, RAX, opts->context_reg, SZ_PTR); |
1086
f0a1e0a2263c
Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement
Michael Pavone <pavone@retrodev.com>
parents:
1084
diff
changeset
|
245 jmp(code, opts->load_context); |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
246 *not_code = code->cur - (not_code+1); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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567
diff
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|
247 } |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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567
diff
changeset
|
248 retn(code); |
2dde38c1744f
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diff
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|
249 } else if (cfun) { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
250 call(code, opts->save_context); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
251 if (is_write) { |
658
6aa29ac33f1a
Use call_args and call_args_abi inside gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
620
diff
changeset
|
252 call_args_abi(code, cfun, 3, opts->scratch2, opts->context_reg, opts->scratch1); |
6aa29ac33f1a
Use call_args and call_args_abi inside gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
620
diff
changeset
|
253 mov_rr(code, RAX, opts->context_reg, SZ_PTR); |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
254 } else { |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
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parents:
567
diff
changeset
|
255 push_r(code, opts->context_reg); |
658
6aa29ac33f1a
Use call_args and call_args_abi inside gen_mem_fun
Michael Pavone <pavone@retrodev.com>
parents:
620
diff
changeset
|
256 call_args_abi(code, cfun, 2, opts->scratch1, opts->context_reg); |
589
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
|
257 pop_r(code, opts->context_reg); |
2dde38c1744f
Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core
Michael Pavone <pavone@retrodev.com>
parents:
567
diff
changeset
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258 mov_rr(code, RAX, opts->scratch1, size); |
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259 } |
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260 jmp(code, opts->load_context); |
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261 } else { |
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262 //Not sure the best course of action here |
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263 if (!is_write) { |
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264 mov_ir(code, size == SZ_B ? 0xFF : 0xFFFF, opts->scratch1, size); |
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265 } |
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266 retn(code); |
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267 } |
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268 if (lb_jcc) { |
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269 *lb_jcc = code->cur - (lb_jcc+1); |
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270 lb_jcc = NULL; |
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271 } |
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272 if (ub_jcc) { |
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273 *ub_jcc = code->cur - (ub_jcc+1); |
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274 ub_jcc = NULL; |
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275 } |
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276 } |
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277 if (!is_write) { |
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278 mov_ir(code, size == SZ_B ? 0xFF : 0xFFFF, opts->scratch1, size); |
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279 } |
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280 retn(code); |
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281 return start; |
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282 } |