repos/blastem: gentests.py annotate

annotate gentests.py @ 2688:b42f00a3a937 default tip

Fix default target. Ensure m68k.h and z80.h are built before anything else when no dep info is available

author	Michael Pavone <pavone@retrodev.com>
date	Mon, 31 Mar 2025 21:06:18 -0700
parents	01cd8aa40573
children

rev	line source
2444 ab577e2ed66a Update some 68K test harness scripts to Python 3 Michael Pavone <pavone@retrodev.com> parents: 1837 diff changeset	1 #!/usr/bin/env python3
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	2
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	3 def split_fields(line):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	4 parts = []
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	5 while line:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 field,_,line = line.partition('\t')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	7 parts.append(field.strip())
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 while line.startswith('\t'):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	9 line = line[1:]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	10 return parts
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	11
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	12 class Program(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	13 def __init__(self, instruction):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	14 self.avail_dregs = {0,1,2,3,4,5,6,7}
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 self.avail_aregs = {0,1,2,3,4,5,6,7}
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	16 instruction.consume_regs(self)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 self.inst = instruction
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	18
224 f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	19 def dirname(self):
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	20 return self.inst.name + '_' + self.inst.size
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	21 def name(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 return str(self.inst).replace('.', '_').replace('#', '_').replace(',', '_').replace(' ', '_').replace('(', '[').replace(')', ']')
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	23
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	24 def write_rom_test(self, outfile):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 outfile.write('\tdc.l $0, start\n')
227 42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	26 needdivzero = self.inst.name.startswith('div')
325 8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	27 needchk = self.inst.name.startswith('chk')
2444 ab577e2ed66a Update some 68K test harness scripts to Python 3 Michael Pavone <pavone@retrodev.com> parents: 1837 diff changeset	28 for i in range(0x8, 0x100, 0x4):
227 42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	29 if needdivzero and i == 0x14:
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	30 outfile.write('\tdc.l div_zero_handler\n')
325 8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	31 elif needchk and i == 0x18:
8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	32 outfile.write('\tdc.l chk_handler\n')
227 42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	33 else:
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	34 outfile.write('\tdc.l empty_handler\n')
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	35 outfile.write('\tdc.b "SEGA"\nempty_handler:\n\trte\n')
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	36 if needdivzero:
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	37 outfile.write('div_zero_handler:\n')
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	38 div_zero_count = self.get_dreg()
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	39 outfile.write('\taddq #1, ' + str(div_zero_count) + '\n')
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	40 outfile.write('\trte\n')
325 8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	41 if needchk:
8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	42 outfile.write('chk_handler:\n')
8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	43 chk_count = self.get_dreg()
8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	44 outfile.write('\taddq #1, ' + str(chk_count) + '\n')
8db584faac4b Fixed decoding of CHK destination Mike Pavone <pavone@retrodev.com> parents: 227 diff changeset	45 outfile.write('\trte\n')
227 42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	46 outfile.write('start:\n\tmove #0, CCR\n')
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	47 if needdivzero:
42123feab62d Added test cases for divs/divu and added divide by zero handler to test generator Mike Pavone <pavone@retrodev.com> parents: 224 diff changeset	48 outfile.write('\tmoveq #0, ' + str(div_zero_count) + '\n')
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	49 already = {}
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	50 self.inst.write_init(outfile, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 if 'label' in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	52 outfile.write('lbl_' + str(already['label']) + ':\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	53 outfile.write('\t'+str(self.inst)+'\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	54 save_ccr = self.get_dreg()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	55 outfile.write('\tmove SR, ' + str(save_ccr) + '\n')
2462 3b1b7b272311 Save SR before saving result in test generator. Move instructions update flags on 68K Michael Pavone <pavone@retrodev.com> parents: 2449 diff changeset	56 outfile.write('\t'+self.inst.save_result(self.get_dreg(), True) + '\n')
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	57 outfile.write('\tmove #$1F, CCR\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	58 self.inst.invalidate_dest(already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	59 self.inst.write_init(outfile, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	60 if 'label' in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	61 outfile.write('lbl_' + str(already['label']) + ':\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	62 outfile.write('\t'+str(self.inst)+'\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	63 outfile.write('\t'+self.inst.save_result(self.get_dreg(), False) + '\n')
1283 188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	64 outfile.write('\treset\nforever:\n\tbra.s forever\n')
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	65
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	66 def consume_dreg(self, num):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	67 self.avail_dregs.discard(num)
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	68
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	69 def consume_areg(self, num):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	70 self.avail_aregs.discard(num)
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	71
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	72 def get_dreg(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	73 return Register('d', self.avail_dregs.pop())
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	74
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	75 class Dummy(object):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	76 def __str__(self):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	77 return ''
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	78 def write_init(self, outfile, size, already):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	79 pass
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	80 def consume_regs(self, program):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	81 pass
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	82
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	83 dummy_op = Dummy()
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	84
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	85 class Register(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	86 def __init__(self, kind, num):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	87 self.kind = kind
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	88 self.num = num
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	89
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	90 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	91 if self.kind == 'd' or self.kind == 'a':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	92 return self.kind + str(self.num)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	93 return self.kind
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	94
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	95 def write_init(self, outfile, size, already):
2582 6c475ddefd6f Add support for ccr/sr update instructions to 68K test generator Michael Pavone <pavone@retrodev.com> parents: 2469 diff changeset	96 if not str(self) in already and not self.kind in ('ccr', 'sr'):
2596 01cd8aa40573 populate registers at full size in test generator to expose masking bugs Michael Pavone <pavone@retrodev.com> parents: 2582 diff changeset	97 if self.kind in ('d', 'a'):
01cd8aa40573 populate registers at full size in test generator to expose masking bugs Michael Pavone <pavone@retrodev.com> parents: 2582 diff changeset	98 #populate all register bits during init to catch masking bugs
01cd8aa40573 populate registers at full size in test generator to expose masking bugs Michael Pavone <pavone@retrodev.com> parents: 2582 diff changeset	99 size = 'l'
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	100 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	101 val = randint(minv,maxv)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	102 already[str(self)] = val
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	103 outfile.write('\tmove.'+size+' #'+str(val)+', ' + str(self) + '\n')
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	104
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	105 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	106 if self.kind == 'd':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	107 program.consume_dreg(self.num)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	108 elif self.kind == 'a':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	109 program.consume_areg(self.num)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	110
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	111 def valid_ram_address(address, size='b'):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	112 return address >= 0xE00000 and address <= 0xFFFFFFFC and (address & 0xE00000) == 0xE00000 and (size == 'b' or not address & 1)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	113
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	114 def random_ram_address(mina=0xE00000, maxa=0xFFFFFFFC):
2444 ab577e2ed66a Update some 68K test harness scripts to Python 3 Michael Pavone <pavone@retrodev.com> parents: 1837 diff changeset	115 return randint(mina//2, maxa//2)*2 \| 0xE00000
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	116
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	117 class Indexed(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	118 def __init__(self, base, index, index_size, disp):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	119 self.base = base
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	120 self.index = index
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	121 self.index_size = index_size
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	122 self.disp = disp
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	123
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	124 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	125 if self.base.kind == 'pc':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	126 if str(self.index) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	127 index = already[str(self.index)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	128 if self.index_size == 'w':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	129 index = index & 0xFFFF
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	130 #sign extend index
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	131 if index & 0x8000:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	132 index -= 65536
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	133 if index > -1024:
1283 188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	134 index = already[str(self.index)] = 2 * randint(-16384, -512)
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	135 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	136 else:
1283 188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	137 index = already[str(self.index)] = 2 * randint(-16384, -512)
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	138 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	139 num = already.get('label', 0)+1
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	140 already['label'] = num
1283 188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	141 if (already[str(self.index)] + self.disp) & 1:
1837 f6ee0df6bb48 Minor fix to 68K test generator script Michael Pavone <pavone@retrodev.com> parents: 1283 diff changeset	142 if self.disp > 0:
f6ee0df6bb48 Minor fix to 68K test generator script Michael Pavone <pavone@retrodev.com> parents: 1283 diff changeset	143 self.disp -= 1
f6ee0df6bb48 Minor fix to 68K test generator script Michael Pavone <pavone@retrodev.com> parents: 1283 diff changeset	144 else:
f6ee0df6bb48 Minor fix to 68K test generator script Michael Pavone <pavone@retrodev.com> parents: 1283 diff changeset	145 self.disp += 1
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	146 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp) + ' + ' + str(index)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	147 else:
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	148 if self.base == self.index:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	149 if str(self.base) in already:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	150 if not valid_ram_address(already[str(self.base)]*2):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	151 del already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	152 self.write_init(outfile, size, already)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	153 return
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	154 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	155 base = index = already[str(self.base)]
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	156 else:
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	157 base = index = already[str(self.base)] = 2 * (random_ram_address()//4)
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	158 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	159 else:
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	160 if str(self.base) in already:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	161 if not valid_ram_address(already[str(self.base)]):
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	162 del already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	163 self.write_init(outfile, size, already)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	164 return
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	165 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	166 base = already[str(self.base)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	167 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	168 base = already[str(self.base)] = random_ram_address()
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	169 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	170 if str(self.index) in already:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	171 index = already[str(self.index)]
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	172 if self.index_size == 'w':
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	173 index = index & 0xFFFF
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	174 #sign extend index
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	175 if index & 0x8000:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	176 index -= 65536
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	177 if not valid_ram_address(base + index):
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	178 index = already[str(self.index)] = randint(-32, 31) * 2
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	179 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	180 else:
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	181 index = already[str(self.index)] = randint(-32, 31) * 2
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	182 outfile.write('\tmove.l #' + str(index) + ', ' + str(self.index) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	183 address = base + index + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	184 if (address & 0xFFFFFF) < 0xE00000:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	185 if (address & 0xFFFFFF) < 128:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	186 self.disp -= (address & 0xFFFFFF)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	187 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	188 self.disp += 0xE00000-(address & 0xFFFFFF)
608 097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range Michael Pavone <pavone@retrodev.com> parents: 439 diff changeset	189 if self.disp > 127:
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range Michael Pavone <pavone@retrodev.com> parents: 439 diff changeset	190 self.disp = 127
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range Michael Pavone <pavone@retrodev.com> parents: 439 diff changeset	191 elif self.disp < -128:
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range Michael Pavone <pavone@retrodev.com> parents: 439 diff changeset	192 self.disp = -128
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	193 address = base + index + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	194 elif (address & 0xFFFFFF) > 0xFFFFFC:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
608 097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range Michael Pavone <pavone@retrodev.com> parents: 439 diff changeset	196 if self.disp > 127:
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range Michael Pavone <pavone@retrodev.com> parents: 439 diff changeset	197 self.disp = 127
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range Michael Pavone <pavone@retrodev.com> parents: 439 diff changeset	198 elif self.disp < -128:
097c172839d4 Don't use out of bounds displacements in indexed mode even if our targeted address is out of RAM range Michael Pavone <pavone@retrodev.com> parents: 439 diff changeset	199 self.disp = -128
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	200 address = base + index + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	201 if size != 'b' and address & 1:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	202 self.disp = self.disp ^ 1
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	203 address = base + index + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	204 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	205 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	206
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	207 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	208 return '(' + str(self.disp) + ', ' + str(self.base) + ', ' + str(self.index) + '.' + self.index_size + ')'
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	209
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	210 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	211 self.base.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	212 self.index.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	213
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	214 class Displacement(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	215 def __init__(self, base, disp):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	216 self.base = base
1283 188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	217 if disp & 1:
188a60def81f Fixed some deficiencies in the 68K test generator Michael Pavone <pavone@retrodev.com> parents: 608 diff changeset	218 disp += 1
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	219 self.disp = disp
bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	220
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	221 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	222 if self.base.kind == 'pc':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	223 num = already.get('label', 0)+1
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	224 already['label'] = num
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	225 address = 'lbl_' + str(num) + ' + 2 + ' + str(self.disp)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	226 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	227 if str(self.base) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	228 if not valid_ram_address(already[str(self.base)]):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	229 del already[str(self.base)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	230 self.write_init(outfile, size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	231 return
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	232 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	233 base = already[str(self.base)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	234 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	235 base = already[str(self.base)] = random_ram_address()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	236 outfile.write('\tmove.l #' + str(base) + ', ' + str(self.base) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	237 address = base + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	238 if (address & 0xFFFFFF) < 0xE00000:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	239 if (address & 0xFFFFFF) < 0x10000:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	240 self.disp -= (address & 0xFFFFFF)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	241 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	242 self.disp += 0xE00000-(address & 0xFFFFFF)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	243 address = base + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	244 elif (address & 0xFFFFFF) > 0xFFFFFC:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	245 self.disp -= (address & 0xFFFFFF) - 0xFFFFFC
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	246 address = base + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	247 if size != 'b' and address & 1:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	248 self.disp = self.disp ^ 1
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	249 address = base + self.disp
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	250 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	251 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	252
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	253 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	254 return '(' + str(self.disp) + ', ' + str(self.base) + ')'
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	255
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	256 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	257 self.base.consume_regs(program)
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	258
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	259 class Indirect(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	260 def __init__(self, reg):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	261 self.reg = reg
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	262
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	263 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	264 return '(' + str(self.reg) + ')'
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	265
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	266 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	267 if str(self.reg) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	268 if not valid_ram_address(already[str(self.reg)], size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	269 del already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	270 self.write_init(outfile, size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	271 return
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	272 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	273 address = already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	274 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	275 address = random_ram_address()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	276 if size != 'b':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	277 address = address & 0xFFFFFFFE
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	278 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	279 already[str(self.reg)] = address
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	280 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	281 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	282
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	283 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	284 self.reg.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	285
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	286 class Increment(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	287 def __init__(self, reg):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	288 self.reg = reg
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	289
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	290 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	291 return '(' + str(self.reg) + ')+'
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	292
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	293 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	294 if str(self.reg) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	295 if not valid_ram_address(already[str(self.reg)], size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	296 del already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	297 self.write_init(outfile, size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	298 return
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	299 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	300 address = already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	301 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	302 address = random_ram_address()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	303 if size != 'b':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	304 address = address & 0xFFFFFFFE
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	305 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	306 already[str(self.reg)] = address
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	307 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	308 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	309
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	310 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	311 self.reg.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	312
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	313 class Decrement(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	314 def __init__(self, reg):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	315 self.reg = reg
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	316
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	317 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	318 return '-(' + str(self.reg) + ')'
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	319
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	320 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	321 if str(self.reg) in already:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	322 if not valid_ram_address(already[str(self.reg)]- 4 if size == 'l' else 2 if size == 'w' else 1, size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	323 del already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	324 self.write_init(outfile, size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	325 return
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	326 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	327 address = already[str(self.reg)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	328 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	329 address = random_ram_address(mina=0xE00004)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	330 if size != 'b':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	331 address = address & 0xFFFFFFFE
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	332 outfile.write('\tmove.l #' + str(address) + ', ' + str(self.reg) + '\n')
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	333 already[str(self.reg)] = address
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	334 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	335 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', (' + str(address) + ').l\n')
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	336
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	337 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	338 self.reg.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	339
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	340 class Absolute(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	341 def __init__(self, address, size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	342 self.address = address
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	343 self.size = size
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	344
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	345 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	346 return '(' + str(self.address) + ').' + self.size
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	347
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	348 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	349 minv,maxv = get_size_range(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	350 outfile.write('\tmove.' + size + ' #' + str(randint(minv, maxv)) + ', '+str(self)+'\n')
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	351
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	352 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	353 pass
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	354
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	355 class Immediate(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	356 def __init__(self, value):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	357 self.value = value
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	358
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	359 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	360 return '#' + str(self.value)
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	361
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	362 def write_init(self, outfile, size, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	363 pass
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	364
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	365 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	366 pass
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	367
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	368 all_dregs = [Register('d', i) for i in range(0, 8)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	369 all_aregs = [Register('a', i) for i in range(0, 8)]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	370 all_indirect = [Indirect(reg) for reg in all_aregs]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	371 all_predec = [Decrement(reg) for reg in all_aregs]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	372 all_postinc = [Increment(reg) for reg in all_aregs]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	373 from random import randint
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	374 def all_indexed():
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	375 return [Indexed(base, index, index_size, randint(-128, 127)) for base in all_aregs for index in all_dregs + all_aregs for index_size in ('w','l')]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	376
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	377 def all_disp():
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	378 return [Displacement(base, randint(-32768, 32767)) for base in all_aregs]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	379
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	380 def rand_pc_disp():
2444 ab577e2ed66a Update some 68K test harness scripts to Python 3 Michael Pavone <pavone@retrodev.com> parents: 1837 diff changeset	381 return [Displacement(Register('pc', 0), randint(-32768, -1024)) for x in range(0, 8)]
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	382
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	383 def all_pc_indexed():
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	384 return [Indexed(Register('pc', 0), index, index_size, randint(-128, 127)) for index in all_dregs + all_aregs for index_size in ('w','l')]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	385
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	386 def rand_abs_short():
2444 ab577e2ed66a Update some 68K test harness scripts to Python 3 Michael Pavone <pavone@retrodev.com> parents: 1837 diff changeset	387 return [Absolute(random_ram_address(0xFFFF8000), 'w') for x in range(0, 8)]
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	388
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	389 def rand_abs_long():
2444 ab577e2ed66a Update some 68K test harness scripts to Python 3 Michael Pavone <pavone@retrodev.com> parents: 1837 diff changeset	390 return [Absolute(random_ram_address(), 'l') for x in range(0, 8)]
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	391
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	392 def get_size_range(size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	393 if size == 'b':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	394 return (-128, 127)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	395 elif size == 'w':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	396 return (-32768, 32767)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	397 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	398 return (-2147483648, 2147483647)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	399
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	400 def rand_immediate(size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	401 minv,maxv = get_size_range(size)
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	402
2444 ab577e2ed66a Update some 68K test harness scripts to Python 3 Michael Pavone <pavone@retrodev.com> parents: 1837 diff changeset	403 return [Immediate(randint(minv, maxv)) for x in range(0,8)]
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	404
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	405 def get_variations(mode, size):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	406 mapping = {
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	407 'd':all_dregs,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	408 'a':all_aregs,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	409 '(a)':all_indirect,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	410 '-(a)':all_predec,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	411 '(a)+':all_postinc,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	412 '(n,a)':all_disp,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	413 '(n,a,x)':all_indexed,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	414 '(n,pc)':rand_pc_disp,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	415 '(n,pc,x)':all_pc_indexed,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	416 '(n).w':rand_abs_short,
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	417 '(n).l':rand_abs_long
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	418 }
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	419 if mode in mapping:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	420 ret = mapping[mode]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	421 if type(ret) != list:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	422 ret = ret()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	423 return ret
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	424 elif mode == '#n':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	425 return rand_immediate(size)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	426 elif mode.startswith('#(') and mode.endswith(')'):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	427 inner = mode[2:-1]
224 f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	428 start,sep,end = inner.rpartition('-')
220 cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 217 diff changeset	429 start,end = int(start),int(end)
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 217 diff changeset	430 if end-start > 16:
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 217 diff changeset	431 return [Immediate(randint(start, end)) for x in range(0,8)]
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 217 diff changeset	432 else:
cb72780e17b1 Add support for picking random numbers in a larger range in test generator. Add support for running a subset of tests in runner. Added testcases for bit and rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 217 diff changeset	433 return [Immediate(num) for num in range(start, end+1)]
2582 6c475ddefd6f Add support for ccr/sr update instructions to 68K test generator Michael Pavone <pavone@retrodev.com> parents: 2469 diff changeset	434 elif mode in ('ccr', 'sr'):
6c475ddefd6f Add support for ccr/sr update instructions to 68K test generator Michael Pavone <pavone@retrodev.com> parents: 2469 diff changeset	435 return [Register(mode, 0)]
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	436 else:
2444 ab577e2ed66a Update some 68K test harness scripts to Python 3 Michael Pavone <pavone@retrodev.com> parents: 1837 diff changeset	437 print("Don't know what to do with source type", mode)
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	438 return None
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	439
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	440 class Inst2Op(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	441 def __init__(self, name, size, src, dst):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	442 self.name = name
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	443 self.size = size
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	444 self.src = src
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	445 self.dst = dst
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	446
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	447 def __str__(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	448 return self.name + '.' + self.size + ' ' + str(self.src) + ', ' + str(self.dst)
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	449
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	450 def write_init(self, outfile, already):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	451 self.src.write_init(outfile, self.size, already)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	452 self.dst.write_init(outfile, self.size, already)
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	453
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	454 def invalidate_dest(self, already):
2582 6c475ddefd6f Add support for ccr/sr update instructions to 68K test generator Michael Pavone <pavone@retrodev.com> parents: 2469 diff changeset	455 if type(self.dst) == Register and not self.dst.kind in ('ccr', 'sr'):
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	456 del already[str(self.dst)]
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	457
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	458 def save_result(self, reg, always):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	459 if always or type(self.dst) != Register:
217 acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	460 if type(self.dst) == Decrement:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	461 src = Increment(self.dst.reg)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	462 elif type(self.dst) == Increment:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	463 src = Decrement(self.dst.reg)
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	464 else:
acd29e2664c6 Added testcases file. Some fixes to test generator for dealing with indexed mode with base and index reg the same. Added support for blastem headless mode in test runner. Mike Pavone <pavone@retrodev.com> parents: 214 diff changeset	465 src = self.dst
2582 6c475ddefd6f Add support for ccr/sr update instructions to 68K test generator Michael Pavone <pavone@retrodev.com> parents: 2469 diff changeset	466 if type(src) is Register and src.kind == 'ccr':
6c475ddefd6f Add support for ccr/sr update instructions to 68K test generator Michael Pavone <pavone@retrodev.com> parents: 2469 diff changeset	467 return 'move sr, ' + str(reg)
6c475ddefd6f Add support for ccr/sr update instructions to 68K test generator Michael Pavone <pavone@retrodev.com> parents: 2469 diff changeset	468 else:
6c475ddefd6f Add support for ccr/sr update instructions to 68K test generator Michael Pavone <pavone@retrodev.com> parents: 2469 diff changeset	469 return 'move.' + self.size + ' ' + str(src) + ', ' + str(reg)
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	470 else:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	471 return ''
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	472
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	473 def consume_regs(self, program):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	474 self.src.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	475 self.dst.consume_regs(program)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	476
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	477 class Inst1Op(Inst2Op):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	478 def __init__(self, name, size, dst):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	479 super(Inst1Op, self).__init__(name, size, dummy_op, dst)
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	480
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	481 def __str__(self):
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	482 return self.name + '.' + self.size + ' ' + str(self.dst)
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	483
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	484 class Entry(object):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	485 def __init__(self, line):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	486 fields = split_fields(line)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	487 self.name = fields[0]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	488 sizes = fields[1]
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	489 sources = fields[2].split(';')
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	490 if len(fields) > 3:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	491 dests = fields[3].split(';')
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	492 else:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	493 dests = None
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	494 combos = []
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	495 for size in sizes:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	496 for source in sources:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	497 if size != 'b' or source != 'a':
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	498 if dests:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	499 for dest in dests:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	500 if size != 'b' or dest != 'a':
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	501 combos.append((size, source, dest))
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	502 else:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	503 combos.append((size, None, source))
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	504 self.cases = combos
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	505
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	506 def programs(self):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	507 res = []
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	508 for (size, src, dst) in self.cases:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	509 dests = get_variations(dst, size)
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	510 if src:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	511 sources = get_variations(src, size)
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	512 for source in sources:
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	513 for dest in dests:
2469 db32408394c3 Update test generator to not generate link instructions with an odd displacement Michael Pavone <pavone@retrodev.com> parents: 2462 diff changeset	514 if self.name == 'link':
db32408394c3 Update test generator to not generate link instructions with an odd displacement Michael Pavone <pavone@retrodev.com> parents: 2462 diff changeset	515 dest.value = (dest.value //2) * 2
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	516 res.append(Program(Inst2Op(self.name, size, source, dest)))
bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	517 else:
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	518 for dest in dests:
439 bfbb8613efb4 Add support for single operand instructions to 68K test generator Mike Pavone <pavone@retrodev.com> parents: 325 diff changeset	519 res.append(Program(Inst1Op(self.name, size, dest)))
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	520 return res
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	521
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	522 def process_entries(f):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	523 entries = []
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	524 for line in f:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	525 if not line.startswith('Name') and not line.startswith('#') and len(line.strip()) > 0:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	526 entries.append(Entry(line))
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	527 return entries
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	528
224 f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	529 from os import path, mkdir
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	530 def main(args):
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	531 entries = process_entries(open('testcases.txt'))
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	532 for entry in entries:
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	533 programs = entry.programs()
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	534 for program in programs:
224 f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	535 dname = program.dirname()
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	536 if not path.exists('generated_tests/' + dname):
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	537 mkdir('generated_tests/' + dname)
f7ff02eeec2f Added testcases for move and roxl/roxr. Made some small improvements to test tools. Mike Pavone <pavone@retrodev.com> parents: 220 diff changeset	538 f = open('generated_tests/' + dname + '/' + program.name() + '.s68', 'w')
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	539 program.write_rom_test(f)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	540 f.close()
2449 bb6cc45518e6 Avoid address errors in generated tests Michael Pavone <pavone@retrodev.com> parents: 2444 diff changeset	541
214 9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	542 if __name__ == '__main__':
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	543 import sys
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	544 main(sys.argv)
9126c33cc33c Add test generator, builder and runner Mike Pavone <pavone@retrodev.com> parents: diff changeset	545

Mercurial > repos > blastem

annotate gentests.py @ 2688:b42f00a3a937 default tip