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annotate m68k.cpu @ 2588:0ea26288d983

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Implement abcd in new 68K core
author Michael Pavone <pavone@retrodev.com>
date Sat, 08 Feb 2025 22:41:36 -0800
parents e04c7e753bf6
children e602dbf776d8
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0c1491818f4b WIP new 68K core using CPU DSL
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1 info
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2 prefix m68k_
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3 opcode_size 16
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4 body m68k_run_op
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5 header m68k.h
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6 interrupt m68k_interrupt
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7 include m68k_util.c
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8 sync_cycle m68k_sync_cycle
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9
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10 declare
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11 typedef m68k_context *(sync_fun)(m68k_context * context, uint32_t address);
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12 typedef m68k_context *(*int_ack_fun)(m68k_context * context);
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13 typedef m68k_context *(*m68k_reset_handler)(m68k_context *context);
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14 void init_m68k_opts(m68k_options *opts, memmap_chunk * memmap, uint32_t num_chunks, uint32_t clock_divider, sync_fun *sync_components, int_ack_fun int_ack);
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15 m68k_context *init_68k_context(m68k_options * opts, m68k_reset_handler *reset_handler);
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16 void m68k_reset(m68k_context *context);
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17 void m68k_print_regs(m68k_context *context);
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18 void m68k_serialize(m68k_context *context, uint32_t pc, serialize_buffer *buf);
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19 void m68k_deserialize(deserialize_buffer *buf, void *vcontext);
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20 void start_68k_context(m68k_context *context, uint32_t pc);
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21 define NUM_MEM_AREAS 10
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22 define M68K_OPT_BROKEN_READ_MODIFY 1
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23 define INT_PENDING_SR_CHANGE 254
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24 define INT_PENDING_NONE 255
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25 define M68K_STATUS_TRACE 0x80
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26 define m68k_invalidate_code_range(context, start, end)
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27 define m68k_options_free free
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28 define m68k_handle_code_write(address, context)
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29 define resume_68k(context) m68k_execute(context, context->target_cycle)
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30 define insert_breakpoint(context, address, handler)
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31 define remove_breakpoint(context, address)
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32 define m68k_add_watchpoint(context, address, size)
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33 define m68k_remove_watchpoint(context, address, size)
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34
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35 regs
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36 dregs 32 d0 d1 d2 d3 d4 d5 d6 d7
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37 aregs 32 a0 a1 a2 a3 a4 a5 a6 a7
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38 pc 32
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39 other_sp 32
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40 scratch1 32
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41 scratch2 32
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42 int_cycle 32
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43 target_cycle 32
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44 wp_hit_address 32
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45 prefetch 16
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46 wp_hit_value 16
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47 wp_old_value 16
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48 int_priority 8
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49 int_num 8
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50 int_pending 8
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51 int_pending_num 8
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52 int_ack 8
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53 status 8
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54 ccr 8
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55 xflag 8
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56 nflag 8
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57 zflag 8
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58 vflag 8
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59 cflag 8
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60 wp_hit 8
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61 trace_pending 8
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62 should_return 8
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63 system ptrvoid
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64 reset_handler ptrvoid
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65 int_ack_handler ptrvoid
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66 sync_components ptrsync_fun
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67 mem_pointers ptr16 10
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68
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69 flags
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70 register ccr
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71 X 4 carry xflag
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72 N 3 sign nflag
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73 Z 2 zero zflag
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74 V 1 overflow vflag
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75 C 0 carry cflag
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76
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77 m68k_prefetch
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78 if dynarec
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79
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80 ccall m68k_read16_noinc context pc
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81 mov result prefetch
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82
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83 end
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84
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85 if interp
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86
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87 mov pc scratch1
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88 ocall read_16
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89 mov scratch1 prefetch
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90
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91 end
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92
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93 add 2 pc pc
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94
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95 check_user_mode_swap_ssp_usp
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96 local tmp 8
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97 and 0x20 status tmp
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98 if tmp
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99 else
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100 xchg other_sp a7
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101 end
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102
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103 m68k_get_sr
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104 lsl status 8 scratch1
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105 or ccr scratch1 scratch1
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106
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107 m68k_write32_lowfirst
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108 arg value 32
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109 add 2 scratch2 scratch2
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110 mov value scratch1
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111 ocall write_16
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112
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113 sub 2 scratch2 scratch2
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114 lsr value 16 scratch1
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115 ocall write_16
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116
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117 m68k_write32
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118 arg value 32
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119 local tmp 32
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120 mov value tmp
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121 lsr value 16 scratch1
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122 ocall write_16
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123
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124 add 2 scratch2 scratch2
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125 mov tmp scratch1
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126 ocall write_16
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127
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128 m68k_read32
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129 local tmp 32
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130 add 2 scratch1 tmp
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131 ocall read_16
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132 xchg scratch1 tmp
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133 ocall read_16
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134 lsl tmp 16 tmp
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135 or tmp scratch1 scratch1
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136
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137 m68k_trap
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138 arg vector 32
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139 check_user_mode_swap_ssp_usp
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140 #save PC
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141 a7 -= 4
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142 scratch2 = a7
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143 m68k_write32_lowfirst pc
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parents: 2502
diff changeset
144 #save SR
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
145 a7 -= 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
146 scratch2 = a7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
147 m68k_get_sr
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Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
148 ocall write_16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
149 #set supervisor bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
150 status |= 0x20
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
151 #clear trace bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
152 status &= 0x7F
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
153 trace_pending = 0
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
154 scratch1 = vector << 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
155 m68k_read32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
156 pc = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
157 cycles 10
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
158 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
159
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
160
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
161
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
162 m68k_interrupt
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
163 if cycles >=U int_cycle
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
164
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
165 #INT_PENDING_NONE
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
166 if 255 = int_pending
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
167 int_pending = int_priority
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
168 int_pending_num = int_num
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
169 else
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
170
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
171 #INT_PENDING_SR_CHANGE
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
172 if 254 = int_pending
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
173 int_pending = int_priority
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
174 int_pending_num = int_num
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
175
2580
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
176 end
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
177
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
178 check_user_mode_swap_ssp_usp
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
179
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
180 cycles 6
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
181 #save status reg
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
182 a7 -= 6
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
183 m68k_get_sr
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
184 scratch2 = a7
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
185 ocall write_16
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
186
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
187 #update status register
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
188 status &= 0x78
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
189 status |= int_pending
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
190 status |= 0x20
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
191
2580
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
192 #Interrupt ack cycle
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
193 int_ack = int_pending
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
194 cycles 4
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
195 if int_ack_handler
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
196 pcall int_ack_handler int_ack_fun context
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
197 end
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
198 if int_pending_num
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
199 else
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
200 int_pending_num = int_pending + 24
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
201 end
2580
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
202
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
203 #save pc
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
204 scratch2 = a7 + 2
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
205 scratch1 = pc - 2
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
206 m68k_write32_lowfirst scratch1
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
207
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
208 scratch1 = int_pending_num << 2
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
209 int_pending = 255 #INT_PENDING_NONE
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
210 int_pending_num = 0
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
211 m68k_read32
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
212 mov scratch1 pc
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
213 m68k_prefetch
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
214 update_sync
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
215 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
216 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
217
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
218 m68k_run_op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
219 dispatch prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
220
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
221 m68k_mem_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
222 arg address 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
223 arg size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
224 arg isdst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
225 mov address scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
226 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
227 mov address scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
228 meta ismem 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
229 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
230 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
231
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
232 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
233 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
234
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
236 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
237
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
239 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
240
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
241 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
242 meta op scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
243
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
244 m68k_write_size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
245 arg size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
246 arg lowfirst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
247 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
248 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
249 ocall write_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
250
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
251 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
252 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
253
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
254 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
255 if lowfirst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
256 m68k_write32_lowfirst scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
257 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
258 m68k_write32 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
259 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
260 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
261
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
262 m68k_index_word
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
263 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
264 local disp 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
265 and prefetch 255 disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
266 sext 16 disp disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
267 sext 32 disp disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
268 local index 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
269 lsr prefetch 12 index
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
270 local isareg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
271 and index 8 isareg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
272 and index 7 index
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
273 local islong 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
274 and prefetch 2048 islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
275
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
276 switch isareg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
277 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
278 switch islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
279 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
280 sext 32 dregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
281 case 2048
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
282 mov dregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
283 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
284 case 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
285 switch islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
286 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
287 sext 32 aregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
288 case 2048
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
289 mov aregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
290 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
291 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
292 add disp scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
293
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
294 m68k_fetch_op_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
295 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
296 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
297 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
298 arg isdst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
299 switch mode
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
300
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
301 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
302 #data reg direct
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
303 meta op dregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
304 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
305 meta ismem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
306 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
307
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
308 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
309 #address reg direct
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
310 meta op aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
311 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
312 meta ismem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
313 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
314
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
315 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
316 #address reg indirect
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
317 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
318
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
319 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
320 #postincrement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
321 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
322 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
323 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
324 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
325 addsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
326 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
327 addsize 1 aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
328 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
329 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
330 addsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
331 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
332
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
333 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
334 #predecrement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
335 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
336 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
337 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
338 decsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
339 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
340 decsize 1 aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
341 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
342 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
343 decsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
344 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
345 cycles 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
346 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
347
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
348 case 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
349 #displacement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
350 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
351 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
352 add scratch1 aregs.reg scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
353 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
354
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
355 case 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
356 #indexed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
357 m68k_index_word
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
358 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
359 add aregs.reg scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
360
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
361 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
362 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
363 #pc-relative and absolute modes
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
364
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
365 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
366 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
367 #absolute short
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
368 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
369 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
370 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
371
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
372 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
373 #absolute long
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
374 local address 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
375 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
376 lsl prefetch 16 address
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
377 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
378 or prefetch address scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
379 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
380
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
381 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
382 #pc displaceent
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
383 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
384 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
385 add scratch1 pc scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
386 sub 2 scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
387 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
388
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
389 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
390 #pc indexed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
391 m68k_index_word
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
392 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
393 add pc scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
394 sub 2 scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
395 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
396
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
397 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
398 #immediate
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
399 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
400 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
401 local tmp32 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
402 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
403 lsl prefetch 16 tmp32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
404 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
405 or prefetch tmp32 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
406
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
407 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
408 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
409 mov prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
410 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
411 meta op scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
412
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
413 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
414
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
415 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
416
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
417 m68k_fetch_src_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
418 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
419 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
420 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
421 m68k_fetch_op_ea mode reg Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
422 meta src op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
423 switch mode
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
424 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
425 meta src_is_mem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
426 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
427 meta src_is_mem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
428 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
429 meta src_is_mem 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
430 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
431
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
432 m68k_fetch_dst_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
433 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
434 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
435 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
436 m68k_fetch_op_ea mode reg Z 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
437 meta dst op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
438
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
439 m68k_save_dst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
440 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
441 if ismem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
442 m68k_write_size Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
443 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
444
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
445 1101DDD0ZZMMMRRR add_ea_dn
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
446 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
447 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
448 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
449 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
450 m68k_fetch_src_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
451
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
452 add src dregs.D dregs.D Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
453 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
454 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
455
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
456 1101DDD1ZZMMMRRR add_dn_ea
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
457 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
458 invalid M 1
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
459 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
460 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
461 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
462 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
463 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
464 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
465 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
466 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
467
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
468 add dregs.D dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
469 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
470 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
471 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
472
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
473 1101AAAZ11MMMRRR adda
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
474 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
475 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
476 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
477 local size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
478 local ext_src 32
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
479 #TODO: ensure "penalty" cycles are in the right place
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
480 if Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
481 size = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
482 switch M
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
483 case 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
484 #dreg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
485 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
486 case 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
487 #areg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
488 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
489 case 7
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
490 if R = 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
491 #immediate
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
492 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
493 else
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
494 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
495 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
496 default
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
497 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
498 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
499 else
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
500 size = 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
501 cycles 4
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
502 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
503 m68k_fetch_src_ea M R size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
505 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
506 sext 32 src ext_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
507 meta src ext_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
508 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
509
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
510 add src aregs.A aregs.A
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
511 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
512
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
513 00000110ZZMMMRRR addi
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
514 local immed 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
515 invalid Z 3
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
516 invalid M 1
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
517 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
518 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
519 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
520 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
521 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
522 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
523 #fetch immediate operand
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
524 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
525 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
526 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
527 lsl prefetch 16 immed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
528 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
529 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
530 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
531 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
532 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
533 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
534 mov prefetch immed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
535 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
536 #fetch dst EA
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
537 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
538
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
539 add immed dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
540 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
541 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
542 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
543
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
544 0101III0ZZMMMRRR addq
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
545 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
546 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
547 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
548 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
549 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
550 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
551 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
552 local src 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
553 switch I
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
554 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
555 mov 8 src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
556 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
557 mov I src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
558 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
559
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
560 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
561 switch M
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
562 case 1
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
563 cycles 4
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
564 add src dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
565 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
566 add src dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
567 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
568 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
569 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
570 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
571
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
572 1101DDD1ZZ000SSS addx_dy_dx
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
573 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
574 adc dregs.S dregs.D dregs.D Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
575 update_flags XNVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
576 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
577 case 0
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
578 local tmp8 8
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
579 mov dregs.D tmp8
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
580 if tmp8
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
581 update_flags Z0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
582 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
583 case 1
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
584 local tmp16 16
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
585 mov dregs.D tmp16
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
586 if tmp16
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
587 update_flags Z0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
588 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
589 case 2
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
590 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
591 if dregs.D
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
592 update_flags Z0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
593 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
594 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
595 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
596
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
597 1101DDD1ZZ001SSS addx_ay_ax
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
598 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
599 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
600 decsize Z aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
601 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
602 switch S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
603 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
604 sub 2 aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
605 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
606 decsize Z aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
607 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
608 end
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
609 #predec penalty on src only
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
610 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
611 mov aregs.S scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
612 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
613 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
614 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
615 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
616 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
617 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
618 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
619 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
620 mov scratch1 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
621 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
622 decsize Z aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
623 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
624 switch D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
625 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
626 sub 2 aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
627 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
628 decsize Z aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
629 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
630 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
631 mov aregs.D scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
632 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
633 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
634 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
635 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
636 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
637 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
638 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
639 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
640 adc scratch2 scratch1 scratch1 Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
641 update_flags XNVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
642 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
643 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
644 local tmp8 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
645 mov dregs.D tmp8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
646 if tmp8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
647 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
648 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
649 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
650 local tmp16 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
651 mov dregs.D tmp16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
652 if tmp16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
653 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
654 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
655 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
656 if dregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
657 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
658 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
659 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
660 mov aregs.D scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
661 m68k_write_size Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
662 m68k_prefetch
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
663
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
664 1100DDD0ZZMMMRRR and_ea_dn
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
665 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
666 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
667 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
668 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
669 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
670 m68k_fetch_src_ea M R Z
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
671
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
672 and src dregs.D dregs.D Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
673 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
674 m68k_prefetch
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
675
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
676 1100XXX100000YYY abcd_dx_dy
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
677 local lowx 16
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
678 local lowy 16
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
679 local highx 16
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
680 local highy 16
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
681 lowx = dregs.X & 0xF
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
682 lowy = dregs.Y & 0xF
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
683 adc lowx lowy lowy
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
684 if lowy >=U 0xA
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
685 lowy += 6
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
686 end
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
687 highx = dregs.X & 0xF0
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
688 highy = dregs.Y & 0xF0
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
689 highy += highx
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
690 highy += lowy
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
691 if highy >=U 0xA0
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
692 dregs.X:0 = highy + 0x60
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
693 update_flags X1C1VN
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
694 highy &= 0xFF
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
695 if highy
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
696 update_flags Z0
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
697 end
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
698 else
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
699 dregs.X:0 = highy
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
700 nflag = highy & 128
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
701 if highy
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
702 update_flags Z0
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
703 end
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
704 update_flags X0C0V0
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
705 end
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
706 cycles 2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
707 m68k_prefetch
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
708
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
709 1100XXX100001YYY abcd_ax_ay
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
710 local lowx 32
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
711 local lowy 32
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
712 if Y = 7
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
713 aregs.Y -= 2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
714 else
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
715 aregs.Y -= 1
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
716 end
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
717 #predec penalty on src only
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
718 cycles 2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
719 scratch1 = aregs.Y
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
720 ocall read_8
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
721 scratch2 = scratch1
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
722 if X = 7
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
723 aregs.X -= 2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
724 else
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
725 aregs.X -= 1
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
726 end
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
727 scratch1 = aregs.X
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
728 ocall read_8
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
729 lowx = scratch1 & 0xF
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
730 lowy = scratch2 & 0xF
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
731 scratch1 &= 0xF0
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
732 scratch2 &= 0xF0
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
733 adc lowx lowy lowy
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
734 if lowy >=U 0xA
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
735 lowy += 6
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
736 end
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
737 scratch1 += scratch2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
738 scratch1 += lowy
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
739 if scratch1 >=U 0xA0
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
740 scratch1:0 += 0x60
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
741 update_flags X1C1VN
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
742 else
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
743 cmp 0 scratch1 0
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
744 update_flags X0C0V0N
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
745 end
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
746 scratch1 &= 0xFF
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
747 if scratch1
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
748 update_flags Z0
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
749 end
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
750 scratch2 = aregs.X
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
751 ocall write_8
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
752 m68k_prefetch
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
753
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
754 1100XXX101000YYY exg_dn_dn
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
755 scratch1 = dregs.X
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
756 dregs.X = dregs.Y
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
757 dregs.Y = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
758 cycles 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
759 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
760
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
761 1100XXX101001YYY exg_an_an
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
762 scratch1 = aregs.X
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
763 aregs.X = aregs.Y
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
764 aregs.Y = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
765 cycles 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
766 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
767
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
768 1100XXX110001YYY exg_dn_an
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
769 scratch1 = dregs.X
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
770 dregs.X = aregs.Y
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
771 aregs.Y = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
772 cycles 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
773 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
774
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
775 1100DDD011MMMRRR mulu
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
776 local a 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
777 local b 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
778 invalid M 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
779 invalid M 7 R 5
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
780 invalid M 7 R 6
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
781 invalid M 7 R 7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
782
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
783 m68k_fetch_src_ea M R 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
784 #2-cycles per bit x 16, 2 for cleanup
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
785 cycles 34
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
786 #popcnt
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
787 a = src & 0b1010101010101010
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
788 a >>= 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
789 b = src & 0b0101010101010101
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
790 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
791 a = b & 0b1100110011001100
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
792 a >>= 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
793 b &= 0b0011001100110011
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
794 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
795 a = b & 0b1111000011110000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
796 a >>= 4
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
797 b &= 0b0000111100001111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
798 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
799 a = b & 0b1111111100000000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
800 a >>= 8
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
801 b &= 0b0000000011111111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
802 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
803 #2 cycles per set bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
804 b += b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
805 cycles b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
806 dregs.D = src * dregs.D
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
807 update_flags NZV0C0
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
808 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
809
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
810 1100DDD111MMMRRR muls
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
811 local a 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
812 local b 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
813 invalid M 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
814 invalid M 7 R 5
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
815 invalid M 7 R 6
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
816 invalid M 7 R 7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
817
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
818 m68k_fetch_src_ea M R 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
819 #2-cycles per bit x 16, 2 for cleanup
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
820 cycles 34
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
821 #muls timing is essentially the same as muls, but it's based on the number of 0/1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
822 #transitions rather than the number of 1 bits. xoring the value with itself shifted
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
823 #by one effectively sets one bit for every transition
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
824 b = src << 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
825 b ^= src
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
826 #popcnt
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
827 a = b & 0b1010101010101010
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
828 a >>= 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
829 b &= 0b0101010101010101
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
830 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
831 a = b & 0b1100110011001100
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
832 a >>= 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
833 b &= 0b0011001100110011
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
834 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
835 a = b & 0b1111000011110000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
836 a >>= 4
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
837 b &= 0b0000111100001111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
838 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
839 a = b & 0b1111111100000000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
840 a >>= 8
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
841 b &= 0b0000000011111111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
842 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
843 #2 cycles per set bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
844 b += b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
845 cycles b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
846 dregs.D = src *S dregs.D
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
847 update_flags NZV0C0
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
848 m68k_prefetch
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
849
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
850 1100DDD1ZZMMMRRR and_dn_ea
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
851 invalid M 0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
852 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
853 invalid M 7 R 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
854 invalid M 7 R 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
855 invalid M 7 R 4
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
856 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
857 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
858 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
859 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
860 m68k_fetch_dst_ea M R Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
861
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
862 and dregs.D dst dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
863 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
864 m68k_save_dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
865 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
866
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
867 00000010ZZMMMRRR andi
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
868 local immed 32
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
869 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
870 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
871 invalid M 7 R 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
872 invalid M 7 R 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
873 invalid M 7 R 4
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
874 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
875 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
876 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
877 #fetch immediate operand
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
878 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
879 switch Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
880 case 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
881 lsl prefetch 16 immed
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
882 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
883 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
884 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
885 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
886 end
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
887 default
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
888 mov prefetch immed
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
889 end
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
890 #fetch dst EA
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
891 m68k_fetch_dst_ea M R Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
892
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
893 and immed dst dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
894 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
895 m68k_save_dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
896 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
897
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
898 0000001000111100 andi_to_ccr
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
899 #fetch immediate operand
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
900 m68k_prefetch
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
901 ccr &= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
902 cycles 12 #TODO: where do these occur relative to fetches
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
903 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
904
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
905 0000001001111100 andi_to_sr
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
906 #TODO: privilege violation exception if in user mode
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
907 #fetch immediate operand
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
908 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
909 ccr &= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
910 scratch1 = prefetch >> 8
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
911 status &= scratch1
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
912 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
913 check_user_mode_swap_ssp_usp
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
914 update_sync
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
915 cycles 12 #TODO: where do these occur relative to fetches
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
916 m68k_prefetch
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
917
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
918 1011DDD1ZZMMMRRR eor_dn_ea
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
919 invalid M 1
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
920 invalid M 7 R 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
921 invalid M 7 R 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
922 invalid M 7 R 4
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
923 invalid M 7 R 5
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
924 invalid M 7 R 6
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
925 invalid M 7 R 7
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
926 invalid Z 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
927 m68k_fetch_dst_ea M R Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
928
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
929 if Z = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
930 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
931 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
932 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
933 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
934
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
935 xor dregs.D dst dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
936 update_flags NZV0C0
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
937 m68k_save_dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
938 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
939
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
940 00001010ZZMMMRRR eori
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
941 local immed 32
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
942 invalid Z 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
943 invalid M 1
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
944 invalid M 7 R 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
945 invalid M 7 R 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
946 invalid M 7 R 4
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
947 invalid M 7 R 5
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
948 invalid M 7 R 6
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
949 invalid M 7 R 7
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
950 #fetch immediate operand
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
951 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
952 switch Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
953 case 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
954 lsl prefetch 16 immed
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
955 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
956 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
957 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
958 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
959 end
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
960 default
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
961 mov prefetch immed
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
962 end
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
963 #fetch dst EA
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
964 m68k_fetch_dst_ea M R Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
965
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
966 xor immed dst dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
967 update_flags NZV0C0
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
968 m68k_save_dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
969 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
970
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
971 0000101000111100 eori_to_ccr
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
972 #fetch immediate operand
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
973 m68k_prefetch
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
974 ccr ^= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
975 cycles 12 #TODO: where do these occur relative to fetches
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
976 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
977
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
978 0000101001111100 eori_to_sr
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
979 #TODO: privilege violation exception if in user mode
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
980 #fetch immediate operand
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
981 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
982 ccr ^= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
983 scratch1 = prefetch >> 8
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
984 status ^= scratch1
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
985 check_user_mode_swap_ssp_usp
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
986 update_sync
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
987 cycles 12 #TODO: where do these occur relative to fetches
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
988 m68k_prefetch
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
989
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
990 1000DDD0ZZMMMRRR or_ea_dn
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
991 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
992 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
993 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
994 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
995 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
996 m68k_fetch_src_ea M R Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
997
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
998 if Z = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
999 switch M
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1000 case 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1001 #dreg
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1002 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1003 case 7
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1004 if R = 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1005 #immediate
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1006 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1007 else
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1008 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1009 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1010 default
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1011 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1012 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1013 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1014
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1015 or src dregs.D dregs.D Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1016 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1017 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1018
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1019 1000DDD1ZZMMMRRR or_dn_ea
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1020 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1021 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1022 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1023 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1024 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1025 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1026 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1027 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1028 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1029 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1030
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1031 or dregs.D dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1032 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1033 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1034 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1035
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1036 00000000ZZMMMRRR ori
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1037 local immed 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1038 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1039 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1040 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1041 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1042 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1043 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1044 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1045 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1046 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1047 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1048 switch Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1049 case 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1050 lsl prefetch 16 immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1051 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1052 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1053 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1054 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1055 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1056 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1057 mov prefetch immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1058 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1059 #fetch dst EA
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1060 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1061
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1062 or immed dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1063 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1064 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1065 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1066
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1067 0000000000111100 ori_to_ccr
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1068 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1069 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1070 or prefetch ccr ccr
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1071 cycles 12 #TODO: where do these occur relative to fetches
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1072 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1073
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1074 0000000001111100 ori_to_sr
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1075 #TODO: privilege violation exception if in user mode
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1076 #fetch immediate operand
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1077 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1078 ccr |= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1079 scratch1 = prefetch >> 8
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1080 status |= scratch1
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1081 update_sync
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1082 cycles 12 #TODO: where do these occur relative to fetches
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1083 m68k_prefetch
2587
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1084
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1085 1000DDD011MMMRRR divu
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1086 invalid M 1
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1087 invalid M 7 R 5
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1088 invalid M 7 R 6
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1089 invalid M 7 R 7
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1090 m68k_fetch_src_ea M R 1
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1091
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1092 if src = 0
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1093 cycles 4
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1094 update_flags N0Z0V0
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1095 m68k_trap 5
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1096 else
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1097 ccall divu context D src
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1098 m68k_prefetch
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1099 end
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1100
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1101
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1102 1000DDD111MMMRRR divs
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1103 invalid M 1
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1104 invalid M 7 R 5
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1105 invalid M 7 R 6
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1106 invalid M 7 R 7
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1107 local tmp 32
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1108 m68k_fetch_src_ea M R 1
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1109
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1110 if src = 0
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1111 cycles 4
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1112 update_flags N0Z0V0
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1113 m68k_trap 5
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1114 else
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1115 ccall divs context D src
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1116 m68k_prefetch
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1117 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1118
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1119 1001DDD0ZZMMMRRR sub_ea_dn
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1120 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1121 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1122 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1123 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1124 m68k_fetch_src_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1125
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1126 sub src dregs.D dregs.D Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1127 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1128 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1129
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1130 1001DDD1ZZMMMRRR sub_dn_ea
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1131 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1132 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1133 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1134 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1135 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1136 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1137 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1138 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1139 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1140 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1141
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1142 sub dregs.D dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1143 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1144 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1145 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1146
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1147 1001AAAZ11MMMRRR suba
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1148 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1149 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1150 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1151 local size 16
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1152 local ext_src 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1153 if Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1154 size = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1155 switch M
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1156 case 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1157 #dreg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1158 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1159 case 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1160 #areg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1161 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1162 case 7
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1163 if R = 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1164 #immediate
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1165 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1166 else
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1167 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1168 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1169 default
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1170 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1171 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1172 else
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1173 size = 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1174 cycles 4
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1175 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1176 m68k_fetch_src_ea M R size
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1177 switch size
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1178 case 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1179 sext 32 src ext_src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1180 meta src ext_src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1181 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1182
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1183 sub src aregs.A aregs.A
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1184 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1185
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1186 00000100ZZMMMRRR subi
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1187 local immed 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1188 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1189 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1190 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1191 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1192 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1193 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1194 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1195 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1196 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1197 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1198 switch Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1199 case 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1200 lsl prefetch 16 immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1201 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1202 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1203 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1204 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1205 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1206 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1207 mov prefetch immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1208 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1209 #fetch dst EA
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1210 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1211
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1212 sub immed dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1213 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1214 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1215 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1216
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1217 0101III1ZZMMMRRR subq
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1218 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1219 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1220 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1221 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1222 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1223 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1224 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1225 local src 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1226 switch I
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1227 case 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1228 mov 8 src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1229 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1230 mov I src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1231 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1232
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1233 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1234 switch M
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1235 case 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1236 sub src dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1237 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1238 sub src dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1239 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1240 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1241 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1242 m68k_prefetch
2586
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1243
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1244 1001DDD1ZZ000SSS subx_dy_dx
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1245 invalid Z 3
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1246 sbc dregs.S dregs.D dregs.D Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1247 update_flags XNVC
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1248 switch Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1249 case 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1250 local tmp8 8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1251 mov dregs.D tmp8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1252 if tmp8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1253 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1254 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1255 case 1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1256 local tmp16 16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1257 mov dregs.D tmp16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1258 if tmp16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1259 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1260 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1261 case 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1262 cycles 4
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1263 if dregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1264 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1265 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1266 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1267 m68k_prefetch
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1268
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1269 1001DDD1ZZ001SSS subx_ay_ax
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1270 invalid Z 3
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1271 if Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1272 decsize Z aregs.S aregs.S
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1273 else
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1274 switch S
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1275 case 7
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1276 sub 2 aregs.S aregs.S
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1277 default
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1278 decsize Z aregs.S aregs.S
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1279 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1280 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1281 #predec penalty on src only
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1282 cycles 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1283 mov aregs.S scratch1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1284 switch Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1285 case 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1286 ocall read_8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1287 case 1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1288 ocall read_16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1289 case 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1290 m68k_read32
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1291 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1292 mov scratch1 scratch2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1293 if Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1294 decsize Z aregs.D aregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1295 else
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1296 switch D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1297 case 7
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1298 sub 2 aregs.D aregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1299 default
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1300 decsize Z aregs.D aregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1301 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1302 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1303 mov aregs.D scratch1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1304 switch Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1305 case 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1306 ocall read_8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1307 case 1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1308 ocall read_16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1309 case 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1310 m68k_read32
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1311 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1312 sbc scratch2 scratch1 scratch1 Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1313 update_flags XNVC
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1314 switch Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1315 case 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1316 local tmp8 8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1317 mov dregs.D tmp8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1318 if tmp8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1319 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1320 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1321 case 1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1322 local tmp16 16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1323 mov dregs.D tmp16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1324 if tmp16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1325 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1326 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1327 case 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1328 if dregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1329 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1330 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1331 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1332 mov aregs.D scratch2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1333 m68k_write_size Z 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1334 m68k_prefetch
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1335
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1336 1110CCC0ZZ001RRR lsri
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1337 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1338 switch C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1339 case 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1340 meta shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1341 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1342 meta shift C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1343 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1344 lsr dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1345 update_flags XNZV0C
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1346 local cyc 32
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1347 cyc = shift + shift
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1348 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1349 case 2
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1350 cyc += 4
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1351 default
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1352 cyc += 2
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1353 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1354 cycles cyc
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1355 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1356 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1357
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1358 1110CCC0ZZ101RRR lsr_dn
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1359 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1360 local shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1361 and dregs.C 63 shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1362 lsr dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1363 update_flags XNZV0C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1364 add shift shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1365 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1366 case 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1367 add 4 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1368 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1369 add 2 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1370 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1371 cycles shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1372 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1373 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1374
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1375 1110001011MMMRRR lsr_ea
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1376 invalid M 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1377 invalid M 1
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1378 invalid M 7 R 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1379 invalid M 7 R 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1380 invalid M 7 R 4
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1381 invalid M 7 R 5
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1382 invalid M 7 R 6
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1383 invalid M 7 R 7
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1384
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1385 m68k_fetch_dst_ea M R 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1386 lsr dst 1 dst
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1387 update_flags XNZV0C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1388 m68k_save_dst 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1389 m68k_prefetch
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1390
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1391 1110CCC0ZZ000RRR asri
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1392 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1393 switch C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1394 case 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1395 meta shift 8
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1396 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1397 meta shift C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1398 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1399 asr dregs.R shift dregs.R Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1400 update_flags XNZV0C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1401 local cyc 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1402 cyc = shift + shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1403 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1404 case 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1405 cyc += 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1406 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1407 cyc += 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1408 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1409 cycles cyc
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1410 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1411 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1412
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1413 1110CCC0ZZ100RRR asr_dn
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1414 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1415 local shift 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1416 local shift_cycles 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1417 and dregs.C 63 shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1418 shift_cycles = shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1419 if shift = 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1420 cmp 0 dregs.R Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1421 update_flags NZV0C0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1422 else
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1423 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1424 case 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1425 if shift >=U 9
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1426 shift = 8
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1427 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1428 case 1
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1429 if shift >=U 17
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1430 shift = 16
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1431 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1432 case 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1433 if shift >=U 33
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1434 shift = 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1435 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1436 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1437 asr dregs.R shift dregs.R Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1438 update_flags XNZV0C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1439 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1440 shift_cycles += shift_cycles
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1441 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1442 case 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1443 shift_cycles += 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1444 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1445 shift_cycles += 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1446 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1447 cycles shift_cycles
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1448 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1449 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1450
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1451 1110000011MMMRRR asr_ea
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1452 invalid M 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1453 invalid M 1
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1454 invalid M 7 R 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1455 invalid M 7 R 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1456 invalid M 7 R 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1457 invalid M 7 R 5
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1458 invalid M 7 R 6
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1459 invalid M 7 R 7
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1460
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1461 m68k_fetch_dst_ea M R 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1462 asr dst 1 dst
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1463 update_flags XNZV0C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1464 m68k_save_dst 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1465 m68k_prefetch
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1466
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1467 1110CCC1ZZ001RRR lsli
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1468 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1469 switch C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1470 case 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1471 meta shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1472 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1473 meta shift C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1474 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1475 lsl dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1476 update_flags XNZV0C
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1477 local cyc 32
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1478 cyc = shift + shift
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1479 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1480 case 2
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1481 cyc += 4
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1482 default
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1483 cyc += 2
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1484 end
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1485 cycles cyc
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1486 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1487 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1488
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1489 1110CCC1ZZ101RRR lsl_dn
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1490 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1491 local shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1492 and dregs.C 63 shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1493 lsl dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1494 update_flags XNZV0C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1495 add shift shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1496 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1497 case 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1498 add 4 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1499 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1500 add 2 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1501 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1502 cycles shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1503 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1504 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1505
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1506 1110001111MMMRRR lsl_ea
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1507 invalid M 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1508 invalid M 1
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1509 invalid M 7 R 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1510 invalid M 7 R 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1511 invalid M 7 R 4
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1512 invalid M 7 R 5
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1513 invalid M 7 R 6
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1514 invalid M 7 R 7
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1515
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1516 m68k_fetch_dst_ea M R 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1517 lsl dst 1 dst
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1518 update_flags XNZV0C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1519 m68k_save_dst 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1520 m68k_prefetch
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1521
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1522 1110CCC1ZZ000RRR asli
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1523 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1524 switch C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1525 case 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1526 meta shift 8
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1527 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1528 meta shift C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1529 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1530 lsl dregs.R shift dregs.R Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1531 update_flags XNZV0C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1532 local cyc 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1533 cyc = shift + shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1534 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1535 case 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1536 cyc += 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1537 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1538 cyc += 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1539 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1540 cycles cyc
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1541 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1542 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1543
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1544 1110CCC1ZZ100RRR asl_dn
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1545 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1546 local shift 8
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1547 and dregs.C 63 shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1548 lsl dregs.R shift dregs.R Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1549 update_flags XNZV0C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1550 add shift shift shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1551 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1552 case 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1553 add 4 shift shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1554 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1555 add 2 shift shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1556 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1557 cycles shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1558 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1559 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1560
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1561 1110000111MMMRRR asl_ea
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1562 invalid M 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1563 invalid M 1
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1564 invalid M 7 R 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1565 invalid M 7 R 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1566 invalid M 7 R 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1567 invalid M 7 R 5
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1568 invalid M 7 R 6
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1569 invalid M 7 R 7
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1570
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1571 m68k_fetch_dst_ea M R 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1572 lsl dst 1 dst
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1573 update_flags XNZV0C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1574 m68k_save_dst 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1575 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1576
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1577 00ZZRRRMMMEEESSS move
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1578 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1579 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1580 invalid M 7 #not actually invalid, but will be handled separately due to DSL limitations
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1581 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1582 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1583 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1584 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1585 local memsrc 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1586 #move uses a different size format than most instructions
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1587 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1588 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1589 mov 0 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1590 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1591 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1592 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1593 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1594 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1595 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1596
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1597 if src_is_mem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1598 #avoid clobbering src if we need scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1599 mov src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1600 meta src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1601 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1602
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1603 cmp 0 src size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1604 update_flags NZV0C0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1605
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1606 switch M
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1607 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1608 mov src dregs.R size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1609
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1610 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1611 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1612 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1613 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1614
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1615 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1616 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1617 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1618 switch R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1619 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1620 if size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1621 addsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1622 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1623 addsize 1 aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1624 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1625 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1626 addsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1627 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1628 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1629
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1630 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1631 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1632 switch R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1633 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1634 if size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1635 decsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1636 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1637 decsize 1 aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1638 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1639 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1640 decsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1641 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1642 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1643 m68k_write_size size 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1644
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1645 case 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1646 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1647 sext 32 prefetch scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1648 add aregs.R scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1649 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1650 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1651
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1652 case 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1653 m68k_index_word
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1654 add aregs.R scratch1 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1655 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1656 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1657 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1658 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1659
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1660
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1661 00ZZ00M111EEESSS move_abs
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1662 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1663 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1664 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1665 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1666 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1667 local memsrc 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1668 #move uses a different size format than most instructions
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1669 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1670 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1671 mov 0 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1672 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1673 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1674 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1675 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1676 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1677 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1678
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1679 if src_is_mem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1680 #avoid clobbering src if we need scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1681 mov src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1682 meta src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1683 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1684
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1685 cmp 0 src size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1686 update_flags NZV0C0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1687
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1688 switch M
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1689 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1690 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1691 sext 32 prefetch scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1692
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1693 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1694 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1695 lsl prefetch 16 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1696 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1697 or prefetch scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1698 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1699 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1700 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1701 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1702
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1703 00ZZRRR001EEESSS movea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1704 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1705 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1706 invalid Z 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1707 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1708 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1709 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1710 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1711 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1712 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1713 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1714 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1715 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1716 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1717 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1718 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1719 mov src aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1720 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1721 sext 32 src aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1722 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1723 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1724
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1725 0100010011MMMRRR move_to_ccr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1726 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1727 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1728 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1729 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1730 m68k_fetch_src_ea M R 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1731 mov scratch1 ccr
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1732 cycles 8
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1733 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1734
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1735 0100011011MMMRRR move_to_sr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1736 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1737 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1738 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1739 invalid M 7 R 7
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
1740 #TODO: privilege violation exception if in user mode
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1741 m68k_fetch_src_ea M R 1
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1742 ccr = scratch1
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1743 status = scratch1 >> 8
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1744 check_user_mode_swap_ssp_usp
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1745 update_sync
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1746 cycles 8
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1747 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1748
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1749 0100000011MMMRRR move_from_sr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1750 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1751 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1752 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1753 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1754 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1755 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1756 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1757 m68k_fetch_dst_ea M R 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1758 lsl status 8 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1759 or ccr scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1760 mov scratch1 dst
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1761 if M
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1762 cycles 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1763 else
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1764 cycles 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1765 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1766 m68k_save_dst 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1767 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1768
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1769 01000000ZZMMMRRR negx
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1770 invalid M 1
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1771 invalid M 7 R 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1772 invalid M 7 R 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1773 invalid M 7 R 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1774 invalid M 7 R 5
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1775 invalid M 7 R 6
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1776 invalid M 7 R 7
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1777 m68k_fetch_dst_ea M R Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1778 sbc dst 0 dst Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1779 update_flags XNZVC
2464
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1780 if Z = 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1781 if M = 0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1782 cycles 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1783 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
1784 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1785 m68k_save_dst Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1786 m68k_prefetch
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1787
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1788 01000010ZZMMMRRR clr
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1789 invalid M 1
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1790 invalid M 7 R 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1791 invalid M 7 R 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1792 invalid M 7 R 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1793 invalid M 7 R 5
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1794 invalid M 7 R 6
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1795 invalid M 7 R 7
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1796 invalid Z 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1797 m68k_fetch_dst_ea M R Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1798 if Z = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1799 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1800 #register clears have 2 cycle penalty for longword size
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1801 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1802 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1803 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1804 dst:Z = 0
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1805 update_flags N0Z1V0C0
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1806 m68k_save_dst Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1807 m68k_prefetch
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1808
2453
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1809 00001100ZZMMMRRR cmpi
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1810 local immed 32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1811 invalid Z 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1812 invalid M 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1813 invalid M 7 R 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1814 invalid M 7 R 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1815 invalid M 7 R 4
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1816 invalid M 7 R 5
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1817 invalid M 7 R 6
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1818 invalid M 7 R 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1819 #fetch immediate operand
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1820 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1821 switch Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1822 case 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1823 immed = prefetch << 16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1824 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1825 immed |= prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1826 if M = 0
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1827 cycles 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1828 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1829 default
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1830 immed = prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1831 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1832 #fetch dst EA
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1833 m68k_fetch_dst_ea M R Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1834
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1835 cmp immed dst Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1836 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1837 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1838
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1839 1011DDD1ZZ001SSS cmpm
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1840 invalid Z 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1841 scratch1 = aregs.S
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1842 switch Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1843 case 0
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1844 ocall read_8
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1845 case 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1846 ocall read_16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1847 case 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1848 m68k_read32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1849 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1850 scratch2 = scratch1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1851 if Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1852 addsize Z aregs.S aregs.S
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1853 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1854 if S = 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1855 aregs.S += 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1856 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1857 aregs.S += 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1858 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1859 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1860 scratch1 = aregs.D
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1861 switch Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1862 case 0
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1863 ocall read_8
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1864 case 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1865 ocall read_16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1866 case 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1867 m68k_read32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1868 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1869 if Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1870 addsize Z aregs.D aregs.D
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1871 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1872 if D = 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1873 aregs.D += 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1874 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1875 aregs.D += 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1876 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1877 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1878 cmp scratch2 scratch1 Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1879 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1880 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1881
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1882 1011DDD0ZZMMMRRR cmp
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1883 invalid M 7 R 5
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1884 invalid M 7 R 6
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1885 invalid M 7 R 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1886 invalid Z 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1887 m68k_fetch_src_ea M R Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1888
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1889 if Z = 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1890 cycles 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1891 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1892
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1893 cmp src dregs.D Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1894 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1895 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1896
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1897 1011DDDZ11MMMRRR cmpa
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1898 invalid M 7 R 5
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1899 invalid M 7 R 6
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1900 invalid M 7 R 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1901 local size 16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1902 local ext_src 32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1903 if Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1904 size = 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1905 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1906 size = 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1907 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1908 m68k_fetch_src_ea M R size
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1909 cycles 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1910 if size = 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1911 sext 32 src ext_src
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1912 meta src ext_src
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1913 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1914 cmp src aregs.D
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1915 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1916 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
1917
2454
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1918 0000100000MMMRRR btsti
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1919 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1920 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1921 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1922 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1923
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1924 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1925 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1926 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1927 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1928 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1929 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1930 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1931 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1932 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1933 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1934 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1935 m68k_fetch_src_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1936 tmp &= src
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1937 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1938 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1939
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1940 0000100001MMMRRR bchgi
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1941 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1942 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1943 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1944 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1945 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1946 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1947 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1948
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1949 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1950 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1951 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1952 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1953 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1954 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1955 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1956 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1957 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1958 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1959 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1960 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1961 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1962 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1963 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1964 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1965 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1966 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1967 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1968 dst ^= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1969 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1970 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1971
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1972 0000100010MMMRRR bclri
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1973 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1974 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1975 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1976 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1977 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1978 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1979 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1980
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1981 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1982 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1983 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1984 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1985 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1986 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1987 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1988 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1989 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1990 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1991 cycles 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1992 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1993 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1994 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1995 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1996 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1997 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1998 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
1999 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2000 tmp = ~tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2001 dst &= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2002 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2003 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2004
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2005 0000100011MMMRRR bseti
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2006 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2007 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2008 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2009 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2010 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2011 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2012 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2013
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2014 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2015 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2016 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2017 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2018 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2019 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2020 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2021 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2022 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2023 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2024 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2025 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2026 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2027 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2028 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2029 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2030 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2031 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2032 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2033 dst |= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2034 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2035 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2036
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2037 0000SSS100MMMRRR btst_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2038 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2039 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2040 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2041 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2042
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2043 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2044 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2045 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2046 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2047 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2048 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2049 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2050 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2051 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2052 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2053 m68k_fetch_src_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2054 tmp &= src
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2055 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2056 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2057
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2058 0000SSS101MMMRRR bchg_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2059 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2060 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2061 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2062 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2063 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2064 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2065 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2066
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2067 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2068 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2069 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2070 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2071 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2072 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2073 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2074 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2075 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2076 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2077 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2078 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2079 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2080 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2081 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2082 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2083 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2084 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2085 dst ^= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2086 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2087 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2088
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2089 0000SSS110MMMRRR bclr_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2090 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2091 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2092 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2093 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2094 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2095 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2096 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2097
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2098 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2099 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2100 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2101 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2102 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2103 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2104 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2105 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2106 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2107 cycles 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2108 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2109 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2110 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2111 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2112 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2113 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2114 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2115 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2116 tmp = ~tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2117 dst &= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2118 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2119 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2120
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2121 0000SSS111MMMRRR bset_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2122 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2123 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2124 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2125 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2126 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2127 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2128 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2129
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2130 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2131 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2132 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2133 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2134 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2135 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2136 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2137 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2138 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2139 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2140 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2141 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2142 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2143 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2144 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2145 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2146 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2147 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2148 dst |= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2149 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2150 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2151
2456
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2152 0000DDD10Z001AAA movep_ay_dx
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2153 local address 32
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2154 m68k_prefetch
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2155 scratch1 += aregs.A
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2156 address = scratch1 + 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2157 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2158 dregs.D:1 = scratch1 << 8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2159 scratch1 = address
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2160 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2161 dregs.D:0 = scratch1
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2162 if Z
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2163 address += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2164 scratch1 = address
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2165 dregs.D <<= 16
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2166 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2167 dregs.D:1 = scratch1 << 8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2168 scratch1 = address + 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2169 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2170 dregs.D:0 = scratch1
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2171 end
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2172 m68k_prefetch
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2173
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2174 0000DDD11Z001AAA movep_dx_ay
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2175 m68k_prefetch
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2176 scratch2 = scratch1 + aregs.A
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2177 if Z
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2178 scratch1 = dregs.D >> 24
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2179 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2180 scratch2 += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2181 scratch1 = dregs.D >> 16
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2182 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2183 scratch2 += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2184 end
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2185 scratch1 = dregs.D >> 8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2186 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2187 scratch2 += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2188 scratch1 = dregs.D
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2189 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2190 m68k_prefetch
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2191
2464
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2192 01000100ZZMMMRRR neg
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2193 invalid Z 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2194 invalid M 1
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2195 invalid M 7 R 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2196 invalid M 7 R 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2197 invalid M 7 R 4
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2198 invalid M 7 R 5
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2199 invalid M 7 R 6
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2200 invalid M 7 R 7
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2201
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2202 m68k_fetch_dst_ea M R Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2203 dst:Z = -dst
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2204 update_flags XNZVC
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2205 if Z = 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2206 if M = 0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2207 cycles 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2208 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2209 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2210 m68k_save_dst Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2211 m68k_prefetch
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2212
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2213 01000110ZZMMMRRR not
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2214 invalid Z 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2215 invalid M 1
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2216 invalid M 7 R 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2217 invalid M 7 R 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2218 invalid M 7 R 4
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2219 invalid M 7 R 5
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2220 invalid M 7 R 6
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2221 invalid M 7 R 7
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2222
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2223 m68k_fetch_dst_ea M R Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2224 dst:Z = ~dst
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2225 update_flags NZV0C0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2226 if Z = 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2227 if M = 0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2228 cycles 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2229 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2230 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2231 m68k_save_dst Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2232 m68k_prefetch
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2233
2468
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2234 01001000ZZ000RRR ext
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2235 invalid Z 0
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2236 invalid Z 1
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2237 if Z = 3
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2238 meta bits 32
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2239 else
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2240 meta bits 16
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2241 end
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2242 sext bits dregs.R dregs.R
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2243 update_flags NZV0C0
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2244 m68k_prefetch
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2245
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2246 010011100100VVVV trap
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2247 local vector 32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2248 scratch1 = pc
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2249 vector = V + 32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2250 m68k_trap vector
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2251
2470
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2252 0100111001010RRR link
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2253 a7 -= 4
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2254 scratch2 = a7
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2255 #TODO: confirm order of fetch and write
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2256 m68k_write32 aregs.R
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2257 m68k_prefetch
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2258 aregs.R = a7
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2259 sext 32 scratch1 scratch1
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2260 a7 += scratch1
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2261 m68k_prefetch
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2262
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2263 0100111001011RRR unlk
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2264 a7 = aregs.R
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2265 scratch1 = a7
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2266 m68k_read32
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2267 a7 += 4
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2268 aregs.R = scratch1
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2269 m68k_prefetch
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2270
2472
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2271 0100100001000RRR swap
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2272 ror dregs.R 16 dregs.R
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2273 update_flags NZV0C0
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2274 m68k_prefetch
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2275
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2276 m68k_calc_ea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2277 arg mode 16
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2278 arg reg 16
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2279 arg index_penalty 32
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2280
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2281 switch mode
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2282 case 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2283 #address reg indirect
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2284 meta ea aregs.reg
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2285 case 3
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2286 #postincrement
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2287 meta ea aregs.reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2288 case 4
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2289 #predecrement
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2290 #note: this case is only used when m68k_calc_ea
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2291 #is called from movem_reg_to_mem which does its own decrementing
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2292 meta ea aregs.reg
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2293 case 5
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2294 #displacement
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2295 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2296 sext 32 prefetch scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2297 scratch1 += aregs.reg
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2298 meta ea scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2299 case 6
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2300 #index
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2301 m68k_index_word
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2302 cycles index_penalty
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2303 scratch1 += aregs.reg
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2304 meta ea scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2305 case 7
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2306 switch reg
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2307 case 0
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2308 #absolute short
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2309 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2310 sext 32 prefetch scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2311 case 1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2312 #absoltue long
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2313 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2314 scratch2 = prefetch << 16
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2315 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2316 scratch1 = scratch2 | prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2317 case 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2318 #pc displacement
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2319 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2320 sext 32 prefetch scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2321 scratch1 += pc
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2322 scratch1 -= 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2323 case 3
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2324 #pc indexed
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2325 m68k_index_word
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2326 cycles index_penalty
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2327 scratch1 += pc
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2328 scratch1 -= 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2329 end
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2330 meta ea scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2331 end
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2332
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2333 0100100001MMMRRR pea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2334 invalid M 0
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2335 invalid M 1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2336 invalid M 3
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2337 invalid M 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2338 invalid M 7 R 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2339 invalid M 7 R 5
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2340 invalid M 7 R 6
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2341 invalid M 7 R 7
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2342
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2343 m68k_calc_ea M R 4
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2344 scratch2 = a7 - 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2345 m68k_write32_lowfirst ea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2346 a7 -= 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2347
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2348 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2349
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2350 0100DDD111MMMRRR lea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2351 invalid M 0
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2352 invalid M 1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2353 invalid M 3
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2354 invalid M 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2355 invalid M 7 R 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2356 invalid M 7 R 5
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2357 invalid M 7 R 6
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2358 invalid M 7 R 7
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2359
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2360 m68k_calc_ea M R 4
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2361 aregs.D = ea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2362
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2363 m68k_prefetch
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2364
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2365 01001010ZZMMMRRR tst
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2366 invalid M 7 R 5
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2367 invalid M 7 R 6
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2368 invalid M 7 R 7
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2369
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2370 m68k_fetch_dst_ea M R Z
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2371
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2372 cmp 0 dst Z
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2373 update_flags NZV0C0
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2374 m68k_prefetch
2472
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2375
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2376 0100111001110000 reset
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2377 if reset_handler
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2378 pcall reset_handler m68k_reset_handler context
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2379 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2380 cycles 128
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2381 m68k_prefetch
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2382
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2383 0100111001110001 nop
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2384 m68k_prefetch
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2385
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2386 0100111001110011 rte
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2387 #TODO: privilege violation exception if in user mode
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2388 #Read saved SR
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2389 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2390 ocall read_16
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2391 a7 += 2
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2392 ccr = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2393 status = scratch1 >> 8
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2394 #Read saved PC
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2395 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2396 m68k_read32
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2397 a7 += 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2398 pc = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2399
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2400 check_user_mode_swap_ssp_usp
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2401 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2402 update_sync
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2403 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2404
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2405 0100111001110101 m68k_rts
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2406 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2407 m68k_read32
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2408 a7 += 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2409 pc = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2410
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2411 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2412 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2413
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2414 0100111001110111 rtr
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2415 #Read saved CCR
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2416 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2417 ocall read_16
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2418 a7 += 2
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2419 ccr = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2420 #Read saved PC
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2421 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2422 m68k_read32
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2423 a7 += 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2424 pc = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2425
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2426 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2427 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2428
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2429 0100111010MMMRRR jsr
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2430 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2431 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2432 invalid M 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2433 invalid M 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2434 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2435 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2436 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2437 invalid M 7 R 7
2585
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2438 local tmp 32
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2439
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2440 m68k_calc_ea M R 2
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2441 tmp = ea
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2442
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2443 a7 -= 4
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2444 scratch2 = a7
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2445 m68k_write32 pc
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2446
2585
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2447 pc = tmp
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2448
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2449 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2450 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2451
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2452 0100111011MMMRRR jmp
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2453 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2454 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2455 invalid M 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2456 invalid M 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2457 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2458 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2459 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2460 invalid M 7 R 7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2461
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2462 m68k_calc_ea M R 2
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2463 pc = ea
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2464
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2465 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2466 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2467
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2468 m68k_movem_reg_to_mem
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2469 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2470 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2471 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2472 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2473
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2474 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2475 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2476 scratch2 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2477 scratch1 = reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2478 m68k_write_size size 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2479 addsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2480 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2481
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2482 m68k_movem_reg_to_mem_dec
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2483 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2484 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2485 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2486 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2487
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2488 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2489 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2490 decsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2491 scratch2 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2492 scratch1 = reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2493 m68k_write_size size 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2494 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2495
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2496
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2497 010010001ZMMMRRR movem_reg_to_mem
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2498 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2499 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2500 invalid M 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2501 invalid M 7 R 2
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2502 invalid M 7 R 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2503 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2504 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2505 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2506 invalid M 7 R 7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2507 local reglist 16
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2508 local address 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2509 local sz 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2510 sz = Z + 1
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2511
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2512 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2513 reglist = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2514
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2515 m68k_calc_ea M R 2
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2516 address = ea
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2517 meta addr address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2518 if M = 4
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2519 m68k_movem_reg_to_mem_dec reglist 1 a7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2520 m68k_movem_reg_to_mem_dec reglist 2 a6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2521 m68k_movem_reg_to_mem_dec reglist 4 a5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2522 m68k_movem_reg_to_mem_dec reglist 8 a4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2523 m68k_movem_reg_to_mem_dec reglist 16 a3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2524 m68k_movem_reg_to_mem_dec reglist 32 a2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2525 m68k_movem_reg_to_mem_dec reglist 64 a1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2526 m68k_movem_reg_to_mem_dec reglist 128 a0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2527 m68k_movem_reg_to_mem_dec reglist 256 d7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2528 m68k_movem_reg_to_mem_dec reglist 512 d6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2529 m68k_movem_reg_to_mem_dec reglist 1024 d5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2530 m68k_movem_reg_to_mem_dec reglist 2048 d4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2531 m68k_movem_reg_to_mem_dec reglist 4096 d3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2532 m68k_movem_reg_to_mem_dec reglist 8192 d2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2533 m68k_movem_reg_to_mem_dec reglist 16384 d1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2534 m68k_movem_reg_to_mem_dec reglist 32768 d0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2535 ea = address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2536 else
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2537 m68k_movem_reg_to_mem reglist 1 d0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2538 m68k_movem_reg_to_mem reglist 2 d1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2539 m68k_movem_reg_to_mem reglist 4 d2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2540 m68k_movem_reg_to_mem reglist 8 d3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2541 m68k_movem_reg_to_mem reglist 16 d4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2542 m68k_movem_reg_to_mem reglist 32 d5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2543 m68k_movem_reg_to_mem reglist 64 d6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2544 m68k_movem_reg_to_mem reglist 128 d7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2545 m68k_movem_reg_to_mem reglist 256 a0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2546 m68k_movem_reg_to_mem reglist 512 a1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2547 m68k_movem_reg_to_mem reglist 1024 a2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2548 m68k_movem_reg_to_mem reglist 2048 a3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2549 m68k_movem_reg_to_mem reglist 4096 a4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2550 m68k_movem_reg_to_mem reglist 8192 a5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2551 m68k_movem_reg_to_mem reglist 16384 a6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2552 m68k_movem_reg_to_mem reglist 32768 a7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2553 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2554 m68k_prefetch
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2555
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2556 m68k_movem_mem_to_dreg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2557 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2558 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2559 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2560 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2561
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2562 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2563 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2564 scratch1 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2565 if sz = 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2566 ocall read_16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2567 sext 32 scratch1 dregs.reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2568 else
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2569 m68k_read32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2570 dregs.reg = scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2571 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2572 addsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2573 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2574
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2575 m68k_movem_mem_to_areg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2576 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2577 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2578 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2579 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2580
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2581 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2582 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2583 scratch1 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2584 if sz = 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2585 ocall read_16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2586 sext 32 scratch1 aregs.reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2587 else
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2588 m68k_read32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2589 aregs.reg = scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2590 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2591 addsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2592 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2593
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2594 010011001ZMMMRRR movem_mem_to_reg
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2595 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2596 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2597 invalid M 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2598 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2599 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2600 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2601 invalid M 7 R 7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2602 local reglist 16
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2603 local address 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2604 local sz 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2605 sz = Z + 1
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2606
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2607 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2608 reglist = scratch1
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2609
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2610 m68k_calc_ea M R 2
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2611 address = ea
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2612 meta addr address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2613
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2614 m68k_movem_mem_to_dreg reglist 1 0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2615 m68k_movem_mem_to_dreg reglist 2 1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2616 m68k_movem_mem_to_dreg reglist 4 2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2617 m68k_movem_mem_to_dreg reglist 8 3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2618 m68k_movem_mem_to_dreg reglist 16 4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2619 m68k_movem_mem_to_dreg reglist 32 5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2620 m68k_movem_mem_to_dreg reglist 64 6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2621 m68k_movem_mem_to_dreg reglist 128 7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2622 m68k_movem_mem_to_areg reglist 256 0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2623 m68k_movem_mem_to_areg reglist 512 1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2624 m68k_movem_mem_to_areg reglist 1024 2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2625 m68k_movem_mem_to_areg reglist 2048 3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2626 m68k_movem_mem_to_areg reglist 4096 4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2627 m68k_movem_mem_to_areg reglist 8192 5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2628 m68k_movem_mem_to_areg reglist 16384 6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2629 m68k_movem_mem_to_areg reglist 32768 7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2630 #dummy read
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2631 scratch1 = address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2632 ocall read_16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2633 if M = 3
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2634 ea = address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2635 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2636
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2637 m68k_prefetch
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2638
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2639 0100111001100RRR move_to_usp
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2640 #TODO: trap if not in supervisor mode
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2641 other_sp = aregs.R
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2642 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2643
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2644 0100111001101RRR move_from_usp
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2645 #TODO: trap if not in supervisor mode
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2646 aregs.R = other_sp
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2647 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2648
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2649 0111RRR0IIIIIIII moveq
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2650 local tmp 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2651 sext 16 I tmp
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2652 sext 32 tmp dregs.R
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2653 cmp 0 dregs.R
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2654 update_flags NZV0C0
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2655 m68k_prefetch
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2656
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2657 0110000100000000 bsr_w
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2658 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2659 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2660 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2661 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2662 sext 32 prefetch offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2663
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2664 a7 -= 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2665 scratch2 = a7
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2666 m68k_write32 pc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2667
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2668 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2669 pc -= 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2670
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2671 cycles 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2672 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2673
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2674
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2675 01100001DDDDDDDD bsr
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2676 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2677 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2678 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2679 sext 16 D offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2680 sext 32 offset offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2681
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2682 a7 -= 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2683 scratch2 = a7
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2684 m68k_write32 pc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2685
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2686 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2687
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2688 cycles 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2689 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2690
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2691 m68k_check_cond
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2692 arg cond 16
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2693 local invert 8
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2694 switch cond
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2695 case 0
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2696 #true
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2697 meta istrue 1
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2698 case 1
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2699 #false
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2700 meta istrue 0
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2701 case 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2702 #high
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2703 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2704 invert = zflag | cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2705 invert = !invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2706 case 3
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2707 #low or same
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2708 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2709 invert = zflag | cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2710 case 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2711 #carry clear
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2712 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2713 invert = !cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2714 case 5
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2715 #carry set
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2716 meta istrue cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2717 case 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2718 #not equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2719 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2720 invert = !zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2721 case 7
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2722 #equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2723 meta istrue zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2724 case 8
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2725 #overflow clear
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2726 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2727 invert = !vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2728 case 9
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2729 #overflow set
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2730 meta istrue vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2731 case 10
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2732 #plus
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2733 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2734 invert = !nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2735 case 11
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2736 #minus
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2737 meta istrue nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2738 case 12
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2739 #greater or equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2740 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2741 invert = nflag - vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2742 invert = !invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2743 case 13
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2744 #less
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2745 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2746 invert = nflag - vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2747 case 14
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2748 #greater
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2749 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2750 invert = vflag ^ nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2751 invert |= zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2752 invert = !invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2753 case 15
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2754 #less or equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2755 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2756 invert = vflag ^ nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2757 invert |= zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2758 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2759
2584
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2760 0101CCCC11MMMDDD scc
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2761 invalid M 1
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2762 invalid M 7 D 2
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2763 invalid M 7 D 3
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2764 invalid M 7 D 4
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2765 invalid M 7 D 5
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2766 invalid M 7 D 6
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2767 invalid M 7 D 7
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2768 m68k_fetch_dst_ea M D 0
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2769 m68k_check_cond C
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2770 if istrue
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2771 if M = 0
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2772 cycles 2
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2773 end
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2774 dst:0 = 0xFF
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2775 else
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2776 dst:0 = 0
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2777 end
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2778 m68k_save_dst 0
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2779 m68k_prefetch
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
2780
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2781 0110CCCC00000000 bcc_w
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2782 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2783 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2784 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2785 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2786 m68k_check_cond C
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2787 if istrue
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2788
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2789 sext 32 prefetch offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2790 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2791 pc -= 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2792 cycles 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2793 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2794 cycles 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2795 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2796 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2797
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2798 0110CCCCDDDDDDDD bcc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2799 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2800 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2801 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2802 m68k_check_cond C
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2803 if istrue
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2804 sext 16 D offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2805 sext 32 offset offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2806
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2807 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2808
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2809 cycles 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2810 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2811 cycles 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2812 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2813 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2814
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2815 0101CCCC11001RRR dbcc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2816 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2817 local tmp 16
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2818 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2819 m68k_check_cond C
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2820 if istrue
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2821 cycles 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2822 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2823 dregs.R:1 -= 1
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2824 tmp = dregs.R
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2825 if tmp = 65535
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2826 cycles 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2827 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2828 sext 32 prefetch offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2829 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2830 pc -= 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2831 cycles 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2832 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2833 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2834 m68k_prefetch
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2835
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2836 1110CCC0ZZ011RRR rori
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2837 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2838 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2839 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2840 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2841 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2842 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2843 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2844 ror dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2845 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2846 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2847 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2848 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2849 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2850 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2851 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2852 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2853 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2854 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2855 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2856 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2857
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2858 1110CCC0ZZ111RRR ror_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2859 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2860 local shift 8
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2861 shift = dregs.C & 63
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2862 ror dregs.R shift dregs.R Z
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2863 update_flags NZV0C
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2864 shift += shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2865 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2866 case 2
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2867 shift += 4
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2868 default
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2869 shift += 2
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2870 end
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2871 cycles shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2872 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2873 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2874
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2875 1110011011MMMRRR ror_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2876 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2877 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2878 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2879 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2880 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2881 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2882 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2883 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2884
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2885 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2886 ror dst 1 dst 1
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2887 update_flags NZV0C
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2888 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2889 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2890
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2891 1110CCC1ZZ011RRR roli
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2892 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2893 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2894 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2895 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2896 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2897 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2898 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2899 rol dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2900 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2901 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2902 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2903 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2904 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2905 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2906 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2907 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2908 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2909 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2910 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2911 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2912
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2913 1110CCC1ZZ111RRR rol_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2914 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2915 local shift 8
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2916 shift = dregs.C & 63
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2917 rol dregs.R shift dregs.R Z
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2918 update_flags NZV0C
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2919 shift += shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2920 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2921 case 2
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2922 shift += 4
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2923 default
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2924 shift += 2
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2925 end
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
2926 cycles shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2927 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2928 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2929
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2930 1110011111MMMRRR rol_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2931 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2932 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2933 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2934 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2935 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2936 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2937 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2938 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2939
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2940 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2941 rol dst 1 dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2942 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2943 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2944 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2945
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2946 1110CCC0ZZ010RRR roxri
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2947 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2948 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2949 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2950 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2951 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2952 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2953 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2954 rrc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2955 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2956 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2957 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2958 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2959 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2960 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2961 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2962 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2963 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2964 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2965 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2966 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2967
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2968 1110CCC0ZZ110RRR roxr_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2969 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2970 local shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2971 local cycle_shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2972 cycle_shift = dregs.C & 63
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2973 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2974 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2975 if cycle_shift = 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2976 rrc dregs.R 31 dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2977 rrc dregs.R 1 dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2978 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2979 else
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2980 shift = dregs.C & 31
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2981 rrc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2982 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2983 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2984 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2985 shift = dregs.C & 31
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2986 rrc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2987 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2988 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2989 cycle_shift += cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2990 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2991 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2992 cycle_shift += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2993 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2994 cycle_shift += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2995 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2996 cycles cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2997 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2998 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
2999
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3000 1110010011MMMRRR roxr_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3001 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3002 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3003 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3004 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3005 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3006 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3007 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3008 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3009
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3010 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3011 rrc dst 1 dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3012 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3013 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3014 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3015
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3016 1110CCC1ZZ010RRR roxli
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3017 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3018 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3019 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3020 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3021 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3022 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3023 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3024 rlc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3025 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3026 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3027 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3028 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3029 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3030 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3031 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3032 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3033 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3034 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3035 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3036 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3037
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3038 1110CCC1ZZ110RRR roxl_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3039 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3040 local shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3041 local cycle_shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3042 cycle_shift = dregs.C & 63
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3043 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3044 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3045 if cycle_shift = 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3046 rrc dregs.R 31 dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3047 rlc dregs.R 1 dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3048 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3049 else
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3050 shift = dregs.C & 31
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3051 rlc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3052 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3053 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3054 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3055 shift = dregs.C & 31
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3056 rlc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3057 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3058 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3059 cycle_shift += cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3060 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3061 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3062 cycle_shift += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3063 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3064 cycle_shift += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3065 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3066 cycles cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3067 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3068 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3069
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3070 1110010111MMMRRR roxl_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3071 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3072 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3073 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3074 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3075 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3076 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3077 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3078 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3079
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3080 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3081 rlc dst 1 dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3082 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3083 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3084 m68k_prefetch