Mercurial > repos > blastem
annotate z80_to_x86.c @ 380:1c8d74f2ab0b
Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run.
author | Mike Pavone <pavone@retrodev.com> |
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date | Mon, 03 Jun 2013 21:43:38 -0700 |
parents | 91d28a868551 |
children | 5500d1d1269e |
rev | line source |
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1 #include "z80inst.h" |
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2 #include "z80_to_x86.h" |
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3 #include "gen_x86.h" |
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4 #include "mem.h" |
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5 #include <stdio.h> |
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6 #include <stdlib.h> |
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7 #include <stddef.h> |
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8 #include <string.h> |
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9 |
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10 #define MODE_UNUSED (MODE_IMMED-1) |
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11 |
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12 #define ZCYCLES RBP |
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13 #define ZLIMIT RDI |
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14 #define SCRATCH1 R13 |
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15 #define SCRATCH2 R14 |
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16 #define CONTEXT RSI |
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17 |
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18 //#define DO_DEBUG_PRINT |
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19 |
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20 #ifdef DO_DEBUG_PRINT |
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21 #define dprintf printf |
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22 #else |
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23 #define dprintf |
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24 #endif |
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25 |
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26 void z80_read_byte(); |
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27 void z80_read_word(); |
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28 void z80_write_byte(); |
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29 void z80_write_word_highfirst(); |
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30 void z80_write_word_lowfirst(); |
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31 void z80_save_context(); |
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32 void z80_native_addr(); |
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33 void z80_do_sync(); |
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34 void z80_handle_cycle_limit_int(); |
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35 void z80_retrans_stub(); |
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36 void z80_io_read(); |
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37 void z80_io_write(); |
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38 void z80_halt(); |
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39 void z80_save_context(); |
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40 void z80_load_context(); |
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41 |
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42 uint8_t z80_size(z80inst * inst) |
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43 { |
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44 uint8_t reg = (inst->reg & 0x1F); |
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45 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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46 return reg < Z80_BC ? SZ_B : SZ_W; |
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47 } |
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48 //TODO: Handle any necessary special cases |
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49 return SZ_B; |
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50 } |
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51 |
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52 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles) |
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53 { |
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54 return add_ir(dst, num_cycles, ZCYCLES, SZ_D); |
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55 } |
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56 |
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57 uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address) |
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58 { |
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59 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
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60 uint8_t * jmp_off = dst+1; |
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61 dst = jcc(dst, CC_NC, dst + 7); |
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62 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
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63 dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int); |
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64 *jmp_off = dst - (jmp_off+1); |
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65 return dst; |
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66 } |
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67 |
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68 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts) |
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69 { |
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70 if (inst->reg == Z80_USE_IMMED) { |
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71 ea->mode = MODE_IMMED; |
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72 ea->disp = inst->immed; |
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73 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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74 ea->mode = MODE_UNUSED; |
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75 } else { |
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76 ea->mode = MODE_REG_DIRECT; |
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77 if (inst->reg == Z80_IYH) { |
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78 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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79 dst = mov_rr(dst, opts->regs[Z80_IY], SCRATCH1, SZ_W); |
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80 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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81 ea->base = SCRATCH1; |
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82 } else { |
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83 ea->base = opts->regs[Z80_IYL]; |
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84 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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85 } |
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86 } else if(opts->regs[inst->reg] >= 0) { |
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87 ea->base = opts->regs[inst->reg]; |
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88 if (ea->base >= AH && ea->base <= BH) { |
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89 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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90 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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91 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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92 //we can't mix an *H reg with a register that requires the REX prefix |
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93 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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94 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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95 } |
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96 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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97 //temp regs require REX prefix too |
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98 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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99 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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100 } |
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101 } |
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102 } else { |
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103 ea->mode = MODE_REG_DISPLACE8; |
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104 ea->base = CONTEXT; |
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105 ea->disp = offsetof(z80_context, regs) + inst->reg; |
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106 } |
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107 } |
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108 return dst; |
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109 } |
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110 |
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111 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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112 { |
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113 if (inst->reg == Z80_IYH) { |
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114 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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115 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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116 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_IYL], SZ_B); |
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117 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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118 } else { |
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119 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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120 } |
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121 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) { |
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122 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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123 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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124 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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125 //we can't mix an *H reg with a register that requires the REX prefix |
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126 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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127 } |
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128 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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129 //temp regs require REX prefix too |
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130 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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131 } |
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132 } |
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133 return dst; |
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134 } |
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135 |
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136 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify) |
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137 { |
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138 uint8_t size, reg, areg; |
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139 ea->mode = MODE_REG_DIRECT; |
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140 areg = read ? SCRATCH1 : SCRATCH2; |
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141 switch(inst->addr_mode & 0x1F) |
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142 { |
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143 case Z80_REG: |
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144 if (inst->ea_reg == Z80_IYH) { |
312
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145 if (inst->reg == Z80_IYL) { |
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146 dst = mov_rr(dst, opts->regs[Z80_IY], SCRATCH1, SZ_W); |
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147 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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148 ea->base = SCRATCH1; |
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149 } else { |
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150 ea->base = opts->regs[Z80_IYL]; |
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151 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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152 } |
213
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153 } else { |
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154 ea->base = opts->regs[inst->ea_reg]; |
267
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155 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) { |
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156 uint8_t other_reg = opts->regs[inst->reg]; |
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157 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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158 //we can't mix an *H reg with a register that requires the REX prefix |
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159 ea->base = opts->regs[z80_low_reg(inst->ea_reg)]; |
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160 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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161 } |
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162 } |
213
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163 } |
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164 break; |
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165 case Z80_REG_INDIRECT: |
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166 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W); |
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167 size = z80_size(inst); |
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168 if (read) { |
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169 if (modify) { |
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170 //dst = push_r(dst, SCRATCH1); |
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171 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(z80_context, scratch1), SZ_W); |
213
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172 } |
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173 if (size == SZ_B) { |
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174 dst = call(dst, (uint8_t *)z80_read_byte); |
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175 } else { |
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176 dst = call(dst, (uint8_t *)z80_read_word); |
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177 } |
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178 if (modify) { |
277
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179 //dst = pop_r(dst, SCRATCH2); |
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180 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, scratch1), SCRATCH2, SZ_W); |
213
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181 } |
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182 } |
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183 ea->base = SCRATCH1; |
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184 break; |
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185 case Z80_IMMED: |
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186 ea->mode = MODE_IMMED; |
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187 ea->disp = inst->immed; |
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188 break; |
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189 case Z80_IMMED_INDIRECT: |
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190 dst = mov_ir(dst, inst->immed, areg, SZ_W); |
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191 size = z80_size(inst); |
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192 if (read) { |
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193 /*if (modify) { |
213
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194 dst = push_r(dst, SCRATCH1); |
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195 }*/ |
213
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196 if (size == SZ_B) { |
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197 dst = call(dst, (uint8_t *)z80_read_byte); |
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198 } else { |
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199 dst = call(dst, (uint8_t *)z80_read_word); |
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200 } |
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201 if (modify) { |
277
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202 //dst = pop_r(dst, SCRATCH2); |
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203 dst = mov_ir(dst, inst->immed, SCRATCH2, SZ_W); |
213
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204 } |
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205 } |
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206 ea->base = SCRATCH1; |
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207 break; |
235
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208 case Z80_IX_DISPLACE: |
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209 case Z80_IY_DISPLACE: |
300
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210 reg = opts->regs[(inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
213
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211 dst = mov_rr(dst, reg, areg, SZ_W); |
306
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212 dst = add_ir(dst, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W); |
213
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213 size = z80_size(inst); |
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214 if (read) { |
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215 if (modify) { |
277
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216 //dst = push_r(dst, SCRATCH1); |
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217 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(z80_context, scratch1), SZ_W); |
213
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218 } |
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219 if (size == SZ_B) { |
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220 dst = call(dst, (uint8_t *)z80_read_byte); |
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221 } else { |
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222 dst = call(dst, (uint8_t *)z80_read_word); |
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223 } |
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224 if (modify) { |
277
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225 //dst = pop_r(dst, SCRATCH2); |
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226 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, scratch1), SCRATCH2, SZ_W); |
213
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227 } |
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228 } |
269
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229 ea->base = SCRATCH1; |
213
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230 break; |
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231 case Z80_UNUSED: |
235
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232 ea->mode = MODE_UNUSED; |
213
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233 break; |
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234 default: |
300
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235 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F); |
213
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236 exit(1); |
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237 } |
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238 return dst; |
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239 } |
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240 |
235
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241 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
213
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242 { |
267
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243 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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244 if (inst->ea_reg == Z80_IYH) { |
312
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311
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245 if (inst->reg == Z80_IYL) { |
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246 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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247 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_IYL], SZ_B); |
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248 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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249 } else { |
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250 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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251 } |
267
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252 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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253 uint8_t other_reg = opts->regs[inst->reg]; |
269
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254 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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255 //we can't mix an *H reg with a register that requires the REX prefix |
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256 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W); |
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257 } |
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258 } |
213
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259 } |
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260 return dst; |
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261 } |
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262 |
235
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263 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst) |
213
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264 { |
253
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265 switch(inst->addr_mode & 0x1f) |
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266 { |
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267 case Z80_REG_INDIRECT: |
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268 case Z80_IMMED_INDIRECT: |
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269 case Z80_IX_DISPLACE: |
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270 case Z80_IY_DISPLACE: |
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271 if (z80_size(inst) == SZ_B) { |
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272 dst = call(dst, (uint8_t *)z80_write_byte); |
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273 } else { |
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274 dst = call(dst, (uint8_t *)z80_write_word_lowfirst); |
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275 } |
213
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276 } |
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277 return dst; |
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278 } |
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279 |
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|
280 enum { |
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281 DONT_READ=0, |
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282 READ |
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|
283 }; |
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284 |
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|
285 enum { |
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286 DONT_MODIFY=0, |
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|
287 MODIFY |
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288 }; |
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289 |
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|
290 uint8_t zf_off(uint8_t flag) |
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291 { |
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292 return offsetof(z80_context, flags) + flag; |
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293 } |
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|
294 |
241
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295 uint8_t zaf_off(uint8_t flag) |
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296 { |
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297 return offsetof(z80_context, alt_flags) + flag; |
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298 } |
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299 |
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300 uint8_t zar_off(uint8_t reg) |
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301 { |
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302 return offsetof(z80_context, alt_regs) + reg; |
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303 } |
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304 |
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305 void z80_print_regs_exit(z80_context * context) |
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306 { |
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307 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
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308 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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309 context->regs[Z80_D], context->regs[Z80_E], |
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310 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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311 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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312 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
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313 context->sp, context->im, context->iff1, context->iff2); |
241
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314 puts("--Alternate Regs--"); |
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315 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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316 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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317 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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318 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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319 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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320 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
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321 exit(0); |
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322 } |
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323 |
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324 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address) |
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325 { |
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326 uint32_t cycles; |
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327 x86_ea src_op, dst_op; |
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328 uint8_t size; |
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329 x86_z80_options *opts = context->options; |
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330 uint8_t * start = dst; |
250
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331 dst = z80_check_cycles_int(dst, address); |
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332 switch(inst->op) |
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333 { |
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334 case Z80_LD: |
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335 size = z80_size(inst); |
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336 switch (inst->addr_mode & 0x1F) |
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337 { |
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338 case Z80_REG: |
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339 case Z80_REG_INDIRECT: |
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340 cycles = size == SZ_B ? 4 : 6; |
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341 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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342 cycles += 4; |
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343 } |
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344 break; |
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345 case Z80_IMMED: |
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346 cycles = size == SZ_B ? 7 : 10; |
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347 break; |
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348 case Z80_IMMED_INDIRECT: |
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349 cycles = 10; |
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350 break; |
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351 case Z80_IX_DISPLACE: |
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352 case Z80_IY_DISPLACE: |
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353 cycles = 12; |
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354 break; |
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355 } |
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356 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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357 cycles += 4; |
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358 } |
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359 dst = zcycles(dst, cycles); |
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360 if (inst->addr_mode & Z80_DIR) { |
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361 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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362 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY); |
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363 } else { |
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364 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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365 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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366 } |
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367 if (src_op.mode == MODE_REG_DIRECT) { |
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368 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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369 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
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370 } else { |
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371 dst = mov_rr(dst, src_op.base, dst_op.base, size); |
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372 } |
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373 } else if(src_op.mode == MODE_IMMED) { |
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374 dst = mov_ir(dst, src_op.disp, dst_op.base, size); |
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375 } else { |
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376 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
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377 } |
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378 dst = z80_save_reg(dst, inst, opts); |
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379 dst = z80_save_ea(dst, inst, opts); |
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380 if (inst->addr_mode & Z80_DIR) { |
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381 dst = z80_save_result(dst, inst); |
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382 } |
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383 break; |
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384 case Z80_PUSH: |
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385 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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386 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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387 if (inst->reg == Z80_AF) { |
363 | 388 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
389 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); | |
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390 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH1, SZ_B); |
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391 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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392 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH1, SZ_B); |
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393 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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394 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH1, SZ_B); |
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395 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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396 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH1, SZ_B); |
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397 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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398 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH1, SZ_B); |
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399 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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400 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH1, SZ_B); |
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401 } else { |
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402 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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403 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
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404 } |
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405 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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406 dst = call(dst, (uint8_t *)z80_write_word_highfirst); |
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407 //no call to save_z80_reg needed since there's no chance we'll use the only |
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408 //the upper half of a register pair |
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409 break; |
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410 case Z80_POP: |
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411 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
235
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412 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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413 dst = call(dst, (uint8_t *)z80_read_word); |
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414 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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415 if (inst->reg == Z80_AF) { |
294 | 416 |
417 dst = bt_ir(dst, 0, SCRATCH1, SZ_W); | |
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418 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
294 | 419 dst = bt_ir(dst, 1, SCRATCH1, SZ_W); |
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420 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N)); |
294 | 421 dst = bt_ir(dst, 2, SCRATCH1, SZ_W); |
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422 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV)); |
294 | 423 dst = bt_ir(dst, 4, SCRATCH1, SZ_W); |
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424 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H)); |
294 | 425 dst = bt_ir(dst, 6, SCRATCH1, SZ_W); |
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426 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
294 | 427 dst = bt_ir(dst, 7, SCRATCH1, SZ_W); |
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428 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S)); |
294 | 429 dst = shr_ir(dst, 8, SCRATCH1, SZ_W); |
430 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); | |
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431 } else { |
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432 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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433 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W); |
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434 } |
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435 //no call to save_z80_reg needed since there's no chance we'll use the only |
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436 //the upper half of a register pair |
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437 break; |
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438 case Z80_EX: |
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439 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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440 cycles = 4; |
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441 } else { |
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442 cycles = 8; |
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443 } |
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444 dst = zcycles(dst, cycles); |
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445 if (inst->addr_mode == Z80_REG) { |
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446 if(inst->reg == Z80_AF) { |
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447 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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448 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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449 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B); |
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450 |
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451 //Flags are currently word aligned, so we can move |
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452 //them efficiently a word at a time |
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453 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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454 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W); |
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455 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W); |
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456 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W); |
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457 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zf_off(f), SZ_W); |
241
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458 } |
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459 } else { |
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460 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
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461 } |
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462 } else { |
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463 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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464 dst = call(dst, (uint8_t *)z80_read_byte); |
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465 dst = xchg_rr(dst, opts->regs[inst->reg], SCRATCH1, SZ_B); |
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466 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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467 dst = call(dst, (uint8_t *)z80_write_byte); |
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468 dst = zcycles(dst, 1); |
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469 uint8_t high_reg = z80_high_reg(inst->reg); |
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470 uint8_t use_reg; |
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471 //even though some of the upper halves can be used directly |
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472 //the limitations on mixing *H regs with the REX prefix |
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473 //prevent us from taking advantage of it |
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474 use_reg = opts->regs[inst->reg]; |
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475 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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476 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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477 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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478 dst = call(dst, (uint8_t *)z80_read_byte); |
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479 dst = xchg_rr(dst, use_reg, SCRATCH1, SZ_B); |
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480 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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481 dst = add_ir(dst, 1, SCRATCH2, SZ_W); |
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482 dst = call(dst, (uint8_t *)z80_write_byte); |
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483 //restore reg to normal rotation |
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484 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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485 dst = zcycles(dst, 2); |
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486 } |
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487 break; |
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488 case Z80_EXX: |
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489 dst = zcycles(dst, 4); |
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490 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W); |
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491 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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492 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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493 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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494 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W); |
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495 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W); |
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496 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W); |
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497 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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498 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W); |
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499 break; |
272 | 500 case Z80_LDI: { |
501 dst = zcycles(dst, 8); | |
502 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
503 dst = call(dst, (uint8_t *)z80_read_byte); | |
504 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
505 dst = call(dst, (uint8_t *)z80_read_byte); | |
506 dst = zcycles(dst, 2); | |
507 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
508 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
509 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
510 //TODO: Implement half-carry | |
511 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
512 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
513 break; | |
514 } | |
261
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515 case Z80_LDIR: { |
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516 dst = zcycles(dst, 8); |
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517 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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518 dst = call(dst, (uint8_t *)z80_read_byte); |
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519 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); |
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520 dst = call(dst, (uint8_t *)z80_read_byte); |
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521 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); |
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522 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); |
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523 |
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524 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); |
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525 uint8_t * cont = dst+1; |
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526 dst = jcc(dst, CC_Z, dst+2); |
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527 dst = zcycles(dst, 7); |
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528 //TODO: Figure out what the flag state should be here |
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529 //TODO: Figure out whether an interrupt can interrupt this |
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530 dst = jmp(dst, start); |
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531 *cont = dst - (cont + 1); |
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532 dst = zcycles(dst, 2); |
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533 //TODO: Implement half-carry |
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534 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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535 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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536 break; |
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537 } |
273 | 538 case Z80_LDD: { |
539 dst = zcycles(dst, 8); | |
540 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
541 dst = call(dst, (uint8_t *)z80_read_byte); | |
542 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
543 dst = call(dst, (uint8_t *)z80_read_byte); | |
544 dst = zcycles(dst, 2); | |
545 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
546 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
547 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
548 //TODO: Implement half-carry | |
549 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
550 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
551 break; | |
552 } | |
553 case Z80_LDDR: { | |
554 dst = zcycles(dst, 8); | |
555 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
556 dst = call(dst, (uint8_t *)z80_read_byte); | |
557 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
558 dst = call(dst, (uint8_t *)z80_read_byte); | |
559 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
560 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
561 | |
562 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
563 uint8_t * cont = dst+1; | |
564 dst = jcc(dst, CC_Z, dst+2); | |
565 dst = zcycles(dst, 7); | |
566 //TODO: Figure out what the flag state should be here | |
567 //TODO: Figure out whether an interrupt can interrupt this | |
568 dst = jmp(dst, start); | |
569 *cont = dst - (cont + 1); | |
570 dst = zcycles(dst, 2); | |
571 //TODO: Implement half-carry | |
572 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
573 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); | |
574 break; | |
575 } | |
576 /*case Z80_CPI: | |
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577 case Z80_CPIR: |
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578 case Z80_CPD: |
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579 case Z80_CPDR: |
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580 break;*/ |
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581 case Z80_ADD: |
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582 cycles = 4; |
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583 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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584 cycles += 12; |
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585 } else if(inst->addr_mode == Z80_IMMED) { |
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586 cycles += 3; |
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587 } else if(z80_size(inst) == SZ_W) { |
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588 cycles += 4; |
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589 } |
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590 dst = zcycles(dst, cycles); |
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591 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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592 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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593 if (src_op.mode == MODE_REG_DIRECT) { |
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594 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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595 } else { |
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596 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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597 } |
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598 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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599 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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600 //TODO: Implement half-carry flag |
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601 if (z80_size(inst) == SZ_B) { |
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602 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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603 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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604 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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605 } |
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606 dst = z80_save_reg(dst, inst, opts); |
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607 dst = z80_save_ea(dst, inst, opts); |
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608 break; |
248
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609 case Z80_ADC: |
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610 cycles = 4; |
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611 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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612 cycles += 12; |
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613 } else if(inst->addr_mode == Z80_IMMED) { |
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614 cycles += 3; |
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615 } else if(z80_size(inst) == SZ_W) { |
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616 cycles += 4; |
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617 } |
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618 dst = zcycles(dst, cycles); |
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619 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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620 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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621 if (src_op.mode == MODE_REG_DIRECT) { |
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622 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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623 } else { |
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624 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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625 } |
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626 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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627 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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628 //TODO: Implement half-carry flag |
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629 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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630 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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631 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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632 dst = z80_save_reg(dst, inst, opts); |
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633 dst = z80_save_ea(dst, inst, opts); |
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634 break; |
213
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635 case Z80_SUB: |
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636 cycles = 4; |
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637 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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638 cycles += 12; |
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639 } else if(inst->addr_mode == Z80_IMMED) { |
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640 cycles += 3; |
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641 } |
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642 dst = zcycles(dst, cycles); |
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643 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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644 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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645 if (src_op.mode == MODE_REG_DIRECT) { |
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646 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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parents:
diff
changeset
|
647 } else { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
648 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
649 } |
4d4559b04c59
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parents:
diff
changeset
|
650 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
235
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651 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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diff
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652 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
213
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diff
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|
653 //TODO: Implement half-carry flag |
235
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213
diff
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654 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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655 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
4d4559b04c59
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parents:
diff
changeset
|
656 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
changeset
|
657 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
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|
658 break; |
248
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659 case Z80_SBC: |
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660 cycles = 4; |
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661 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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662 cycles += 12; |
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663 } else if(inst->addr_mode == Z80_IMMED) { |
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664 cycles += 3; |
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665 } else if(z80_size(inst) == SZ_W) { |
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666 cycles += 4; |
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667 } |
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668 dst = zcycles(dst, cycles); |
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669 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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670 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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671 if (src_op.mode == MODE_REG_DIRECT) { |
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672 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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673 } else { |
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674 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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675 } |
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676 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
309
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677 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
248
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|
678 //TODO: Implement half-carry flag |
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679 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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680 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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681 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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682 dst = z80_save_reg(dst, inst, opts); |
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683 dst = z80_save_ea(dst, inst, opts); |
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684 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
685 case Z80_AND: |
236
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235
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686 cycles = 4; |
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687 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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688 cycles += 12; |
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689 } else if(inst->addr_mode == Z80_IMMED) { |
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690 cycles += 3; |
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691 } else if(z80_size(inst) == SZ_W) { |
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692 cycles += 4; |
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693 } |
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694 dst = zcycles(dst, cycles); |
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695 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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696 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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697 if (src_op.mode == MODE_REG_DIRECT) { |
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698 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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699 } else { |
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diff
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|
700 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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|
701 } |
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|
702 //TODO: Cleanup flags |
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diff
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|
703 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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|
704 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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235
diff
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|
705 //TODO: Implement half-carry flag |
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235
diff
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|
706 if (z80_size(inst) == SZ_B) { |
305
a57fac5b3d65
Contrary to the official documenation, OR and AND also set PV based on parity instead of overflow
Mike Pavone <pavone@retrodev.com>
parents:
304
diff
changeset
|
707 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
236
19fb3523a9e5
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parents:
235
diff
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|
708 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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235
diff
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|
709 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
19fb3523a9e5
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235
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|
710 } |
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235
diff
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|
711 dst = z80_save_reg(dst, inst, opts); |
19fb3523a9e5
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235
diff
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|
712 dst = z80_save_ea(dst, inst, opts); |
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parents:
235
diff
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|
713 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
714 case Z80_OR: |
236
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235
diff
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|
715 cycles = 4; |
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235
diff
changeset
|
716 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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235
diff
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|
717 cycles += 12; |
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235
diff
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|
718 } else if(inst->addr_mode == Z80_IMMED) { |
19fb3523a9e5
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parents:
235
diff
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|
719 cycles += 3; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
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|
720 } else if(z80_size(inst) == SZ_W) { |
19fb3523a9e5
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235
diff
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|
721 cycles += 4; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
722 } |
19fb3523a9e5
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235
diff
changeset
|
723 dst = zcycles(dst, cycles); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
724 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
725 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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235
diff
changeset
|
726 if (src_op.mode == MODE_REG_DIRECT) { |
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235
diff
changeset
|
727 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
19fb3523a9e5
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parents:
235
diff
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|
728 } else { |
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parents:
235
diff
changeset
|
729 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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235
diff
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|
730 } |
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235
diff
changeset
|
731 //TODO: Cleanup flags |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
732 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
733 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
734 //TODO: Implement half-carry flag |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
735 if (z80_size(inst) == SZ_B) { |
305
a57fac5b3d65
Contrary to the official documenation, OR and AND also set PV based on parity instead of overflow
Mike Pavone <pavone@retrodev.com>
parents:
304
diff
changeset
|
736 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
236
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
737 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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235
diff
changeset
|
738 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
739 } |
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235
diff
changeset
|
740 dst = z80_save_reg(dst, inst, opts); |
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235
diff
changeset
|
741 dst = z80_save_ea(dst, inst, opts); |
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parents:
235
diff
changeset
|
742 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
743 case Z80_XOR: |
236
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parents:
235
diff
changeset
|
744 cycles = 4; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
745 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
19fb3523a9e5
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parents:
235
diff
changeset
|
746 cycles += 12; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
747 } else if(inst->addr_mode == Z80_IMMED) { |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
748 cycles += 3; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
749 } else if(z80_size(inst) == SZ_W) { |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
750 cycles += 4; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
751 } |
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752 dst = zcycles(dst, cycles); |
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753 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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754 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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755 if (src_op.mode == MODE_REG_DIRECT) { |
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756 dst = xor_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
236
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757 } else { |
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758 dst = xor_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
236
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759 } |
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760 //TODO: Cleanup flags |
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761 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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762 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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763 //TODO: Implement half-carry flag |
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764 if (z80_size(inst) == SZ_B) { |
304
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303
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765 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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766 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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767 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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768 } |
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769 dst = z80_save_reg(dst, inst, opts); |
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770 dst = z80_save_ea(dst, inst, opts); |
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771 break; |
242 | 772 case Z80_CP: |
773 cycles = 4; | |
774 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { | |
775 cycles += 12; | |
776 } else if(inst->addr_mode == Z80_IMMED) { | |
777 cycles += 3; | |
778 } | |
779 dst = zcycles(dst, cycles); | |
780 dst = translate_z80_reg(inst, &dst_op, dst, opts); | |
781 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); | |
782 if (src_op.mode == MODE_REG_DIRECT) { | |
783 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst)); | |
784 } else { | |
785 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); | |
786 } | |
787 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); | |
788 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); | |
789 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); | |
790 //TODO: Implement half-carry flag | |
791 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); | |
792 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); | |
793 dst = z80_save_reg(dst, inst, opts); | |
794 dst = z80_save_ea(dst, inst, opts); | |
795 break; | |
213
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796 case Z80_INC: |
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797 cycles = 4; |
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798 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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|
799 cycles += 6; |
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800 } else if(z80_size(inst) == SZ_W) { |
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changeset
|
801 cycles += 2; |
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802 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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|
803 cycles += 4; |
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804 } |
373
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805 dst = zcycles(dst, cycles); |
213
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|
806 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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807 if (dst_op.mode == MODE_UNUSED) { |
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808 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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809 } |
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810 dst = add_ir(dst, 1, dst_op.base, z80_size(inst)); |
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811 if (z80_size(inst) == SZ_B) { |
235
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812 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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813 //TODO: Implement half-carry flag |
235
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814 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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815 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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816 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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817 } |
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818 dst = z80_save_reg(dst, inst, opts); |
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|
819 dst = z80_save_ea(dst, inst, opts); |
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820 break; |
236
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821 case Z80_DEC: |
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822 cycles = 4; |
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823 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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824 cycles += 6; |
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825 } else if(z80_size(inst) == SZ_W) { |
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826 cycles += 2; |
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827 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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828 cycles += 4; |
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829 } |
373
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830 dst = zcycles(dst, cycles); |
236
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831 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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832 if (dst_op.mode == MODE_UNUSED) { |
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833 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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834 } |
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835 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst)); |
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836 if (z80_size(inst) == SZ_B) { |
311
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310
diff
changeset
|
837 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
236
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838 //TODO: Implement half-carry flag |
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839 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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840 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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841 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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842 } |
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843 dst = z80_save_reg(dst, inst, opts); |
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844 dst = z80_save_ea(dst, inst, opts); |
213
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|
845 break; |
274
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|
846 //case Z80_DAA: |
213
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|
847 case Z80_CPL: |
274
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848 dst = zcycles(dst, 4); |
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|
849 dst = not_r(dst, opts->regs[Z80_A], SZ_B); |
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850 //TODO: Implement half-carry flag |
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851 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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852 break; |
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853 case Z80_NEG: |
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854 dst = zcycles(dst, 8); |
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855 dst = neg_r(dst, opts->regs[Z80_A], SZ_B); |
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856 //TODO: Implement half-carry flag |
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857 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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858 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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859 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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|
860 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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861 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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862 break; |
213
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|
863 case Z80_CCF: |
257 | 864 dst = zcycles(dst, 4); |
865 dst = xor_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
866 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
867 //TODO: Implement half-carry flag | |
868 break; | |
869 case Z80_SCF: | |
870 dst = zcycles(dst, 4); | |
871 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
872 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
873 //TODO: Implement half-carry flag | |
874 break; | |
213
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changeset
|
875 case Z80_NOP: |
4d4559b04c59
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changeset
|
876 if (inst->immed == 42) { |
4d4559b04c59
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changeset
|
877 dst = call(dst, (uint8_t *)z80_save_context); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 dst = jmp(dst, (uint8_t *)z80_print_regs_exit); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 } else { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 dst = zcycles(dst, 4 * inst->immed); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
882 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
883 break; |
285
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
884 case Z80_HALT: |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
885 dst = zcycles(dst, 4); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
886 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
887 uint8_t * call_inst = dst; |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
888 dst = call(dst, (uint8_t *)z80_halt); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
889 dst = jmp(dst, call_inst); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
890 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 case Z80_DI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
892 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
893 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
894 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
895 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
896 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 case Z80_EI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
898 //TODO: Implement interrupt enable latency of 1 instruction afer EI |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
899 dst = zcycles(dst, 4); |
335 | 900 dst = mov_rrdisp8(dst, ZCYCLES, CONTEXT, offsetof(z80_context, int_enable_cycle), SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
901 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
902 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
335 | 903 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles |
904 dst = add_irdisp8(dst, 4, CONTEXT, offsetof(z80_context, int_enable_cycle), SZ_D); | |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
905 dst = call(dst, (uint8_t *)z80_do_sync); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
906 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 case Z80_IM: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
908 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
909 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
910 break; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
911 case Z80_RLC: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
912 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
913 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
914 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
915 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
916 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
917 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
918 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
919 src_op.mode = MODE_UNUSED; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
920 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
921 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
922 dst = rol_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
923 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
924 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
925 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
926 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
927 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
928 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
929 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
930 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
931 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
932 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
933 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
934 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
935 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
936 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
937 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
938 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
939 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
940 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
941 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
942 case Z80_RL: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
943 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
944 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
945 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
946 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
947 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
948 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
949 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
950 src_op.mode = MODE_UNUSED; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
951 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
952 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
953 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
954 dst = rcl_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
955 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
956 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
957 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
958 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
959 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
960 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
961 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
962 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
963 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
964 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
965 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
966 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
967 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
968 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
969 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
970 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
971 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
972 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
973 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
974 case Z80_RRC: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
975 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
976 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
977 if (inst->addr_mode != Z80_UNUSED) { |
247
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
978 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
979 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
980 dst = zcycles(dst, 1); |
682e505f5757
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parents:
246
diff
changeset
|
981 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
982 src_op.mode = MODE_UNUSED; |
247
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
983 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
984 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
985 dst = ror_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
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Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
986 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
987 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
988 } |
247
682e505f5757
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parents:
246
diff
changeset
|
989 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
990 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
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parents:
246
diff
changeset
|
991 //TODO: Implement half-carry flag |
682e505f5757
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parents:
246
diff
changeset
|
992 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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parents:
246
diff
changeset
|
993 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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parents:
246
diff
changeset
|
994 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
995 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
996 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
997 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
998 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
999 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1000 } |
247
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1001 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1002 dst = z80_save_reg(dst, inst, opts); |
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1003 } |
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1004 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 case Z80_RR: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1006 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
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246
diff
changeset
|
1007 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1008 if (inst->addr_mode != Z80_UNUSED) { |
247
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parents:
246
diff
changeset
|
1009 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1010 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1011 dst = zcycles(dst, 1); |
682e505f5757
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parents:
246
diff
changeset
|
1012 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1013 src_op.mode = MODE_UNUSED; |
247
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parents:
246
diff
changeset
|
1014 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
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246
diff
changeset
|
1015 } |
682e505f5757
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246
diff
changeset
|
1016 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
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246
diff
changeset
|
1017 dst = rcr_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
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Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
1018 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1019 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1020 } |
247
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1021 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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246
diff
changeset
|
1022 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
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246
diff
changeset
|
1023 //TODO: Implement half-carry flag |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1024 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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parents:
246
diff
changeset
|
1025 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1026 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1027 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1028 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1029 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1030 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1031 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1032 } |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1033 } else { |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1034 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1035 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1036 break; |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1037 case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1038 case Z80_SLL: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1039 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1040 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1041 if (inst->addr_mode != Z80_UNUSED) { |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1042 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1043 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1044 dst = zcycles(dst, 1); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1045 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1046 src_op.mode = MODE_UNUSED; |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1047 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1048 } |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1049 dst = shl_ir(dst, 1, dst_op.base, SZ_B); |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1050 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1051 if (inst->op == Z80_SLL) { |
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1052 dst = or_ir(dst, 1, dst_op.base, SZ_B); |
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1053 } |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
1054 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1055 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1056 } |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1057 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1058 //TODO: Implement half-carry flag |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1059 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1060 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1061 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1062 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1063 if (inst->addr_mode != Z80_UNUSED) { |
275
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1064 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1065 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1066 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1067 } |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1068 } else { |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1069 dst = z80_save_reg(dst, inst, opts); |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1070 } |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1071 break; |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1072 case Z80_SRA: |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1073 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1074 dst = zcycles(dst, cycles); |
299
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parents:
295
diff
changeset
|
1075 if (inst->addr_mode != Z80_UNUSED) { |
275
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274
diff
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|
1076 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1077 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
275
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diff
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1078 dst = zcycles(dst, 1); |
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diff
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|
1079 } else { |
302
3b831fe32c15
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Mike Pavone <pavone@retrodev.com>
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301
diff
changeset
|
1080 src_op.mode = MODE_UNUSED; |
275
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274
diff
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1081 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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274
diff
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|
1082 } |
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diff
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1083 dst = sar_ir(dst, 1, dst_op.base, SZ_B); |
301
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300
diff
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|
1084 if (src_op.mode != MODE_UNUSED) { |
299
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parents:
295
diff
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|
1085 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
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parents:
295
diff
changeset
|
1086 } |
310
bf440db64086
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Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1087 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
275
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diff
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1088 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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diff
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|
1089 //TODO: Implement half-carry flag |
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274
diff
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|
1090 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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diff
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|
1091 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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diff
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1092 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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diff
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|
1093 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1094 if (inst->addr_mode != Z80_UNUSED) { |
275
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274
diff
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|
1095 dst = z80_save_result(dst, inst); |
299
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Mike Pavone <pavone@retrodev.com>
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295
diff
changeset
|
1096 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1097 dst = z80_save_reg(dst, inst, opts); |
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295
diff
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|
1098 } |
275
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274
diff
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|
1099 } else { |
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274
diff
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|
1100 dst = z80_save_reg(dst, inst, opts); |
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diff
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1101 } |
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diff
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1102 break; |
213
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1103 case Z80_SRL: |
275
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diff
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|
1104 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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diff
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|
1105 dst = zcycles(dst, cycles); |
299
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parents:
295
diff
changeset
|
1106 if (inst->addr_mode != Z80_UNUSED) { |
275
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274
diff
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|
1107 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
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|
1108 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
275
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diff
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|
1109 dst = zcycles(dst, 1); |
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diff
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|
1110 } else { |
302
3b831fe32c15
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301
diff
changeset
|
1111 src_op.mode = MODE_UNUSED; |
275
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diff
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|
1112 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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diff
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|
1113 } |
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diff
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|
1114 dst = shr_ir(dst, 1, dst_op.base, SZ_B); |
301
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300
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|
1115 if (src_op.mode != MODE_UNUSED) { |
299
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295
diff
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|
1116 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
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diff
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|
1117 } |
310
bf440db64086
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Mike Pavone <pavone@retrodev.com>
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309
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changeset
|
1118 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
275
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diff
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|
1119 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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274
diff
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|
1120 //TODO: Implement half-carry flag |
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diff
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|
1121 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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diff
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|
1122 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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diff
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1123 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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274
diff
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|
1124 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1125 if (inst->addr_mode != Z80_UNUSED) { |
275
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Mike Pavone <pavone@retrodev.com>
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274
diff
changeset
|
1126 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1127 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
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Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1128 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
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diff
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|
1129 } |
275
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diff
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|
1130 } else { |
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274
diff
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|
1131 dst = z80_save_reg(dst, inst, opts); |
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diff
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|
1132 } |
310
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Mike Pavone <pavone@retrodev.com>
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309
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|
1133 break; |
286 | 1134 case Z80_RLD: |
1135 dst = zcycles(dst, 8); | |
1136 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
1137 dst = call(dst, (uint8_t *)z80_read_byte); | |
1138 //Before: (HL) = 0x12, A = 0x34 | |
1139 //After: (HL) = 0x24, A = 0x31 | |
1140 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B); | |
1141 dst = shl_ir(dst, 4, SCRATCH1, SZ_W); | |
1142 dst = and_ir(dst, 0xF, SCRATCH2, SZ_W); | |
1143 dst = and_ir(dst, 0xFFF, SCRATCH1, SZ_W); | |
1144 dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B); | |
1145 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_W); | |
1146 //SCRATCH1 = 0x0124 | |
1147 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); | |
1148 dst = zcycles(dst, 4); | |
1149 dst = or_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); | |
287
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286
diff
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|
1150 //set flags |
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286
diff
changeset
|
1151 //TODO: Implement half-carry flag |
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diff
changeset
|
1152 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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|
1153 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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286
diff
changeset
|
1154 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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diff
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|
1155 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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286
diff
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|
1156 |
286 | 1157 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
1158 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); | |
1159 dst = call(dst, (uint8_t *)z80_write_byte); | |
1160 break; | |
287
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286
diff
changeset
|
1161 case Z80_RRD: |
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286
diff
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|
1162 dst = zcycles(dst, 8); |
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changeset
|
1163 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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|
1164 dst = call(dst, (uint8_t *)z80_read_byte); |
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286
diff
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|
1165 //Before: (HL) = 0x12, A = 0x34 |
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286
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|
1166 //After: (HL) = 0x41, A = 0x32 |
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|
1167 dst = movzx_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B, SZ_W); |
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1168 dst = ror_ir(dst, 4, SCRATCH1, SZ_W); |
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|
1169 dst = shl_ir(dst, 4, SCRATCH2, SZ_W); |
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|
1170 dst = and_ir(dst, 0xF00F, SCRATCH1, SZ_W); |
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|
1171 dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B); |
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|
1172 //SCRATCH1 = 0x2001 |
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|
1173 //SCRATCH2 = 0x0040 |
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|
1174 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_W); |
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|
1175 //SCRATCH1 = 0x2041 |
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|
1176 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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|
1177 dst = zcycles(dst, 4); |
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|
1178 dst = shr_ir(dst, 4, SCRATCH1, SZ_B); |
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|
1179 dst = or_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); |
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|
1180 //set flags |
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|
1181 //TODO: Implement half-carry flag |
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|
1182 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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|
1183 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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|
1184 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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|
1185 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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diff
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|
1186 |
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|
1187 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
fb840e0a48cd
Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1188 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
fb840e0a48cd
Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1189 dst = call(dst, (uint8_t *)z80_write_byte); |
fb840e0a48cd
Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1190 break; |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1191 case Z80_BIT: { |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1192 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1193 dst = zcycles(dst, cycles); |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1194 uint8_t bit; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1195 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1196 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1197 size = SZ_W; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1198 bit = inst->immed + 8; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1199 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1200 size = SZ_B; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1201 bit = inst->immed; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1202 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1203 } |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1204 if (inst->addr_mode != Z80_REG) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1205 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1206 dst = zcycles(dst, 1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1207 } |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1208 dst = bt_ir(dst, bit, src_op.base, size); |
303
8290d3086ff0
BIT was setting the zero flag to the opposite of what it should have. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents:
302
diff
changeset
|
1209 dst = setcc_rdisp8(dst, CC_NC, CONTEXT, zf_off(ZF_Z)); |
307
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1210 dst = setcc_rdisp8(dst, CC_NC, CONTEXT, zf_off(ZF_PV)); |
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1211 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1212 if (inst->immed == 7) { |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1213 dst = cmp_ir(dst, 0, src_op.base, size); |
307
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1214 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1215 } else { |
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1216 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1217 } |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1218 break; |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1219 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1220 case Z80_SET: { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1221 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1222 dst = zcycles(dst, cycles); |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1223 uint8_t bit; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1224 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1225 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1226 size = SZ_W; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1227 bit = inst->immed + 8; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1228 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1229 size = SZ_B; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1230 bit = inst->immed; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1231 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1232 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1233 if (inst->reg != Z80_USE_IMMED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1234 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1235 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1236 if (inst->addr_mode != Z80_REG) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1237 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1238 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1239 } |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1240 dst = bts_ir(dst, bit, src_op.base, size); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1241 if (inst->reg != Z80_USE_IMMED) { |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1242 if (size == SZ_W) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1243 if (dst_op.base >= R8) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1244 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1245 dst = mov_rr(dst, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1246 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1247 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1248 dst = mov_rr(dst, opts->regs[inst->ea_reg], dst_op.base, SZ_B); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1249 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1250 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1251 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_B); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1252 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1253 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1254 if ((inst->addr_mode & 0x1F) != Z80_REG) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1255 dst = z80_save_result(dst, inst); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1256 if (inst->reg != Z80_USE_IMMED) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1257 dst = z80_save_reg(dst, inst, opts); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1258 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1259 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1260 break; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1261 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1262 case Z80_RES: { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1263 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1264 dst = zcycles(dst, cycles); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1265 uint8_t bit; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1266 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1267 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1268 size = SZ_W; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1269 bit = inst->immed + 8; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1270 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1271 size = SZ_B; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1272 bit = inst->immed; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1273 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1274 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1275 if (inst->reg != Z80_USE_IMMED) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1276 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1277 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1278 if (inst->addr_mode != Z80_REG) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1279 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1280 dst = zcycles(dst, 1); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1281 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1282 dst = btr_ir(dst, bit, src_op.base, size); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1283 if (inst->reg != Z80_USE_IMMED) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1284 if (size == SZ_W) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1285 if (dst_op.base >= R8) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1286 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1287 dst = mov_rr(dst, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1288 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1289 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1290 dst = mov_rr(dst, opts->regs[inst->ea_reg], dst_op.base, SZ_B); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1291 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1292 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1293 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_B); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1294 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1295 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1296 if (inst->addr_mode != Z80_REG) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1297 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1298 if (inst->reg != Z80_USE_IMMED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1299 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1300 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1301 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1302 break; |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1303 } |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1304 case Z80_JP: { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1305 cycles = 4; |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1306 if (inst->addr_mode != Z80_REG) { |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1307 cycles += 6; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1308 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1309 cycles += 4; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1310 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1311 dst = zcycles(dst, cycles); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1312 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) { |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1313 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1314 if (!call_dst) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1315 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1316 //fake address to force large displacement |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1317 call_dst = dst + 256; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1318 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1319 dst = jmp(dst, call_dst); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1320 } else { |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1321 if (inst->addr_mode == Z80_REG_INDIRECT) { |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1322 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1323 } else { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1324 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1325 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1326 dst = call(dst, (uint8_t *)z80_native_addr); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1327 dst = jmp_r(dst, SCRATCH1); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1328 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1329 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1330 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1331 case Z80_JPCC: { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1332 dst = zcycles(dst, 7);//T States: 4,3 |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1333 uint8_t cond = CC_Z; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1334 switch (inst->reg) |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1335 { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1336 case Z80_CC_NZ: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1337 cond = CC_NZ; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1338 case Z80_CC_Z: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1339 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1340 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1341 case Z80_CC_NC: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1342 cond = CC_NZ; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1343 case Z80_CC_C: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1344 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1345 break; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1346 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1347 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1348 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1349 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1350 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1351 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1352 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1353 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1354 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1355 break; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1356 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1357 uint8_t *no_jump_off = dst+1; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1358 dst = jcc(dst, cond, dst+2); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1359 dst = zcycles(dst, 5);//T States: 5 |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1360 uint16_t dest_addr = inst->immed; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1361 if (dest_addr < 0x4000) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1362 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1363 if (!call_dst) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1364 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1365 //fake address to force large displacement |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1366 call_dst = dst + 256; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1367 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1368 dst = jmp(dst, call_dst); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1369 } else { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1370 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1371 dst = call(dst, (uint8_t *)z80_native_addr); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1372 dst = jmp_r(dst, SCRATCH1); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1373 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1374 *no_jump_off = dst - (no_jump_off+1); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1375 break; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1376 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1377 case Z80_JR: { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1378 dst = zcycles(dst, 12);//T States: 4,3,5 |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1379 uint16_t dest_addr = address + inst->immed + 2; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1380 if (dest_addr < 0x4000) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1381 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
19fb3523a9e5
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parents:
235
diff
changeset
|
1382 if (!call_dst) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1383 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1384 //fake address to force large displacement |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1385 call_dst = dst + 256; |
19fb3523a9e5
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parents:
235
diff
changeset
|
1386 } |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1387 dst = jmp(dst, call_dst); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1388 } else { |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1389 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
19fb3523a9e5
Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
1390 dst = call(dst, (uint8_t *)z80_native_addr); |
19fb3523a9e5
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parents:
235
diff
changeset
|
1391 dst = jmp_r(dst, SCRATCH1); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1392 } |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1393 break; |
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235
diff
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|
1394 } |
235
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1395 case Z80_JRCC: { |
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1396 dst = zcycles(dst, 7);//T States: 4,3 |
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diff
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|
1397 uint8_t cond = CC_Z; |
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213
diff
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|
1398 switch (inst->reg) |
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diff
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|
1399 { |
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|
1400 case Z80_CC_NZ: |
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diff
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|
1401 cond = CC_NZ; |
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diff
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|
1402 case Z80_CC_Z: |
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diff
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|
1403 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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|
1404 break; |
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diff
changeset
|
1405 case Z80_CC_NC: |
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diff
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|
1406 cond = CC_NZ; |
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Get Z80 core working for simple programs
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213
diff
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|
1407 case Z80_CC_C: |
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Get Z80 core working for simple programs
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diff
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|
1408 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1409 break; |
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213
diff
changeset
|
1410 } |
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Get Z80 core working for simple programs
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213
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changeset
|
1411 uint8_t *no_jump_off = dst+1; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1412 dst = jcc(dst, cond, dst+2); |
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Get Z80 core working for simple programs
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213
diff
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|
1413 dst = zcycles(dst, 5);//T States: 5 |
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Get Z80 core working for simple programs
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213
diff
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|
1414 uint16_t dest_addr = address + inst->immed + 2; |
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213
diff
changeset
|
1415 if (dest_addr < 0x4000) { |
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Get Z80 core working for simple programs
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213
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|
1416 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1417 if (!call_dst) { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1418 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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Get Z80 core working for simple programs
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213
diff
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|
1419 //fake address to force large displacement |
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Get Z80 core working for simple programs
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213
diff
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|
1420 call_dst = dst + 256; |
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213
diff
changeset
|
1421 } |
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213
diff
changeset
|
1422 dst = jmp(dst, call_dst); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1423 } else { |
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213
diff
changeset
|
1424 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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Get Z80 core working for simple programs
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213
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changeset
|
1425 dst = call(dst, (uint8_t *)z80_native_addr); |
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213
diff
changeset
|
1426 dst = jmp_r(dst, SCRATCH1); |
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213
diff
changeset
|
1427 } |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1428 *no_jump_off = dst - (no_jump_off+1); |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1429 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1430 } |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1431 case Z80_DJNZ: |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1432 dst = zcycles(dst, 8);//T States: 5,3 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1433 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1434 uint8_t *no_jump_off = dst+1; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1435 dst = jcc(dst, CC_Z, dst+2); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1436 dst = zcycles(dst, 5);//T States: 5 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1437 uint16_t dest_addr = address + inst->immed + 2; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1438 if (dest_addr < 0x4000) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1439 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1440 if (!call_dst) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1441 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1442 //fake address to force large displacement |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1443 call_dst = dst + 256; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1444 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1445 dst = jmp(dst, call_dst); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1446 } else { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1447 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1448 dst = call(dst, (uint8_t *)z80_native_addr); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1449 dst = jmp_r(dst, SCRATCH1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1450 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1451 *no_jump_off = dst - (no_jump_off+1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1452 break; |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1453 case Z80_CALL: { |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1454 dst = zcycles(dst, 11);//T States: 4,3,4 |
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Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
1455 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1456 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1457 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1458 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1459 if (inst->immed < 0x4000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
1460 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1461 if (!call_dst) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1462 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
1463 //fake address to force large displacement |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1464 call_dst = dst + 256; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1465 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1466 dst = jmp(dst, call_dst); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1467 } else { |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1468 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1469 dst = call(dst, (uint8_t *)z80_native_addr); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1470 dst = jmp_r(dst, SCRATCH1); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1471 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1472 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1473 } |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1474 case Z80_CALLCC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1475 dst = zcycles(dst, 10);//T States: 4,3,3 (false case) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1476 uint8_t cond = CC_Z; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1477 switch (inst->reg) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1478 { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1479 case Z80_CC_NZ: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1480 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1481 case Z80_CC_Z: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1482 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1483 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1484 case Z80_CC_NC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1485 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1486 case Z80_CC_C: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1487 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1488 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1489 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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parents:
236
diff
changeset
|
1490 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1491 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1492 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1493 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1494 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1495 cond = CC_NZ; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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parents:
236
diff
changeset
|
1496 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1497 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1498 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1499 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1500 uint8_t *no_call_off = dst+1; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1501 dst = jcc(dst, cond, dst+2); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1502 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1503 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1504 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1505 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1506 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1507 if (inst->immed < 0x4000) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1508 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1509 if (!call_dst) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1510 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1511 //fake address to force large displacement |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1512 call_dst = dst + 256; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1513 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1514 dst = jmp(dst, call_dst); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1515 } else { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1516 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1517 dst = call(dst, (uint8_t *)z80_native_addr); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1518 dst = jmp_r(dst, SCRATCH1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1519 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1520 *no_call_off = dst - (no_call_off+1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1521 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1522 case Z80_RET: |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1523 dst = zcycles(dst, 4);//T States: 4 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1524 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1525 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1526 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1527 dst = call(dst, (uint8_t *)z80_native_addr); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1528 dst = jmp_r(dst, SCRATCH1); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1529 break; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1530 case Z80_RETCC: { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1531 dst = zcycles(dst, 5);//T States: 5 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1532 uint8_t cond = CC_Z; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1533 switch (inst->reg) |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1534 { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1535 case Z80_CC_NZ: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1536 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1537 case Z80_CC_Z: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1538 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1539 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1540 case Z80_CC_NC: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1541 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1542 case Z80_CC_C: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1543 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1544 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1545 case Z80_CC_PO: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1546 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1547 case Z80_CC_PE: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1548 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1549 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1550 case Z80_CC_P: |
367
f20562f2a570
Fix P condition in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
366
diff
changeset
|
1551 cond = CC_NZ; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1552 case Z80_CC_M: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1553 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1554 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1555 } |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1556 uint8_t *no_call_off = dst+1; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1557 dst = jcc(dst, cond, dst+2); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1558 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1559 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1560 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1561 dst = call(dst, (uint8_t *)z80_native_addr); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1562 dst = jmp_r(dst, SCRATCH1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1563 *no_call_off = dst - (no_call_off+1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1564 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1565 } |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1566 case Z80_RETI: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1567 //For some systems, this may need a callback for signalling interrupt routine completion |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1568 dst = zcycles(dst, 8);//T States: 4, 4 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1569 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1570 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1571 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1572 dst = call(dst, (uint8_t *)z80_native_addr); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1573 dst = jmp_r(dst, SCRATCH1); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1574 break; |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1575 case Z80_RETN: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1576 dst = zcycles(dst, 8);//T States: 4, 4 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1577 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, iff2), SCRATCH2, SZ_B); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1578 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1579 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1580 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1581 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1582 dst = call(dst, (uint8_t *)z80_native_addr); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1583 dst = jmp_r(dst, SCRATCH1); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1584 break; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1585 case Z80_RST: { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1586 //RST is basically CALL to an address in page 0 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1587 dst = zcycles(dst, 5);//T States: 5 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1588 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
315
684e71e9f0d0
Fix return address for RST
Mike Pavone <pavone@retrodev.com>
parents:
314
diff
changeset
|
1589 dst = mov_ir(dst, address + 1, SCRATCH1, SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1590 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1591 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1592 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1593 if (!call_dst) { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1594 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1595 //fake address to force large displacement |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1596 call_dst = dst + 256; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1597 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1598 dst = jmp(dst, call_dst); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1599 break; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1600 } |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1601 case Z80_IN: |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1602 dst = zcycles(dst, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1603 if (inst->addr_mode == Z80_IMMED_INDIRECT) { |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1604 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1605 } else { |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1606 dst = mov_rr(dst, opts->regs[Z80_C], SCRATCH1, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1607 } |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1608 dst = call(dst, (uint8_t *)z80_io_read); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1609 translate_z80_reg(inst, &dst_op, dst, opts); |
ed7098f717d7
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1610 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
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|
1611 dst = z80_save_reg(dst, inst, opts); |
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diff
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|
1612 break; |
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283
diff
changeset
|
1613 /*case Z80_INI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1614 case Z80_INIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1615 case Z80_IND: |
284
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283
diff
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|
1616 case Z80_INDR:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1617 case Z80_OUT: |
284
ed7098f717d7
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diff
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|
1618 dst = zcycles(dst, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
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|
1619 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) { |
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|
1620 dst = mov_ir(dst, inst->immed, SCRATCH2, SZ_B); |
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283
diff
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|
1621 } else { |
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diff
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|
1622 dst = mov_rr(dst, opts->regs[Z80_C], SCRATCH2, SZ_B); |
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diff
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|
1623 } |
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|
1624 translate_z80_reg(inst, &src_op, dst, opts); |
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|
1625 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
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|
1626 dst = call(dst, (uint8_t *)z80_io_write); |
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|
1627 dst = z80_save_reg(dst, inst, opts); |
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|
1628 break; |
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|
1629 /*case Z80_OUTI: |
213
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1630 case Z80_OTIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1631 case Z80_OUTD: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1632 case Z80_OTDR:*/ |
235
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diff
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|
1633 default: { |
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|
1634 char disbuf[80]; |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
1635 z80_disasm(inst, disbuf, address); |
235
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|
1636 fprintf(stderr, "unimplemented instruction: %s\n", disbuf); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
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257
diff
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|
1637 FILE * f = fopen("zram.bin", "wb"); |
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Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
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257
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|
1638 fwrite(context->mem_pointers[0], 1, 8 * 1024, f); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
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257
diff
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|
1639 fclose(f); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1640 exit(1); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1641 } |
235
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|
1642 } |
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|
1643 return dst; |
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changeset
|
1644 } |
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|
1645 |
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|
1646 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
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Get Z80 core working for simple programs
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213
diff
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|
1647 { |
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|
1648 native_map_slot *map; |
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213
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|
1649 if (address < 0x4000) { |
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|
1650 address &= 0x1FFF; |
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|
1651 map = context->static_code_map; |
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|
1652 } else if (address >= 0x8000) { |
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Get Z80 core working for simple programs
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213
diff
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|
1653 address &= 0x7FFF; |
279
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Fix native address lookup in bannked memory area
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277
diff
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|
1654 map = context->banked_code_map + context->bank_reg; |
235
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Get Z80 core working for simple programs
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|
1655 } else { |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents:
312
diff
changeset
|
1656 //dprintf("z80_get_native_address: %X NULL\n", address); |
235
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Get Z80 core working for simple programs
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213
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|
1657 return NULL; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1658 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1659 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET || map->offsets[address] == EXTENSION_WORD) { |
313
a13329645ea3
Fix terminal instruction detection in disassembler
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parents:
312
diff
changeset
|
1660 //dprintf("z80_get_native_address: %X NULL\n", address); |
235
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diff
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|
1661 return NULL; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1662 } |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
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312
diff
changeset
|
1663 //dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]); |
235
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|
1664 return map->base + map->offsets[address]; |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1665 } |
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diff
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|
1666 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
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|
1667 uint8_t z80_get_native_inst_size(x86_z80_options * opts, uint32_t address) |
235
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213
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|
1668 { |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
changeset
|
1669 if (address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
diff
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|
1670 return 0; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
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|
1671 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1672 return opts->ram_inst_sizes[address & 0x1FFF]; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1673 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
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|
1674 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1675 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
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changeset
|
1676 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1677 uint32_t orig_address = address; |
235
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|
1678 native_map_slot *map; |
252
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|
1679 x86_z80_options * opts = context->options; |
235
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diff
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|
1680 if (address < 0x4000) { |
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Get Z80 core working for simple programs
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diff
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|
1681 address &= 0x1FFF; |
d9bf8e61c33c
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diff
changeset
|
1682 map = context->static_code_map; |
252
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|
1683 opts->ram_inst_sizes[address] = native_size; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1684 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1685 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7); |
235
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diff
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|
1686 } else if (address >= 0x8000) { |
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Get Z80 core working for simple programs
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213
diff
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|
1687 address &= 0x7FFF; |
279
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Fix native address lookup in bannked memory area
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277
diff
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|
1688 map = context->banked_code_map + context->bank_reg; |
235
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diff
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|
1689 if (!map->offsets) { |
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diff
changeset
|
1690 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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213
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|
1691 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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diff
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|
1692 } |
d9bf8e61c33c
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diff
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|
1693 } else { |
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Get Z80 core working for simple programs
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diff
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|
1694 return; |
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diff
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|
1695 } |
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|
1696 if (!map->base) { |
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diff
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|
1697 map->base = native_address; |
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|
1698 } |
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|
1699 map->offsets[address] = native_address - map->base; |
253
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Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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|
1700 for(--size, orig_address++; size; --size, orig_address++) { |
252
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|
1701 address = orig_address; |
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|
1702 if (address < 0x4000) { |
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|
1703 address &= 0x1FFF; |
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|
1704 map = context->static_code_map; |
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|
1705 } else if (address >= 0x8000) { |
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|
1706 address &= 0x7FFF; |
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|
1707 map = context->banked_code_map + context->bank_reg; |
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|
1708 } else { |
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|
1709 return; |
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1710 } |
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|
1711 if (!map->offsets) { |
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|
1712 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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|
1713 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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1714 } |
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Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1715 map->offsets[address] = EXTENSION_WORD; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1716 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1717 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1718 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1719 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1720 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1721 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1722 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1723 if (!static_code_map->base || address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1724 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1725 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1726 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1727 if (static_code_map->offsets[address] == INVALID_OFFSET) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1728 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1729 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1730 while (static_code_map->offsets[address] == EXTENSION_WORD) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1731 --address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1732 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1733 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1734 return address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1735 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1736 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1737 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1738 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1739 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1740 if (inst_start != INVALID_INSTRUCTION_START) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1741 uint8_t * dst = z80_get_native_address(context, inst_start); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1742 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", dst, inst_start, address); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1743 dst = mov_ir(dst, inst_start, SCRATCH1, SZ_D); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1744 dst = jmp(dst, (uint8_t *)z80_retrans_stub); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1745 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1746 return context; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1747 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1748 |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1749 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1750 { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1751 uint8_t * addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1752 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1753 translate_z80_stream(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1754 addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1755 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1756 printf("Failed to translate %X to native code\n", address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1757 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1758 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1759 return addr; |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1760 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1761 |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1762 void z80_handle_deferred(z80_context * context) |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1763 { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1764 x86_z80_options * opts = context->options; |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1765 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1766 if (opts->deferred) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1767 translate_z80_stream(context, opts->deferred->address); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1768 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1769 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1770 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1771 void * z80_retranslate_inst(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1772 { |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1773 char disbuf[80]; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1774 x86_z80_options * opts = context->options; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1775 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1776 uint8_t * orig_start = z80_get_native_address(context, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1777 uint32_t orig = address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1778 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1779 uint8_t * dst = opts->cur_code; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1780 uint8_t * dst_end = opts->code_end; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1781 uint8_t *after, *inst = context->mem_pointers[0] + address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1782 z80inst instbuf; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1783 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1784 after = z80_decode(inst, &instbuf); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1785 #ifdef DO_DEBUG_PRINT |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
1786 z80_disasm(&instbuf, disbuf, address); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1787 if (instbuf.op == Z80_NOP) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1788 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1789 } else { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1790 printf("%X\t%s\n", address, disbuf); |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
1791 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1792 #endif |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1793 if (orig_size != ZMAX_NATIVE_SIZE) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1794 if (dst_end - dst < ZMAX_NATIVE_SIZE) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1795 size_t size = 1024*1024; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1796 dst = alloc_code(&size); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1797 opts->code_end = dst_end = dst + size; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1798 opts->cur_code = dst; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1799 } |
282
7b8a49220e3b
Remove deferred address entries from abandoned translations inside z80_retrans_inst
Mike Pavone <pavone@retrodev.com>
parents:
279
diff
changeset
|
1800 deferred_addr * orig_deferred = opts->deferred; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1801 uint8_t * native_end = translate_z80inst(&instbuf, dst, context, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1802 if ((native_end - dst) <= orig_size) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1803 uint8_t * native_next = z80_get_native_address(context, address + after-inst); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1804 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) { |
282
7b8a49220e3b
Remove deferred address entries from abandoned translations inside z80_retrans_inst
Mike Pavone <pavone@retrodev.com>
parents:
279
diff
changeset
|
1805 remove_deferred_until(&opts->deferred, orig_deferred); |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1806 native_end = translate_z80inst(&instbuf, orig_start, context, address); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1807 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1808 while (native_end < orig_start + orig_size) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1809 *(native_end++) = 0x90; //NOP |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1810 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1811 } else { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1812 jmp(native_end, native_next); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1813 } |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1814 z80_handle_deferred(context); |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1815 return orig_start; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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1816 } |
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1817 } |
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1818 z80_map_native_address(context, address, dst, after-inst, ZMAX_NATIVE_SIZE); |
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1819 opts->cur_code = dst+ZMAX_NATIVE_SIZE; |
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1820 jmp(orig_start, dst); |
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1821 if (!z80_is_terminal(&instbuf)) { |
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1822 jmp(native_end, z80_get_native_address_trans(context, address + after-inst)); |
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1823 } |
266
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1824 z80_handle_deferred(context); |
264
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1825 return dst; |
252
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1826 } else { |
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1827 dst = translate_z80inst(&instbuf, orig_start, context, address); |
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1828 if (!z80_is_terminal(&instbuf)) { |
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1829 dst = jmp(dst, z80_get_native_address_trans(context, address + after-inst)); |
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1830 } |
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1831 z80_handle_deferred(context); |
252
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1832 return orig_start; |
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1833 } |
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1834 } |
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1835 |
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1836 void translate_z80_stream(z80_context * context, uint32_t address) |
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1837 { |
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1838 char disbuf[80]; |
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1839 if (z80_get_native_address(context, address)) { |
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1840 return; |
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1841 } |
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1842 x86_z80_options * opts = context->options; |
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1843 uint8_t * encoded = NULL, *next; |
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1844 if (address < 0x4000) { |
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1845 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1846 } else if(address >= 0x8000 && context->mem_pointers[1]) { |
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1847 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1848 } |
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1849 while (encoded != NULL) |
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1850 { |
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1851 z80inst inst; |
268
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1852 dprintf("translating Z80 code at address %X\n", address); |
235
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1853 do { |
252
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1854 if (opts->code_end-opts->cur_code < ZMAX_NATIVE_SIZE) { |
235
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1855 if (opts->code_end-opts->cur_code < 5) { |
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1856 puts("out of code memory, not enough space for jmp to next chunk"); |
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1857 exit(1); |
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1858 } |
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1859 size_t size = 1024*1024; |
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1860 opts->cur_code = alloc_code(&size); |
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1861 opts->code_end = opts->cur_code + size; |
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1862 jmp(opts->cur_code, opts->cur_code); |
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1863 } |
255
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1864 if (address > 0x4000 && address < 0x8000) { |
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1865 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D); |
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1866 opts->cur_code = call(opts->cur_code, (uint8_t *)exit); |
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1867 break; |
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1868 } |
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1869 uint8_t * existing = z80_get_native_address(context, address); |
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1870 if (existing) { |
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1871 opts->cur_code = jmp(opts->cur_code, existing); |
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1872 break; |
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1873 } |
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1874 next = z80_decode(encoded, &inst); |
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1875 #ifdef DO_DEBUG_PRINT |
314
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1876 z80_disasm(&inst, disbuf, address); |
235
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1877 if (inst.op == Z80_NOP) { |
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1878 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
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1879 } else { |
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1880 printf("%X\t%s\n", address, disbuf); |
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1881 } |
268
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1882 #endif |
248
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1883 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address); |
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1884 z80_map_native_address(context, address, opts->cur_code, next-encoded, after - opts->cur_code); |
248
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1885 opts->cur_code = after; |
235
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1886 address += next-encoded; |
255
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1887 if (address > 0xFFFF) { |
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1888 address &= 0xFFFF; |
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1889 |
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1890 } else { |
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1891 encoded = next; |
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1892 } |
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1893 } while (!z80_is_terminal(&inst)); |
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1894 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
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1895 if (opts->deferred) { |
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1896 address = opts->deferred->address; |
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1897 dprintf("defferred address: %X\n", address); |
235
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1898 if (address < 0x4000) { |
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1899 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1900 } else if (address > 0x8000 && context->mem_pointers[1]) { |
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1901 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1902 } else { |
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1903 printf("attempt to translate non-memory address: %X\n", address); |
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1904 exit(1); |
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1905 } |
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1906 } else { |
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1907 encoded = NULL; |
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1908 } |
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1909 } |
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|
1910 } |
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1911 |
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1912 void init_x86_z80_opts(x86_z80_options * options) |
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1913 { |
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1914 options->flags = 0; |
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1915 options->regs[Z80_B] = BH; |
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1916 options->regs[Z80_C] = RBX; |
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1917 options->regs[Z80_D] = CH; |
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1918 options->regs[Z80_E] = RCX; |
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1919 options->regs[Z80_H] = AH; |
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1920 options->regs[Z80_L] = RAX; |
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1921 options->regs[Z80_IXH] = DH; |
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1922 options->regs[Z80_IXL] = RDX; |
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1923 options->regs[Z80_IYH] = -1; |
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1924 options->regs[Z80_IYL] = R8; |
235
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1925 options->regs[Z80_I] = -1; |
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1926 options->regs[Z80_R] = -1; |
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1927 options->regs[Z80_A] = R10; |
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1928 options->regs[Z80_BC] = RBX; |
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1929 options->regs[Z80_DE] = RCX; |
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1930 options->regs[Z80_HL] = RAX; |
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1931 options->regs[Z80_SP] = R9; |
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1932 options->regs[Z80_AF] = -1; |
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1933 options->regs[Z80_IX] = RDX; |
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1934 options->regs[Z80_IY] = R8; |
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1935 size_t size = 1024 * 1024; |
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1936 options->cur_code = alloc_code(&size); |
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1937 options->code_end = options->cur_code + size; |
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1938 options->ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000); |
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1939 memset(options->ram_inst_sizes, 0, sizeof(uint8_t) * 0x2000); |
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1940 options->deferred = NULL; |
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1941 } |
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1942 |
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1943 void init_z80_context(z80_context * context, x86_z80_options * options) |
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1944 { |
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1945 memset(context, 0, sizeof(*context)); |
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1946 context->static_code_map = malloc(sizeof(*context->static_code_map)); |
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1947 context->static_code_map->base = NULL; |
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1948 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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1949 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
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1950 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9)); |
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1951 memset(context->banked_code_map, 0, sizeof(native_map_slot) * (1 << 9)); |
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1952 context->options = options; |
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1953 } |
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1954 |
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1955 void z80_reset(z80_context * context) |
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1956 { |
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1957 context->im = 0; |
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1958 context->iff1 = context->iff2 = 0; |
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1959 context->native_pc = z80_get_native_address_trans(context, 0); |
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1960 context->extra_pc = NULL; |
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1961 } |
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1962 |
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1963 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler) |
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1964 { |
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1965 static uint8_t * bp_stub = NULL; |
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1966 uint8_t * native = z80_get_native_address_trans(context, address); |
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1967 uint8_t * start_native = native; |
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1968 native = mov_ir(native, address, SCRATCH1, SZ_W); |
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1969 if (!bp_stub) { |
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1970 x86_z80_options * opts = context->options; |
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1971 uint8_t * dst = opts->cur_code; |
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1972 uint8_t * dst_end = opts->code_end; |
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1973 if (dst_end - dst < 128) { |
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1974 size_t size = 1024*1024; |
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1975 dst = alloc_code(&size); |
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1976 opts->code_end = dst_end = dst + size; |
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1977 } |
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1978 bp_stub = dst; |
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1979 native = call(native, bp_stub); |
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1980 |
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1981 //Calculate length of prologue |
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1982 dst = z80_check_cycles_int(dst, address); |
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1983 int check_int_size = dst-bp_stub; |
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1984 dst = bp_stub; |
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1985 |
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1986 //Save context and call breakpoint handler |
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1987 dst = call(dst, (uint8_t *)z80_save_context); |
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1988 dst = push_r(dst, SCRATCH1); |
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1989 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
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1990 dst = mov_rr(dst, SCRATCH1, RSI, SZ_W); |
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1991 dst = call(dst, bp_handler); |
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1992 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q); |
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1993 //Restore context |
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1994 dst = call(dst, (uint8_t *)z80_load_context); |
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1995 dst = pop_r(dst, SCRATCH1); |
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1996 //do prologue stuff |
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1997 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
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1998 uint8_t * jmp_off = dst+1; |
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1999 dst = jcc(dst, CC_NC, dst + 7); |
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2000 dst = pop_r(dst, SCRATCH1); |
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2001 dst = add_ir(dst, check_int_size - (native-start_native), SCRATCH1, SZ_Q); |
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2002 dst = push_r(dst, SCRATCH1); |
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2003 dst = jmp(dst, (uint8_t *)z80_handle_cycle_limit_int); |
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2004 *jmp_off = dst - (jmp_off+1); |
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2005 //jump back to body of translated instruction |
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2006 dst = pop_r(dst, SCRATCH1); |
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2007 dst = add_ir(dst, check_int_size - (native-start_native), SCRATCH1, SZ_Q); |
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2008 dst = jmp_r(dst, SCRATCH1); |
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2009 opts->cur_code = dst; |
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2010 } else { |
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2011 native = call(native, bp_stub); |
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2012 } |
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2013 } |
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2014 |
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2015 void zremove_breakpoint(z80_context * context, uint16_t address) |
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2016 { |
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2017 uint8_t * native = z80_get_native_address(context, address); |
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2018 z80_check_cycles_int(native, address); |
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2019 } |
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2020 |
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2021 |