Mercurial > repos > blastem
annotate z80_to_x86.c @ 284:ed7098f717d7
Implement IN and OUT (untested)
author | Mike Pavone <pavone@retrodev.com> |
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date | Sat, 04 May 2013 15:58:15 -0700 |
parents | 61f5d88ea01a |
children | 021aeb6df19b |
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1 #include "z80inst.h" |
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2 #include "z80_to_x86.h" |
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3 #include "gen_x86.h" |
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4 #include "mem.h" |
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5 #include <stdio.h> |
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6 #include <stdlib.h> |
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7 #include <stddef.h> |
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8 #include <string.h> |
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9 |
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10 #define MODE_UNUSED (MODE_IMMED-1) |
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11 |
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12 #define ZCYCLES RBP |
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13 #define ZLIMIT RDI |
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14 #define SCRATCH1 R13 |
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15 #define SCRATCH2 R14 |
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16 #define CONTEXT RSI |
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17 |
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18 //#define DO_DEBUG_PRINT |
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19 |
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20 #ifdef DO_DEBUG_PRINT |
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21 #define dprintf printf |
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22 #else |
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23 #define dprintf |
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24 #endif |
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25 |
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26 void z80_read_byte(); |
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27 void z80_read_word(); |
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28 void z80_write_byte(); |
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29 void z80_write_word_highfirst(); |
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30 void z80_write_word_lowfirst(); |
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31 void z80_save_context(); |
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32 void z80_native_addr(); |
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33 void z80_do_sync(); |
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34 void z80_handle_cycle_limit_int(); |
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35 void z80_retrans_stub(); |
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36 void z80_io_read(); |
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37 void z80_io_write(); |
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38 |
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39 uint8_t z80_size(z80inst * inst) |
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40 { |
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41 uint8_t reg = (inst->reg & 0x1F); |
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42 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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43 return reg < Z80_BC ? SZ_B : SZ_W; |
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44 } |
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45 //TODO: Handle any necessary special cases |
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46 return SZ_B; |
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47 } |
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48 |
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49 uint8_t z80_high_reg(uint8_t reg) |
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50 { |
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51 switch(reg) |
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52 { |
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53 case Z80_C: |
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54 case Z80_BC: |
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55 return Z80_B; |
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56 case Z80_E: |
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57 case Z80_DE: |
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58 return Z80_D; |
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59 case Z80_L: |
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60 case Z80_HL: |
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61 return Z80_H; |
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62 case Z80_IXL: |
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63 case Z80_IX: |
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64 return Z80_IXH; |
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65 case Z80_IYL: |
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66 case Z80_IY: |
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67 return Z80_IYH; |
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68 default: |
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69 return Z80_UNUSED; |
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70 } |
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71 } |
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72 |
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73 uint8_t z80_low_reg(uint8_t reg) |
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74 { |
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75 switch(reg) |
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76 { |
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77 case Z80_B: |
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78 case Z80_BC: |
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79 return Z80_C; |
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80 case Z80_D: |
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81 case Z80_DE: |
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82 return Z80_E; |
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83 case Z80_H: |
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84 case Z80_HL: |
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85 return Z80_L; |
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86 case Z80_IXH: |
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87 case Z80_IX: |
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88 return Z80_IXL; |
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89 case Z80_IYH: |
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90 case Z80_IY: |
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91 return Z80_IYL; |
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92 default: |
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93 return Z80_UNUSED; |
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94 } |
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95 } |
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96 |
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97 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles) |
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98 { |
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99 return add_ir(dst, num_cycles, ZCYCLES, SZ_D); |
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100 } |
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101 |
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102 uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address) |
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103 { |
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104 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
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105 uint8_t * jmp_off = dst+1; |
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106 dst = jcc(dst, CC_NC, dst + 7); |
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107 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
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108 dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int); |
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109 *jmp_off = dst - (jmp_off+1); |
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110 return dst; |
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111 } |
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112 |
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113 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts) |
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114 { |
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115 if (inst->reg == Z80_USE_IMMED) { |
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116 ea->mode = MODE_IMMED; |
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117 ea->disp = inst->immed; |
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118 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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119 ea->mode = MODE_UNUSED; |
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120 } else { |
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121 ea->mode = MODE_REG_DIRECT; |
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122 if (inst->reg == Z80_IYH) { |
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123 ea->base = opts->regs[Z80_IYL]; |
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124 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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125 } else if(opts->regs[inst->reg] >= 0) { |
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126 ea->base = opts->regs[inst->reg]; |
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127 if (ea->base >= AH && ea->base <= BH) { |
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128 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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129 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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130 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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131 //we can't mix an *H reg with a register that requires the REX prefix |
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132 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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133 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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134 } |
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135 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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136 //temp regs require REX prefix too |
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137 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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138 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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139 } |
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140 } |
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141 } else { |
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142 ea->mode = MODE_REG_DISPLACE8; |
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143 ea->base = CONTEXT; |
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144 ea->disp = offsetof(z80_context, regs) + inst->reg; |
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145 } |
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146 } |
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147 return dst; |
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148 } |
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149 |
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150 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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151 { |
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152 if (inst->reg == Z80_IYH) { |
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153 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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154 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) { |
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155 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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156 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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157 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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158 //we can't mix an *H reg with a register that requires the REX prefix |
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159 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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160 } |
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161 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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162 //temp regs require REX prefix too |
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163 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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164 } |
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165 } |
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166 return dst; |
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167 } |
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168 |
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169 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify) |
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170 { |
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171 uint8_t size, reg, areg; |
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172 ea->mode = MODE_REG_DIRECT; |
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173 areg = read ? SCRATCH1 : SCRATCH2; |
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174 switch(inst->addr_mode & 0x1F) |
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175 { |
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176 case Z80_REG: |
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177 if (inst->ea_reg == Z80_IYH) { |
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178 ea->base = opts->regs[Z80_IYL]; |
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179 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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180 } else { |
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181 ea->base = opts->regs[inst->ea_reg]; |
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182 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) { |
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183 uint8_t other_reg = opts->regs[inst->reg]; |
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184 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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185 //we can't mix an *H reg with a register that requires the REX prefix |
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186 ea->base = opts->regs[z80_low_reg(inst->ea_reg)]; |
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187 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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188 } |
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189 } |
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190 } |
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191 break; |
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192 case Z80_REG_INDIRECT: |
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193 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W); |
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194 size = z80_size(inst); |
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195 if (read) { |
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196 if (modify) { |
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197 //dst = push_r(dst, SCRATCH1); |
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198 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(z80_context, scratch1), SZ_W); |
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199 } |
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200 if (size == SZ_B) { |
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201 dst = call(dst, (uint8_t *)z80_read_byte); |
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202 } else { |
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203 dst = call(dst, (uint8_t *)z80_read_word); |
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204 } |
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205 if (modify) { |
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206 //dst = pop_r(dst, SCRATCH2); |
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207 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, scratch1), SCRATCH2, SZ_W); |
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208 } |
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209 } |
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210 ea->base = SCRATCH1; |
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211 break; |
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212 case Z80_IMMED: |
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213 ea->mode = MODE_IMMED; |
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214 ea->disp = inst->immed; |
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215 break; |
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216 case Z80_IMMED_INDIRECT: |
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217 dst = mov_ir(dst, inst->immed, areg, SZ_W); |
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218 size = z80_size(inst); |
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219 if (read) { |
277
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220 /*if (modify) { |
213
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221 dst = push_r(dst, SCRATCH1); |
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222 }*/ |
213
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223 if (size == SZ_B) { |
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224 dst = call(dst, (uint8_t *)z80_read_byte); |
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225 } else { |
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226 dst = call(dst, (uint8_t *)z80_read_word); |
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227 } |
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228 if (modify) { |
277
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229 //dst = pop_r(dst, SCRATCH2); |
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230 dst = mov_ir(dst, inst->immed, SCRATCH2, SZ_W); |
213
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231 } |
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232 } |
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233 ea->base = SCRATCH1; |
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234 break; |
235
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235 case Z80_IX_DISPLACE: |
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236 case Z80_IY_DISPLACE: |
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237 reg = opts->regs[inst->addr_mode == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
213
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238 dst = mov_rr(dst, reg, areg, SZ_W); |
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239 dst = add_ir(dst, inst->immed, areg, SZ_W); |
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240 size = z80_size(inst); |
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241 if (read) { |
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242 if (modify) { |
277
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243 //dst = push_r(dst, SCRATCH1); |
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244 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(z80_context, scratch1), SZ_W); |
213
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245 } |
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246 if (size == SZ_B) { |
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247 dst = call(dst, (uint8_t *)z80_read_byte); |
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248 } else { |
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249 dst = call(dst, (uint8_t *)z80_read_word); |
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250 } |
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251 if (modify) { |
277
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252 //dst = pop_r(dst, SCRATCH2); |
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253 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, scratch1), SCRATCH2, SZ_W); |
213
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254 } |
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255 } |
269
3c054d977175
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268
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256 ea->base = SCRATCH1; |
213
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257 break; |
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258 case Z80_UNUSED: |
235
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259 ea->mode = MODE_UNUSED; |
213
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260 break; |
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261 default: |
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262 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode); |
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263 exit(1); |
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264 } |
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265 return dst; |
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266 } |
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267 |
235
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|
268 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
213
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269 { |
267
1788e3f29c28
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266
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270 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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271 if (inst->ea_reg == Z80_IYH) { |
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272 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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273 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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274 uint8_t other_reg = opts->regs[inst->reg]; |
269
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268
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275 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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276 //we can't mix an *H reg with a register that requires the REX prefix |
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277 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W); |
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278 } |
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279 } |
213
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280 } |
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281 return dst; |
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282 } |
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283 |
235
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284 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst) |
213
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285 { |
253
3b34deba4ca0
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286 switch(inst->addr_mode & 0x1f) |
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287 { |
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288 case Z80_REG_INDIRECT: |
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289 case Z80_IMMED_INDIRECT: |
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290 case Z80_IX_DISPLACE: |
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291 case Z80_IY_DISPLACE: |
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292 if (z80_size(inst) == SZ_B) { |
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293 dst = call(dst, (uint8_t *)z80_write_byte); |
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294 } else { |
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295 dst = call(dst, (uint8_t *)z80_write_word_lowfirst); |
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296 } |
213
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297 } |
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298 return dst; |
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299 } |
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300 |
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301 enum { |
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302 DONT_READ=0, |
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|
303 READ |
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304 }; |
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305 |
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|
306 enum { |
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|
307 DONT_MODIFY=0, |
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308 MODIFY |
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309 }; |
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310 |
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311 uint8_t zf_off(uint8_t flag) |
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312 { |
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313 return offsetof(z80_context, flags) + flag; |
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314 } |
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315 |
241
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316 uint8_t zaf_off(uint8_t flag) |
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317 { |
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318 return offsetof(z80_context, alt_flags) + flag; |
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319 } |
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320 |
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321 uint8_t zar_off(uint8_t reg) |
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322 { |
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323 return offsetof(z80_context, alt_regs) + reg; |
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324 } |
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325 |
235
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326 void z80_print_regs_exit(z80_context * context) |
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327 { |
243
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328 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
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329 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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330 context->regs[Z80_D], context->regs[Z80_E], |
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331 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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332 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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333 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
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334 context->sp, context->im, context->iff1, context->iff2); |
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335 puts("--Alternate Regs--"); |
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336 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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337 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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338 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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339 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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340 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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341 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
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342 exit(0); |
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343 } |
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344 |
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345 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address) |
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346 { |
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347 uint32_t cycles; |
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348 x86_ea src_op, dst_op; |
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349 uint8_t size; |
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350 x86_z80_options *opts = context->options; |
261
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351 uint8_t * start = dst; |
250
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352 dst = z80_check_cycles_int(dst, address); |
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353 switch(inst->op) |
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354 { |
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355 case Z80_LD: |
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356 size = z80_size(inst); |
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357 switch (inst->addr_mode & 0x1F) |
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358 { |
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359 case Z80_REG: |
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360 case Z80_REG_INDIRECT: |
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361 cycles = size == SZ_B ? 4 : 6; |
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362 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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363 cycles += 4; |
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364 } |
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365 break; |
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366 case Z80_IMMED: |
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367 cycles = size == SZ_B ? 7 : 10; |
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368 break; |
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369 case Z80_IMMED_INDIRECT: |
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370 cycles = 10; |
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371 break; |
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372 case Z80_IX_DISPLACE: |
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373 case Z80_IY_DISPLACE: |
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374 cycles = 12; |
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375 break; |
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376 } |
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377 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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378 cycles += 4; |
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379 } |
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380 dst = zcycles(dst, cycles); |
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381 if (inst->addr_mode & Z80_DIR) { |
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382 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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383 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY); |
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384 } else { |
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385 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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386 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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387 } |
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388 if (src_op.mode == MODE_REG_DIRECT) { |
262
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389 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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390 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
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391 } else { |
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392 dst = mov_rr(dst, src_op.base, dst_op.base, size); |
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393 } |
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394 } else if(src_op.mode == MODE_IMMED) { |
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395 dst = mov_ir(dst, src_op.disp, dst_op.base, size); |
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396 } else { |
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397 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
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398 } |
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399 dst = z80_save_reg(dst, inst, opts); |
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400 dst = z80_save_ea(dst, inst, opts); |
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401 if (inst->addr_mode & Z80_DIR) { |
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402 dst = z80_save_result(dst, inst); |
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403 } |
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404 break; |
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405 case Z80_PUSH: |
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406 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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407 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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408 if (inst->reg == Z80_AF) { |
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409 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH1, SZ_B); |
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410 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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411 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH1, SZ_B); |
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412 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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413 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH1, SZ_B); |
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414 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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415 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH1, SZ_B); |
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416 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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417 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH1, SZ_B); |
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418 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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419 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH1, SZ_B); |
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420 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); |
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421 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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422 } else { |
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423 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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424 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
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425 } |
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426 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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427 dst = call(dst, (uint8_t *)z80_write_word_highfirst); |
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428 //no call to save_z80_reg needed since there's no chance we'll use the only |
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429 //the upper half of a register pair |
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430 break; |
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431 case Z80_POP: |
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432 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
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433 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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434 dst = call(dst, (uint8_t *)z80_read_word); |
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435 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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436 if (inst->reg == Z80_AF) { |
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437 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); |
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438 dst = bt_ir(dst, 8, SCRATCH1, SZ_W); |
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439 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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440 dst = bt_ir(dst, 9, SCRATCH1, SZ_W); |
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441 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N)); |
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442 dst = bt_ir(dst, 10, SCRATCH1, SZ_W); |
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443 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV)); |
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444 dst = bt_ir(dst, 12, SCRATCH1, SZ_W); |
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445 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H)); |
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446 dst = bt_ir(dst, 14, SCRATCH1, SZ_W); |
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447 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
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448 dst = bt_ir(dst, 15, SCRATCH1, SZ_W); |
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449 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S)); |
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450 } else { |
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451 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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452 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W); |
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453 } |
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454 //no call to save_z80_reg needed since there's no chance we'll use the only |
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455 //the upper half of a register pair |
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456 break; |
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457 case Z80_EX: |
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458 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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459 cycles = 4; |
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460 } else { |
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461 cycles = 8; |
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462 } |
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463 dst = zcycles(dst, cycles); |
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464 if (inst->addr_mode == Z80_REG) { |
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465 if(inst->reg == Z80_AF) { |
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466 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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467 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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468 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B); |
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469 |
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470 //Flags are currently word aligned, so we can move |
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471 //them efficiently a word at a time |
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472 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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473 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W); |
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474 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W); |
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475 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W); |
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476 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zf_off(f), SZ_W); |
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477 } |
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478 } else { |
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479 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
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480 } |
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481 } else { |
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482 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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483 dst = call(dst, (uint8_t *)z80_read_byte); |
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484 dst = xchg_rr(dst, opts->regs[inst->reg], SCRATCH1, SZ_B); |
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485 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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486 dst = call(dst, (uint8_t *)z80_write_byte); |
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487 dst = zcycles(dst, 1); |
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488 uint8_t high_reg = z80_high_reg(inst->reg); |
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489 uint8_t use_reg; |
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490 //even though some of the upper halves can be used directly |
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491 //the limitations on mixing *H regs with the REX prefix |
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492 //prevent us from taking advantage of it |
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493 use_reg = opts->regs[inst->reg]; |
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494 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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495 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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496 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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497 dst = call(dst, (uint8_t *)z80_read_byte); |
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498 dst = xchg_rr(dst, use_reg, SCRATCH1, SZ_B); |
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499 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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500 dst = add_ir(dst, 1, SCRATCH2, SZ_W); |
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501 dst = call(dst, (uint8_t *)z80_write_byte); |
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502 //restore reg to normal rotation |
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503 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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504 dst = zcycles(dst, 2); |
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505 } |
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506 break; |
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507 case Z80_EXX: |
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508 dst = zcycles(dst, 4); |
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509 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W); |
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510 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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511 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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512 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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513 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W); |
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514 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W); |
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515 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W); |
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516 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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517 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W); |
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518 break; |
272 | 519 case Z80_LDI: { |
520 dst = zcycles(dst, 8); | |
521 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
522 dst = call(dst, (uint8_t *)z80_read_byte); | |
523 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
524 dst = call(dst, (uint8_t *)z80_read_byte); | |
525 dst = zcycles(dst, 2); | |
526 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
527 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
528 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
529 //TODO: Implement half-carry | |
530 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
531 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
532 break; | |
533 } | |
261
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534 case Z80_LDIR: { |
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535 dst = zcycles(dst, 8); |
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536 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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537 dst = call(dst, (uint8_t *)z80_read_byte); |
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538 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); |
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539 dst = call(dst, (uint8_t *)z80_read_byte); |
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540 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); |
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541 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); |
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542 |
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543 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); |
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544 uint8_t * cont = dst+1; |
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545 dst = jcc(dst, CC_Z, dst+2); |
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546 dst = zcycles(dst, 7); |
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547 //TODO: Figure out what the flag state should be here |
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548 //TODO: Figure out whether an interrupt can interrupt this |
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549 dst = jmp(dst, start); |
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550 *cont = dst - (cont + 1); |
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551 dst = zcycles(dst, 2); |
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552 //TODO: Implement half-carry |
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553 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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554 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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555 break; |
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556 } |
273 | 557 case Z80_LDD: { |
558 dst = zcycles(dst, 8); | |
559 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
560 dst = call(dst, (uint8_t *)z80_read_byte); | |
561 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
562 dst = call(dst, (uint8_t *)z80_read_byte); | |
563 dst = zcycles(dst, 2); | |
564 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
565 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
566 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
567 //TODO: Implement half-carry | |
568 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
569 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
570 break; | |
571 } | |
572 case Z80_LDDR: { | |
573 dst = zcycles(dst, 8); | |
574 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
575 dst = call(dst, (uint8_t *)z80_read_byte); | |
576 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
577 dst = call(dst, (uint8_t *)z80_read_byte); | |
578 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
579 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
580 | |
581 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
582 uint8_t * cont = dst+1; | |
583 dst = jcc(dst, CC_Z, dst+2); | |
584 dst = zcycles(dst, 7); | |
585 //TODO: Figure out what the flag state should be here | |
586 //TODO: Figure out whether an interrupt can interrupt this | |
587 dst = jmp(dst, start); | |
588 *cont = dst - (cont + 1); | |
589 dst = zcycles(dst, 2); | |
590 //TODO: Implement half-carry | |
591 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
592 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); | |
593 break; | |
594 } | |
595 /*case Z80_CPI: | |
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596 case Z80_CPIR: |
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597 case Z80_CPD: |
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598 case Z80_CPDR: |
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599 break;*/ |
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600 case Z80_ADD: |
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601 cycles = 4; |
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602 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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603 cycles += 12; |
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604 } else if(inst->addr_mode == Z80_IMMED) { |
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605 cycles += 3; |
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606 } else if(z80_size(inst) == SZ_W) { |
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607 cycles += 4; |
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608 } |
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609 dst = zcycles(dst, cycles); |
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610 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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611 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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612 if (src_op.mode == MODE_REG_DIRECT) { |
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613 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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614 } else { |
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615 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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616 } |
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617 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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618 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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619 //TODO: Implement half-carry flag |
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620 if (z80_size(inst) == SZ_B) { |
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621 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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622 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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623 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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624 } |
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625 dst = z80_save_reg(dst, inst, opts); |
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626 dst = z80_save_ea(dst, inst, opts); |
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627 break; |
248
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628 case Z80_ADC: |
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629 cycles = 4; |
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630 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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631 cycles += 12; |
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632 } else if(inst->addr_mode == Z80_IMMED) { |
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633 cycles += 3; |
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634 } else if(z80_size(inst) == SZ_W) { |
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635 cycles += 4; |
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636 } |
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637 dst = zcycles(dst, cycles); |
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638 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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639 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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640 if (src_op.mode == MODE_REG_DIRECT) { |
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641 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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642 } else { |
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643 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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644 } |
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645 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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646 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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647 //TODO: Implement half-carry flag |
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648 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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649 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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650 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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651 dst = z80_save_reg(dst, inst, opts); |
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652 dst = z80_save_ea(dst, inst, opts); |
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653 break; |
213
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|
654 case Z80_SUB: |
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655 cycles = 4; |
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656 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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|
657 cycles += 12; |
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658 } else if(inst->addr_mode == Z80_IMMED) { |
4d4559b04c59
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659 cycles += 3; |
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660 } |
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661 dst = zcycles(dst, cycles); |
4d4559b04c59
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662 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
4d4559b04c59
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663 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
4d4559b04c59
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changeset
|
664 if (src_op.mode == MODE_REG_DIRECT) { |
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665 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
4d4559b04c59
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666 } else { |
4d4559b04c59
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667 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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668 } |
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669 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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670 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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671 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
213
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|
672 //TODO: Implement half-carry flag |
235
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673 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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674 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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changeset
|
675 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
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changeset
|
676 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
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677 break; |
248
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678 case Z80_SBC: |
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679 cycles = 4; |
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680 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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681 cycles += 12; |
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682 } else if(inst->addr_mode == Z80_IMMED) { |
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683 cycles += 3; |
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684 } else if(z80_size(inst) == SZ_W) { |
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685 cycles += 4; |
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686 } |
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687 dst = zcycles(dst, cycles); |
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688 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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689 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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690 if (src_op.mode == MODE_REG_DIRECT) { |
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691 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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692 } else { |
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693 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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694 } |
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695 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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|
696 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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|
697 //TODO: Implement half-carry flag |
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|
698 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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699 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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247
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700 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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701 dst = z80_save_reg(dst, inst, opts); |
9c7a3db7bcd0
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702 dst = z80_save_ea(dst, inst, opts); |
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|
703 break; |
213
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
704 case Z80_AND: |
236
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235
diff
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|
705 cycles = 4; |
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|
706 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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|
707 cycles += 12; |
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|
708 } else if(inst->addr_mode == Z80_IMMED) { |
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235
diff
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|
709 cycles += 3; |
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235
diff
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|
710 } else if(z80_size(inst) == SZ_W) { |
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235
diff
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|
711 cycles += 4; |
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235
diff
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|
712 } |
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diff
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|
713 dst = zcycles(dst, cycles); |
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235
diff
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|
714 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
19fb3523a9e5
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235
diff
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|
715 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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235
diff
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|
716 if (src_op.mode == MODE_REG_DIRECT) { |
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235
diff
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|
717 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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235
diff
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|
718 } else { |
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235
diff
changeset
|
719 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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235
diff
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|
720 } |
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235
diff
changeset
|
721 //TODO: Cleanup flags |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
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|
722 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
19fb3523a9e5
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235
diff
changeset
|
723 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
19fb3523a9e5
Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
724 //TODO: Implement half-carry flag |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
725 if (z80_size(inst) == SZ_B) { |
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235
diff
changeset
|
726 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
changeset
|
727 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
19fb3523a9e5
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235
diff
changeset
|
728 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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235
diff
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|
729 } |
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235
diff
changeset
|
730 dst = z80_save_reg(dst, inst, opts); |
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
changeset
|
731 dst = z80_save_ea(dst, inst, opts); |
19fb3523a9e5
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parents:
235
diff
changeset
|
732 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
733 case Z80_OR: |
236
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
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|
734 cycles = 4; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
735 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
19fb3523a9e5
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parents:
235
diff
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|
736 cycles += 12; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
737 } else if(inst->addr_mode == Z80_IMMED) { |
19fb3523a9e5
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parents:
235
diff
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|
738 cycles += 3; |
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235
diff
changeset
|
739 } else if(z80_size(inst) == SZ_W) { |
19fb3523a9e5
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235
diff
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|
740 cycles += 4; |
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235
diff
changeset
|
741 } |
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235
diff
changeset
|
742 dst = zcycles(dst, cycles); |
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235
diff
changeset
|
743 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
19fb3523a9e5
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235
diff
changeset
|
744 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
19fb3523a9e5
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235
diff
changeset
|
745 if (src_op.mode == MODE_REG_DIRECT) { |
19fb3523a9e5
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parents:
235
diff
changeset
|
746 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
19fb3523a9e5
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parents:
235
diff
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|
747 } else { |
19fb3523a9e5
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235
diff
changeset
|
748 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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235
diff
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|
749 } |
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235
diff
changeset
|
750 //TODO: Cleanup flags |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
751 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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752 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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753 //TODO: Implement half-carry flag |
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754 if (z80_size(inst) == SZ_B) { |
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755 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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756 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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757 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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758 } |
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759 dst = z80_save_reg(dst, inst, opts); |
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760 dst = z80_save_ea(dst, inst, opts); |
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761 break; |
213
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762 case Z80_XOR: |
236
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763 cycles = 4; |
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764 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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765 cycles += 12; |
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766 } else if(inst->addr_mode == Z80_IMMED) { |
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767 cycles += 3; |
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768 } else if(z80_size(inst) == SZ_W) { |
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769 cycles += 4; |
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770 } |
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771 dst = zcycles(dst, cycles); |
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772 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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773 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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774 if (src_op.mode == MODE_REG_DIRECT) { |
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775 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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776 } else { |
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777 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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778 } |
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779 //TODO: Cleanup flags |
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780 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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781 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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782 //TODO: Implement half-carry flag |
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783 if (z80_size(inst) == SZ_B) { |
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784 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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785 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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786 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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787 } |
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788 dst = z80_save_reg(dst, inst, opts); |
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789 dst = z80_save_ea(dst, inst, opts); |
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790 break; |
242 | 791 case Z80_CP: |
792 cycles = 4; | |
793 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { | |
794 cycles += 12; | |
795 } else if(inst->addr_mode == Z80_IMMED) { | |
796 cycles += 3; | |
797 } | |
798 dst = zcycles(dst, cycles); | |
799 dst = translate_z80_reg(inst, &dst_op, dst, opts); | |
800 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); | |
801 if (src_op.mode == MODE_REG_DIRECT) { | |
802 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst)); | |
803 } else { | |
804 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); | |
805 } | |
806 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); | |
807 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); | |
808 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); | |
809 //TODO: Implement half-carry flag | |
810 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); | |
811 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); | |
812 dst = z80_save_reg(dst, inst, opts); | |
813 dst = z80_save_ea(dst, inst, opts); | |
814 break; | |
213
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815 case Z80_INC: |
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816 cycles = 4; |
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817 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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818 cycles += 6; |
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819 } else if(z80_size(inst) == SZ_W) { |
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|
820 cycles += 2; |
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821 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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|
822 cycles += 4; |
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|
823 } |
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824 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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|
825 if (dst_op.mode == MODE_UNUSED) { |
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826 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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|
827 } |
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828 dst = add_ir(dst, 1, dst_op.base, z80_size(inst)); |
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829 if (z80_size(inst) == SZ_B) { |
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830 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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|
831 //TODO: Implement half-carry flag |
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832 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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833 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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834 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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|
835 } |
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diff
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|
836 dst = z80_save_reg(dst, inst, opts); |
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diff
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|
837 dst = z80_save_ea(dst, inst, opts); |
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838 break; |
236
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839 case Z80_DEC: |
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840 cycles = 4; |
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841 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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842 cycles += 6; |
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843 } else if(z80_size(inst) == SZ_W) { |
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844 cycles += 2; |
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845 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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846 cycles += 4; |
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847 } |
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848 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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849 if (dst_op.mode == MODE_UNUSED) { |
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850 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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851 } |
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852 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst)); |
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853 if (z80_size(inst) == SZ_B) { |
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854 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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855 //TODO: Implement half-carry flag |
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856 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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857 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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858 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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859 } |
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860 dst = z80_save_reg(dst, inst, opts); |
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861 dst = z80_save_ea(dst, inst, opts); |
213
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862 break; |
274
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273
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|
863 //case Z80_DAA: |
213
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|
864 case Z80_CPL: |
274
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|
865 dst = zcycles(dst, 4); |
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866 dst = not_r(dst, opts->regs[Z80_A], SZ_B); |
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867 //TODO: Implement half-carry flag |
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868 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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869 break; |
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870 case Z80_NEG: |
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871 dst = zcycles(dst, 8); |
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Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
872 dst = neg_r(dst, opts->regs[Z80_A], SZ_B); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
873 //TODO: Implement half-carry flag |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
874 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
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273
diff
changeset
|
875 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
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273
diff
changeset
|
876 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
877 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
be2b845d3e94
Implement CPL and NEG (untested)
Mike Pavone <pavone@retrodev.com>
parents:
273
diff
changeset
|
878 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
be2b845d3e94
Implement CPL and NEG (untested)
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parents:
273
diff
changeset
|
879 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 case Z80_CCF: |
257 | 881 dst = zcycles(dst, 4); |
882 dst = xor_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
883 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
884 //TODO: Implement half-carry flag | |
885 break; | |
886 case Z80_SCF: | |
887 dst = zcycles(dst, 4); | |
888 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
889 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
890 //TODO: Implement half-carry flag | |
891 break; | |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 case Z80_NOP: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 if (inst->immed == 42) { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 dst = call(dst, (uint8_t *)z80_save_context); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 dst = jmp(dst, (uint8_t *)z80_print_regs_exit); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 } else { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 dst = zcycles(dst, 4 * inst->immed); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 break; |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
901 //case Z80_HALT: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 case Z80_DI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
903 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
904 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
905 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
906 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
907 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 case Z80_EI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
909 //TODO: Implement interrupt enable latency of 1 instruction afer EI |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
910 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
911 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
912 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
913 dst = call(dst, (uint8_t *)z80_do_sync); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
914 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 case Z80_IM: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
916 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
917 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B); |
2f069a0b487e
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Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
918 break; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
919 case Z80_RLC: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
920 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
921 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
922 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
923 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
924 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
925 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
926 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
927 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
928 dst = rol_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
929 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
930 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
931 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
932 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
933 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
934 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
935 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
936 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
937 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
938 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
939 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
940 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
941 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
942 case Z80_RL: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
943 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
944 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
945 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
946 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
947 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
948 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
949 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
950 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
951 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
952 dst = rcl_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
953 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
954 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
955 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
956 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
957 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
958 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
959 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
960 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
961 dst = z80_save_result(dst, inst); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
962 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
963 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
964 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
965 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
966 case Z80_RRC: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
967 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
968 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
969 if (inst->reg == Z80_UNUSED) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
970 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
971 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
972 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
973 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
974 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
975 dst = ror_ir(dst, 1, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
976 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
977 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
978 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
979 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
980 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
981 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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246
diff
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|
982 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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diff
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|
983 if (inst->reg == Z80_UNUSED) { |
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diff
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|
984 dst = z80_save_result(dst, inst); |
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246
diff
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|
985 } else { |
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246
diff
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|
986 dst = z80_save_reg(dst, inst, opts); |
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246
diff
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|
987 } |
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diff
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|
988 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
989 case Z80_RR: |
275
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274
diff
changeset
|
990 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
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246
diff
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|
991 dst = zcycles(dst, cycles); |
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246
diff
changeset
|
992 if (inst->reg == Z80_UNUSED) { |
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246
diff
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|
993 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
682e505f5757
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246
diff
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|
994 dst = zcycles(dst, 1); |
682e505f5757
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parents:
246
diff
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|
995 } else { |
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parents:
246
diff
changeset
|
996 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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246
diff
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|
997 } |
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246
diff
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|
998 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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diff
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|
999 dst = rcr_ir(dst, 1, dst_op.base, SZ_B); |
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diff
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|
1000 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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246
diff
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|
1001 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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246
diff
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|
1002 //TODO: Implement half-carry flag |
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246
diff
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|
1003 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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246
diff
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|
1004 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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diff
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|
1005 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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246
diff
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|
1006 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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Mike Pavone <pavone@retrodev.com>
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246
diff
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|
1007 if (inst->reg == Z80_UNUSED) { |
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246
diff
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|
1008 dst = z80_save_result(dst, inst); |
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246
diff
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|
1009 } else { |
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246
diff
changeset
|
1010 dst = z80_save_reg(dst, inst, opts); |
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246
diff
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|
1011 } |
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246
diff
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|
1012 break; |
275
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274
diff
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|
1013 case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1014 case Z80_SLL: |
275
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
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274
diff
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|
1015 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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274
diff
changeset
|
1016 dst = zcycles(dst, cycles); |
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274
diff
changeset
|
1017 if (inst->reg == Z80_UNUSED) { |
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Mike Pavone <pavone@retrodev.com>
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274
diff
changeset
|
1018 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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274
diff
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|
1019 dst = zcycles(dst, 1); |
1a7d0a964ad2
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parents:
274
diff
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|
1020 } else { |
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274
diff
changeset
|
1021 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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274
diff
changeset
|
1022 } |
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Mike Pavone <pavone@retrodev.com>
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274
diff
changeset
|
1023 dst = shl_ir(dst, 1, dst_op.base, SZ_B); |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
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274
diff
changeset
|
1024 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1025 //TODO: Implement half-carry flag |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1026 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1027 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1028 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1029 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1030 if (inst->reg == Z80_UNUSED) { |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1031 dst = z80_save_result(dst, inst); |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1032 } else { |
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Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1033 dst = z80_save_reg(dst, inst, opts); |
1a7d0a964ad2
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274
diff
changeset
|
1034 } |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1035 break; |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1036 case Z80_SRA: |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1037 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1038 dst = zcycles(dst, cycles); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1039 if (inst->reg == Z80_UNUSED) { |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1040 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1041 dst = zcycles(dst, 1); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1042 } else { |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1043 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1044 } |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1045 dst = sar_ir(dst, 1, dst_op.base, SZ_B); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1046 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1047 //TODO: Implement half-carry flag |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1048 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1049 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1050 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1051 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1052 if (inst->reg == Z80_UNUSED) { |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1053 dst = z80_save_result(dst, inst); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1054 } else { |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1055 dst = z80_save_reg(dst, inst, opts); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1056 } |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1057 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1058 case Z80_SRL: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1059 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1060 dst = zcycles(dst, cycles); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1061 if (inst->reg == Z80_UNUSED) { |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1062 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1063 dst = zcycles(dst, 1); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1064 } else { |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1065 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1066 } |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1067 dst = shr_ir(dst, 1, dst_op.base, SZ_B); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1068 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1069 //TODO: Implement half-carry flag |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1070 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1071 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1072 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1073 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1074 if (inst->reg == Z80_UNUSED) { |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1075 dst = z80_save_result(dst, inst); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1076 } else { |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1077 dst = z80_save_reg(dst, inst, opts); |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1078 } |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1079 /*case Z80_RLD: |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1080 case Z80_RRD:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1081 case Z80_BIT: |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1082 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
a5bea9711a46
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Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1083 dst = zcycles(dst, cycles); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1084 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
a5bea9711a46
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Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1085 if (inst->addr_mode != Z80_REG) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1086 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1087 dst = zcycles(dst, 1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1088 } |
a5bea9711a46
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238
diff
changeset
|
1089 dst = bt_ir(dst, inst->immed, src_op.base, SZ_B); |
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238
diff
changeset
|
1090 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
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238
diff
changeset
|
1091 break; |
247
682e505f5757
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246
diff
changeset
|
1092 case Z80_SET: |
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246
diff
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|
1093 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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246
diff
changeset
|
1094 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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246
diff
changeset
|
1095 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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246
diff
changeset
|
1096 if (inst->addr_mode != Z80_REG) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
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246
diff
changeset
|
1097 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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246
diff
changeset
|
1098 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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246
diff
changeset
|
1099 } |
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246
diff
changeset
|
1100 dst = bts_ir(dst, inst->immed, src_op.base, SZ_B); |
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246
diff
changeset
|
1101 if (inst->addr_mode != Z80_REG) { |
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246
diff
changeset
|
1102 dst = z80_save_result(dst, inst); |
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246
diff
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|
1103 } |
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1104 break; |
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parents:
246
diff
changeset
|
1105 case Z80_RES: |
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Implement rotation and bit set/reset instructions (untested).
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246
diff
changeset
|
1106 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
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246
diff
changeset
|
1107 dst = zcycles(dst, cycles); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
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246
diff
changeset
|
1108 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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246
diff
changeset
|
1109 if (inst->addr_mode != Z80_REG) { |
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246
diff
changeset
|
1110 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
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246
diff
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|
1111 dst = zcycles(dst, 1); |
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246
diff
changeset
|
1112 } |
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246
diff
changeset
|
1113 dst = btr_ir(dst, inst->immed, src_op.base, SZ_B); |
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246
diff
changeset
|
1114 if (inst->addr_mode != Z80_REG) { |
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246
diff
changeset
|
1115 dst = z80_save_result(dst, inst); |
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246
diff
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|
1116 } |
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1117 break; |
236
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235
diff
changeset
|
1118 case Z80_JP: { |
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235
diff
changeset
|
1119 cycles = 4; |
239
a5bea9711a46
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238
diff
changeset
|
1120 if (inst->addr_mode != Z80_REG) { |
236
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235
diff
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|
1121 cycles += 6; |
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235
diff
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|
1122 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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235
diff
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|
1123 cycles += 4; |
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235
diff
changeset
|
1124 } |
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235
diff
changeset
|
1125 dst = zcycles(dst, cycles); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1126 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) { |
236
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235
diff
changeset
|
1127 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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235
diff
changeset
|
1128 if (!call_dst) { |
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235
diff
changeset
|
1129 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
1130 //fake address to force large displacement |
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235
diff
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|
1131 call_dst = dst + 256; |
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235
diff
changeset
|
1132 } |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
1133 dst = jmp(dst, call_dst); |
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235
diff
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|
1134 } else { |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1135 if (inst->addr_mode == Z80_REG_INDIRECT) { |
236
19fb3523a9e5
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235
diff
changeset
|
1136 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W); |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
1137 } else { |
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235
diff
changeset
|
1138 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
1139 } |
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235
diff
changeset
|
1140 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
diff
changeset
|
1141 dst = jmp_r(dst, SCRATCH1); |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1142 } |
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Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
1143 break; |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1144 } |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1145 case Z80_JPCC: { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1146 dst = zcycles(dst, 7);//T States: 4,3 |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1147 uint8_t cond = CC_Z; |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
1148 switch (inst->reg) |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
1149 { |
19fb3523a9e5
Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
1150 case Z80_CC_NZ: |
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
changeset
|
1151 cond = CC_NZ; |
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Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
1152 case Z80_CC_Z: |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
1153 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1154 break; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1155 case Z80_CC_NC: |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
1156 cond = CC_NZ; |
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235
diff
changeset
|
1157 case Z80_CC_C: |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
1158 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
1159 break; |
238
827ebce557bf
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Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1160 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1161 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1162 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1163 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
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Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1164 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1165 case Z80_CC_P: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1166 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1167 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1168 break; |
236
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1169 } |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1170 uint8_t *no_jump_off = dst+1; |
19fb3523a9e5
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235
diff
changeset
|
1171 dst = jcc(dst, cond, dst+2); |
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235
diff
changeset
|
1172 dst = zcycles(dst, 5);//T States: 5 |
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235
diff
changeset
|
1173 uint16_t dest_addr = inst->immed; |
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235
diff
changeset
|
1174 if (dest_addr < 0x4000) { |
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235
diff
changeset
|
1175 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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235
diff
changeset
|
1176 if (!call_dst) { |
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235
diff
changeset
|
1177 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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parents:
235
diff
changeset
|
1178 //fake address to force large displacement |
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235
diff
changeset
|
1179 call_dst = dst + 256; |
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235
diff
changeset
|
1180 } |
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235
diff
changeset
|
1181 dst = jmp(dst, call_dst); |
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235
diff
changeset
|
1182 } else { |
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235
diff
changeset
|
1183 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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235
diff
changeset
|
1184 dst = call(dst, (uint8_t *)z80_native_addr); |
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235
diff
changeset
|
1185 dst = jmp_r(dst, SCRATCH1); |
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235
diff
changeset
|
1186 } |
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235
diff
changeset
|
1187 *no_jump_off = dst - (no_jump_off+1); |
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parents:
235
diff
changeset
|
1188 break; |
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parents:
235
diff
changeset
|
1189 } |
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235
diff
changeset
|
1190 case Z80_JR: { |
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235
diff
changeset
|
1191 dst = zcycles(dst, 12);//T States: 4,3,5 |
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235
diff
changeset
|
1192 uint16_t dest_addr = address + inst->immed + 2; |
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parents:
235
diff
changeset
|
1193 if (dest_addr < 0x4000) { |
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235
diff
changeset
|
1194 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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235
diff
changeset
|
1195 if (!call_dst) { |
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235
diff
changeset
|
1196 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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235
diff
changeset
|
1197 //fake address to force large displacement |
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235
diff
changeset
|
1198 call_dst = dst + 256; |
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235
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|
1199 } |
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1200 dst = jmp(dst, call_dst); |
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|
1201 } else { |
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1202 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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1203 dst = call(dst, (uint8_t *)z80_native_addr); |
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|
1204 dst = jmp_r(dst, SCRATCH1); |
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|
1205 } |
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changeset
|
1206 break; |
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diff
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|
1207 } |
235
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1208 case Z80_JRCC: { |
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1209 dst = zcycles(dst, 7);//T States: 4,3 |
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|
1210 uint8_t cond = CC_Z; |
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|
1211 switch (inst->reg) |
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|
1212 { |
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|
1213 case Z80_CC_NZ: |
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diff
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|
1214 cond = CC_NZ; |
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|
1215 case Z80_CC_Z: |
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1216 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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Get Z80 core working for simple programs
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|
1217 break; |
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|
1218 case Z80_CC_NC: |
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|
1219 cond = CC_NZ; |
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|
1220 case Z80_CC_C: |
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1221 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1222 break; |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1223 } |
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Get Z80 core working for simple programs
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changeset
|
1224 uint8_t *no_jump_off = dst+1; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1225 dst = jcc(dst, cond, dst+2); |
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Get Z80 core working for simple programs
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|
1226 dst = zcycles(dst, 5);//T States: 5 |
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Get Z80 core working for simple programs
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213
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|
1227 uint16_t dest_addr = address + inst->immed + 2; |
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213
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|
1228 if (dest_addr < 0x4000) { |
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Get Z80 core working for simple programs
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213
diff
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|
1229 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1230 if (!call_dst) { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1231 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1232 //fake address to force large displacement |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1233 call_dst = dst + 256; |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1234 } |
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diff
changeset
|
1235 dst = jmp(dst, call_dst); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1236 } else { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1237 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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Get Z80 core working for simple programs
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|
1238 dst = call(dst, (uint8_t *)z80_native_addr); |
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Get Z80 core working for simple programs
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213
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|
1239 dst = jmp_r(dst, SCRATCH1); |
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Get Z80 core working for simple programs
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213
diff
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|
1240 } |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1241 *no_jump_off = dst - (no_jump_off+1); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
1242 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1243 } |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
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|
1244 case Z80_DJNZ: |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1245 dst = zcycles(dst, 8);//T States: 5,3 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1246 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1247 uint8_t *no_jump_off = dst+1; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1248 dst = jcc(dst, CC_Z, dst+2); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
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|
1249 dst = zcycles(dst, 5);//T States: 5 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1250 uint16_t dest_addr = address + inst->immed + 2; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1251 if (dest_addr < 0x4000) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1252 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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diff
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|
1253 if (!call_dst) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1254 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1255 //fake address to force large displacement |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1256 call_dst = dst + 256; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1257 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1258 dst = jmp(dst, call_dst); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1259 } else { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1260 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1261 dst = call(dst, (uint8_t *)z80_native_addr); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1262 dst = jmp_r(dst, SCRATCH1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
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|
1263 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1264 *no_jump_off = dst - (no_jump_off+1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1265 break; |
235
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Get Z80 core working for simple programs
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213
diff
changeset
|
1266 case Z80_CALL: { |
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Get Z80 core working for simple programs
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diff
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|
1267 dst = zcycles(dst, 11);//T States: 4,3,4 |
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Get Z80 core working for simple programs
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diff
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|
1268 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
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252
diff
changeset
|
1269 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
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252
diff
changeset
|
1270 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
235
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|
1271 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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diff
changeset
|
1272 if (inst->immed < 0x4000) { |
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213
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|
1273 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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diff
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|
1274 if (!call_dst) { |
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213
diff
changeset
|
1275 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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diff
changeset
|
1276 //fake address to force large displacement |
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diff
changeset
|
1277 call_dst = dst + 256; |
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changeset
|
1278 } |
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changeset
|
1279 dst = jmp(dst, call_dst); |
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|
1280 } else { |
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changeset
|
1281 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
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|
1282 dst = call(dst, (uint8_t *)z80_native_addr); |
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|
1283 dst = jmp_r(dst, SCRATCH1); |
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|
1284 } |
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changeset
|
1285 break; |
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changeset
|
1286 } |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1287 case Z80_CALLCC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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diff
changeset
|
1288 dst = zcycles(dst, 10);//T States: 4,3,3 (false case) |
827ebce557bf
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|
1289 uint8_t cond = CC_Z; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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diff
changeset
|
1290 switch (inst->reg) |
827ebce557bf
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236
diff
changeset
|
1291 { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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diff
changeset
|
1292 case Z80_CC_NZ: |
827ebce557bf
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changeset
|
1293 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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changeset
|
1294 case Z80_CC_Z: |
827ebce557bf
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diff
changeset
|
1295 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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diff
changeset
|
1296 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1297 case Z80_CC_NC: |
827ebce557bf
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changeset
|
1298 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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diff
changeset
|
1299 case Z80_CC_C: |
827ebce557bf
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diff
changeset
|
1300 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
827ebce557bf
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diff
changeset
|
1301 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1302 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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diff
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|
1303 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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changeset
|
1304 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1305 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1306 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1307 case Z80_CC_P: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1308 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1309 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1310 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1311 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1312 uint8_t *no_call_off = dst+1; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1313 dst = jcc(dst, cond, dst+2); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1314 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1315 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1316 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1317 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1318 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1319 if (inst->immed < 0x4000) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1320 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1321 if (!call_dst) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1322 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1323 //fake address to force large displacement |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1324 call_dst = dst + 256; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1325 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1326 dst = jmp(dst, call_dst); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1327 } else { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1328 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1329 dst = call(dst, (uint8_t *)z80_native_addr); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1330 dst = jmp_r(dst, SCRATCH1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1331 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1332 *no_call_off = dst - (no_call_off+1); |
827ebce557bf
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Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1333 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1334 case Z80_RET: |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1335 dst = zcycles(dst, 4);//T States: 4 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1336 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1337 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1338 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1339 dst = call(dst, (uint8_t *)z80_native_addr); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1340 dst = jmp_r(dst, SCRATCH1); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1341 break; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1342 case Z80_RETCC: { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1343 dst = zcycles(dst, 5);//T States: 5 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1344 uint8_t cond = CC_Z; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1345 switch (inst->reg) |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1346 { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1347 case Z80_CC_NZ: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1348 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1349 case Z80_CC_Z: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1350 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1351 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1352 case Z80_CC_NC: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1353 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1354 case Z80_CC_C: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1355 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1356 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1357 case Z80_CC_PO: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1358 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1359 case Z80_CC_PE: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1360 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1361 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1362 case Z80_CC_P: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1363 case Z80_CC_M: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1364 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1365 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1366 } |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1367 uint8_t *no_call_off = dst+1; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1368 dst = jcc(dst, cond, dst+2); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1369 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1370 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1371 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1372 dst = call(dst, (uint8_t *)z80_native_addr); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1373 dst = jmp_r(dst, SCRATCH1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1374 *no_call_off = dst - (no_call_off+1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1375 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1376 } |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1377 case Z80_RETI: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1378 //For some systems, this may need a callback for signalling interrupt routine completion |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1379 dst = zcycles(dst, 8);//T States: 4, 4 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1380 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1381 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1382 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1383 dst = call(dst, (uint8_t *)z80_native_addr); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1384 dst = jmp_r(dst, SCRATCH1); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1385 break; |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1386 case Z80_RETN: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1387 dst = zcycles(dst, 8);//T States: 4, 4 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1388 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, iff2), SCRATCH2, SZ_B); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1389 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1390 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1391 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1392 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1393 dst = call(dst, (uint8_t *)z80_native_addr); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1394 dst = jmp_r(dst, SCRATCH1); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1395 break; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1396 case Z80_RST: { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1397 //RST is basically CALL to an address in page 0 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1398 dst = zcycles(dst, 5);//T States: 5 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1399 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1400 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1401 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1402 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1403 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1404 if (!call_dst) { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1405 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1406 //fake address to force large displacement |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1407 call_dst = dst + 256; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1408 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1409 dst = jmp(dst, call_dst); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1410 break; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1411 } |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1412 case Z80_IN: |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1413 dst = zcycles(dst, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1414 if (inst->addr_mode == Z80_IMMED_INDIRECT) { |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1415 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_B); |
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1416 } else { |
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|
1417 dst = mov_rr(dst, opts->regs[Z80_C], SCRATCH1, SZ_B); |
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|
1418 } |
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|
1419 dst = call(dst, (uint8_t *)z80_io_read); |
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|
1420 translate_z80_reg(inst, &dst_op, dst, opts); |
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|
1421 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
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|
1422 dst = z80_save_reg(dst, inst, opts); |
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283
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|
1423 break; |
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|
1424 /*case Z80_INI: |
213
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1425 case Z80_INIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1426 case Z80_IND: |
284
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|
1427 case Z80_INDR:*/ |
213
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1428 case Z80_OUT: |
284
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|
1429 dst = zcycles(dst, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
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|
1430 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) { |
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|
1431 dst = mov_ir(dst, inst->immed, SCRATCH2, SZ_B); |
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283
diff
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|
1432 } else { |
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Implement IN and OUT (untested)
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283
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|
1433 dst = mov_rr(dst, opts->regs[Z80_C], SCRATCH2, SZ_B); |
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|
1434 } |
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|
1435 translate_z80_reg(inst, &src_op, dst, opts); |
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|
1436 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
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|
1437 dst = call(dst, (uint8_t *)z80_io_write); |
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|
1438 dst = z80_save_reg(dst, inst, opts); |
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283
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|
1439 break; |
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|
1440 /*case Z80_OUTI: |
213
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1441 case Z80_OTIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1442 case Z80_OUTD: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1443 case Z80_OTDR:*/ |
235
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|
1444 default: { |
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|
1445 char disbuf[80]; |
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|
1446 z80_disasm(inst, disbuf); |
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|
1447 fprintf(stderr, "unimplemented instruction: %s\n", disbuf); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
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|
1448 FILE * f = fopen("zram.bin", "wb"); |
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Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
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|
1449 fwrite(context->mem_pointers[0], 1, 8 * 1024, f); |
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257
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|
1450 fclose(f); |
213
4d4559b04c59
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1451 exit(1); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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|
1452 } |
235
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|
1453 } |
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|
1454 return dst; |
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|
1455 } |
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|
1456 |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
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282
diff
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|
1457 uint8_t z80_is_terminal(z80inst * inst) |
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Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
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|
1458 { |
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Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
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282
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|
1459 return inst->op == Z80_RET || inst->op == Z80_RETI || inst->op == Z80_RETN || inst->op == Z80_JP |
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282
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|
1460 || inst->op == Z80_JR || inst->op == Z80_HALT || (inst->op == Z80_NOP && inst->immed == 42); |
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|
1461 } |
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Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
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|
1462 |
235
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|
1463 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
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|
1464 { |
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|
1465 native_map_slot *map; |
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|
1466 if (address < 0x4000) { |
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|
1467 address &= 0x1FFF; |
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|
1468 map = context->static_code_map; |
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|
1469 } else if (address >= 0x8000) { |
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Get Z80 core working for simple programs
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|
1470 address &= 0x7FFF; |
279
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277
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|
1471 map = context->banked_code_map + context->bank_reg; |
235
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|
1472 } else { |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
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267
diff
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|
1473 dprintf("z80_get_native_address: %X NULL\n", address); |
235
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|
1474 return NULL; |
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|
1475 } |
268
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Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
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changeset
|
1476 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET || map->offsets[address] == EXTENSION_WORD) { |
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|
1477 dprintf("z80_get_native_address: %X NULL\n", address); |
235
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|
1478 return NULL; |
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|
1479 } |
268
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|
1480 dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]); |
235
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1481 return map->base + map->offsets[address]; |
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|
1482 } |
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|
1483 |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1484 uint8_t z80_get_native_inst_size(x86_z80_options * opts, uint32_t address) |
235
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|
1485 { |
252
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|
1486 if (address >= 0x4000) { |
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|
1487 return 0; |
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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1488 } |
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|
1489 return opts->ram_inst_sizes[address & 0x1FFF]; |
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|
1490 } |
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1491 |
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|
1492 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
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1493 { |
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|
1494 uint32_t orig_address = address; |
235
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|
1495 native_map_slot *map; |
252
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|
1496 x86_z80_options * opts = context->options; |
235
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|
1497 if (address < 0x4000) { |
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|
1498 address &= 0x1FFF; |
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|
1499 map = context->static_code_map; |
252
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|
1500 opts->ram_inst_sizes[address] = native_size; |
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1501 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7); |
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|
1502 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7); |
235
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1503 } else if (address >= 0x8000) { |
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|
1504 address &= 0x7FFF; |
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|
1505 map = context->banked_code_map + context->bank_reg; |
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1506 if (!map->offsets) { |
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1507 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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|
1508 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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|
1509 } |
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|
1510 } else { |
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|
1511 return; |
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|
1512 } |
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1513 if (!map->base) { |
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1514 map->base = native_address; |
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1515 } |
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1516 map->offsets[address] = native_address - map->base; |
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|
1517 for(--size, orig_address++; size; --size, orig_address++) { |
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|
1518 address = orig_address; |
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|
1519 if (address < 0x4000) { |
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1520 address &= 0x1FFF; |
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changeset
|
1521 map = context->static_code_map; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1522 } else if (address >= 0x8000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1523 address &= 0x7FFF; |
279
6be6056735a9
Fix native address lookup in bannked memory area
Mike Pavone <pavone@retrodev.com>
parents:
277
diff
changeset
|
1524 map = context->banked_code_map + context->bank_reg; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1525 } else { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1526 return; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1527 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1528 if (!map->offsets) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1529 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1530 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1531 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1532 map->offsets[address] = EXTENSION_WORD; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1533 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1534 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1535 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1536 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1537 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1538 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1539 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1540 if (!static_code_map->base || address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1541 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1542 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1543 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1544 if (static_code_map->offsets[address] == INVALID_OFFSET) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1545 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1546 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1547 while (static_code_map->offsets[address] == EXTENSION_WORD) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1548 --address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1549 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1550 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1551 return address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1552 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1553 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1554 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1555 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1556 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1557 if (inst_start != INVALID_INSTRUCTION_START) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1558 uint8_t * dst = z80_get_native_address(context, inst_start); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1559 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", dst, inst_start, address); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1560 dst = mov_ir(dst, inst_start, SCRATCH1, SZ_D); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1561 dst = jmp(dst, (uint8_t *)z80_retrans_stub); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1562 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1563 return context; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1564 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1565 |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1566 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1567 { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1568 uint8_t * addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1569 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1570 translate_z80_stream(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1571 addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1572 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1573 printf("Failed to translate %X to native code\n", address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1574 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1575 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1576 return addr; |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1577 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1578 |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1579 void z80_handle_deferred(z80_context * context) |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1580 { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1581 x86_z80_options * opts = context->options; |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1582 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1583 if (opts->deferred) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1584 translate_z80_stream(context, opts->deferred->address); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1585 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1586 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1587 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1588 void * z80_retranslate_inst(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1589 { |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1590 char disbuf[80]; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1591 x86_z80_options * opts = context->options; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1592 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1593 uint8_t * orig_start = z80_get_native_address(context, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1594 uint32_t orig = address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1595 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1596 uint8_t * dst = opts->cur_code; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1597 uint8_t * dst_end = opts->code_end; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1598 uint8_t *after, *inst = context->mem_pointers[0] + address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1599 z80inst instbuf; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1600 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1601 after = z80_decode(inst, &instbuf); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1602 #ifdef DO_DEBUG_PRINT |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
1603 z80_disasm(&instbuf, disbuf); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1604 if (instbuf.op == Z80_NOP) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1605 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1606 } else { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1607 printf("%X\t%s\n", address, disbuf); |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
1608 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1609 #endif |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1610 if (orig_size != ZMAX_NATIVE_SIZE) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1611 if (dst_end - dst < ZMAX_NATIVE_SIZE) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1612 size_t size = 1024*1024; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1613 dst = alloc_code(&size); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1614 opts->code_end = dst_end = dst + size; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1615 opts->cur_code = dst; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1616 } |
282
7b8a49220e3b
Remove deferred address entries from abandoned translations inside z80_retrans_inst
Mike Pavone <pavone@retrodev.com>
parents:
279
diff
changeset
|
1617 deferred_addr * orig_deferred = opts->deferred; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1618 uint8_t * native_end = translate_z80inst(&instbuf, dst, context, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1619 if ((native_end - dst) <= orig_size) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1620 uint8_t * native_next = z80_get_native_address(context, address + after-inst); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1621 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) { |
282
7b8a49220e3b
Remove deferred address entries from abandoned translations inside z80_retrans_inst
Mike Pavone <pavone@retrodev.com>
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279
diff
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|
1622 remove_deferred_until(&opts->deferred, orig_deferred); |
264
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1623 native_end = translate_z80inst(&instbuf, orig_start, context, address); |
266
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Fix some more retranslation bugs in the Z80 core
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264
diff
changeset
|
1624 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
264
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Fix a crash bug in instruction retranslation
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262
diff
changeset
|
1625 while (native_end < orig_start + orig_size) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
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parents:
262
diff
changeset
|
1626 *(native_end++) = 0x90; //NOP |
8fd6652e56f8
Fix a crash bug in instruction retranslation
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262
diff
changeset
|
1627 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
changeset
|
1628 } else { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
changeset
|
1629 jmp(native_end, native_next); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
changeset
|
1630 } |
266
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Fix some more retranslation bugs in the Z80 core
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parents:
264
diff
changeset
|
1631 z80_handle_deferred(context); |
264
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
changeset
|
1632 return orig_start; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1633 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1634 } |
264
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
changeset
|
1635 z80_map_native_address(context, address, dst, after-inst, ZMAX_NATIVE_SIZE); |
266
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Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
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264
diff
changeset
|
1636 opts->cur_code = dst+ZMAX_NATIVE_SIZE; |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1637 jmp(orig_start, dst); |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
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282
diff
changeset
|
1638 if (!z80_is_terminal(&instbuf)) { |
264
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Fix a crash bug in instruction retranslation
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262
diff
changeset
|
1639 jmp(native_end, z80_get_native_address_trans(context, address + after-inst)); |
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Fix a crash bug in instruction retranslation
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262
diff
changeset
|
1640 } |
266
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Fix some more retranslation bugs in the Z80 core
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264
diff
changeset
|
1641 z80_handle_deferred(context); |
264
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Fix a crash bug in instruction retranslation
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262
diff
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|
1642 return dst; |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1643 } else { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1644 dst = translate_z80inst(&instbuf, orig_start, context, address); |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
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282
diff
changeset
|
1645 if (!z80_is_terminal(&instbuf)) { |
264
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Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
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262
diff
changeset
|
1646 dst = jmp(dst, z80_get_native_address_trans(context, address + after-inst)); |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1647 } |
266
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Fix some more retranslation bugs in the Z80 core
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264
diff
changeset
|
1648 z80_handle_deferred(context); |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1649 return orig_start; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1650 } |
235
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213
diff
changeset
|
1651 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1652 |
d9bf8e61c33c
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diff
changeset
|
1653 void translate_z80_stream(z80_context * context, uint32_t address) |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1654 { |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1655 char disbuf[80]; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1656 if (z80_get_native_address(context, address)) { |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1657 return; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1658 } |
d9bf8e61c33c
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213
diff
changeset
|
1659 x86_z80_options * opts = context->options; |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1660 uint8_t * encoded = NULL, *next; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1661 if (address < 0x4000) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1662 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
1663 } else if(address >= 0x8000 && context->mem_pointers[1]) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1664 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1665 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1666 while (encoded != NULL) |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1667 { |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1668 z80inst inst; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
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267
diff
changeset
|
1669 dprintf("translating Z80 code at address %X\n", address); |
235
d9bf8e61c33c
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213
diff
changeset
|
1670 do { |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1671 if (opts->code_end-opts->cur_code < ZMAX_NATIVE_SIZE) { |
235
d9bf8e61c33c
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213
diff
changeset
|
1672 if (opts->code_end-opts->cur_code < 5) { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
1673 puts("out of code memory, not enough space for jmp to next chunk"); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1674 exit(1); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1675 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
1676 size_t size = 1024*1024; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1677 opts->cur_code = alloc_code(&size); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1678 opts->code_end = opts->cur_code + size; |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1679 jmp(opts->cur_code, opts->cur_code); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1680 } |
255
572b935dd030
Properly handle wrapping around to 0 in translate_z80_stream
Mike Pavone <pavone@retrodev.com>
parents:
254
diff
changeset
|
1681 if (address > 0x4000 && address < 0x8000) { |
235
d9bf8e61c33c
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213
diff
changeset
|
1682 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1683 opts->cur_code = call(opts->cur_code, (uint8_t *)exit); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1684 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1685 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1686 uint8_t * existing = z80_get_native_address(context, address); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1687 if (existing) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1688 opts->cur_code = jmp(opts->cur_code, existing); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1689 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1690 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1691 next = z80_decode(encoded, &inst); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
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267
diff
changeset
|
1692 #ifdef DO_DEBUG_PRINT |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1693 z80_disasm(&inst, disbuf); |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1694 if (inst.op == Z80_NOP) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1695 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1696 } else { |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1697 printf("%X\t%s\n", address, disbuf); |
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Get Z80 core working for simple programs
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213
diff
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|
1698 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
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267
diff
changeset
|
1699 #endif |
248
9c7a3db7bcd0
Implement ADC and SBC in Z80 core (untested)
Mike Pavone <pavone@retrodev.com>
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247
diff
changeset
|
1700 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address); |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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diff
changeset
|
1701 z80_map_native_address(context, address, opts->cur_code, next-encoded, after - opts->cur_code); |
248
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Implement ADC and SBC in Z80 core (untested)
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|
1702 opts->cur_code = after; |
235
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213
diff
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|
1703 address += next-encoded; |
255
572b935dd030
Properly handle wrapping around to 0 in translate_z80_stream
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254
diff
changeset
|
1704 if (address > 0xFFFF) { |
572b935dd030
Properly handle wrapping around to 0 in translate_z80_stream
Mike Pavone <pavone@retrodev.com>
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diff
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|
1705 address &= 0xFFFF; |
572b935dd030
Properly handle wrapping around to 0 in translate_z80_stream
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diff
changeset
|
1706 |
572b935dd030
Properly handle wrapping around to 0 in translate_z80_stream
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diff
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|
1707 } else { |
572b935dd030
Properly handle wrapping around to 0 in translate_z80_stream
Mike Pavone <pavone@retrodev.com>
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254
diff
changeset
|
1708 encoded = next; |
572b935dd030
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diff
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|
1709 } |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
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diff
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|
1710 } while (!z80_is_terminal(&inst)); |
235
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|
1711 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
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diff
changeset
|
1712 if (opts->deferred) { |
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diff
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|
1713 address = opts->deferred->address; |
268
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|
1714 dprintf("defferred address: %X\n", address); |
235
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|
1715 if (address < 0x4000) { |
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|
1716 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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|
1717 } else if (address > 0x8000 && context->mem_pointers[1]) { |
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changeset
|
1718 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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changeset
|
1719 } else { |
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diff
changeset
|
1720 printf("attempt to translate non-memory address: %X\n", address); |
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changeset
|
1721 exit(1); |
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diff
changeset
|
1722 } |
d9bf8e61c33c
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213
diff
changeset
|
1723 } else { |
d9bf8e61c33c
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diff
changeset
|
1724 encoded = NULL; |
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diff
changeset
|
1725 } |
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diff
changeset
|
1726 } |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
1727 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
1728 |
235
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changeset
|
1729 void init_x86_z80_opts(x86_z80_options * options) |
213
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
1730 { |
235
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diff
changeset
|
1731 options->flags = 0; |
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diff
changeset
|
1732 options->regs[Z80_B] = BH; |
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1733 options->regs[Z80_C] = RBX; |
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1734 options->regs[Z80_D] = CH; |
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1735 options->regs[Z80_E] = RCX; |
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1736 options->regs[Z80_H] = AH; |
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1737 options->regs[Z80_L] = RAX; |
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1738 options->regs[Z80_IXH] = DH; |
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1739 options->regs[Z80_IXL] = RDX; |
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1740 options->regs[Z80_IYH] = -1; |
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1741 options->regs[Z80_IYL] = R8; |
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1742 options->regs[Z80_I] = -1; |
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1743 options->regs[Z80_R] = -1; |
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1744 options->regs[Z80_A] = R10; |
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1745 options->regs[Z80_BC] = RBX; |
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1746 options->regs[Z80_DE] = RCX; |
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1747 options->regs[Z80_HL] = RAX; |
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1748 options->regs[Z80_SP] = R9; |
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1749 options->regs[Z80_AF] = -1; |
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1750 options->regs[Z80_IX] = RDX; |
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1751 options->regs[Z80_IY] = R8; |
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1752 size_t size = 1024 * 1024; |
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1753 options->cur_code = alloc_code(&size); |
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1754 options->code_end = options->cur_code + size; |
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1755 options->ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000); |
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1756 memset(options->ram_inst_sizes, 0, sizeof(uint8_t) * 0x2000); |
235
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1757 options->deferred = NULL; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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1758 } |
235
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1759 |
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1760 void init_z80_context(z80_context * context, x86_z80_options * options) |
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1761 { |
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1762 memset(context, 0, sizeof(*context)); |
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1763 context->static_code_map = malloc(sizeof(context->static_code_map)); |
259
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1764 context->static_code_map->base = NULL; |
235
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1765 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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1766 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
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1767 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9)); |
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1768 memset(context->banked_code_map, 0, sizeof(native_map_slot) * (1 << 9)); |
235
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1769 context->options = options; |
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1770 } |
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1771 |
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1772 void z80_reset(z80_context * context) |
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1773 { |
259
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1774 context->im = 0; |
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1775 context->iff1 = context->iff2 = 0; |
235
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1776 context->native_pc = z80_get_native_address_trans(context, 0); |
268
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Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
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1777 context->extra_pc = NULL; |
235
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1778 } |
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1779 |
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1780 |