Mercurial > repos > blastem
annotate z80_to_x86.c @ 345:29d2ca563499
Don't sync the 68K clock to the VDP clock unless the 68K had to wait for the VDP. This unfortunately breaks the direct color DMA demos, but should be more correct overall.
author | Mike Pavone <pavone@retrodev.com> |
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date | Sun, 19 May 2013 13:47:47 -0700 |
parents | 14a937097c2b |
children | c42fae88d346 |
rev | line source |
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1 #include "z80inst.h" |
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2 #include "z80_to_x86.h" |
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3 #include "gen_x86.h" |
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4 #include "mem.h" |
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5 #include <stdio.h> |
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6 #include <stdlib.h> |
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7 #include <stddef.h> |
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8 #include <string.h> |
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9 |
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10 #define MODE_UNUSED (MODE_IMMED-1) |
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11 |
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12 #define ZCYCLES RBP |
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13 #define ZLIMIT RDI |
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14 #define SCRATCH1 R13 |
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15 #define SCRATCH2 R14 |
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16 #define CONTEXT RSI |
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17 |
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18 //#define DO_DEBUG_PRINT |
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19 |
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20 #ifdef DO_DEBUG_PRINT |
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21 #define dprintf printf |
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22 #else |
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23 #define dprintf |
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24 #endif |
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25 |
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26 void z80_read_byte(); |
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27 void z80_read_word(); |
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28 void z80_write_byte(); |
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29 void z80_write_word_highfirst(); |
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30 void z80_write_word_lowfirst(); |
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31 void z80_save_context(); |
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32 void z80_native_addr(); |
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33 void z80_do_sync(); |
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34 void z80_handle_cycle_limit_int(); |
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35 void z80_retrans_stub(); |
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36 void z80_io_read(); |
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37 void z80_io_write(); |
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38 void z80_halt(); |
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39 |
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40 uint8_t z80_size(z80inst * inst) |
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41 { |
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42 uint8_t reg = (inst->reg & 0x1F); |
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43 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) { |
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44 return reg < Z80_BC ? SZ_B : SZ_W; |
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45 } |
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46 //TODO: Handle any necessary special cases |
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47 return SZ_B; |
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48 } |
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49 |
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50 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles) |
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51 { |
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52 return add_ir(dst, num_cycles, ZCYCLES, SZ_D); |
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53 } |
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54 |
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55 uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address) |
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56 { |
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57 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D); |
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58 uint8_t * jmp_off = dst+1; |
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59 dst = jcc(dst, CC_NC, dst + 7); |
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60 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
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61 dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int); |
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62 *jmp_off = dst - (jmp_off+1); |
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63 return dst; |
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64 } |
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65 |
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66 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts) |
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67 { |
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68 if (inst->reg == Z80_USE_IMMED) { |
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69 ea->mode = MODE_IMMED; |
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70 ea->disp = inst->immed; |
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71 } else if ((inst->reg & 0x1F) == Z80_UNUSED) { |
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72 ea->mode = MODE_UNUSED; |
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73 } else { |
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74 ea->mode = MODE_REG_DIRECT; |
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75 if (inst->reg == Z80_IYH) { |
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76 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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77 dst = mov_rr(dst, opts->regs[Z80_IY], SCRATCH1, SZ_W); |
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78 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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79 ea->base = SCRATCH1; |
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80 } else { |
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81 ea->base = opts->regs[Z80_IYL]; |
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82 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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83 } |
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84 } else if(opts->regs[inst->reg] >= 0) { |
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85 ea->base = opts->regs[inst->reg]; |
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86 if (ea->base >= AH && ea->base <= BH) { |
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87 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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88 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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89 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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90 //we can't mix an *H reg with a register that requires the REX prefix |
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91 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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92 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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93 } |
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94 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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95 //temp regs require REX prefix too |
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96 ea->base = opts->regs[z80_low_reg(inst->reg)]; |
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97 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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98 } |
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99 } |
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100 } else { |
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101 ea->mode = MODE_REG_DISPLACE8; |
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102 ea->base = CONTEXT; |
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103 ea->disp = offsetof(z80_context, regs) + inst->reg; |
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104 } |
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105 } |
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106 return dst; |
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107 } |
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108 |
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109 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
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110 { |
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111 if (inst->reg == Z80_IYH) { |
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112 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) { |
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113 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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114 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_IYL], SZ_B); |
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115 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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116 } else { |
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117 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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118 } |
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119 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) { |
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120 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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121 uint8_t other_reg = opts->regs[inst->ea_reg]; |
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122 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
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123 //we can't mix an *H reg with a register that requires the REX prefix |
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124 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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125 } |
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126 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) { |
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127 //temp regs require REX prefix too |
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128 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W); |
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129 } |
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130 } |
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131 return dst; |
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132 } |
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133 |
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134 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify) |
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135 { |
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136 uint8_t size, reg, areg; |
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137 ea->mode = MODE_REG_DIRECT; |
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138 areg = read ? SCRATCH1 : SCRATCH2; |
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139 switch(inst->addr_mode & 0x1F) |
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140 { |
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141 case Z80_REG: |
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142 if (inst->ea_reg == Z80_IYH) { |
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143 if (inst->reg == Z80_IYL) { |
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144 dst = mov_rr(dst, opts->regs[Z80_IY], SCRATCH1, SZ_W); |
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145 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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146 ea->base = SCRATCH1; |
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147 } else { |
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148 ea->base = opts->regs[Z80_IYL]; |
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149 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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150 } |
213
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151 } else { |
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152 ea->base = opts->regs[inst->ea_reg]; |
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153 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) { |
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154 uint8_t other_reg = opts->regs[inst->reg]; |
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155 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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156 //we can't mix an *H reg with a register that requires the REX prefix |
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157 ea->base = opts->regs[z80_low_reg(inst->ea_reg)]; |
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158 dst = ror_ir(dst, 8, ea->base, SZ_W); |
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159 } |
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160 } |
213
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161 } |
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162 break; |
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163 case Z80_REG_INDIRECT: |
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164 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W); |
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165 size = z80_size(inst); |
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166 if (read) { |
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167 if (modify) { |
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168 //dst = push_r(dst, SCRATCH1); |
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169 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(z80_context, scratch1), SZ_W); |
213
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170 } |
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171 if (size == SZ_B) { |
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172 dst = call(dst, (uint8_t *)z80_read_byte); |
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173 } else { |
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174 dst = call(dst, (uint8_t *)z80_read_word); |
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175 } |
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176 if (modify) { |
277
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177 //dst = pop_r(dst, SCRATCH2); |
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178 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, scratch1), SCRATCH2, SZ_W); |
213
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179 } |
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180 } |
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181 ea->base = SCRATCH1; |
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182 break; |
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183 case Z80_IMMED: |
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184 ea->mode = MODE_IMMED; |
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185 ea->disp = inst->immed; |
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186 break; |
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187 case Z80_IMMED_INDIRECT: |
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188 dst = mov_ir(dst, inst->immed, areg, SZ_W); |
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189 size = z80_size(inst); |
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190 if (read) { |
277
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191 /*if (modify) { |
213
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192 dst = push_r(dst, SCRATCH1); |
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193 }*/ |
213
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194 if (size == SZ_B) { |
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195 dst = call(dst, (uint8_t *)z80_read_byte); |
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196 } else { |
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197 dst = call(dst, (uint8_t *)z80_read_word); |
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198 } |
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199 if (modify) { |
277
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200 //dst = pop_r(dst, SCRATCH2); |
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201 dst = mov_ir(dst, inst->immed, SCRATCH2, SZ_W); |
213
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202 } |
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203 } |
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204 ea->base = SCRATCH1; |
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205 break; |
235
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206 case Z80_IX_DISPLACE: |
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207 case Z80_IY_DISPLACE: |
300
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208 reg = opts->regs[(inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY]; |
213
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209 dst = mov_rr(dst, reg, areg, SZ_W); |
306
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210 dst = add_ir(dst, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W); |
213
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211 size = z80_size(inst); |
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212 if (read) { |
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213 if (modify) { |
277
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214 //dst = push_r(dst, SCRATCH1); |
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215 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(z80_context, scratch1), SZ_W); |
213
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216 } |
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217 if (size == SZ_B) { |
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218 dst = call(dst, (uint8_t *)z80_read_byte); |
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219 } else { |
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220 dst = call(dst, (uint8_t *)z80_read_word); |
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221 } |
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222 if (modify) { |
277
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223 //dst = pop_r(dst, SCRATCH2); |
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224 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, scratch1), SCRATCH2, SZ_W); |
213
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225 } |
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226 } |
269
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227 ea->base = SCRATCH1; |
213
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228 break; |
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229 case Z80_UNUSED: |
235
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230 ea->mode = MODE_UNUSED; |
213
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231 break; |
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232 default: |
300
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233 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F); |
213
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234 exit(1); |
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235 } |
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236 return dst; |
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237 } |
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238 |
235
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239 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts) |
213
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240 { |
267
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241 if ((inst->addr_mode & 0x1F) == Z80_REG) { |
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242 if (inst->ea_reg == Z80_IYH) { |
312
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311
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243 if (inst->reg == Z80_IYL) { |
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244 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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245 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_IYL], SZ_B); |
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246 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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247 } else { |
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248 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W); |
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249 } |
267
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250 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
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251 uint8_t other_reg = opts->regs[inst->reg]; |
269
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252 if (other_reg >= R8 || (other_reg >= RSP && other_reg <= RDI)) { |
267
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253 //we can't mix an *H reg with a register that requires the REX prefix |
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254 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W); |
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255 } |
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256 } |
213
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257 } |
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258 return dst; |
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259 } |
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260 |
235
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261 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst) |
213
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262 { |
253
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263 switch(inst->addr_mode & 0x1f) |
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264 { |
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265 case Z80_REG_INDIRECT: |
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266 case Z80_IMMED_INDIRECT: |
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267 case Z80_IX_DISPLACE: |
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268 case Z80_IY_DISPLACE: |
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269 if (z80_size(inst) == SZ_B) { |
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270 dst = call(dst, (uint8_t *)z80_write_byte); |
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271 } else { |
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272 dst = call(dst, (uint8_t *)z80_write_word_lowfirst); |
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273 } |
213
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|
274 } |
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275 return dst; |
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276 } |
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277 |
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|
278 enum { |
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279 DONT_READ=0, |
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|
280 READ |
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|
281 }; |
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282 |
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|
283 enum { |
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284 DONT_MODIFY=0, |
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|
285 MODIFY |
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286 }; |
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|
287 |
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|
288 uint8_t zf_off(uint8_t flag) |
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289 { |
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290 return offsetof(z80_context, flags) + flag; |
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291 } |
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|
292 |
241
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293 uint8_t zaf_off(uint8_t flag) |
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239
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|
294 { |
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295 return offsetof(z80_context, alt_flags) + flag; |
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239
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296 } |
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297 |
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298 uint8_t zar_off(uint8_t reg) |
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239
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299 { |
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300 return offsetof(z80_context, alt_regs) + reg; |
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301 } |
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302 |
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303 void z80_print_regs_exit(z80_context * context) |
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304 { |
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305 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n", |
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306 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C], |
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307 context->regs[Z80_D], context->regs[Z80_E], |
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308 (context->regs[Z80_H] << 8) | context->regs[Z80_L], |
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309 (context->regs[Z80_IXH] << 8) | context->regs[Z80_IXL], |
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310 (context->regs[Z80_IYH] << 8) | context->regs[Z80_IYL], |
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311 context->sp, context->im, context->iff1, context->iff2); |
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312 puts("--Alternate Regs--"); |
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313 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n", |
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314 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C], |
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315 context->alt_regs[Z80_D], context->alt_regs[Z80_E], |
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316 (context->alt_regs[Z80_H] << 8) | context->alt_regs[Z80_L], |
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317 (context->alt_regs[Z80_IXH] << 8) | context->alt_regs[Z80_IXL], |
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318 (context->alt_regs[Z80_IYH] << 8) | context->alt_regs[Z80_IYL]); |
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319 exit(0); |
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320 } |
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321 |
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322 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address) |
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323 { |
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324 uint32_t cycles; |
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325 x86_ea src_op, dst_op; |
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326 uint8_t size; |
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327 x86_z80_options *opts = context->options; |
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328 uint8_t * start = dst; |
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329 dst = z80_check_cycles_int(dst, address); |
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330 switch(inst->op) |
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331 { |
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332 case Z80_LD: |
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333 size = z80_size(inst); |
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334 switch (inst->addr_mode & 0x1F) |
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335 { |
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336 case Z80_REG: |
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337 case Z80_REG_INDIRECT: |
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338 cycles = size == SZ_B ? 4 : 6; |
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339 if (inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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340 cycles += 4; |
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341 } |
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342 break; |
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343 case Z80_IMMED: |
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344 cycles = size == SZ_B ? 7 : 10; |
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345 break; |
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346 case Z80_IMMED_INDIRECT: |
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347 cycles = 10; |
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348 break; |
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349 case Z80_IX_DISPLACE: |
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350 case Z80_IY_DISPLACE: |
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351 cycles = 12; |
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352 break; |
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353 } |
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354 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) || inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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355 cycles += 4; |
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356 } |
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357 dst = zcycles(dst, cycles); |
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358 if (inst->addr_mode & Z80_DIR) { |
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359 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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360 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY); |
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361 } else { |
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362 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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363 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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364 } |
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365 if (src_op.mode == MODE_REG_DIRECT) { |
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366 if(dst_op.mode == MODE_REG_DISPLACE8) { |
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367 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size); |
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368 } else { |
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369 dst = mov_rr(dst, src_op.base, dst_op.base, size); |
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370 } |
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371 } else if(src_op.mode == MODE_IMMED) { |
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372 dst = mov_ir(dst, src_op.disp, dst_op.base, size); |
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373 } else { |
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374 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size); |
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375 } |
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376 dst = z80_save_reg(dst, inst, opts); |
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377 dst = z80_save_ea(dst, inst, opts); |
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378 if (inst->addr_mode & Z80_DIR) { |
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379 dst = z80_save_result(dst, inst); |
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380 } |
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381 break; |
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382 case Z80_PUSH: |
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383 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 9 : 5); |
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384 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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385 if (inst->reg == Z80_AF) { |
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386 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH1, SZ_B); |
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387 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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388 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH1, SZ_B); |
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389 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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390 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH1, SZ_B); |
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391 dst = shl_ir(dst, 2, SCRATCH1, SZ_B); |
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392 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH1, SZ_B); |
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393 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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394 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH1, SZ_B); |
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395 dst = shl_ir(dst, 1, SCRATCH1, SZ_B); |
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396 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH1, SZ_B); |
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397 dst = shl_ir(dst, 8, SCRATCH1, SZ_W); |
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398 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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399 } else { |
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400 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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401 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W); |
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402 } |
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403 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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404 dst = call(dst, (uint8_t *)z80_write_word_highfirst); |
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405 //no call to save_z80_reg needed since there's no chance we'll use the only |
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406 //the upper half of a register pair |
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407 break; |
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408 case Z80_POP: |
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409 dst = zcycles(dst, (inst->reg == Z80_IX || inst->reg == Z80_IY) ? 8 : 4); |
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410 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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411 dst = call(dst, (uint8_t *)z80_read_word); |
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412 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
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413 if (inst->reg == Z80_AF) { |
294 | 414 |
415 dst = bt_ir(dst, 0, SCRATCH1, SZ_W); | |
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416 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
294 | 417 dst = bt_ir(dst, 1, SCRATCH1, SZ_W); |
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418 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N)); |
294 | 419 dst = bt_ir(dst, 2, SCRATCH1, SZ_W); |
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420 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV)); |
294 | 421 dst = bt_ir(dst, 4, SCRATCH1, SZ_W); |
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422 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H)); |
294 | 423 dst = bt_ir(dst, 6, SCRATCH1, SZ_W); |
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424 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z)); |
294 | 425 dst = bt_ir(dst, 7, SCRATCH1, SZ_W); |
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426 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S)); |
294 | 427 dst = shr_ir(dst, 8, SCRATCH1, SZ_W); |
428 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); | |
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429 } else { |
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430 dst = translate_z80_reg(inst, &src_op, dst, opts); |
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431 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W); |
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432 } |
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433 //no call to save_z80_reg needed since there's no chance we'll use the only |
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434 //the upper half of a register pair |
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435 break; |
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436 case Z80_EX: |
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437 if (inst->addr_mode == Z80_REG || inst->reg == Z80_HL) { |
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438 cycles = 4; |
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439 } else { |
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440 cycles = 8; |
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441 } |
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442 dst = zcycles(dst, cycles); |
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443 if (inst->addr_mode == Z80_REG) { |
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444 if(inst->reg == Z80_AF) { |
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445 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B); |
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446 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B); |
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447 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B); |
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448 |
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449 //Flags are currently word aligned, so we can move |
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450 //them efficiently a word at a time |
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451 for (int f = ZF_C; f < ZF_NUM; f+=2) { |
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452 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W); |
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453 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W); |
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454 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W); |
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455 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zf_off(f), SZ_W); |
241
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456 } |
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457 } else { |
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458 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W); |
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459 } |
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460 } else { |
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461 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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462 dst = call(dst, (uint8_t *)z80_read_byte); |
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463 dst = xchg_rr(dst, opts->regs[inst->reg], SCRATCH1, SZ_B); |
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464 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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465 dst = call(dst, (uint8_t *)z80_write_byte); |
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466 dst = zcycles(dst, 1); |
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467 uint8_t high_reg = z80_high_reg(inst->reg); |
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468 uint8_t use_reg; |
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469 //even though some of the upper halves can be used directly |
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470 //the limitations on mixing *H regs with the REX prefix |
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471 //prevent us from taking advantage of it |
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472 use_reg = opts->regs[inst->reg]; |
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473 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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474 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
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475 dst = add_ir(dst, 1, SCRATCH1, SZ_W); |
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476 dst = call(dst, (uint8_t *)z80_read_byte); |
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477 dst = xchg_rr(dst, use_reg, SCRATCH1, SZ_B); |
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478 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
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479 dst = add_ir(dst, 1, SCRATCH2, SZ_W); |
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480 dst = call(dst, (uint8_t *)z80_write_byte); |
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481 //restore reg to normal rotation |
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482 dst = ror_ir(dst, 8, use_reg, SZ_W); |
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483 dst = zcycles(dst, 2); |
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484 } |
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485 break; |
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486 case Z80_EXX: |
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487 dst = zcycles(dst, 4); |
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488 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W); |
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489 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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490 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W); |
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491 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W); |
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492 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W); |
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493 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W); |
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494 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W); |
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495 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W); |
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496 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W); |
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497 break; |
272 | 498 case Z80_LDI: { |
499 dst = zcycles(dst, 8); | |
500 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
501 dst = call(dst, (uint8_t *)z80_read_byte); | |
502 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
503 dst = call(dst, (uint8_t *)z80_read_byte); | |
504 dst = zcycles(dst, 2); | |
505 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
506 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
507 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
508 //TODO: Implement half-carry | |
509 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
510 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
511 break; | |
512 } | |
261
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513 case Z80_LDIR: { |
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514 dst = zcycles(dst, 8); |
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515 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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516 dst = call(dst, (uint8_t *)z80_read_byte); |
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517 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); |
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518 dst = call(dst, (uint8_t *)z80_read_byte); |
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519 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W); |
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520 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W); |
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521 |
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522 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); |
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523 uint8_t * cont = dst+1; |
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524 dst = jcc(dst, CC_Z, dst+2); |
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525 dst = zcycles(dst, 7); |
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526 //TODO: Figure out what the flag state should be here |
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527 //TODO: Figure out whether an interrupt can interrupt this |
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528 dst = jmp(dst, start); |
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529 *cont = dst - (cont + 1); |
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530 dst = zcycles(dst, 2); |
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531 //TODO: Implement half-carry |
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532 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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533 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
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534 break; |
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535 } |
273 | 536 case Z80_LDD: { |
537 dst = zcycles(dst, 8); | |
538 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
539 dst = call(dst, (uint8_t *)z80_read_byte); | |
540 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
541 dst = call(dst, (uint8_t *)z80_read_byte); | |
542 dst = zcycles(dst, 2); | |
543 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
544 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
545 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
546 //TODO: Implement half-carry | |
547 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
548 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV)); | |
549 break; | |
550 } | |
551 case Z80_LDDR: { | |
552 dst = zcycles(dst, 8); | |
553 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
554 dst = call(dst, (uint8_t *)z80_read_byte); | |
555 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W); | |
556 dst = call(dst, (uint8_t *)z80_read_byte); | |
557 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W); | |
558 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W); | |
559 | |
560 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W); | |
561 uint8_t * cont = dst+1; | |
562 dst = jcc(dst, CC_Z, dst+2); | |
563 dst = zcycles(dst, 7); | |
564 //TODO: Figure out what the flag state should be here | |
565 //TODO: Figure out whether an interrupt can interrupt this | |
566 dst = jmp(dst, start); | |
567 *cont = dst - (cont + 1); | |
568 dst = zcycles(dst, 2); | |
569 //TODO: Implement half-carry | |
570 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
571 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); | |
572 break; | |
573 } | |
574 /*case Z80_CPI: | |
213
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575 case Z80_CPIR: |
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576 case Z80_CPD: |
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577 case Z80_CPDR: |
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578 break;*/ |
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579 case Z80_ADD: |
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580 cycles = 4; |
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581 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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582 cycles += 12; |
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583 } else if(inst->addr_mode == Z80_IMMED) { |
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584 cycles += 3; |
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585 } else if(z80_size(inst) == SZ_W) { |
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586 cycles += 4; |
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587 } |
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588 dst = zcycles(dst, cycles); |
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589 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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590 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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591 if (src_op.mode == MODE_REG_DIRECT) { |
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592 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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593 } else { |
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594 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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595 } |
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596 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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597 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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598 //TODO: Implement half-carry flag |
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599 if (z80_size(inst) == SZ_B) { |
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600 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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601 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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602 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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603 } |
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604 dst = z80_save_reg(dst, inst, opts); |
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605 dst = z80_save_ea(dst, inst, opts); |
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606 break; |
248
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607 case Z80_ADC: |
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608 cycles = 4; |
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609 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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610 cycles += 12; |
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611 } else if(inst->addr_mode == Z80_IMMED) { |
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612 cycles += 3; |
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613 } else if(z80_size(inst) == SZ_W) { |
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614 cycles += 4; |
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615 } |
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616 dst = zcycles(dst, cycles); |
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617 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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618 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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619 if (src_op.mode == MODE_REG_DIRECT) { |
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620 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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621 } else { |
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622 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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623 } |
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624 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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625 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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626 //TODO: Implement half-carry flag |
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627 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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628 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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629 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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630 dst = z80_save_reg(dst, inst, opts); |
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631 dst = z80_save_ea(dst, inst, opts); |
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632 break; |
213
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633 case Z80_SUB: |
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634 cycles = 4; |
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635 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
213
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636 cycles += 12; |
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637 } else if(inst->addr_mode == Z80_IMMED) { |
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638 cycles += 3; |
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639 } |
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640 dst = zcycles(dst, cycles); |
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641 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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642 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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643 if (src_op.mode == MODE_REG_DIRECT) { |
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|
644 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
4d4559b04c59
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parents:
diff
changeset
|
645 } else { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
changeset
|
646 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
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|
647 } |
4d4559b04c59
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diff
changeset
|
648 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
235
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649 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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650 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
213
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diff
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|
651 //TODO: Implement half-carry flag |
235
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652 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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653 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
4d4559b04c59
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diff
changeset
|
654 dst = z80_save_reg(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
655 dst = z80_save_ea(dst, inst, opts); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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parents:
diff
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|
656 break; |
248
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657 case Z80_SBC: |
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658 cycles = 4; |
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659 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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660 cycles += 12; |
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661 } else if(inst->addr_mode == Z80_IMMED) { |
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662 cycles += 3; |
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663 } else if(z80_size(inst) == SZ_W) { |
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664 cycles += 4; |
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665 } |
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666 dst = zcycles(dst, cycles); |
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667 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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668 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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669 if (src_op.mode == MODE_REG_DIRECT) { |
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670 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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671 } else { |
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672 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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673 } |
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674 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
309
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308
diff
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|
675 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
248
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676 //TODO: Implement half-carry flag |
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677 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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678 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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679 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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680 dst = z80_save_reg(dst, inst, opts); |
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changeset
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681 dst = z80_save_ea(dst, inst, opts); |
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682 break; |
213
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Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
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diff
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|
683 case Z80_AND: |
236
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diff
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684 cycles = 4; |
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685 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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|
686 cycles += 12; |
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687 } else if(inst->addr_mode == Z80_IMMED) { |
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688 cycles += 3; |
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689 } else if(z80_size(inst) == SZ_W) { |
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690 cycles += 4; |
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|
691 } |
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692 dst = zcycles(dst, cycles); |
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693 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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694 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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695 if (src_op.mode == MODE_REG_DIRECT) { |
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696 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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697 } else { |
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diff
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|
698 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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|
699 } |
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diff
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|
700 //TODO: Cleanup flags |
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235
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|
701 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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diff
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|
702 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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|
703 //TODO: Implement half-carry flag |
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235
diff
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|
704 if (z80_size(inst) == SZ_B) { |
305
a57fac5b3d65
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Mike Pavone <pavone@retrodev.com>
parents:
304
diff
changeset
|
705 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
236
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235
diff
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|
706 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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235
diff
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|
707 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
19fb3523a9e5
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235
diff
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|
708 } |
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235
diff
changeset
|
709 dst = z80_save_reg(dst, inst, opts); |
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235
diff
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|
710 dst = z80_save_ea(dst, inst, opts); |
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235
diff
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|
711 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
712 case Z80_OR: |
236
19fb3523a9e5
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235
diff
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|
713 cycles = 4; |
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235
diff
changeset
|
714 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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235
diff
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|
715 cycles += 12; |
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235
diff
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|
716 } else if(inst->addr_mode == Z80_IMMED) { |
19fb3523a9e5
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235
diff
changeset
|
717 cycles += 3; |
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235
diff
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|
718 } else if(z80_size(inst) == SZ_W) { |
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235
diff
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|
719 cycles += 4; |
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parents:
235
diff
changeset
|
720 } |
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235
diff
changeset
|
721 dst = zcycles(dst, cycles); |
19fb3523a9e5
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235
diff
changeset
|
722 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
19fb3523a9e5
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235
diff
changeset
|
723 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
19fb3523a9e5
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235
diff
changeset
|
724 if (src_op.mode == MODE_REG_DIRECT) { |
19fb3523a9e5
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235
diff
changeset
|
725 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
19fb3523a9e5
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235
diff
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|
726 } else { |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
727 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
19fb3523a9e5
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235
diff
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|
728 } |
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235
diff
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|
729 //TODO: Cleanup flags |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
730 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
731 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
19fb3523a9e5
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235
diff
changeset
|
732 //TODO: Implement half-carry flag |
19fb3523a9e5
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parents:
235
diff
changeset
|
733 if (z80_size(inst) == SZ_B) { |
305
a57fac5b3d65
Contrary to the official documenation, OR and AND also set PV based on parity instead of overflow
Mike Pavone <pavone@retrodev.com>
parents:
304
diff
changeset
|
734 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
236
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
735 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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parents:
235
diff
changeset
|
736 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
737 } |
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235
diff
changeset
|
738 dst = z80_save_reg(dst, inst, opts); |
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parents:
235
diff
changeset
|
739 dst = z80_save_ea(dst, inst, opts); |
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parents:
235
diff
changeset
|
740 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
741 case Z80_XOR: |
236
19fb3523a9e5
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parents:
235
diff
changeset
|
742 cycles = 4; |
19fb3523a9e5
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parents:
235
diff
changeset
|
743 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
19fb3523a9e5
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235
diff
changeset
|
744 cycles += 12; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
745 } else if(inst->addr_mode == Z80_IMMED) { |
19fb3523a9e5
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parents:
235
diff
changeset
|
746 cycles += 3; |
19fb3523a9e5
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parents:
235
diff
changeset
|
747 } else if(z80_size(inst) == SZ_W) { |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
748 cycles += 4; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
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|
749 } |
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750 dst = zcycles(dst, cycles); |
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751 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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752 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
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753 if (src_op.mode == MODE_REG_DIRECT) { |
295
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754 dst = xor_rr(dst, src_op.base, dst_op.base, z80_size(inst)); |
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755 } else { |
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756 dst = xor_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); |
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757 } |
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758 //TODO: Cleanup flags |
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759 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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760 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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761 //TODO: Implement half-carry flag |
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762 if (z80_size(inst) == SZ_B) { |
304
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763 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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764 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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765 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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766 } |
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767 dst = z80_save_reg(dst, inst, opts); |
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768 dst = z80_save_ea(dst, inst, opts); |
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769 break; |
242 | 770 case Z80_CP: |
771 cycles = 4; | |
772 if (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { | |
773 cycles += 12; | |
774 } else if(inst->addr_mode == Z80_IMMED) { | |
775 cycles += 3; | |
776 } | |
777 dst = zcycles(dst, cycles); | |
778 dst = translate_z80_reg(inst, &dst_op, dst, opts); | |
779 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); | |
780 if (src_op.mode == MODE_REG_DIRECT) { | |
781 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst)); | |
782 } else { | |
783 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst)); | |
784 } | |
785 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); | |
786 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); | |
787 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); | |
788 //TODO: Implement half-carry flag | |
789 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); | |
790 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); | |
791 dst = z80_save_reg(dst, inst, opts); | |
792 dst = z80_save_ea(dst, inst, opts); | |
793 break; | |
213
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794 case Z80_INC: |
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795 cycles = 4; |
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796 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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797 cycles += 6; |
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798 } else if(z80_size(inst) == SZ_W) { |
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changeset
|
799 cycles += 2; |
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800 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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801 cycles += 4; |
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802 } |
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803 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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804 if (dst_op.mode == MODE_UNUSED) { |
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805 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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806 } |
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807 dst = add_ir(dst, 1, dst_op.base, z80_size(inst)); |
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808 if (z80_size(inst) == SZ_B) { |
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809 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
213
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810 //TODO: Implement half-carry flag |
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811 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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812 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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813 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
213
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814 } |
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815 dst = z80_save_reg(dst, inst, opts); |
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816 dst = z80_save_ea(dst, inst, opts); |
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817 break; |
236
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818 case Z80_DEC: |
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819 cycles = 4; |
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820 if (inst->reg == Z80_IX || inst->reg == Z80_IY) { |
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821 cycles += 6; |
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822 } else if(z80_size(inst) == SZ_W) { |
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823 cycles += 2; |
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824 } else if(inst->reg == Z80_IXH || inst->reg == Z80_IXL || inst->reg == Z80_IYH || inst->reg == Z80_IYL || inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) { |
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825 cycles += 4; |
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826 } |
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827 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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828 if (dst_op.mode == MODE_UNUSED) { |
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829 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
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830 } |
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831 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst)); |
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832 if (z80_size(inst) == SZ_B) { |
311
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833 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
236
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834 //TODO: Implement half-carry flag |
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835 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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836 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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837 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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838 } |
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839 dst = z80_save_reg(dst, inst, opts); |
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840 dst = z80_save_ea(dst, inst, opts); |
213
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841 break; |
274
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842 //case Z80_DAA: |
213
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843 case Z80_CPL: |
274
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844 dst = zcycles(dst, 4); |
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845 dst = not_r(dst, opts->regs[Z80_A], SZ_B); |
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846 //TODO: Implement half-carry flag |
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847 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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848 break; |
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849 case Z80_NEG: |
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850 dst = zcycles(dst, 8); |
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851 dst = neg_r(dst, opts->regs[Z80_A], SZ_B); |
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852 //TODO: Implement half-carry flag |
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853 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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854 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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855 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
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856 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV)); |
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857 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B); |
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858 break; |
213
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|
859 case Z80_CCF: |
257 | 860 dst = zcycles(dst, 4); |
861 dst = xor_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
862 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
863 //TODO: Implement half-carry flag | |
864 break; | |
865 case Z80_SCF: | |
866 dst = zcycles(dst, 4); | |
867 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B); | |
868 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); | |
869 //TODO: Implement half-carry flag | |
870 break; | |
213
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|
871 case Z80_NOP: |
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|
872 if (inst->immed == 42) { |
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|
873 dst = call(dst, (uint8_t *)z80_save_context); |
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|
874 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q); |
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changeset
|
875 dst = jmp(dst, (uint8_t *)z80_print_regs_exit); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
876 } else { |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
877 dst = zcycles(dst, 4 * inst->immed); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 } |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 break; |
285
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
880 case Z80_HALT: |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
881 dst = zcycles(dst, 4); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
882 dst = mov_ir(dst, address, SCRATCH1, SZ_W); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
883 uint8_t * call_inst = dst; |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
884 dst = call(dst, (uint8_t *)z80_halt); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
885 dst = jmp(dst, call_inst); |
021aeb6df19b
Implement HALT (sort of tested)
Mike Pavone <pavone@retrodev.com>
parents:
284
diff
changeset
|
886 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 case Z80_DI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
888 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
889 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
890 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
891 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
892 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 case Z80_EI: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
894 //TODO: Implement interrupt enable latency of 1 instruction afer EI |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
895 dst = zcycles(dst, 4); |
335 | 896 dst = mov_rrdisp8(dst, ZCYCLES, CONTEXT, offsetof(z80_context, int_enable_cycle), SZ_D); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
897 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
898 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B); |
335 | 899 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles |
900 dst = add_irdisp8(dst, 4, CONTEXT, offsetof(z80_context, int_enable_cycle), SZ_D); | |
250
5f1b68cecfc7
Implemented basic interrupt support in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
248
diff
changeset
|
901 dst = call(dst, (uint8_t *)z80_do_sync); |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
902 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
903 case Z80_IM: |
243
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
904 dst = zcycles(dst, 4); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
905 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B); |
2f069a0b487e
Implement EI, DI and IM in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
242
diff
changeset
|
906 break; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
907 case Z80_RLC: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
908 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
909 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
910 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
911 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
912 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
913 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
914 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
915 src_op.mode = MODE_UNUSED; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
916 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
917 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
918 dst = rol_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
919 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
920 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
921 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
922 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
923 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
924 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
925 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
926 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
927 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
928 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
929 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
930 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
931 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
932 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
933 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
934 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
935 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
936 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
937 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
938 case Z80_RL: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
939 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
940 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
941 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
942 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
943 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
944 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
945 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
946 src_op.mode = MODE_UNUSED; |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
947 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
948 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
949 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
950 dst = rcl_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
951 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
952 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
953 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
954 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
955 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
956 //TODO: Implement half-carry flag |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
957 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
958 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
959 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
960 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
961 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
962 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
963 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
964 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
965 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
966 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
967 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
968 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
969 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
970 case Z80_RRC: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
971 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
972 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
973 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
974 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
975 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
976 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
977 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
978 src_op.mode = MODE_UNUSED; |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
979 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
980 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
981 dst = ror_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
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Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
982 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
983 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
984 } |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
985 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
986 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
987 //TODO: Implement half-carry flag |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
988 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
989 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
990 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
991 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
992 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
993 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
994 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
995 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
996 } |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
997 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
998 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
999 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1000 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1001 case Z80_RR: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1002 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8); |
247
682e505f5757
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parents:
246
diff
changeset
|
1003 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1004 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1005 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1006 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1007 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1008 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1009 src_op.mode = MODE_UNUSED; |
247
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1010 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
682e505f5757
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parents:
246
diff
changeset
|
1011 } |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1012 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1013 dst = rcr_ir(dst, 1, dst_op.base, SZ_B); |
301
6e15509a1257
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Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
1014 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1015 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1016 } |
247
682e505f5757
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parents:
246
diff
changeset
|
1017 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1018 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
682e505f5757
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parents:
246
diff
changeset
|
1019 //TODO: Implement half-carry flag |
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1020 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
682e505f5757
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parents:
246
diff
changeset
|
1021 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1022 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1023 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1024 if (inst->addr_mode != Z80_UNUSED) { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1025 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1026 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1027 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1028 } |
247
682e505f5757
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Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1029 } else { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1030 dst = z80_save_reg(dst, inst, opts); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1031 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1032 break; |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1033 case Z80_SLA: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1034 case Z80_SLL: |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1035 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1036 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1037 if (inst->addr_mode != Z80_UNUSED) { |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1038 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1039 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1040 dst = zcycles(dst, 1); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1041 } else { |
302
3b831fe32c15
More fixes for confusion between Z80_UNUSED and MODE_UNUSED
Mike Pavone <pavone@retrodev.com>
parents:
301
diff
changeset
|
1042 src_op.mode = MODE_UNUSED; |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1043 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1044 } |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1045 dst = shl_ir(dst, 1, dst_op.base, SZ_B); |
310
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1046 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1047 if (inst->op == Z80_SLL) { |
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1048 dst = or_ir(dst, 1, dst_op.base, SZ_B); |
bf440db64086
Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL.
Mike Pavone <pavone@retrodev.com>
parents:
309
diff
changeset
|
1049 } |
301
6e15509a1257
Compare src_op.mode with the correct constant in shift/rotate instructions
Mike Pavone <pavone@retrodev.com>
parents:
300
diff
changeset
|
1050 if (src_op.mode != MODE_UNUSED) { |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1051 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1052 } |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1053 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1054 //TODO: Implement half-carry flag |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1055 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1056 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1057 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1058 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1059 if (inst->addr_mode != Z80_UNUSED) { |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1060 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1061 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1062 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1063 } |
275
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1064 } else { |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1065 dst = z80_save_reg(dst, inst, opts); |
1a7d0a964ad2
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Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1066 } |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1067 break; |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1068 case Z80_SRA: |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1069 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
1a7d0a964ad2
Implement shift instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
274
diff
changeset
|
1070 dst = zcycles(dst, cycles); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1071 if (inst->addr_mode != Z80_UNUSED) { |
275
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1072 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
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295
diff
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|
1073 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
275
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diff
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1074 dst = zcycles(dst, 1); |
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diff
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1075 } else { |
302
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Mike Pavone <pavone@retrodev.com>
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301
diff
changeset
|
1076 src_op.mode = MODE_UNUSED; |
275
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1077 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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274
diff
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|
1078 } |
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1079 dst = sar_ir(dst, 1, dst_op.base, SZ_B); |
301
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|
1080 if (src_op.mode != MODE_UNUSED) { |
299
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diff
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|
1081 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
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diff
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|
1082 } |
310
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309
diff
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|
1083 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
275
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diff
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1084 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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diff
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1085 //TODO: Implement half-carry flag |
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1086 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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diff
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1087 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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diff
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1088 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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diff
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1089 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
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295
diff
changeset
|
1090 if (inst->addr_mode != Z80_UNUSED) { |
275
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diff
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1091 dst = z80_save_result(dst, inst); |
299
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295
diff
changeset
|
1092 if (src_op.mode != MODE_UNUSED) { |
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295
diff
changeset
|
1093 dst = z80_save_reg(dst, inst, opts); |
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diff
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|
1094 } |
275
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diff
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|
1095 } else { |
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diff
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|
1096 dst = z80_save_reg(dst, inst, opts); |
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|
1097 } |
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diff
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|
1098 break; |
213
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Mike Pavone <pavone@retrodev.com>
parents:
diff
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|
1099 case Z80_SRL: |
275
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diff
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1100 cycles = inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8; |
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diff
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1101 dst = zcycles(dst, cycles); |
299
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295
diff
changeset
|
1102 if (inst->addr_mode != Z80_UNUSED) { |
275
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diff
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|
1103 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY); |
299
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295
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|
1104 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register |
275
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1105 dst = zcycles(dst, 1); |
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diff
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1106 } else { |
302
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301
diff
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|
1107 src_op.mode = MODE_UNUSED; |
275
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diff
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|
1108 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
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diff
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|
1109 } |
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1110 dst = shr_ir(dst, 1, dst_op.base, SZ_B); |
301
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|
1111 if (src_op.mode != MODE_UNUSED) { |
299
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295
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|
1112 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B); |
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diff
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|
1113 } |
310
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|
1114 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C)); |
275
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1115 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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1116 //TODO: Implement half-carry flag |
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1117 dst = cmp_ir(dst, 0, dst_op.base, SZ_B); |
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1118 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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1119 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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diff
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|
1120 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
299
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295
diff
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|
1121 if (inst->addr_mode != Z80_UNUSED) { |
275
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diff
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|
1122 dst = z80_save_result(dst, inst); |
299
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295
diff
changeset
|
1123 if (src_op.mode != MODE_UNUSED) { |
42e1a986f2d0
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|
1124 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
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|
1125 } |
275
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|
1126 } else { |
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diff
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|
1127 dst = z80_save_reg(dst, inst, opts); |
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diff
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|
1128 } |
310
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|
1129 break; |
286 | 1130 case Z80_RLD: |
1131 dst = zcycles(dst, 8); | |
1132 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); | |
1133 dst = call(dst, (uint8_t *)z80_read_byte); | |
1134 //Before: (HL) = 0x12, A = 0x34 | |
1135 //After: (HL) = 0x24, A = 0x31 | |
1136 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B); | |
1137 dst = shl_ir(dst, 4, SCRATCH1, SZ_W); | |
1138 dst = and_ir(dst, 0xF, SCRATCH2, SZ_W); | |
1139 dst = and_ir(dst, 0xFFF, SCRATCH1, SZ_W); | |
1140 dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B); | |
1141 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_W); | |
1142 //SCRATCH1 = 0x0124 | |
1143 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); | |
1144 dst = zcycles(dst, 4); | |
1145 dst = or_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); | |
287
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286
diff
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|
1146 //set flags |
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|
1147 //TODO: Implement half-carry flag |
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|
1148 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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1149 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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|
1150 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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1151 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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|
1152 |
286 | 1153 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
1154 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); | |
1155 dst = call(dst, (uint8_t *)z80_write_byte); | |
1156 break; | |
287
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diff
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|
1157 case Z80_RRD: |
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|
1158 dst = zcycles(dst, 8); |
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|
1159 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W); |
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1160 dst = call(dst, (uint8_t *)z80_read_byte); |
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diff
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|
1161 //Before: (HL) = 0x12, A = 0x34 |
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1162 //After: (HL) = 0x41, A = 0x32 |
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1163 dst = movzx_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B, SZ_W); |
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1164 dst = ror_ir(dst, 4, SCRATCH1, SZ_W); |
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1165 dst = shl_ir(dst, 4, SCRATCH2, SZ_W); |
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1166 dst = and_ir(dst, 0xF00F, SCRATCH1, SZ_W); |
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1167 dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B); |
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1168 //SCRATCH1 = 0x2001 |
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1169 //SCRATCH2 = 0x0040 |
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1170 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_W); |
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1171 //SCRATCH1 = 0x2041 |
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1172 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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1173 dst = zcycles(dst, 4); |
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1174 dst = shr_ir(dst, 4, SCRATCH1, SZ_B); |
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1175 dst = or_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B); |
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|
1176 //set flags |
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|
1177 //TODO: Implement half-carry flag |
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|
1178 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
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|
1179 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV)); |
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1180 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z)); |
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|
1181 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
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|
1182 |
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1183 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W); |
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1184 dst = ror_ir(dst, 8, SCRATCH1, SZ_W); |
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parents:
286
diff
changeset
|
1185 dst = call(dst, (uint8_t *)z80_write_byte); |
fb840e0a48cd
Implement RRD and implement flags on RLD
Mike Pavone <pavone@retrodev.com>
parents:
286
diff
changeset
|
1186 break; |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1187 case Z80_BIT: { |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1188 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1189 dst = zcycles(dst, cycles); |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1190 uint8_t bit; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1191 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1192 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1193 size = SZ_W; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1194 bit = inst->immed + 8; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1195 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1196 size = SZ_B; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1197 bit = inst->immed; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1198 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1199 } |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1200 if (inst->addr_mode != Z80_REG) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1201 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1202 dst = zcycles(dst, 1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1203 } |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1204 dst = bt_ir(dst, bit, src_op.base, size); |
303
8290d3086ff0
BIT was setting the zero flag to the opposite of what it should have. This is now fixed.
Mike Pavone <pavone@retrodev.com>
parents:
302
diff
changeset
|
1205 dst = setcc_rdisp8(dst, CC_NC, CONTEXT, zf_off(ZF_Z)); |
307
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1206 dst = setcc_rdisp8(dst, CC_NC, CONTEXT, zf_off(ZF_PV)); |
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1207 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B); |
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1208 if (inst->immed == 7) { |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1209 dst = cmp_ir(dst, 0, src_op.base, size); |
307
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1210 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S)); |
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1211 } else { |
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1212 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
b6393b89a7e4
Complete flag behavior for Z80 BIT instruction
Mike Pavone <pavone@retrodev.com>
parents:
306
diff
changeset
|
1213 } |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1214 break; |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1215 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1216 case Z80_SET: { |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1217 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1218 dst = zcycles(dst, cycles); |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1219 uint8_t bit; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1220 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1221 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1222 size = SZ_W; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1223 bit = inst->immed + 8; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1224 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1225 size = SZ_B; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1226 bit = inst->immed; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1227 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1228 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1229 if (inst->reg != Z80_USE_IMMED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1230 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1231 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1232 if (inst->addr_mode != Z80_REG) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1233 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1234 dst = zcycles(dst, 1); |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1235 } |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1236 dst = bts_ir(dst, bit, src_op.base, size); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1237 if (inst->reg != Z80_USE_IMMED) { |
308
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1238 if (size == SZ_W) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1239 if (dst_op.base >= R8) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1240 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1241 dst = mov_rr(dst, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1242 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1243 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1244 dst = mov_rr(dst, opts->regs[inst->ea_reg], dst_op.base, SZ_B); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1245 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1246 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1247 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_B); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1248 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1249 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1250 if ((inst->addr_mode & 0x1F) != Z80_REG) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1251 dst = z80_save_result(dst, inst); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1252 if (inst->reg != Z80_USE_IMMED) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1253 dst = z80_save_reg(dst, inst, opts); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1254 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1255 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1256 break; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1257 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1258 case Z80_RES: { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1259 cycles = (inst->addr_mode == Z80_IX_DISPLACE || inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1260 dst = zcycles(dst, cycles); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1261 uint8_t bit; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1262 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1263 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)]; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1264 size = SZ_W; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1265 bit = inst->immed + 8; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1266 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1267 size = SZ_B; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1268 bit = inst->immed; |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1269 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1270 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1271 if (inst->reg != Z80_USE_IMMED) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1272 dst = translate_z80_reg(inst, &dst_op, dst, opts); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1273 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1274 if (inst->addr_mode != Z80_REG) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1275 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4 |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1276 dst = zcycles(dst, 1); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1277 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1278 dst = btr_ir(dst, bit, src_op.base, size); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1279 if (inst->reg != Z80_USE_IMMED) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1280 if (size == SZ_W) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1281 if (dst_op.base >= R8) { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1282 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1283 dst = mov_rr(dst, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1284 dst = ror_ir(dst, 8, src_op.base, SZ_W); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1285 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1286 dst = mov_rr(dst, opts->regs[inst->ea_reg], dst_op.base, SZ_B); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1287 } |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1288 } else { |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1289 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_B); |
e0e81551fd7e
Deal with the fact that there's no 8-bit version of the BT family of instructions on x86
Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1290 } |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1291 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1292 if (inst->addr_mode != Z80_REG) { |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1293 dst = z80_save_result(dst, inst); |
299
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1294 if (inst->reg != Z80_USE_IMMED) { |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1295 dst = z80_save_reg(dst, inst, opts); |
42e1a986f2d0
Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions.
Mike Pavone <pavone@retrodev.com>
parents:
295
diff
changeset
|
1296 } |
247
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1297 } |
682e505f5757
Implement rotation and bit set/reset instructions (untested).
Mike Pavone <pavone@retrodev.com>
parents:
246
diff
changeset
|
1298 break; |
308
e0e81551fd7e
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Mike Pavone <pavone@retrodev.com>
parents:
307
diff
changeset
|
1299 } |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
1300 case Z80_JP: { |
19fb3523a9e5
Implement more Z80 instructions (untested)
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235
diff
changeset
|
1301 cycles = 4; |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1302 if (inst->addr_mode != Z80_REG) { |
236
19fb3523a9e5
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parents:
235
diff
changeset
|
1303 cycles += 6; |
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235
diff
changeset
|
1304 } else if(inst->ea_reg == Z80_IX || inst->ea_reg == Z80_IY) { |
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Implement more Z80 instructions (untested)
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235
diff
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|
1305 cycles += 4; |
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235
diff
changeset
|
1306 } |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
1307 dst = zcycles(dst, cycles); |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1308 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) { |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
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235
diff
changeset
|
1309 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
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Implement more Z80 instructions (untested)
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235
diff
changeset
|
1310 if (!call_dst) { |
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Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
1311 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1312 //fake address to force large displacement |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1313 call_dst = dst + 256; |
19fb3523a9e5
Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
1314 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1315 dst = jmp(dst, call_dst); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1316 } else { |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1317 if (inst->addr_mode == Z80_REG_INDIRECT) { |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1318 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1319 } else { |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1320 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1321 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1322 dst = call(dst, (uint8_t *)z80_native_addr); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1323 dst = jmp_r(dst, SCRATCH1); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1324 } |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1325 break; |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1326 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1327 case Z80_JPCC: { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1328 dst = zcycles(dst, 7);//T States: 4,3 |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1329 uint8_t cond = CC_Z; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1330 switch (inst->reg) |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1331 { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1332 case Z80_CC_NZ: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1333 cond = CC_NZ; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1334 case Z80_CC_Z: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1335 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1336 break; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1337 case Z80_CC_NC: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1338 cond = CC_NZ; |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1339 case Z80_CC_C: |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1340 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1341 break; |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1342 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1343 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1344 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1345 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1346 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1347 case Z80_CC_P: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1348 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1349 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1350 break; |
236
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1351 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1352 uint8_t *no_jump_off = dst+1; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1353 dst = jcc(dst, cond, dst+2); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1354 dst = zcycles(dst, 5);//T States: 5 |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1355 uint16_t dest_addr = inst->immed; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1356 if (dest_addr < 0x4000) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1357 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1358 if (!call_dst) { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1359 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1360 //fake address to force large displacement |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1361 call_dst = dst + 256; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1362 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1363 dst = jmp(dst, call_dst); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1364 } else { |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1365 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1366 dst = call(dst, (uint8_t *)z80_native_addr); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1367 dst = jmp_r(dst, SCRATCH1); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1368 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1369 *no_jump_off = dst - (no_jump_off+1); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1370 break; |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1371 } |
19fb3523a9e5
Implement more Z80 instructions (untested)
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parents:
235
diff
changeset
|
1372 case Z80_JR: { |
19fb3523a9e5
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parents:
235
diff
changeset
|
1373 dst = zcycles(dst, 12);//T States: 4,3,5 |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1374 uint16_t dest_addr = address + inst->immed + 2; |
19fb3523a9e5
Implement more Z80 instructions (untested)
Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1375 if (dest_addr < 0x4000) { |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1376 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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parents:
235
diff
changeset
|
1377 if (!call_dst) { |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1378 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1379 //fake address to force large displacement |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1380 call_dst = dst + 256; |
19fb3523a9e5
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parents:
235
diff
changeset
|
1381 } |
19fb3523a9e5
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1382 dst = jmp(dst, call_dst); |
19fb3523a9e5
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parents:
235
diff
changeset
|
1383 } else { |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1384 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
19fb3523a9e5
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235
diff
changeset
|
1385 dst = call(dst, (uint8_t *)z80_native_addr); |
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parents:
235
diff
changeset
|
1386 dst = jmp_r(dst, SCRATCH1); |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1387 } |
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Mike Pavone <pavone@retrodev.com>
parents:
235
diff
changeset
|
1388 break; |
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parents:
235
diff
changeset
|
1389 } |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1390 case Z80_JRCC: { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1391 dst = zcycles(dst, 7);//T States: 4,3 |
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1392 uint8_t cond = CC_Z; |
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1393 switch (inst->reg) |
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1394 { |
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1395 case Z80_CC_NZ: |
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1396 cond = CC_NZ; |
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1397 case Z80_CC_Z: |
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1398 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
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1399 break; |
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|
1400 case Z80_CC_NC: |
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1401 cond = CC_NZ; |
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|
1402 case Z80_CC_C: |
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1403 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
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|
1404 break; |
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|
1405 } |
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|
1406 uint8_t *no_jump_off = dst+1; |
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|
1407 dst = jcc(dst, cond, dst+2); |
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|
1408 dst = zcycles(dst, 5);//T States: 5 |
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|
1409 uint16_t dest_addr = address + inst->immed + 2; |
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1410 if (dest_addr < 0x4000) { |
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|
1411 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
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|
1412 if (!call_dst) { |
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diff
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|
1413 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
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|
1414 //fake address to force large displacement |
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|
1415 call_dst = dst + 256; |
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|
1416 } |
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|
1417 dst = jmp(dst, call_dst); |
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|
1418 } else { |
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|
1419 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
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Get Z80 core working for simple programs
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1420 dst = call(dst, (uint8_t *)z80_native_addr); |
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|
1421 dst = jmp_r(dst, SCRATCH1); |
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|
1422 } |
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|
1423 *no_jump_off = dst - (no_jump_off+1); |
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Get Z80 core working for simple programs
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213
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changeset
|
1424 break; |
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diff
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|
1425 } |
239
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
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|
1426 case Z80_DJNZ: |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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diff
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|
1427 dst = zcycles(dst, 8);//T States: 5,3 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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|
1428 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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diff
changeset
|
1429 uint8_t *no_jump_off = dst+1; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
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|
1430 dst = jcc(dst, CC_Z, dst+2); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
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|
1431 dst = zcycles(dst, 5);//T States: 5 |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
diff
changeset
|
1432 uint16_t dest_addr = address + inst->immed + 2; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1433 if (dest_addr < 0x4000) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1434 uint8_t * call_dst = z80_get_native_address(context, dest_addr); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
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238
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|
1435 if (!call_dst) { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1436 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1437 //fake address to force large displacement |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1438 call_dst = dst + 256; |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
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|
1439 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1440 dst = jmp(dst, call_dst); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1441 } else { |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1442 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1443 dst = call(dst, (uint8_t *)z80_native_addr); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1444 dst = jmp_r(dst, SCRATCH1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1445 } |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
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238
diff
changeset
|
1446 *no_jump_off = dst - (no_jump_off+1); |
a5bea9711a46
Implement BIT and DJNZ (tested). Fix register mapping for IYL.
Mike Pavone <pavone@retrodev.com>
parents:
238
diff
changeset
|
1447 break; |
235
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Get Z80 core working for simple programs
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213
diff
changeset
|
1448 case Z80_CALL: { |
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diff
changeset
|
1449 dst = zcycles(dst, 11);//T States: 4,3,4 |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1450 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
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252
diff
changeset
|
1451 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
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252
diff
changeset
|
1452 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
235
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Get Z80 core working for simple programs
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213
diff
changeset
|
1453 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
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Get Z80 core working for simple programs
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213
diff
changeset
|
1454 if (inst->immed < 0x4000) { |
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Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
1455 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1456 if (!call_dst) { |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1457 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
1458 //fake address to force large displacement |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1459 call_dst = dst + 256; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1460 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1461 dst = jmp(dst, call_dst); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1462 } else { |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
1463 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1464 dst = call(dst, (uint8_t *)z80_native_addr); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1465 dst = jmp_r(dst, SCRATCH1); |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1466 } |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
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213
diff
changeset
|
1467 break; |
d9bf8e61c33c
Get Z80 core working for simple programs
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parents:
213
diff
changeset
|
1468 } |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1469 case Z80_CALLCC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1470 dst = zcycles(dst, 10);//T States: 4,3,3 (false case) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1471 uint8_t cond = CC_Z; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1472 switch (inst->reg) |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1473 { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1474 case Z80_CC_NZ: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1475 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1476 case Z80_CC_Z: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1477 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1478 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1479 case Z80_CC_NC: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1480 cond = CC_NZ; |
827ebce557bf
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236
diff
changeset
|
1481 case Z80_CC_C: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1482 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1483 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1484 case Z80_CC_PO: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1485 cond = CC_NZ; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1486 case Z80_CC_PE: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1487 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1488 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1489 case Z80_CC_P: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1490 case Z80_CC_M: |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1491 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1492 break; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1493 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1494 uint8_t *no_call_off = dst+1; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1495 dst = jcc(dst, cond, dst+2); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1496 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
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236
diff
changeset
|
1497 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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252
diff
changeset
|
1498 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W); |
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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252
diff
changeset
|
1499 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
238
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
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236
diff
changeset
|
1500 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1501 if (inst->immed < 0x4000) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1502 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1503 if (!call_dst) { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1504 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1505 //fake address to force large displacement |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1506 call_dst = dst + 256; |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1507 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1508 dst = jmp(dst, call_dst); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1509 } else { |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1510 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1511 dst = call(dst, (uint8_t *)z80_native_addr); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1512 dst = jmp_r(dst, SCRATCH1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1513 } |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1514 *no_call_off = dst - (no_call_off+1); |
827ebce557bf
Added the rest of the conditions to JPCC, implemented CALLCC (untested)
Mike Pavone <pavone@retrodev.com>
parents:
236
diff
changeset
|
1515 break; |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1516 case Z80_RET: |
235
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1517 dst = zcycles(dst, 4);//T States: 4 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1518 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1519 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1520 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1521 dst = call(dst, (uint8_t *)z80_native_addr); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1522 dst = jmp_r(dst, SCRATCH1); |
d9bf8e61c33c
Get Z80 core working for simple programs
Mike Pavone <pavone@retrodev.com>
parents:
213
diff
changeset
|
1523 break; |
246
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1524 case Z80_RETCC: { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1525 dst = zcycles(dst, 5);//T States: 5 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1526 uint8_t cond = CC_Z; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1527 switch (inst->reg) |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1528 { |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1529 case Z80_CC_NZ: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1530 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1531 case Z80_CC_Z: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1532 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1533 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1534 case Z80_CC_NC: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1535 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1536 case Z80_CC_C: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1537 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1538 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1539 case Z80_CC_PO: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1540 cond = CC_NZ; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1541 case Z80_CC_PE: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1542 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1543 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1544 case Z80_CC_P: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1545 case Z80_CC_M: |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1546 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1547 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1548 } |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1549 uint8_t *no_call_off = dst+1; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1550 dst = jcc(dst, cond, dst+2); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1551 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1552 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1553 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1554 dst = call(dst, (uint8_t *)z80_native_addr); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1555 dst = jmp_r(dst, SCRATCH1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1556 *no_call_off = dst - (no_call_off+1); |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1557 break; |
ed548c77b598
Implement RETCC in Z80 core.
Mike Pavone <pavone@retrodev.com>
parents:
243
diff
changeset
|
1558 } |
283
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1559 case Z80_RETI: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1560 //For some systems, this may need a callback for signalling interrupt routine completion |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1561 dst = zcycles(dst, 8);//T States: 4, 4 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1562 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1563 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1564 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1565 dst = call(dst, (uint8_t *)z80_native_addr); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1566 dst = jmp_r(dst, SCRATCH1); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1567 break; |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1568 case Z80_RETN: |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1569 dst = zcycles(dst, 8);//T States: 4, 4 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1570 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, iff2), SCRATCH2, SZ_B); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1571 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1572 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(z80_context, iff1), SZ_B); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1573 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3 |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1574 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1575 dst = call(dst, (uint8_t *)z80_native_addr); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1576 dst = jmp_r(dst, SCRATCH1); |
61f5d88ea01a
Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions.
Mike Pavone <pavone@retrodev.com>
parents:
282
diff
changeset
|
1577 break; |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1578 case Z80_RST: { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1579 //RST is basically CALL to an address in page 0 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1580 dst = zcycles(dst, 5);//T States: 5 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1581 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W); |
315
684e71e9f0d0
Fix return address for RST
Mike Pavone <pavone@retrodev.com>
parents:
314
diff
changeset
|
1582 dst = mov_ir(dst, address + 1, SCRATCH1, SZ_W); |
253
3b34deba4ca0
Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
Mike Pavone <pavone@retrodev.com>
parents:
252
diff
changeset
|
1583 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W); |
241
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1584 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3 |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1585 uint8_t * call_dst = z80_get_native_address(context, inst->immed); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1586 if (!call_dst) { |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1587 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1588 //fake address to force large displacement |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1589 call_dst = dst + 256; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1590 } |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1591 dst = jmp(dst, call_dst); |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1592 break; |
2586d49ddd46
Implement EX, EXX and RST in Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
239
diff
changeset
|
1593 } |
284
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1594 case Z80_IN: |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1595 dst = zcycles(dst, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1596 if (inst->addr_mode == Z80_IMMED_INDIRECT) { |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1597 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1598 } else { |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1599 dst = mov_rr(dst, opts->regs[Z80_C], SCRATCH1, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1600 } |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1601 dst = call(dst, (uint8_t *)z80_io_read); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1602 translate_z80_reg(inst, &dst_op, dst, opts); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1603 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1604 dst = z80_save_reg(dst, inst, opts); |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1605 break; |
ed7098f717d7
Implement IN and OUT (untested)
Mike Pavone <pavone@retrodev.com>
parents:
283
diff
changeset
|
1606 /*case Z80_INI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1607 case Z80_INIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1608 case Z80_IND: |
284
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Implement IN and OUT (untested)
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283
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|
1609 case Z80_INDR:*/ |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1610 case Z80_OUT: |
284
ed7098f717d7
Implement IN and OUT (untested)
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283
diff
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|
1611 dst = zcycles(dst, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4 |
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|
1612 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) { |
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|
1613 dst = mov_ir(dst, inst->immed, SCRATCH2, SZ_B); |
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diff
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|
1614 } else { |
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diff
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|
1615 dst = mov_rr(dst, opts->regs[Z80_C], SCRATCH2, SZ_B); |
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diff
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|
1616 } |
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|
1617 translate_z80_reg(inst, &src_op, dst, opts); |
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283
diff
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|
1618 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B); |
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Implement IN and OUT (untested)
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|
1619 dst = call(dst, (uint8_t *)z80_io_write); |
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|
1620 dst = z80_save_reg(dst, inst, opts); |
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diff
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|
1621 break; |
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|
1622 /*case Z80_OUTI: |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
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changeset
|
1623 case Z80_OTIR: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1624 case Z80_OUTD: |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
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|
1625 case Z80_OTDR:*/ |
235
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diff
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|
1626 default: { |
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|
1627 char disbuf[80]; |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
1628 z80_disasm(inst, disbuf, address); |
235
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|
1629 fprintf(stderr, "unimplemented instruction: %s\n", disbuf); |
259
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
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257
diff
changeset
|
1630 FILE * f = fopen("zram.bin", "wb"); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
Mike Pavone <pavone@retrodev.com>
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257
diff
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|
1631 fwrite(context->mem_pointers[0], 1, 8 * 1024, f); |
d9417261366f
Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called.
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257
diff
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|
1632 fclose(f); |
213
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1633 exit(1); |
4d4559b04c59
Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag.
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1634 } |
235
d9bf8e61c33c
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diff
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|
1635 } |
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|
1636 return dst; |
d9bf8e61c33c
Get Z80 core working for simple programs
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changeset
|
1637 } |
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Get Z80 core working for simple programs
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diff
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|
1638 |
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|
1639 uint8_t * z80_get_native_address(z80_context * context, uint32_t address) |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
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|
1640 { |
d9bf8e61c33c
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diff
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|
1641 native_map_slot *map; |
d9bf8e61c33c
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213
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|
1642 if (address < 0x4000) { |
d9bf8e61c33c
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|
1643 address &= 0x1FFF; |
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|
1644 map = context->static_code_map; |
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Get Z80 core working for simple programs
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|
1645 } else if (address >= 0x8000) { |
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Get Z80 core working for simple programs
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213
diff
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|
1646 address &= 0x7FFF; |
279
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277
diff
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|
1647 map = context->banked_code_map + context->bank_reg; |
235
d9bf8e61c33c
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213
diff
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|
1648 } else { |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
parents:
312
diff
changeset
|
1649 //dprintf("z80_get_native_address: %X NULL\n", address); |
235
d9bf8e61c33c
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213
diff
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|
1650 return NULL; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1651 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1652 if (!map->base || !map->offsets || map->offsets[address] == INVALID_OFFSET || map->offsets[address] == EXTENSION_WORD) { |
313
a13329645ea3
Fix terminal instruction detection in disassembler
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parents:
312
diff
changeset
|
1653 //dprintf("z80_get_native_address: %X NULL\n", address); |
235
d9bf8e61c33c
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213
diff
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|
1654 return NULL; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
changeset
|
1655 } |
313
a13329645ea3
Fix terminal instruction detection in disassembler
Mike Pavone <pavone@retrodev.com>
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312
diff
changeset
|
1656 //dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]); |
235
d9bf8e61c33c
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|
1657 return map->base + map->offsets[address]; |
d9bf8e61c33c
Get Z80 core working for simple programs
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213
diff
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|
1658 } |
d9bf8e61c33c
Get Z80 core working for simple programs
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|
1659 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
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|
1660 uint8_t z80_get_native_inst_size(x86_z80_options * opts, uint32_t address) |
235
d9bf8e61c33c
Get Z80 core working for simple programs
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213
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|
1661 { |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1662 if (address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
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|
1663 return 0; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
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|
1664 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1665 return opts->ram_inst_sizes[address & 0x1FFF]; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
diff
changeset
|
1666 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
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|
1667 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
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250
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|
1668 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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250
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|
1669 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1670 uint32_t orig_address = address; |
235
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|
1671 native_map_slot *map; |
252
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|
1672 x86_z80_options * opts = context->options; |
235
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diff
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|
1673 if (address < 0x4000) { |
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Get Z80 core working for simple programs
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diff
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|
1674 address &= 0x1FFF; |
d9bf8e61c33c
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diff
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|
1675 map = context->static_code_map; |
252
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Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1676 opts->ram_inst_sizes[address] = native_size; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1677 context->ram_code_flags[(address & 0x1C00) >> 10] |= 1 << ((address & 0x380) >> 7); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
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|
1678 context->ram_code_flags[((address + size) & 0x1C00) >> 10] |= 1 << (((address + size) & 0x380) >> 7); |
235
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Get Z80 core working for simple programs
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diff
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|
1679 } else if (address >= 0x8000) { |
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Get Z80 core working for simple programs
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213
diff
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|
1680 address &= 0x7FFF; |
279
6be6056735a9
Fix native address lookup in bannked memory area
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277
diff
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|
1681 map = context->banked_code_map + context->bank_reg; |
235
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diff
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|
1682 if (!map->offsets) { |
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213
diff
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|
1683 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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213
diff
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|
1684 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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diff
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|
1685 } |
d9bf8e61c33c
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diff
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|
1686 } else { |
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Get Z80 core working for simple programs
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|
1687 return; |
d9bf8e61c33c
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|
1688 } |
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|
1689 if (!map->base) { |
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|
1690 map->base = native_address; |
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diff
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|
1691 } |
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|
1692 map->offsets[address] = native_address - map->base; |
253
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Squashing some bugs introduced when I switched the register assignments for z80_write_byte around.
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|
1693 for(--size, orig_address++; size; --size, orig_address++) { |
252
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|
1694 address = orig_address; |
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|
1695 if (address < 0x4000) { |
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|
1696 address &= 0x1FFF; |
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|
1697 map = context->static_code_map; |
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1698 } else if (address >= 0x8000) { |
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|
1699 address &= 0x7FFF; |
279
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|
1700 map = context->banked_code_map + context->bank_reg; |
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|
1701 } else { |
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1702 return; |
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1703 } |
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1704 if (!map->offsets) { |
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|
1705 map->offsets = malloc(sizeof(int32_t) * 0x8000); |
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|
1706 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000); |
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1707 } |
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|
1708 map->offsets[address] = EXTENSION_WORD; |
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1709 } |
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1710 } |
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1711 |
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|
1712 #define INVALID_INSTRUCTION_START 0xFEEDFEED |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1713 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1714 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1715 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1716 if (!static_code_map->base || address >= 0x4000) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1717 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1718 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1719 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1720 if (static_code_map->offsets[address] == INVALID_OFFSET) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1721 return INVALID_INSTRUCTION_START; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1722 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1723 while (static_code_map->offsets[address] == EXTENSION_WORD) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1724 --address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1725 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1726 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1727 return address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1728 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1729 |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1730 z80_context * z80_handle_code_write(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1731 { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1732 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1733 if (inst_start != INVALID_INSTRUCTION_START) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1734 uint8_t * dst = z80_get_native_address(context, inst_start); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1735 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", dst, inst_start, address); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1736 dst = mov_ir(dst, inst_start, SCRATCH1, SZ_D); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1737 dst = jmp(dst, (uint8_t *)z80_retrans_stub); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1738 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1739 return context; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1740 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1741 |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1742 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address) |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1743 { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1744 uint8_t * addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1745 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1746 translate_z80_stream(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1747 addr = z80_get_native_address(context, address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1748 if (!addr) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1749 printf("Failed to translate %X to native code\n", address); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1750 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1751 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1752 return addr; |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1753 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1754 |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1755 void z80_handle_deferred(z80_context * context) |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1756 { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1757 x86_z80_options * opts = context->options; |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1758 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1759 if (opts->deferred) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1760 translate_z80_stream(context, opts->deferred->address); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1761 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1762 } |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1763 |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1764 void * z80_retranslate_inst(uint32_t address, z80_context * context) |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1765 { |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1766 char disbuf[80]; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1767 x86_z80_options * opts = context->options; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1768 uint8_t orig_size = z80_get_native_inst_size(opts, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1769 uint8_t * orig_start = z80_get_native_address(context, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1770 uint32_t orig = address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1771 address &= 0x1FFF; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1772 uint8_t * dst = opts->cur_code; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1773 uint8_t * dst_end = opts->code_end; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1774 uint8_t *after, *inst = context->mem_pointers[0] + address; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1775 z80inst instbuf; |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1776 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start); |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1777 after = z80_decode(inst, &instbuf); |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1778 #ifdef DO_DEBUG_PRINT |
314
54c0e5f22198
Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
Mike Pavone <pavone@retrodev.com>
parents:
313
diff
changeset
|
1779 z80_disasm(&instbuf, disbuf, address); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1780 if (instbuf.op == Z80_NOP) { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1781 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed); |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1782 } else { |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1783 printf("%X\t%s\n", address, disbuf); |
267
1788e3f29c28
Don't mix *H regs with the REX prefix
Mike Pavone <pavone@retrodev.com>
parents:
266
diff
changeset
|
1784 } |
268
6c2d7e003a55
Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset
Mike Pavone <pavone@retrodev.com>
parents:
267
diff
changeset
|
1785 #endif |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1786 if (orig_size != ZMAX_NATIVE_SIZE) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1787 if (dst_end - dst < ZMAX_NATIVE_SIZE) { |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1788 size_t size = 1024*1024; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1789 dst = alloc_code(&size); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1790 opts->code_end = dst_end = dst + size; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1791 opts->cur_code = dst; |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1792 } |
282
7b8a49220e3b
Remove deferred address entries from abandoned translations inside z80_retrans_inst
Mike Pavone <pavone@retrodev.com>
parents:
279
diff
changeset
|
1793 deferred_addr * orig_deferred = opts->deferred; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1794 uint8_t * native_end = translate_z80inst(&instbuf, dst, context, address); |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1795 if ((native_end - dst) <= orig_size) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1796 uint8_t * native_next = z80_get_native_address(context, address + after-inst); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1797 if (native_next && ((native_next == orig_start + orig_size) || (orig_size - (native_end - dst)) > 5)) { |
282
7b8a49220e3b
Remove deferred address entries from abandoned translations inside z80_retrans_inst
Mike Pavone <pavone@retrodev.com>
parents:
279
diff
changeset
|
1798 remove_deferred_until(&opts->deferred, orig_deferred); |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1799 native_end = translate_z80inst(&instbuf, orig_start, context, address); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1800 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) { |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1801 while (native_end < orig_start + orig_size) { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1802 *(native_end++) = 0x90; //NOP |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1803 } |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1804 } else { |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1805 jmp(native_end, native_next); |
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1806 } |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1807 z80_handle_deferred(context); |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1808 return orig_start; |
252
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1809 } |
63b9a500a00b
Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test.
Mike Pavone <pavone@retrodev.com>
parents:
250
diff
changeset
|
1810 } |
264
8fd6652e56f8
Fix a crash bug in instruction retranslation
Mike Pavone <pavone@retrodev.com>
parents:
262
diff
changeset
|
1811 z80_map_native_address(context, address, dst, after-inst, ZMAX_NATIVE_SIZE); |
266
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1812 opts->cur_code = dst+ZMAX_NATIVE_SIZE; |
376df762ddf5
Fix some more retranslation bugs in the Z80 core
Mike Pavone <pavone@retrodev.com>
parents:
264
diff
changeset
|
1813 jmp(orig_start, dst); |
283
61f5d88ea01a
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1814 if (!z80_is_terminal(&instbuf)) { |
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1815 jmp(native_end, z80_get_native_address_trans(context, address + after-inst)); |
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1816 } |
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1817 z80_handle_deferred(context); |
264
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1818 return dst; |
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1819 } else { |
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1820 dst = translate_z80inst(&instbuf, orig_start, context, address); |
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1821 if (!z80_is_terminal(&instbuf)) { |
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1822 dst = jmp(dst, z80_get_native_address_trans(context, address + after-inst)); |
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1823 } |
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1824 z80_handle_deferred(context); |
252
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1825 return orig_start; |
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1826 } |
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1827 } |
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1828 |
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1829 void translate_z80_stream(z80_context * context, uint32_t address) |
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1830 { |
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1831 char disbuf[80]; |
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1832 if (z80_get_native_address(context, address)) { |
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1833 return; |
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1834 } |
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1835 x86_z80_options * opts = context->options; |
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1836 uint8_t * encoded = NULL, *next; |
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1837 if (address < 0x4000) { |
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1838 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1839 } else if(address >= 0x8000 && context->mem_pointers[1]) { |
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1840 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1841 } |
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1842 while (encoded != NULL) |
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1843 { |
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1844 z80inst inst; |
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1845 dprintf("translating Z80 code at address %X\n", address); |
235
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1846 do { |
252
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1847 if (opts->code_end-opts->cur_code < ZMAX_NATIVE_SIZE) { |
235
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1848 if (opts->code_end-opts->cur_code < 5) { |
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1849 puts("out of code memory, not enough space for jmp to next chunk"); |
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1850 exit(1); |
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1851 } |
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1852 size_t size = 1024*1024; |
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1853 opts->cur_code = alloc_code(&size); |
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1854 opts->code_end = opts->cur_code + size; |
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1855 jmp(opts->cur_code, opts->cur_code); |
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1856 } |
255
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1857 if (address > 0x4000 && address < 0x8000) { |
235
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1858 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D); |
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1859 opts->cur_code = call(opts->cur_code, (uint8_t *)exit); |
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1860 break; |
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1861 } |
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1862 uint8_t * existing = z80_get_native_address(context, address); |
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1863 if (existing) { |
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1864 opts->cur_code = jmp(opts->cur_code, existing); |
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1865 break; |
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1866 } |
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1867 next = z80_decode(encoded, &inst); |
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1868 #ifdef DO_DEBUG_PRINT |
314
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Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler
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diff
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1869 z80_disasm(&inst, disbuf, address); |
235
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1870 if (inst.op == Z80_NOP) { |
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1871 printf("%X\t%s(%d)\n", address, disbuf, inst.immed); |
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1872 } else { |
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1873 printf("%X\t%s\n", address, disbuf); |
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1874 } |
268
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1875 #endif |
248
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1876 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address); |
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1877 z80_map_native_address(context, address, opts->cur_code, next-encoded, after - opts->cur_code); |
248
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1878 opts->cur_code = after; |
235
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1879 address += next-encoded; |
255
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1880 if (address > 0xFFFF) { |
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1881 address &= 0xFFFF; |
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1882 |
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1883 } else { |
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1884 encoded = next; |
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1885 } |
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1886 } while (!z80_is_terminal(&inst)); |
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1887 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address); |
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1888 if (opts->deferred) { |
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1889 address = opts->deferred->address; |
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1890 dprintf("defferred address: %X\n", address); |
235
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1891 if (address < 0x4000) { |
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1892 encoded = context->mem_pointers[0] + (address & 0x1FFF); |
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1893 } else if (address > 0x8000 && context->mem_pointers[1]) { |
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1894 encoded = context->mem_pointers[1] + (address & 0x7FFF); |
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1895 } else { |
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1896 printf("attempt to translate non-memory address: %X\n", address); |
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1897 exit(1); |
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1898 } |
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1899 } else { |
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1900 encoded = NULL; |
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1901 } |
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1902 } |
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|
1903 } |
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1904 |
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1905 void init_x86_z80_opts(x86_z80_options * options) |
213
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1906 { |
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1907 options->flags = 0; |
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1908 options->regs[Z80_B] = BH; |
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1909 options->regs[Z80_C] = RBX; |
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1910 options->regs[Z80_D] = CH; |
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1911 options->regs[Z80_E] = RCX; |
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1912 options->regs[Z80_H] = AH; |
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1913 options->regs[Z80_L] = RAX; |
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1914 options->regs[Z80_IXH] = DH; |
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1915 options->regs[Z80_IXL] = RDX; |
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1916 options->regs[Z80_IYH] = -1; |
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1917 options->regs[Z80_IYL] = R8; |
235
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1918 options->regs[Z80_I] = -1; |
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1919 options->regs[Z80_R] = -1; |
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1920 options->regs[Z80_A] = R10; |
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1921 options->regs[Z80_BC] = RBX; |
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1922 options->regs[Z80_DE] = RCX; |
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1923 options->regs[Z80_HL] = RAX; |
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1924 options->regs[Z80_SP] = R9; |
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1925 options->regs[Z80_AF] = -1; |
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1926 options->regs[Z80_IX] = RDX; |
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1927 options->regs[Z80_IY] = R8; |
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1928 size_t size = 1024 * 1024; |
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1929 options->cur_code = alloc_code(&size); |
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1930 options->code_end = options->cur_code + size; |
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1931 options->ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000); |
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1932 memset(options->ram_inst_sizes, 0, sizeof(uint8_t) * 0x2000); |
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1933 options->deferred = NULL; |
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1934 } |
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1935 |
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1936 void init_z80_context(z80_context * context, x86_z80_options * options) |
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1937 { |
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1938 memset(context, 0, sizeof(*context)); |
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1939 context->static_code_map = malloc(sizeof(context->static_code_map)); |
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1940 context->static_code_map->base = NULL; |
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1941 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000); |
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1942 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000); |
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1943 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9)); |
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1944 memset(context->banked_code_map, 0, sizeof(native_map_slot) * (1 << 9)); |
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1945 context->options = options; |
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1946 } |
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1947 |
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1948 void z80_reset(z80_context * context) |
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1949 { |
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1950 context->im = 0; |
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1951 context->iff1 = context->iff2 = 0; |
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1952 context->native_pc = z80_get_native_address_trans(context, 0); |
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1953 context->extra_pc = NULL; |
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1954 } |
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1955 |
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1956 |