repos/blastem: segacd.c annotate

annotate segacd.c @ 2148:2da377ea932f

Initial stab at CDC DMA cycle stealing and sub CPU refresh delays

author	Michael Pavone <pavone@retrodev.com>
date	Sat, 26 Mar 2022 20:14:41 -0700
parents	10e4439d8f13
children	3f09312685e3

rev	line source
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1 #include <stdlib.h>
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	2 #include <string.h>
2126 da1fae7d5407 Fix embarassing typo Michael Pavone <pavone@retrodev.com> parents: 2125 diff changeset	3 #include <ctype.h>
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	4 #include "cd_graphics.h"
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	5 #include "genesis.h"
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	6 #include "util.h"
2104 ff32a90260c9 Initial support for using debugger on sub CPU Michael Pavone <pavone@retrodev.com> parents: 2099 diff changeset	7 #include "debug.h"
ff32a90260c9 Initial support for using debugger on sub CPU Michael Pavone <pavone@retrodev.com> parents: 2099 diff changeset	8 #include "gdb_remote.h"
2123 50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	9 #include "blastem.h"
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	10
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	11 #define SCD_MCLKS 50000000
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	12 #define SCD_PERIPH_RESET_CLKS (SCD_MCLKS / 10)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	13 #define TIMER_TICK_CLKS 1536
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	14
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	15 enum {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	16 GA_SUB_CPU_CTRL,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	17 GA_MEM_MODE,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	18 GA_CDC_CTRL,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	19 GA_CDC_REG_DATA,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	20 GA_CDC_HOST_DATA,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	21 GA_CDC_DMA_ADDR,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	22 GA_STOP_WATCH,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	23 GA_COMM_FLAG,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	24 GA_COMM_CMD0,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	25 GA_COMM_CMD1,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	26 GA_COMM_CMD2,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	27 GA_COMM_CMD3,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	28 GA_COMM_CMD4,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	29 GA_COMM_CMD5,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	30 GA_COMM_CMD6,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	31 GA_COMM_CMD7,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	32 GA_COMM_STATUS0,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	33 GA_COMM_STATUS1,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	34 GA_COMM_STATUS2,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	35 GA_COMM_STATUS3,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	36 GA_COMM_STATUS4,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	37 GA_COMM_STATUS5,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	38 GA_COMM_STATUS6,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	39 GA_COMM_STATUS7,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	40 GA_TIMER,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	41 GA_INT_MASK,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	42 GA_CDD_FADER,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	43 GA_CDD_CTRL,
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	44 GA_CDD_STATUS0,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	45 GA_CDD_STATUS1,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	46 GA_CDD_STATUS2,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	47 GA_CDD_STATUS3,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	48 GA_CDD_STATUS4,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	49 GA_CDD_CMD0,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	50 GA_CDD_CMD1,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	51 GA_CDD_CMD2,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	52 GA_CDD_CMD3,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	53 GA_CDD_CMD4,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	54 GA_FONT_COLOR,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	55 GA_FONT_BITS,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	56 GA_FONT_DATA0,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	57 GA_FONT_DATA1,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	58 GA_FONT_DATA2,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	59 GA_FONT_DATA3,
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	60 GA_SUBCODE_START = 0x80,
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	61 GA_SUBCODE_MIRROR = 0xC0,
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	62
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	63 GA_HINT_VECTOR = GA_CDC_REG_DATA
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	64 };
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	65 //GA_SUB_CPU_CTRL
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	66 #define BIT_IEN2 0x8000
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	67 #define BIT_IFL2 0x0100
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	68 #define BIT_LEDG 0x0200
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	69 #define BIT_LEDR 0x0100
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	70 #define BIT_SBRQ 0x0002
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	71 #define BIT_SRES 0x0001
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	72 #define BIT_PRES 0x0001
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	73 //GA_MEM_MODE
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	74 #define MASK_PROG_BANK 0x00C0
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	75 #define BIT_OVERWRITE 0x0010
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	76 #define BIT_UNDERWRITE 0x0008
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	77 #define MASK_PRIORITY (BIT_OVERWRITE\|BIT_UNDERWRITE)
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	78 #define BIT_MEM_MODE 0x0004
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	79 #define BIT_DMNA 0x0002
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	80 #define BIT_RET 0x0001
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	81
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	82 //GA_CDC_CTRL
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	83 #define BIT_EDT 0x8000
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	84 #define BIT_DSR 0x4000
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	85
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	86 //GA_CDD_CTRL
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	87 #define BIT_MUTE 0x0100
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	88
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	89 enum {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	90 DST_MAIN_CPU = 2,
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	91 DST_SUB_CPU,
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	92 DST_PCM_RAM,
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	93 DST_PROG_RAM,
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	94 DST_WORD_RAM = 7
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	95 };
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	96
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	97 //GA_INT_MASK
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	98 #define BIT_MASK_IEN1 0x0002
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	99 #define BIT_MASK_IEN2 0x0004
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	100 #define BIT_MASK_IEN3 0x0008
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	101 #define BIT_MASK_IEN4 0x0010
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	102 #define BIT_MASK_IEN5 0x0020
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	103 #define BIT_MASK_IEN6 0x0040
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	104
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	105 //GA_CDD_CTRL
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	106 #define BIT_HOCK 0x0004
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	107
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	108 static void prog_ram_wp_write16(uint32_t address, void vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	109 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	110 m68k_context *m68k = vcontext;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	111 segacd_context *cd = m68k->system;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	112 //if (!(cd->gate_array[GA_MEM_MODE] & (1 << ((address >> 9) + 8)))) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	113 if (address >= ((cd->gate_array[GA_MEM_MODE] & 0xFF00) << 1)) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	114 cd->prog_ram[address >> 1] = value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	115 m68k_invalidate_code_range(m68k, address, address + 2);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	116 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	117 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	118 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	119
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	120 static void prog_ram_wp_write8(uint32_t address, void vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	121 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	122 m68k_context *m68k = vcontext;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	123 segacd_context *cd = m68k->system;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	124 if (address >= ((cd->gate_array[GA_MEM_MODE] & 0xFF00) << 1)) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	125 ((uint8_t *)cd->prog_ram)[address ^ 1] = value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	126 m68k_invalidate_code_range(m68k, address, address + 1);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	127 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	128 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	129 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	130
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	131 static uint16_t word_ram_2M_read16(uint32_t address, void *vcontext)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	132 {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	133 m68k_context *m68k = vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	134 uint16_t* bank = m68k->mem_pointers[1];
2099 b92c998c6742 Add some missing null checks in the Sega CD code dealing with word RAM switching Michael Pavone <pavone@retrodev.com> parents: 2094 diff changeset	135 if (!bank) {
b92c998c6742 Add some missing null checks in the Sega CD code dealing with word RAM switching Michael Pavone <pavone@retrodev.com> parents: 2094 diff changeset	136 return 0xFFFF;
b92c998c6742 Add some missing null checks in the Sega CD code dealing with word RAM switching Michael Pavone <pavone@retrodev.com> parents: 2094 diff changeset	137 }
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	138 uint16_t raw = bank[address >> 1 & ~1];
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	139 if (address & 2) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	140 return (raw & 0xF) \| (raw << 4 & 0xF00);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	141 } else {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	142 return (raw >> 4 & 0xF00) \| (raw >> 8 & 0xF);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	143 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	144 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	145
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	146 static uint8_t word_ram_2M_read8(uint32_t address, void *vcontext)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	147 {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	148 uint16_t word = word_ram_2M_read16(address, vcontext);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	149 if (address & 1) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	150 return word;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	151 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	152 return word >> 8;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	153 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	154
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	155 static void word_ram_2M_write8(uint32_t address, void vcontext, uint8_t value)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	156 {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	157 m68k_context *m68k = vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	158 segacd_context *cd = m68k->system;
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	159 if (!(cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE)) {
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2137 diff changeset	160 //TODO: Confirm this first write goes through (seemed like it in initial testing)
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	161 if (address & 1) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	162 address >>= 1;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	163 cd->word_ram[address] &= 0xFF00;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	164 cd->word_ram[address] \|= value;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	165 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	166 address >>= 1;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	167 cd->word_ram[address] &= 0x00FF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	168 cd->word_ram[address] \|= value << 8;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	169 }
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2137 diff changeset	170 m68k_invalidate_code_range(cd->genesis->m68k, cd->base + 0x200000 + (address & ~1), cd->base + 0x200000 + (address & ~1) + 1);
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	171 cd->sub_paused_wordram = 1;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	172 m68k->sync_cycle = m68k->target_cycle = m68k->current_cycle;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	173 m68k->should_return = 1;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	174 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	175 value &= 0xF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	176 uint16_t priority = cd->gate_array[GA_MEM_MODE] & MASK_PRIORITY;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	177
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	178 if (priority == BIT_OVERWRITE && !value) {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	179 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	180 }
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	181 if (priority == BIT_UNDERWRITE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	182 if (!value) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	183 return vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	184 }
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	185 uint8_t old = word_ram_2M_read8(address, vcontext);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	186 if (old) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	187 return vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	188 }
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	189 }
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	190 uint16_t* bank = m68k->mem_pointers[1];
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	191 if (!bank) {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	192 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	193 }
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	194 uint16_t raw = bank[address >> 1 & ~1];
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	195 uint16_t shift = ((address & 3) * 4);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	196 raw &= ~(0xF000 >> shift);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	197 raw \|= value << (12 - shift);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	198 bank[address >> 1 & ~1] = raw;
2099 b92c998c6742 Add some missing null checks in the Sega CD code dealing with word RAM switching Michael Pavone <pavone@retrodev.com> parents: 2094 diff changeset	199 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	200 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	201 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	202
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	203
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	204 static void word_ram_2M_write16(uint32_t address, void vcontext, uint16_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	205 {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	206 word_ram_2M_write8(address, vcontext, value >> 8);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	207 return word_ram_2M_write8(address + 1, vcontext, value);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	208 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	209
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	210 static uint16_t word_ram_1M_read16(uint32_t address, void *vcontext)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	211 {
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2137 diff changeset	212 //TODO: check behavior for these on hardware
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	213 return 0;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	214 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	215
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	216 static uint8_t word_ram_1M_read8(uint32_t address, void *vcontext)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	217 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	218 return 0;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	219 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	220
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	221 static void word_ram_1M_write16(uint32_t address, void vcontext, uint16_t value)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	222 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	223 return vcontext;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	224 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	225
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	226 static void word_ram_1M_write8(uint32_t address, void vcontext, uint8_t value)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	227 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	228 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	229 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	230
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	231
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	232 static uint16_t unmapped_prog_read16(uint32_t address, void *vcontext)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	233 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	234 return 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	235 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	236
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	237 static uint8_t unmapped_prog_read8(uint32_t address, void *vcontext)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	238 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	239 return 0xFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	240 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	241
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	242 static void unmapped_prog_write16(uint32_t address, void vcontext, uint16_t value)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	243 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	244 return vcontext;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	245 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	246
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	247 static void unmapped_prog_write8(uint32_t address, void vcontext, uint8_t value)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	248 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	249 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	250 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	251
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	252 static uint16_t unmapped_word_read16(uint32_t address, void *vcontext)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	253 {
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	254 m68k_context *m68k = vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	255 genesis_context *gen = m68k->system;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	256 segacd_context *cd = gen->expansion;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	257 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	258 return cd->word_ram[address + cd->bank_toggle];
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	259 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	260 return 0xFFFF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	261 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	262 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	263
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	264 static uint8_t unmapped_word_read8(uint32_t address, void *vcontext)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	265 {
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	266 m68k_context *m68k = vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	267 genesis_context *gen = m68k->system;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	268 segacd_context *cd = gen->expansion;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	269 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	270 if (address & 1) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	271 return cd->word_ram[(address & ~1) + cd->bank_toggle];
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	272 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	273 return cd->word_ram[address + cd->bank_toggle] >> 8;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	274 }
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	275 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	276 return 0xFF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	277 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	278 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	279
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	280 static void unmapped_word_write16(uint32_t address, void vcontext, uint16_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	281 {
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	282 m68k_context *m68k = vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	283 genesis_context *gen = m68k->system;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	284 segacd_context *cd = gen->expansion;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	285 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	286 cd->word_ram[address + cd->bank_toggle] = value;
2137 3ef9456b76cf Fix a crash regression from word RAM interleave changes Michael Pavone <pavone@retrodev.com> parents: 2136 diff changeset	287 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + address, cd->base + 0x200000 + address + 1);
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	288 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	289 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	290 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	291
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	292 static void unmapped_word_write8(uint32_t address, void vcontext, uint8_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	293 {
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	294 m68k_context *m68k = vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	295 genesis_context *gen = m68k->system;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	296 segacd_context *cd = gen->expansion;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	297 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	298 if (address & 1) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	299 uint32_t offset = (address & ~1) + cd->bank_toggle;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	300 cd->word_ram[offset] &= 0xFF00;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	301 cd->word_ram[offset] \|= value;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	302 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	303 cd->word_ram[address + cd->bank_toggle] &= 0xFF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	304 cd->word_ram[address + cd->bank_toggle] \|= value << 8;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	305 }
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2137 diff changeset	306 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + (address & ~1), cd->base + 0x200000 + (address & ~1) + 1);
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	307 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	308 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	309 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	310
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	311 static uint32_t cell_image_translate_address(uint32_t address)
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	312 {
2087 3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	313 uint32_t word_of_cell = address & 2;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	314 if (address < 0x10000) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	315 //64x32 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	316 uint32_t line_of_column = address & 0x3FC;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	317 uint32_t column = address & 0xFC00;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	318 address = (line_of_column << 6) \| (column >> 8) \| word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	319 } else if (address < 0x18000) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	320 //64x16 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	321 uint32_t line_of_column = address & 0x1FC;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	322 uint32_t column = address & 0x7E00;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	323 address = 0x10000 \| (line_of_column << 6) \| (column >> 7) \| word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	324 } else if (address < 0x1C000) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	325 //64x8 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	326 uint32_t line_of_column = address & 0x00FC;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	327 uint32_t column = address & 0x3F00;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	328 address = 0x18000 \| (line_of_column << 6) \| (column >> 6) \| word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	329 } else {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	330 //64x4 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	331 uint32_t line_of_column = address & 0x007C;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	332 uint32_t column = address & 0x1F80;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	333 address &= 0x1E000;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	334 address \|= (line_of_column << 6) \| (column >> 5) \| word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	335 }
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	336 return address;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	337 }
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	338
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	339 static uint16_t cell_image_read16(uint32_t address, void *vcontext)
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	340 {
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	341 address = cell_image_translate_address(address);
2087 3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	342 m68k_context *m68k = vcontext;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	343 genesis_context *gen = m68k->system;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	344 segacd_context *cd = gen->expansion;
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	345 if (!(cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE)) {
2099 b92c998c6742 Add some missing null checks in the Sega CD code dealing with word RAM switching Michael Pavone <pavone@retrodev.com> parents: 2094 diff changeset	346 return 0xFFFF;
b92c998c6742 Add some missing null checks in the Sega CD code dealing with word RAM switching Michael Pavone <pavone@retrodev.com> parents: 2094 diff changeset	347 }
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	348 return cd->word_ram[address + cd->bank_toggle];
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	349 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	350
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	351 static uint8_t cell_image_read8(uint32_t address, void *vcontext)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	352 {
2087 3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	353 uint16_t word = cell_image_read16(address & 0xFFFFFE, vcontext);
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	354 if (address & 1) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	355 return word;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	356 }
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	357 return word >> 8;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	358 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	359
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	360 static void cell_image_write16(uint32_t address, void vcontext, uint16_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	361 {
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	362 m68k_context *m68k = vcontext;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	363 genesis_context *gen = m68k->system;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	364 segacd_context *cd = gen->expansion;
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	365 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	366 address = cell_image_translate_address(address);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	367 cd->word_ram[address + cd->bank_toggle] = value;
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2137 diff changeset	368 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + address, cd->base + 0x200000 + address + 1);
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	369 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	370 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	371 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	372
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	373 static void cell_image_write8(uint32_t address, void vcontext, uint8_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	374 {
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	375 uint32_t byte = address & 1;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	376 address = cell_image_translate_address(address);
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	377 m68k_context *m68k = vcontext;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	378 genesis_context *gen = m68k->system;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	379 segacd_context *cd = gen->expansion;
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	380 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	381 if (byte) {
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	382 cd->word_ram[address + cd->bank_toggle] &= 0xFF00;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	383 cd->word_ram[address + cd->bank_toggle] \|= value;
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	384 } else {
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	385 cd->word_ram[address + cd->bank_toggle] &= 0x00FF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	386 cd->word_ram[address + cd->bank_toggle] \|= value << 8;
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	387 }
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2137 diff changeset	388 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + address, cd->base + 0x200000 + address + 1);
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	389 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	390 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	391 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	392
2127 1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	393 static void cdd_run(segacd_context *cd, uint32_t cycle)
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	394 {
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	395 cdd_mcu_run(&cd->cdd, cycle, cd->gate_array + GA_CDD_CTRL, &cd->cdc, &cd->fader);
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	396 lc8951_run(&cd->cdc, cycle);
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	397 }
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	398
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	399 static uint8_t pcm_read8(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	400 {
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	401 m68k_context *m68k = vcontext;
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	402 segacd_context *cd = m68k->system;
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	403 if (address & 1) {
2127 1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	404 //need to run CD drive because there may be a PCM DMA underway
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	405 cdd_run(cd, m68k->current_cycle);
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	406 rf5c164_run(&cd->pcm, m68k->current_cycle);
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	407 return rf5c164_read(&cd->pcm, address >> 1);
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	408 } else {
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	409 return 0xFF;
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	410 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	411 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	412
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	413 static uint16_t pcm_read16(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	414 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	415 return 0xFF00 \| pcm_read8(address+1, vcontext);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	416 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	417
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	418 static void pcm_write8(uint32_t address, void vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	419 {
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	420 m68k_context *m68k = vcontext;
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	421 segacd_context *cd = m68k->system;
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	422 if (address & 1) {
2127 1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	423 //need to run CD drive because there may be a PCM DMA underway
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	424 cdd_run(cd, m68k->current_cycle);
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	425 rf5c164_run(&cd->pcm, m68k->current_cycle);
2128 b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	426 while ((cd->pcm.flags & 0x81) == 1) {
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	427 //not sounding, but pending write
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	428 //DMA write conflict presumably adds wait states
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	429 m68k->current_cycle += 4;
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	430 rf5c164_run(&cd->pcm, m68k->current_cycle);
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	431 }
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	432 rf5c164_write(&cd->pcm, address >> 1, value);
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	433 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	434 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	435 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	436
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	437 static void pcm_write16(uint32_t address, void vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	438 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	439 return pcm_write8(address+1, vcontext, value);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	440 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	441
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	442
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	443 static void timers_run(segacd_context *cd, uint32_t cycle)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	444 {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	445 if (cycle <= cd->stopwatch_cycle) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	446 return;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	447 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	448 uint32_t ticks = (cycle - cd->stopwatch_cycle) / TIMER_TICK_CLKS;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	449 cd->stopwatch_cycle += ticks * TIMER_TICK_CLKS;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	450 cd->gate_array[GA_STOP_WATCH] += ticks;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	451 cd->gate_array[GA_STOP_WATCH] &= 0xFFF;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	452 if (ticks && !cd->timer_value) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	453 --ticks;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	454 cd->timer_value = cd->gate_array[GA_TIMER];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	455 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	456 if (ticks && cd->timer_value) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	457 while (ticks >= (cd->timer_value + 1)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	458 ticks -= cd->timer_value + 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	459 cd->timer_value = cd->gate_array[GA_TIMER];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	460 cd->timer_pending = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	461 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	462 cd->timer_value -= ticks;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	463 if (!cd->timer_value) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	464 cd->timer_pending = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	465 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	466 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	467 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	468
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	469 static uint32_t next_timer_int(segacd_context *cd)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	470 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	471 if (cd->timer_pending) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	472 return cd->stopwatch_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	473 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	474 if (cd->timer_value) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	475 return cd->stopwatch_cycle + TIMER_TICK_CLKS * cd->timer_value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	476 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	477 if (cd->gate_array[GA_TIMER]) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	478 return cd->stopwatch_cycle + TIMER_TICK_CLKS * (cd->gate_array[GA_TIMER] + 1);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	479 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	480 return CYCLE_NEVER;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	481 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	482
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	483 static void calculate_target_cycle(m68k_context * context)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	484 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	485 segacd_context *cd = context->system;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	486 context->int_cycle = CYCLE_NEVER;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	487 uint8_t mask = context->status & 0x7;
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	488 uint32_t cdc_cycle = CYCLE_NEVER;
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	489 if (mask < 6) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	490 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN6) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	491 uint32_t subcode_cycle = cd->cdd.subcode_int_pending ? context->current_cycle : cd->cdd.next_subcode_int_cycle;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	492 if (subcode_cycle != CYCLE_NEVER) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	493 context->int_cycle = subcode_cycle;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	494 context->int_num = 6;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	495 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	496 }
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	497 if (mask < 5) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	498 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN5) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	499 cdc_cycle = lc8951_next_interrupt(&cd->cdc);
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	500 //CDC interrupts only generated on falling edge of !INT signal
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	501 if (cd->cdc_int_ack) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	502 if (cdc_cycle > cd->cdc.cycle) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	503 cd->cdc_int_ack = 0;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	504 } else {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	505 cdc_cycle = CYCLE_NEVER;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	506 }
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	507 }
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	508 if (cdc_cycle < context->int_cycle) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	509 context->int_cycle = cdc_cycle;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	510 context->int_num = 5;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	511 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	512 }
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	513 if (mask < 4) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	514 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN4) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	515 uint32_t cdd_cycle = cd->cdd.int_pending ? context->current_cycle : cd->cdd.next_int_cycle;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	516 if (cdd_cycle < context->int_cycle) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	517 context->int_cycle = cdd_cycle;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	518 context->int_num = 4;
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	519 }
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	520 }
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	521 if (mask < 3) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	522 uint32_t next_timer;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	523 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN3) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	524 uint32_t next_timer_cycle = next_timer_int(cd);
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	525 if (next_timer_cycle < context->int_cycle) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	526 context->int_cycle = next_timer_cycle;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	527 context->int_num = 3;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	528 }
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	529 }
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	530 if (mask < 2) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	531 if (cd->int2_cycle < context->int_cycle && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2)) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	532 context->int_cycle = cd->int2_cycle;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	533 context->int_num = 2;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	534 }
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	535 if (mask < 1) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	536 if (cd->graphics_int_cycle < context->int_cycle && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN1)) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	537 context->int_cycle = cd->graphics_int_cycle;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	538 context->int_num = 1;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	539 }
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	540 }
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	541 }
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	542 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	543 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	544 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	545 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	546 if (context->int_cycle > context->current_cycle && context->int_pending == INT_PENDING_SR_CHANGE) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	547 context->int_pending = INT_PENDING_NONE;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	548 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	549 if (context->current_cycle >= context->sync_cycle) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	550 context->should_return = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	551 context->target_cycle = context->current_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	552 return;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	553 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	554 if (context->status & M68K_STATUS_TRACE \|\| context->trace_pending) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	555 context->target_cycle = context->current_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	556 return;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	557 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	558 context->target_cycle = context->sync_cycle < context->int_cycle ? context->sync_cycle : context->int_cycle;
2136 01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test Michael Pavone <pavone@retrodev.com> parents: 2135 diff changeset	559 if (context->int_cycle == cdc_cycle && context->int_num == 5) {
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	560 uint32_t before = context->target_cycle - 2 * cd->cdc.clock_step;
2136 01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test Michael Pavone <pavone@retrodev.com> parents: 2135 diff changeset	561 if (before < context->target_cycle) {
2131 d90d92ce5cab Improve CDC decode timing accuracy Michael Pavone <pavone@retrodev.com> parents: 2129 diff changeset	562 if (before > context->current_cycle) {
d90d92ce5cab Improve CDC decode timing accuracy Michael Pavone <pavone@retrodev.com> parents: 2129 diff changeset	563 context->target_cycle = context->sync_cycle = before;
2136 01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test Michael Pavone <pavone@retrodev.com> parents: 2135 diff changeset	564 } else {
01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test Michael Pavone <pavone@retrodev.com> parents: 2135 diff changeset	565 before = context->target_cycle - cd->cdc.clock_step;
01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test Michael Pavone <pavone@retrodev.com> parents: 2135 diff changeset	566 if (before > context->current_cycle) {
01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test Michael Pavone <pavone@retrodev.com> parents: 2135 diff changeset	567 context->target_cycle = context->sync_cycle = before;
01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test Michael Pavone <pavone@retrodev.com> parents: 2135 diff changeset	568 }
2131 d90d92ce5cab Improve CDC decode timing accuracy Michael Pavone <pavone@retrodev.com> parents: 2129 diff changeset	569 }
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	570 }
ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	571 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	572 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	573
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	574 static uint16_t sub_gate_read16(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	575 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	576 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	577 segacd_context *cd = m68k->system;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	578 uint32_t reg = address >> 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	579 switch (reg)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	580 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	581 case GA_SUB_CPU_CTRL: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	582 uint16_t value = cd->gate_array[reg] & 0xFFFE;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	583 if (cd->periph_reset_cycle == CYCLE_NEVER \|\| (m68k->current_cycle - cd->periph_reset_cycle) > SCD_PERIPH_RESET_CLKS) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	584 value \|= BIT_PRES;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	585 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	586 return value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	587 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	588 case GA_MEM_MODE:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	589 return cd->gate_array[reg] & 0xFF1F;
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	590 case GA_CDC_CTRL:
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	591 cdd_run(cd, m68k->current_cycle);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	592 return cd->gate_array[reg] \| cd->cdc.ar;
70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	593 case GA_CDC_REG_DATA:
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	594 cdd_run(cd, m68k->current_cycle);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	595 return lc8951_reg_read(&cd->cdc);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	596 case GA_CDC_HOST_DATA: {
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	597 cdd_run(cd, m68k->current_cycle);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	598 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	599 if (dst == DST_SUB_CPU) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	600 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	601 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	602 lc8951_resume_transfer(&cd->cdc, cd->cdc.cycle);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	603 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	604 calculate_target_cycle(cd->m68k);
2068 f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	605
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	606 }
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	607 return cd->gate_array[reg];
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	608 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	609 case GA_STOP_WATCH:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	610 case GA_TIMER:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	611 timers_run(cd, m68k->current_cycle);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	612 return cd->gate_array[reg];
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	613 case GA_CDD_STATUS0:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	614 case GA_CDD_STATUS1:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	615 case GA_CDD_STATUS2:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	616 case GA_CDD_STATUS3:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	617 case GA_CDD_STATUS4:
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	618 cdd_run(cd, m68k->current_cycle);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	619 return cd->gate_array[reg];
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	620 break;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	621 case GA_FONT_DATA0:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	622 case GA_FONT_DATA1:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	623 case GA_FONT_DATA2:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	624 case GA_FONT_DATA3: {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	625 uint16_t shift = 4 * (3 - (reg - GA_FONT_DATA0));
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	626 uint16_t value = 0;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	627 uint16_t fg = cd->gate_array[GA_FONT_COLOR] >> 4;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	628 uint16_t bg = cd->gate_array[GA_FONT_COLOR] & 0xF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	629 for (int i = 0; i < 4; i++) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	630 uint16_t pixel = 0;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	631 if (cd->gate_array[GA_FONT_BITS] & 1 << (shift + i)) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	632 pixel = fg;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	633 } else {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	634 pixel = bg;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	635 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	636 value \|= pixel << (i * 4);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	637 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	638 return value;
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	639 }
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	640 case GA_STAMP_SIZE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	641 case GA_IMAGE_BUFFER_LINES:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	642 //these two have bits that change based on graphics operations
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	643 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	644 return cd->gate_array[reg];
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	645 case GA_TRACE_VECTOR_BASE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	646 //write only
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	647 return 0xFFFF;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	648 default:
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	649 if (reg >= GA_SUBCODE_MIRROR) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	650 return cd->gate_array[GA_SUBCODE_START + (reg & 0x3F)];
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	651 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	652 return cd->gate_array[reg];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	653 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	654 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	655
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	656 static uint8_t sub_gate_read8(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	657 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	658 uint16_t val = sub_gate_read16(address, vcontext);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	659 return address & 1 ? val : val >> 8;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	660 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	661
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	662 static void sub_gate_write16(uint32_t address, void vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	663 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	664 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	665 segacd_context *cd = m68k->system;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	666 uint32_t reg = address >> 1;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	667 switch (reg)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	668 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	669 case GA_SUB_CPU_CTRL:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	670 cd->gate_array[reg] &= 0xF0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	671 cd->gate_array[reg] \|= value & (BIT_LEDG\|BIT_LEDR);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	672 if (value & BIT_PRES) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	673 cd->periph_reset_cycle = m68k->current_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	674 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	675 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	676 case GA_MEM_MODE: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	677 uint16_t changed = value ^ cd->gate_array[reg];
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	678 uint8_t old_main_has_word2m = cd->main_has_word2m;
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	679 if (value & BIT_RET) {
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	680 cd->main_has_word2m = 1;
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	681 }
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	682 uint8_t old_bank_toggle = cd->bank_toggle;
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	683 cd->bank_toggle = value & BIT_RET;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	684 genesis_context *gen = cd->genesis;
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	685 cd->gate_array[reg] &= 0xFFC0;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	686 if (changed & BIT_MEM_MODE) {
2120 91ed3c4cdfd9 Fix the regression in Stellar Fire while still passing RET/DMNA tests Michael Pavone <pavone@retrodev.com> parents: 2119 diff changeset	687 cd->main_swap_request = cd->bank_toggle && !old_bank_toggle;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	688 if (value & BIT_MEM_MODE) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	689 //switch to 1M mode
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	690 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL; //(value & BIT_RET) ? cd->word_ram + 0x10000 : cd->word_ram;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	691 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	692 m68k->mem_pointers[0] = NULL;
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	693 m68k->mem_pointers[1] = cd->bank_toggle ? cd->word_ram : cd->word_ram + 1;
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	694 cd->gate_array[reg] \|= value & (MASK_PRIORITY\|BIT_RET\|BIT_MEM_MODE);
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	695 if (cd->main_swap_request) {
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	696 cd->gate_array[reg] \|= BIT_DMNA;
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	697 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	698 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	699 //switch to 2M mode
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	700 if (cd->main_has_word2m) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	701 //Main CPU will have word ram
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	702 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	703 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	704 m68k->mem_pointers[0] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	705 m68k->mem_pointers[1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	706 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	707 //sub cpu will have word ram
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	708 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	709 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	710 m68k->mem_pointers[0] = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	711 m68k->mem_pointers[1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	712 }
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	713 cd->gate_array[reg] \|= value & (MASK_PRIORITY\|BIT_MEM_MODE);
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	714 cd->gate_array[reg] \|= cd->main_has_word2m ? BIT_RET : BIT_DMNA;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	715 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	716 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	717 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000);
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	718 } else if (value & BIT_MEM_MODE) {
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	719 //1M mode
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	720 if (old_bank_toggle != cd->bank_toggle) {
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	721 m68k->mem_pointers[1] = (value & BIT_RET) ? cd->word_ram : cd->word_ram + 1;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	722 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	723 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000);
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	724 cd->main_swap_request = 0;
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	725 }
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	726 cd->gate_array[reg] \|= value & (MASK_PRIORITY\|BIT_RET\|BIT_MEM_MODE);
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	727 if (cd->main_swap_request) {
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	728 cd->gate_array[reg] \|= BIT_DMNA;
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	729 }
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	730 } else {
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	731 //2M mode
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	732 if (old_main_has_word2m != cd->main_has_word2m) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	733 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	734 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	735 m68k->mem_pointers[0] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	736 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	737 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	738 }
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	739 cd->gate_array[reg] \|= value & MASK_PRIORITY;
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	740 cd->gate_array[reg] \|= cd->main_has_word2m ? BIT_RET : BIT_DMNA;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	741 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	742 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	743 }
2144 10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	744 case GA_CDC_CTRL: {
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	745 cdd_run(cd, m68k->current_cycle);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	746 lc8951_ar_write(&cd->cdc, value);
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	747 //cd->gate_array[reg] &= 0xC000;
2144 10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	748 uint16_t old_dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	749 //apparently this clears EDT, should it also clear DSR?
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	750 cd->gate_array[reg] = value & 0x0700;
2144 10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	751 uint16_t dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	752 if (dest != old_dest) {
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	753 if (dest == DST_PCM_RAM) {
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	754 lc8951_set_dma_multiple(&cd->cdc, 21);
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	755 } else {
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	756 lc8951_set_dma_multiple(&cd->cdc, 6);
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	757 }
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	758 if ((old_dest < DST_MAIN_CPU \|\| old_dest == 6) && dest >= DST_MAIN_CPU && dest != 6) {
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	759 lc8951_resume_transfer(&cd->cdc, m68k->current_cycle);
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	760 }
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	761 calculate_target_cycle(m68k);
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	762 }
2135 95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	763 cd->gate_array[GA_CDC_DMA_ADDR] = 0;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	764 cd->cdc_dst_low = 0;
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	765 break;
2144 10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	766 }
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	767 case GA_CDC_REG_DATA:
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	768 cdd_run(cd, m68k->current_cycle);
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	769 printf("CDC write %X: %X @ %u\n", cd->cdc.ar, value, m68k->current_cycle);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	770 lc8951_reg_write(&cd->cdc, value);
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	771 calculate_target_cycle(m68k);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	772 break;
2135 95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	773 case GA_CDC_HOST_DATA:
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	774 //writes to this register have the same side effects as reads
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	775 sub_gate_read16(address, vcontext);
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	776 break;
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	777 case GA_CDC_DMA_ADDR:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	778 cdd_run(cd, m68k->current_cycle);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	779 cd->gate_array[reg] = value;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	780 cd->cdc_dst_low = 0;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	781 break;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	782 case GA_STOP_WATCH:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	783 //docs say you should only write zero to reset
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	784 //mcd-verificator comments suggest any value will reset
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	785 timers_run(cd, m68k->current_cycle);
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	786 cd->gate_array[reg] = 0;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	787 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	788 case GA_COMM_FLAG:
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	789 cd->gate_array[reg] &= 0xFF00;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	790 cd->gate_array[reg] \|= value & 0xFF;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	791 break;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	792 case GA_COMM_STATUS0:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	793 case GA_COMM_STATUS1:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	794 case GA_COMM_STATUS2:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	795 case GA_COMM_STATUS3:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	796 case GA_COMM_STATUS4:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	797 case GA_COMM_STATUS5:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	798 case GA_COMM_STATUS6:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	799 case GA_COMM_STATUS7:
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	800 //no effects for these other than saving the value
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	801 cd->gate_array[reg] = value;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	802 break;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	803 case GA_TIMER:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	804 timers_run(cd, m68k->current_cycle);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	805 cd->gate_array[reg] = value & 0xFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	806 calculate_target_cycle(m68k);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	807 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	808 case GA_INT_MASK:
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	809 if (!(cd->gate_array[reg] & BIT_MASK_IEN6)) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	810 //subcode interrupts can't be made pending when they are disabled in this reg
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	811 cd->cdd.subcode_int_pending = 0;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	812 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	813 cd->gate_array[reg] = value & (BIT_MASK_IEN6\|BIT_MASK_IEN5\|BIT_MASK_IEN4\|BIT_MASK_IEN3\|BIT_MASK_IEN2\|BIT_MASK_IEN1);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	814 calculate_target_cycle(m68k);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	815 break;
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	816 case GA_CDD_FADER:
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	817 cdd_run(cd, m68k->current_cycle);
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	818 value &= 0x7FFF;
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	819 cdd_fader_attenuation_write(&cd->fader, value);
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	820 cd->gate_array[reg] &= 0x8000;
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	821 cd->gate_array[reg] \|= value;
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	822 break;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	823 case GA_CDD_CTRL: {
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	824 cdd_run(cd, m68k->current_cycle);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	825 uint16_t changed = cd->gate_array[reg] ^ value;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	826 if (changed & BIT_HOCK) {
2073 c69e42444f96 Fix some cycle adjustment stuff and an off-by one on hte TOCT response Michael Pavone <pavone@retrodev.com> parents: 2069 diff changeset	827 cd->gate_array[reg] &= ~BIT_HOCK;
c69e42444f96 Fix some cycle adjustment stuff and an off-by one on hte TOCT response Michael Pavone <pavone@retrodev.com> parents: 2069 diff changeset	828 cd->gate_array[reg] \|= value & BIT_HOCK;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	829 if (value & BIT_HOCK) {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	830 cdd_hock_enabled(&cd->cdd);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	831 } else {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	832 cdd_hock_disabled(&cd->cdd);
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	833 cd->gate_array[reg] \|= BIT_MUTE;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	834 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	835 calculate_target_cycle(m68k);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	836 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	837 break;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	838 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	839 case GA_CDD_CMD0:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	840 case GA_CDD_CMD1:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	841 case GA_CDD_CMD2:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	842 case GA_CDD_CMD3:
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	843 cdd_run(cd, m68k->current_cycle);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	844 cd->gate_array[reg] = value & 0x0F0F;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	845 break;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	846 case GA_CDD_CMD4:
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	847 cdd_run(cd, m68k->current_cycle);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	848 cd->gate_array[reg] = value & 0x0F0F;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	849 cdd_mcu_start_cmd_recv(&cd->cdd, cd->gate_array + GA_CDD_CTRL);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	850 break;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	851 case GA_FONT_COLOR:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	852 cd->gate_array[reg] = value & 0xFF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	853 break;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	854 case GA_FONT_BITS:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	855 cd->gate_array[reg] = value;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	856 break;
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	857 case GA_STAMP_SIZE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	858 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	859 cd->gate_array[reg] &= BIT_GRON;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	860 cd->gate_array[reg] \|= value & (BIT_SMS\|BIT_STS\|BIT_RPT);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	861 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	862 case GA_STAMP_MAP_BASE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	863 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	864 cd->gate_array[reg] = value & 0xFFE0;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	865 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	866 case GA_IMAGE_BUFFER_VCELLS:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	867 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	868 cd->gate_array[reg] = value & 0x1F;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	869 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	870 case GA_IMAGE_BUFFER_START:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	871 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	872 cd->gate_array[reg] = value & 0xFFF8;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	873 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	874 case GA_IMAGE_BUFFER_OFFSET:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	875 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	876 cd->gate_array[reg] = value & 0x3F;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	877 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	878 case GA_IMAGE_BUFFER_HDOTS:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	879 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	880 cd->gate_array[reg] = value & 0x1FF;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	881 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	882 case GA_IMAGE_BUFFER_LINES:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	883 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	884 cd->gate_array[reg] = value & 0xFF;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	885 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	886 case GA_TRACE_VECTOR_BASE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	887 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	888 cd->gate_array[reg] = value & 0xFFFE;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	889 cd_graphics_start(cd);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	890 break;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	891 default:
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	892 printf("Unhandled gate array write %X:%X\n", address, value);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	893 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	894 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	895 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	896
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	897 static void sub_gate_write8(uint32_t address, void vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	898 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	899 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	900 segacd_context *cd = m68k->system;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	901 uint32_t reg = (address & 0x1FF) >> 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	902 uint16_t value16;
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	903 switch (address >> 1)
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	904 {
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	905 case GA_MEM_MODE:
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	906 case GA_CDC_HOST_DATA:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	907 case GA_CDC_DMA_ADDR:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	908 case GA_STOP_WATCH:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	909 case GA_COMM_FLAG:
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	910 case GA_TIMER:
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	911 case GA_CDD_FADER:
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	912 case GA_FONT_COLOR:
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	913 //these registers treat all writes as word-wide
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	914 value16 = value \| (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	915 break;
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	916 case GA_CDC_CTRL:
70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	917 if (address & 1) {
70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	918 lc8951_ar_write(&cd->cdc, value);
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	919 return vcontext;
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	920 } else {
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	921 value16 = cd->cdc.ar \| (value << 8);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	922 }
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	923 break;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	924 case GA_CDD_CMD4:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	925 if (!address) {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	926 //byte write to $FF804A should not trigger transfer
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	927 cdd_run(cd, m68k->current_cycle);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	928 cd->gate_array[reg] &= 0x0F;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	929 cd->gate_array[reg] \|= (value << 8 & 0x0F00);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	930 return vcontext;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	931 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	932 //intentional fallthrough for $FF804B
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	933 default:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	934 if (address & 1) {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	935 value16 = cd->gate_array[reg] & 0xFF00 \| value;
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	936 } else {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	937 value16 = cd->gate_array[reg] & 0xFF \| (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	938 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	939 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	940 return sub_gate_write16(address, vcontext, value16);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	941 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	942
2135 95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	943 static uint8_t can_main_access_prog(segacd_context *cd)
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	944 {
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	945 //TODO: use actual busack
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	946 return cd->busreq \|\| !cd->reset;
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	947 }
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	948
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	949 static uint8_t handle_cdc_byte(void *vsys, uint8_t value)
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	950 {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	951 segacd_context *cd = vsys;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	952 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	953 //host reg is already full, pause transfer
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	954 return 0;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	955 }
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	956 if (cd->cdc.cycle == cd->cdc.transfer_end) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	957 cd->gate_array[GA_CDC_CTRL] \|= BIT_EDT;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	958 printf("EDT set at %u\n", cd->cdc.cycle);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	959 }
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	960 uint16_t dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	961 if (!(cd->cdc_dst_low & 1)) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	962 cd->gate_array[GA_CDC_HOST_DATA] &= 0xFF;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	963 cd->gate_array[GA_CDC_HOST_DATA] \|= value << 8;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	964 cd->cdc_dst_low++;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	965 if (dest != DST_PCM_RAM) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	966 //PCM RAM writes a byte at a time
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	967 return 1;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	968 }
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	969 } else {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	970 cd->gate_array[GA_CDC_HOST_DATA] &= 0xFF00;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	971 cd->gate_array[GA_CDC_HOST_DATA] \|= value;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	972 }
2068 f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	973
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	974 uint32_t dma_addr = cd->gate_array[GA_CDC_DMA_ADDR] << 3;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	975 dma_addr \|= cd->cdc_dst_low;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	976 switch (dest)
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	977 {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	978 case DST_MAIN_CPU:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	979 case DST_SUB_CPU:
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	980 cd->cdc_dst_low = 0;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	981 cd->gate_array[GA_CDC_CTRL] \|= BIT_DSR;
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	982 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	983 case DST_PCM_RAM:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	984 dma_addr &= (1 << 13) - 1;
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	985 rf5c164_run(&cd->pcm, cd->cdc.cycle);
2128 b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	986 while ((cd->pcm.flags & 0x81) == 1) {
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	987 //not sounding, but pending write
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	988 //DMA write conflict with CPU
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	989 rf5c164_run(&cd->pcm, cd->pcm.cycle + 4);
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	990 }
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	991 rf5c164_write(&cd->pcm, 0x1000 \| (dma_addr >> 1), value);
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	992 dma_addr += 2;
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	993 cd->cdc_dst_low = dma_addr & 7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	994 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3;
2148 2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	995 //TODO: determine actual main CPU penalty
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	996 cd->m68k->current_cycle += 2 * cd->m68k->options->gen.bus_cycles;
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	997 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	998 case DST_PROG_RAM:
2135 95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	999 if (can_main_access_prog(cd)) {
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1000 return 0;
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1001 }
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1002 cd->prog_ram[dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA];
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1003 m68k_invalidate_code_range(cd->m68k, dma_addr - 1, dma_addr + 1);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1004 dma_addr++;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1005 cd->cdc_dst_low = dma_addr & 7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1006 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3;
2148 2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1007 //TODO: determine actual main CPU penalty
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1008 cd->m68k->current_cycle += 2 * cd->m68k->options->gen.bus_cycles;
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1009 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1010 case DST_WORD_RAM:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1011 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1012 //1M mode, write to bank assigned to Sub CPU
2135 95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1013
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1014 uint32_t masked = dma_addr & (1 << 17) - 2;
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1015 cd->m68k->mem_pointers[1][masked] = cd->gate_array[GA_CDC_HOST_DATA];
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1016 m68k_invalidate_code_range(cd->m68k, 0x0C0000 + masked - 1, 0x0C0000 + masked + 1);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1017 } else {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1018 //2M mode, check if Sub CPU has access
2129 4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU Michael Pavone <pavone@retrodev.com> parents: 2128 diff changeset	1019 if (cd->main_has_word2m) {
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU Michael Pavone <pavone@retrodev.com> parents: 2128 diff changeset	1020 return 0;
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU Michael Pavone <pavone@retrodev.com> parents: 2128 diff changeset	1021 } else {
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	1022 cd_graphics_run(cd, cd->cdc.cycle);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1023 dma_addr &= (1 << 18) - 1;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1024 cd->word_ram[dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA];
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1025 m68k_invalidate_code_range(cd->m68k, 0x080000 + dma_addr, 0x080000 + dma_addr + 1);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1026 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1027 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1028 dma_addr++;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1029 cd->cdc_dst_low = dma_addr & 7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1030 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1031 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1032 default:
2144 10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	1033 return 0;
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1034 printf("Invalid CDC transfer destination %d\n", dest);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1035 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1036 return 1;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1037 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1038
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1039 static void scd_peripherals_run(segacd_context *cd, uint32_t cycle)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1040 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1041 timers_run(cd, cycle);
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	1042 cdd_run(cd, cycle);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1043 cd_graphics_run(cd, cycle);
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	1044 rf5c164_run(&cd->pcm, cycle);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1045 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1046
2148 2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1047 //TODO: do some logic analyzer captuers to get actual values
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1048 #define REFRESH_INTERVAL 256
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1049 #define REFRESH_DELAY 4
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1050
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1051 static m68k_context sync_components(m68k_context context, uint32_t address)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1052 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1053 segacd_context *cd = context->system;
2148 2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1054
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1055 uint32_t num_refresh = (context->current_cycle - cd->last_refresh_cycle) / REFRESH_INTERVAL;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1056 cd->last_refresh_cycle = cd->last_refresh_cycle + num_refresh * REFRESH_INTERVAL;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1057 context->current_cycle += num_refresh * REFRESH_DELAY;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1058
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1059 scd_peripherals_run(cd, context->current_cycle);
2104 ff32a90260c9 Initial support for using debugger on sub CPU Michael Pavone <pavone@retrodev.com> parents: 2099 diff changeset	1060 if (address && cd->enter_debugger) {
ff32a90260c9 Initial support for using debugger on sub CPU Michael Pavone <pavone@retrodev.com> parents: 2099 diff changeset	1061 genesis_context *gen = cd->genesis;
2106 d2989e32c026 Fix bug in Sub CPU debugger suport Michael Pavone <pavone@retrodev.com> parents: 2104 diff changeset	1062 cd->enter_debugger = 0;
2104 ff32a90260c9 Initial support for using debugger on sub CPU Michael Pavone <pavone@retrodev.com> parents: 2099 diff changeset	1063 if (gen->header.debugger_type == DEBUGGER_NATIVE) {
ff32a90260c9 Initial support for using debugger on sub CPU Michael Pavone <pavone@retrodev.com> parents: 2099 diff changeset	1064 debugger(context, address);
ff32a90260c9 Initial support for using debugger on sub CPU Michael Pavone <pavone@retrodev.com> parents: 2099 diff changeset	1065 } else {
ff32a90260c9 Initial support for using debugger on sub CPU Michael Pavone <pavone@retrodev.com> parents: 2099 diff changeset	1066 gdb_debug_enter(context, address);
ff32a90260c9 Initial support for using debugger on sub CPU Michael Pavone <pavone@retrodev.com> parents: 2099 diff changeset	1067 }
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	1068 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1069 switch (context->int_ack)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1070 {
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1071 case 1:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1072 cd->graphics_int_cycle = CYCLE_NEVER;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1073 break;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1074 case 2:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1075 cd->int2_cycle = CYCLE_NEVER;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1076 break;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1077 case 3:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1078 cd->timer_pending = 0;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1079 break;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1080 case 4:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1081 cd->cdd.int_pending = 0;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1082 break;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1083 case 5:
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1084 cd->cdc_int_ack = 1;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1085 break;
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	1086 case 6:
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	1087 cd->cdd.subcode_int_pending = 0;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	1088 break;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1089 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1090 context->int_ack = 0;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1091 calculate_target_cycle(context);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1092 return context;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1093 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1094
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1095 void scd_run(segacd_context *cd, uint32_t cycle)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1096 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1097 uint8_t m68k_run = !can_main_access_prog(cd);
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	1098 while (cycle > cd->m68k->current_cycle) {
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	1099 if (m68k_run && !cd->sub_paused_wordram) {
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1100 uint32_t start = cd->m68k->current_cycle;
2148 2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1101
2104 ff32a90260c9 Initial support for using debugger on sub CPU Michael Pavone <pavone@retrodev.com> parents: 2099 diff changeset	1102 cd->m68k->sync_cycle = cd->enter_debugger ? cd->m68k->current_cycle + 1 : cycle;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1103 if (cd->need_reset) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1104 cd->need_reset = 0;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1105 m68k_reset(cd->m68k);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1106 } else {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1107 calculate_target_cycle(cd->m68k);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1108 resume_68k(cd->m68k);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1109 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1110 } else {
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1111 cd->m68k->current_cycle = cycle;
2148 2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1112 cd->last_refresh_cycle = cycle;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1113 }
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	1114 scd_peripherals_run(cd, cd->m68k->current_cycle);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1115 }
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	1116
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1117 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1118
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1119 uint32_t gen_cycle_to_scd(uint32_t cycle, genesis_context *gen)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1120 {
2055 c4d066d798c4 Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works Michael Pavone <pavone@retrodev.com> parents: 2054 diff changeset	1121 return ((uint64_t)cycle) * ((uint64_t)SCD_MCLKS) / ((uint64_t)gen->normal_clock);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1122 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1123
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1124 void scd_adjust_cycle(segacd_context *cd, uint32_t deduction)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1125 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1126 deduction = gen_cycle_to_scd(deduction, cd->genesis);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1127 cd->m68k->current_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1128 cd->stopwatch_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1129 if (deduction >= cd->int2_cycle) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1130 cd->int2_cycle = 0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1131 } else if (cd->int2_cycle != CYCLE_NEVER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1132 cd->int2_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1133 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1134 if (deduction >= cd->periph_reset_cycle) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1135 cd->periph_reset_cycle = CYCLE_NEVER;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1136 } else if (cd->periph_reset_cycle != CYCLE_NEVER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1137 cd->periph_reset_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1138 }
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1139 cdd_mcu_adjust_cycle(&cd->cdd, deduction);
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1140 lc8951_adjust_cycles(&cd->cdc, deduction);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1141 cd->graphics_cycle -= deduction;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1142 if (cd->graphics_int_cycle != CYCLE_NEVER) {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1143 if (cd->graphics_int_cycle > deduction) {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1144 cd->graphics_int_cycle -= deduction;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1145 } else {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1146 cd->graphics_int_cycle = 0;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1147 }
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1148 }
2148 2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1149 if (deduction >= cd->last_refresh_cycle) {
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1150 cd->last_refresh_cycle -= deduction;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1151 } else {
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1152 cd->last_refresh_cycle = 0;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1153 }
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	1154 cd->pcm.cycle -= deduction;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1155 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1156
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1157 static uint16_t main_gate_read16(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1158 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1159 m68k_context *m68k = vcontext;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1160 genesis_context *gen = m68k->system;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1161 segacd_context *cd = gen->expansion;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1162 uint32_t scd_cycle = gen_cycle_to_scd(m68k->current_cycle, gen);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1163 scd_run(cd, scd_cycle);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1164 uint32_t offset = (address & 0x1FF) >> 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1165 switch (offset)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1166 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1167 case GA_SUB_CPU_CTRL: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1168 uint16_t value = 0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1169 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1170 value \|= BIT_IEN2;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1171 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1172 if (cd->int2_cycle != CYCLE_NEVER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1173 value \|= BIT_IFL2;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1174 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1175 if (can_main_access_prog(cd)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1176 value \|= BIT_SBRQ;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1177 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1178 if (cd->reset) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1179 value \|= BIT_SRES;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1180 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1181 return value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1182 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1183 case GA_MEM_MODE:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1184 //Main CPU can't read priority mode bits
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1185 return cd->gate_array[offset] & 0xFFE7;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1186 case GA_HINT_VECTOR:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1187 return cd->rom_mut[0x72/2];
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1188 case GA_CDC_HOST_DATA: {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1189 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1190 if (dst == DST_MAIN_CPU) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1191 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1192 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1193 lc8951_resume_transfer(&cd->cdc, scd_cycle);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1194 } else {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1195 printf("Read of CDC host data with DSR clear at %u\n", scd_cycle);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1196 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1197 calculate_target_cycle(cd->m68k);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1198 }
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1199 return cd->gate_array[offset];
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1200 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1201 case GA_CDC_DMA_ADDR:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1202 //TODO: open bus maybe?
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1203 return 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1204 default:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1205 if (offset < GA_TIMER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1206 return cd->gate_array[offset];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1207 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1208 //TODO: open bus maybe?
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1209 return 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1210 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1211 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1212
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1213 static uint8_t main_gate_read8(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1214 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1215 uint16_t val = main_gate_read16(address & 0xFE, vcontext);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1216 return address & 1 ? val : val >> 8;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1217 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1218
2068 f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1219 static void dump_prog_ram(segacd_context *cd)
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1220 {
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1221 static int dump_count;
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1222 char fname[256];
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1223 sprintf(fname, "prog_ram_%d.bin", dump_count++);
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1224 FILE *f = fopen(fname, "wb");
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1225 if (f) {
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1226 uint32_t last = 256*1024-1;
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1227 for(; last > 0; --last)
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1228 {
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1229 if (cd->prog_ram[last]) {
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1230 break;
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1231 }
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1232 }
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1233 for (uint32_t i = 0; i <= last; i++)
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1234 {
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1235 uint8_t pair[2];
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1236 pair[0] = cd->prog_ram[i] >> 8;
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1237 pair[1] = cd->prog_ram[i];
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1238 fwrite(pair, 1, sizeof(pair), f);
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1239 }
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1240
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1241 fclose(f);
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1242 }
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1243 }
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1244
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1245 static void main_gate_write16(uint32_t address, void vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1246 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1247 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1248 genesis_context *gen = m68k->system;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1249 segacd_context *cd = gen->expansion;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1250 uint32_t scd_cycle = gen_cycle_to_scd(m68k->current_cycle, gen);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1251 scd_run(cd, scd_cycle);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1252 uint32_t reg = (address & 0x1FF) >> 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1253 switch (reg)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1254 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1255 case GA_SUB_CPU_CTRL: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1256 uint8_t old_access = can_main_access_prog(cd);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1257 cd->busreq = value & BIT_SBRQ;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1258 uint8_t old_reset = cd->reset;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1259 cd->reset = value & BIT_SRES;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1260 if (cd->reset && !old_reset) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1261 cd->need_reset = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1262 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1263 if (value & BIT_IFL2) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1264 cd->int2_cycle = scd_cycle;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1265 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1266 /*cd->gate_array[reg] &= 0x7FFF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1267 cd->gate_array[reg] \|= value & 0x8000;*/
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1268 uint8_t new_access = can_main_access_prog(cd);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1269 uint32_t bank = cd->gate_array[GA_MEM_MODE] >> 6 & 0x3;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1270 if (new_access) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1271 if (!old_access) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1272 m68k->mem_pointers[cd->memptr_start_index] = cd->prog_ram + bank * 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1273 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1274 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1275 } else if (old_access) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1276 m68k->mem_pointers[cd->memptr_start_index] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1277 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1278 m68k_invalidate_code_range(cd->m68k, bank * 0x20000, (bank + 1) * 0x20000);
2135 95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1279 dump_prog_ram(cd);
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1280 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1281 if (dst == DST_PROG_RAM) {
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1282 lc8951_resume_transfer(&cd->cdc, cd->cdc.cycle);
2068 f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1283 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1284 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1285 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1286 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1287 case GA_MEM_MODE: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1288 uint16_t changed = cd->gate_array[reg] ^ value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1289 //Main CPU can't write priority mode bits, MODE or RET
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1290 cd->gate_array[reg] &= 0x001F;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1291 cd->gate_array[reg] \|= value & 0xFFC0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1292 if ((cd->gate_array[reg] & BIT_MEM_MODE)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1293 //1M mode
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1294 if (!(value & BIT_DMNA)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1295 cd->gate_array[reg] \|= BIT_DMNA;
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	1296 cd->main_swap_request = 1;
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	1297 } else {
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	1298 cd->main_has_word2m = 0;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1299 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1300 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1301 //2M mode
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1302 if (changed & value & BIT_DMNA) {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1303 cd->gate_array[reg] \|= BIT_DMNA;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1304 m68k->mem_pointers[cd->memptr_start_index + 1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1305 m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1306 cd->m68k->mem_pointers[0] = cd->word_ram;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1307 cd->gate_array[reg] &= ~BIT_RET;
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	1308 cd->main_has_word2m = 0;
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	1309 if (cd->sub_paused_wordram) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	1310 cd->sub_paused_wordram = 0;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	1311 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1312
2129 4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU Michael Pavone <pavone@retrodev.com> parents: 2128 diff changeset	1313 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU Michael Pavone <pavone@retrodev.com> parents: 2128 diff changeset	1314 if (dst == DST_WORD_RAM) {
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU Michael Pavone <pavone@retrodev.com> parents: 2128 diff changeset	1315 lc8951_resume_transfer(&cd->cdc, cd->cdc.cycle);
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU Michael Pavone <pavone@retrodev.com> parents: 2128 diff changeset	1316 }
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU Michael Pavone <pavone@retrodev.com> parents: 2128 diff changeset	1317
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1318 m68k_invalidate_code_range(m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1319 m68k_invalidate_code_range(cd->m68k, 0x080000, 0x0C0000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1320 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1321 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1322 if (changed & MASK_PROG_BANK && can_main_access_prog(cd)) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1323 uint32_t bank = cd->gate_array[GA_MEM_MODE] >> 6 & 0x3;
2055 c4d066d798c4 Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works Michael Pavone <pavone@retrodev.com> parents: 2054 diff changeset	1324 m68k->mem_pointers[cd->memptr_start_index] = cd->prog_ram + bank * 0x10000;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1325 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1326 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1327 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1328 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1329 case GA_HINT_VECTOR:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1330 cd->rom_mut[0x72/2] = value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1331 break;
2135 95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1332 case GA_CDC_HOST_DATA:
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1333 //writes to this register have the same side effects as reads
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1334 main_gate_read16(address, vcontext);
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1335 break;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1336 case GA_COMM_FLAG:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1337 //Main CPU can only write the upper byte;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1338 cd->gate_array[reg] &= 0xFF;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1339 cd->gate_array[reg] \|= value & 0xFF00;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1340 break;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1341 case GA_COMM_CMD0:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1342 case GA_COMM_CMD1:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1343 case GA_COMM_CMD2:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1344 case GA_COMM_CMD3:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1345 case GA_COMM_CMD4:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1346 case GA_COMM_CMD5:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1347 case GA_COMM_CMD6:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1348 case GA_COMM_CMD7:
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1349 //no effects for these other than saving the value
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1350 cd->gate_array[reg] = value;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1351 break;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1352 default:
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1353 printf("Unhandled gate array write %X:%X\n", address, value);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1354 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1355 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1356 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1357
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1358 static void main_gate_write8(uint32_t address, void vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1359 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1360 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1361 genesis_context *gen = m68k->system;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1362 segacd_context *cd = gen->expansion;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1363 uint32_t reg = (address & 0x1FF) >> 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1364 uint16_t value16;
2108 68d61ba1b762 Fix handling of byte writes to gate array regs from main CPU Michael Pavone <pavone@retrodev.com> parents: 2106 diff changeset	1365 switch (reg)
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1366 {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1367 case GA_SUB_CPU_CTRL:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1368 if (address & 1) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1369 value16 = value;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1370 } else {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1371 value16 = value << 8;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1372 if (cd->reset) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1373 value16 \|= BIT_SRES;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1374 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1375 if (cd->busreq) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1376 value16 \|= BIT_SBRQ;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1377 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1378 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1379 break;
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1380 case GA_HINT_VECTOR:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1381 case GA_COMM_FLAG:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1382 //writes to these regs are always treated as word wide
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1383 value16 = value \| (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1384 break;
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1385 default:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1386 if (address & 1) {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1387 value16 = cd->gate_array[reg] & 0xFF00 \| value;
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1388 } else {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1389 value16 = cd->gate_array[reg] & 0xFF \| (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1390 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1391 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1392 return main_gate_write16(address, vcontext, value16);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1393 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1394
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1395 segacd_context alloc_configure_segacd(system_media media, uint32_t opts, uint8_t force_region, rom_info *info)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1396 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1397 static memmap_chunk sub_cpu_map[] = {
2111 4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1398 {0x000000, 0x01FF00, 0xFFFFFF, .flags=MMAP_READ \| MMAP_CODE, .write_16 = prog_ram_wp_write16, .write_8 = prog_ram_wp_write8},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1399 {0x01FF00, 0x080000, 0xFFFFFF, .flags=MMAP_READ \| MMAP_WRITE \| MMAP_CODE},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1400 {0x080000, 0x0C0000, 0x03FFFF, .flags=MMAP_READ \| MMAP_WRITE \| MMAP_CODE \| MMAP_PTR_IDX \| MMAP_FUNC_NULL, .ptr_index = 0,
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1401 .read_16 = word_ram_2M_read16, .write_16 = word_ram_2M_write16, .read_8 = word_ram_2M_read8, .write_8 = word_ram_2M_write8},
2111 4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1402 {0x0C0000, 0x0E0000, 0x01FFFF, .flags=MMAP_READ \| MMAP_WRITE \| MMAP_CODE \| MMAP_PTR_IDX \| MMAP_FUNC_NULL, .ptr_index = 1,
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	1403 .read_16 = word_ram_1M_read16, .write_16 = word_ram_1M_write16, .read_8 = word_ram_1M_read8, .write_8 = word_ram_1M_write8, .shift = 1},
2111 4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1404 {0xFE0000, 0xFF0000, 0x003FFF, .flags=MMAP_READ \| MMAP_WRITE \| MMAP_ONLY_ODD},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1405 {0xFF0000, 0xFF8000, 0x003FFF, .read_16 = pcm_read16, .write_16 = pcm_write16, .read_8 = pcm_read8, .write_8 = pcm_write8},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1406 {0xFF8000, 0xFF8200, 0x0001FF, .read_16 = sub_gate_read16, .write_16 = sub_gate_write16, .read_8 = sub_gate_read8, .write_8 = sub_gate_write8}
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1407 };
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1408
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1409 segacd_context *cd = calloc(sizeof(segacd_context), 1);
2083 372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1410 uint32_t firmware_size;
2123 50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1411 uint8_t region = force_region;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1412 if (!region) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1413 char * def_region = tern_find_path_default(config, "system\0default_region\0", (tern_val){.ptrval = "U"}, TVAL_PTR).ptrval;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1414 if (!info->regions \|\| (info->regions & translate_region_char(toupper(*def_region)))) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1415 region = translate_region_char(toupper(*def_region));
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1416 } else {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1417 region = info->regions;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1418 }
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1419 }
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1420 const char *key;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1421 if (region & REGION_E) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1422 key = "system\0scd_bios_eu\0";
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1423 } else if (region & REGION_J) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1424 key = "system\0scd_bios_jp\0";
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1425 } else {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1426 key = "system\0scd_bios_us\0";
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1427 }
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1428 char *bios_path = tern_find_path_default(config, key, (tern_val){.ptrval = "cdbios.bin"}, TVAL_PTR).ptrval;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1429 cd->rom = (uint16_t *)read_bundled_file(bios_path, &firmware_size);
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1430 if (!cd->rom) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1431 fatal_error("Failed to load Sega CD BIOS from %s\n", bios_path);
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1432 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1433 uint32_t adjusted_size = nearest_pow2(firmware_size);
2083 372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1434 if (adjusted_size != firmware_size) {
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1435 cd->rom = realloc(cd->rom, adjusted_size);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1436 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1437 cd->rom_mut = malloc(adjusted_size);
1503 a763523dadf4 Added code for initializing a combined Genesis + Sega CD system when a Sega CD ISO is loaded Michael Pavone <pavone@retrodev.com> parents: 1502 diff changeset	1438 byteswap_rom(adjusted_size, cd->rom);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1439 memcpy(cd->rom_mut, cd->rom, adjusted_size);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1440 cd->rom_mut[0x72/2] = 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1441
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1442 //memset(info, 0, sizeof(*info));
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1443 //tern_node *db = get_rom_db();
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1444 //*info = configure_rom(db, media->buffer, media->size, media->chain ? media->chain->buffer : NULL, media->chain ? media->chain->size : 0, NULL, 0);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1445
2083 372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1446 cd->prog_ram = calloc(512*1024, 1);
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1447 cd->word_ram = calloc(256*1024, 1);
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1448 cd->pcm_ram = calloc(64*1024, 1);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1449 //TODO: Load state from file
2083 372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1450 cd->bram = calloc(8*1024, 1);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1451
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1452
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1453 sub_cpu_map[0].buffer = sub_cpu_map[1].buffer = cd->prog_ram;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1454 sub_cpu_map[4].buffer = cd->bram;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1455 m68k_options *mopts = malloc(sizeof(m68k_options));
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1456 init_m68k_opts(mopts, sub_cpu_map, sizeof(sub_cpu_map) / sizeof(*sub_cpu_map), 4, sync_components);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1457 cd->m68k = init_68k_context(mopts, NULL);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1458 cd->m68k->system = cd;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1459 cd->int2_cycle = CYCLE_NEVER;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1460 cd->busreq = 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1461 cd->busack = 1;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1462 cd->need_reset = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1463 cd->reset = 1; //active low, so reset is not active on start
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1464 cd->memptr_start_index = 0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1465 cd->gate_array[1] = 1;
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	1466 cd->gate_array[GA_CDD_CTRL] = BIT_MUTE; //Data/mute flag is set on start
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	1467 cd->main_has_word2m = 1;
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1468 lc8951_init(&cd->cdc, handle_cdc_byte, cd);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1469 if (media->chain && media->type != MEDIA_CDROM) {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1470 media = media->chain;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1471 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1472 cdd_mcu_init(&cd->cdd, media);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1473 cd_graphics_init(cd);
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	1474 cdd_fader_init(&cd->fader);
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	1475 rf5c164_init(&cd->pcm, SCD_MCLKS, 4);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1476 return cd;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1477 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1478
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1479 memmap_chunk segacd_main_cpu_map(segacd_context cd, uint8_t cart_boot, uint32_t *num_chunks)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1480 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1481 static memmap_chunk main_cpu_map[] = {
2111 4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1482 {0x000000, 0x020000, 0x01FFFF, .flags=MMAP_READ},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1483 {0x020000, 0x040000, 0x01FFFF, .flags=MMAP_READ\|MMAP_WRITE\|MMAP_PTR_IDX\|MMAP_FUNC_NULL\|MMAP_CODE, .ptr_index = 0,
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1484 .read_16 = unmapped_prog_read16, .write_16 = unmapped_prog_write16, .read_8 = unmapped_prog_read8, .write_8 = unmapped_prog_write8},
2111 4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1485 {0x040000, 0x060000, 0x01FFFF, .flags=MMAP_READ}, //first ROM alias
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1486 //TODO: additional ROM/prog RAM aliases
2111 4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1487 {0x200000, 0x220000, 0x01FFFF, .flags=MMAP_READ\|MMAP_WRITE\|MMAP_PTR_IDX\|MMAP_FUNC_NULL\|MMAP_CODE, .ptr_index = 1,
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1488 .read_16 = unmapped_word_read16, .write_16 = unmapped_word_write16, .read_8 = unmapped_word_read8, .write_8 = unmapped_word_write8},
2111 4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1489 {0x220000, 0x240000, 0x01FFFF, .flags=MMAP_READ\|MMAP_WRITE\|MMAP_PTR_IDX\|MMAP_FUNC_NULL\|MMAP_CODE, .ptr_index = 2,
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1490 .read_16 = cell_image_read16, .write_16 = cell_image_write16, .read_8 = cell_image_read8, .write_8 = cell_image_write8},
2111 4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1491 {0xA12000, 0xA13000, 0xFFFFFF, .read_16 = main_gate_read16, .write_16 = main_gate_write16, .read_8 = main_gate_read8, .write_8 = main_gate_write8}
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1492 };
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1493 for (int i = 0; i < sizeof(main_cpu_map) / sizeof(*main_cpu_map); i++)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1494 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1495 if (main_cpu_map[i].start < 0x800000) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1496 if (cart_boot) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1497 main_cpu_map[i].start \|= 0x400000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1498 main_cpu_map[i].end \|= 0x400000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1499 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1500 main_cpu_map[i].start &= 0x3FFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1501 main_cpu_map[i].end &= 0x3FFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1502 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1503 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1504 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1505 //TODO: support BRAM cart
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1506 main_cpu_map[0].buffer = cd->rom_mut;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1507 main_cpu_map[2].buffer = cd->rom;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1508 main_cpu_map[1].buffer = cd->prog_ram;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1509 main_cpu_map[3].buffer = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1510 main_cpu_map[4].buffer = cd->word_ram + 0x10000;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1511 num_chunks = sizeof(main_cpu_map) / sizeof(main_cpu_map);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1512 return main_cpu_map;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1513 }

Mercurial > repos > blastem

annotate segacd.c @ 2148:2da377ea932f