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annotate segacd.c @ 2332:7518db62d232

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Add a couple of SG-1000 games with on-cart RAM to ROM DB
author Michael Pavone <pavone@retrodev.com>
date Wed, 23 Aug 2023 23:36:35 -0700
parents 06d5e9b08bdb
children c05b7c5e6f11
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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parents: 1467
diff changeset
1 #include <stdlib.h>
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2 #include <string.h>
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3 #include <ctype.h>
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8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
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4 #include "cd_graphics.h"
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2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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5 #include "genesis.h"
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6 #include "util.h"
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7 #include "debug.h"
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8 #include "gdb_remote.h"
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50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
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9 #include "blastem.h"
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9ead0fe69d9b Implement savestate support for Sega CD
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10 #include "cdimage.h"
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2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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11
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12 #define SCD_MCLKS 50000000
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13 #define SCD_PERIPH_RESET_CLKS (SCD_MCLKS / 10)
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14 #define TIMER_TICK_CLKS 1536
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15
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16 enum {
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17 GA_SUB_CPU_CTRL,
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18 GA_MEM_MODE,
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19 GA_CDC_CTRL,
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20 GA_CDC_REG_DATA,
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21 GA_CDC_HOST_DATA,
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22 GA_CDC_DMA_ADDR,
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23 GA_STOP_WATCH,
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24 GA_COMM_FLAG,
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25 GA_COMM_CMD0,
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26 GA_COMM_CMD1,
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27 GA_COMM_CMD2,
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28 GA_COMM_CMD3,
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29 GA_COMM_CMD4,
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30 GA_COMM_CMD5,
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31 GA_COMM_CMD6,
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32 GA_COMM_CMD7,
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33 GA_COMM_STATUS0,
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34 GA_COMM_STATUS1,
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35 GA_COMM_STATUS2,
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36 GA_COMM_STATUS3,
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37 GA_COMM_STATUS4,
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38 GA_COMM_STATUS5,
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39 GA_COMM_STATUS6,
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40 GA_COMM_STATUS7,
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41 GA_TIMER,
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42 GA_INT_MASK,
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43 GA_CDD_FADER,
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44 GA_CDD_CTRL,
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45 GA_CDD_STATUS0,
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46 GA_CDD_STATUS1,
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47 GA_CDD_STATUS2,
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48 GA_CDD_STATUS3,
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49 GA_CDD_STATUS4,
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50 GA_CDD_CMD0,
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51 GA_CDD_CMD1,
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52 GA_CDD_CMD2,
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53 GA_CDD_CMD3,
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54 GA_CDD_CMD4,
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55 GA_FONT_COLOR,
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56 GA_FONT_BITS,
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57 GA_FONT_DATA0,
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58 GA_FONT_DATA1,
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59 GA_FONT_DATA2,
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60 GA_FONT_DATA3,
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61 GA_SUBCODE_START = 0x80,
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62 GA_SUBCODE_MIRROR = 0xC0,
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63
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64 GA_HINT_VECTOR = GA_CDC_REG_DATA
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65 };
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66 //GA_SUB_CPU_CTRL
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67 #define BIT_IEN2 0x8000
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68 #define BIT_IFL2 0x0100
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69 #define BIT_LEDG 0x0200
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70 #define BIT_LEDR 0x0100
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71 #define BIT_SBRQ 0x0002
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72 #define BIT_SRES 0x0001
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73 #define BIT_PRES 0x0001
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74 //GA_MEM_MODE
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75 #define MASK_PROG_BANK 0x00C0
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76 #define BIT_OVERWRITE 0x0010
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77 #define BIT_UNDERWRITE 0x0008
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78 #define MASK_PRIORITY (BIT_OVERWRITE|BIT_UNDERWRITE)
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79 #define BIT_MEM_MODE 0x0004
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80 #define BIT_DMNA 0x0002
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81 #define BIT_RET 0x0001
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82
2065
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83 //GA_CDC_CTRL
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84 #define BIT_EDT 0x8000
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85 #define BIT_DSR 0x4000
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86
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87 //GA_CDD_CTRL
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88 #define BIT_MUTE 0x0100
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89
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90 enum {
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91 DST_MAIN_CPU = 2,
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92 DST_SUB_CPU,
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93 DST_PCM_RAM,
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94 DST_PROG_RAM,
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95 DST_WORD_RAM = 7
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96 };
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97
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98 //GA_INT_MASK
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99 #define BIT_MASK_IEN1 0x0002
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100 #define BIT_MASK_IEN2 0x0004
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101 #define BIT_MASK_IEN3 0x0008
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102 #define BIT_MASK_IEN4 0x0010
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103 #define BIT_MASK_IEN5 0x0020
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104 #define BIT_MASK_IEN6 0x0040
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105
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106 //GA_CDD_CTRL
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107 #define BIT_HOCK 0x0004
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108
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109 static void *prog_ram_wp_write16(uint32_t address, void *vcontext, uint16_t value)
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110 {
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111 m68k_context *m68k = vcontext;
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112 segacd_context *cd = m68k->system;
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113 //if (!(cd->gate_array[GA_MEM_MODE] & (1 << ((address >> 9) + 8)))) {
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114 if (address >= ((cd->gate_array[GA_MEM_MODE] & 0xFF00) << 1)) {
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115 cd->prog_ram[address >> 1] = value;
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116 m68k_invalidate_code_range(m68k, address, address + 2);
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117 }
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118 return vcontext;
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119 }
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120
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121 static void *prog_ram_wp_write8(uint32_t address, void *vcontext, uint8_t value)
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122 {
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123 m68k_context *m68k = vcontext;
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124 segacd_context *cd = m68k->system;
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125 if (address >= ((cd->gate_array[GA_MEM_MODE] & 0xFF00) << 1)) {
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126 ((uint8_t *)cd->prog_ram)[address ^ 1] = value;
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127 m68k_invalidate_code_range(m68k, address, address + 1);
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128 }
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129 return vcontext;
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130 }
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131
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132 static uint16_t word_ram_2M_read16(uint32_t address, void *vcontext)
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133 {
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134 m68k_context *m68k = vcontext;
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135 uint16_t* bank = m68k->mem_pointers[1];
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136 if (!bank) {
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137 return 0xFFFF;
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138 }
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139 uint16_t raw = bank[address >> 1 & ~1];
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140 if (address & 2) {
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141 return (raw & 0xF) | (raw << 4 & 0xF00);
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142 } else {
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143 return (raw >> 4 & 0xF00) | (raw >> 8 & 0xF);
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144 }
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145 }
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146
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147 static uint8_t word_ram_2M_read8(uint32_t address, void *vcontext)
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148 {
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149 uint16_t word = word_ram_2M_read16(address, vcontext);
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150 if (address & 1) {
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151 return word;
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152 }
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153 return word >> 8;
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154 }
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155
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156 static void *word_ram_2M_write8(uint32_t address, void *vcontext, uint8_t value)
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157 {
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158 m68k_context *m68k = vcontext;
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159 segacd_context *cd = m68k->system;
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160 if (!(cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE)) {
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161 //TODO: Confirm this first write goes through (seemed like it in initial testing)
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162 if (address & 1) {
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163 address >>= 1;
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164 cd->word_ram[address] &= 0xFF00;
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165 cd->word_ram[address] |= value;
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166 } else {
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167 address >>= 1;
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168 cd->word_ram[address] &= 0x00FF;
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169 cd->word_ram[address] |= value << 8;
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170 }
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171 m68k_invalidate_code_range(cd->genesis->m68k, cd->base + 0x200000 + (address & ~1), cd->base + 0x200000 + (address & ~1) + 1);
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172 cd->sub_paused_wordram = 1;
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173 m68k->sync_cycle = m68k->target_cycle = m68k->current_cycle;
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174 m68k->should_return = 1;
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175 } else {
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176 value &= 0xF;
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177 uint16_t priority = cd->gate_array[GA_MEM_MODE] & MASK_PRIORITY;
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178
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179 if (priority == BIT_OVERWRITE && !value) {
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180 return vcontext;
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181 }
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182 if (priority == BIT_UNDERWRITE) {
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183 if (!value) {
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184 return vcontext;
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185 }
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186 uint8_t old = word_ram_2M_read8(address, vcontext);
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187 if (old) {
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188 return vcontext;
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189 }
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190 }
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191 uint16_t* bank = m68k->mem_pointers[1];
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192 if (!bank) {
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193 return vcontext;
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194 }
2134
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195 uint16_t raw = bank[address >> 1 & ~1];
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196 uint16_t shift = ((address & 3) * 4);
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197 raw &= ~(0xF000 >> shift);
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198 raw |= value << (12 - shift);
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199 bank[address >> 1 & ~1] = raw;
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200 }
1502
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201 return vcontext;
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202 }
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diff changeset
203
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diff changeset
204
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diff changeset
205 static void *word_ram_2M_write16(uint32_t address, void *vcontext, uint16_t value)
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diff changeset
206 {
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diff changeset
207 word_ram_2M_write8(address, vcontext, value >> 8);
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208 return word_ram_2M_write8(address + 1, vcontext, value);
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diff changeset
209 }
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diff changeset
210
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diff changeset
211 static uint16_t word_ram_1M_read16(uint32_t address, void *vcontext)
1502
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diff changeset
212 {
2138
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diff changeset
213 //TODO: check behavior for these on hardware
2054
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214 return 0;
1502
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215 }
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diff changeset
216
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217 static uint8_t word_ram_1M_read8(uint32_t address, void *vcontext)
1502
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diff changeset
218 {
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diff changeset
219 return 0;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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diff changeset
220 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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diff changeset
221
2054
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diff changeset
222 static void *word_ram_1M_write16(uint32_t address, void *vcontext, uint16_t value)
1502
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diff changeset
223 {
2054
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diff changeset
224 return vcontext;
1502
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diff changeset
225 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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diff changeset
226
2054
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diff changeset
227 static void *word_ram_1M_write8(uint32_t address, void *vcontext, uint8_t value)
1502
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diff changeset
228 {
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diff changeset
229 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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diff changeset
230 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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diff changeset
231
2054
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diff changeset
232
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diff changeset
233 static uint16_t unmapped_prog_read16(uint32_t address, void *vcontext)
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diff changeset
234 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff changeset
235 return 0xFFFF;
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diff changeset
236 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff changeset
237
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff changeset
238 static uint8_t unmapped_prog_read8(uint32_t address, void *vcontext)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff changeset
239 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff changeset
240 return 0xFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff changeset
241 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff changeset
242
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
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diff changeset
243 static void *unmapped_prog_write16(uint32_t address, void *vcontext, uint16_t value)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff changeset
244 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff changeset
245 return vcontext;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
246 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
247
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
248 static void *unmapped_prog_write8(uint32_t address, void *vcontext, uint8_t value)
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
249 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
250 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
251 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
252
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
253 static uint16_t unmapped_word_read16(uint32_t address, void *vcontext)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
254 {
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
255 m68k_context *m68k = vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
256 genesis_context *gen = m68k->system;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
257 segacd_context *cd = gen->expansion;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
258 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
259 return cd->word_ram[address + cd->bank_toggle];
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
260 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
261 return 0xFFFF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
262 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
263 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
264
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
265 static uint8_t unmapped_word_read8(uint32_t address, void *vcontext)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
266 {
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
267 m68k_context *m68k = vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
268 genesis_context *gen = m68k->system;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
269 segacd_context *cd = gen->expansion;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
270 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
271 if (address & 1) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
272 return cd->word_ram[(address & ~1) + cd->bank_toggle];
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
273 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
274 return cd->word_ram[address + cd->bank_toggle] >> 8;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
275 }
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
276 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
277 return 0xFF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
278 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
279 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
280
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
281 static void *unmapped_word_write16(uint32_t address, void *vcontext, uint16_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
282 {
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents: 2131
diff changeset
283 m68k_context *m68k = vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
284 genesis_context *gen = m68k->system;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
285 segacd_context *cd = gen->expansion;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
286 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
287 cd->word_ram[address + cd->bank_toggle] = value;
2137
3ef9456b76cf Fix a crash regression from word RAM interleave changes
Michael Pavone <pavone@retrodev.com>
parents: 2136
diff changeset
288 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + address, cd->base + 0x200000 + address + 1);
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
289 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
290 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
291 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
292
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
293 static void *unmapped_word_write8(uint32_t address, void *vcontext, uint8_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
294 {
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents: 2131
diff changeset
295 m68k_context *m68k = vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
296 genesis_context *gen = m68k->system;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
297 segacd_context *cd = gen->expansion;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
298 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
299 if (address & 1) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
300 uint32_t offset = (address & ~1) + cd->bank_toggle;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
301 cd->word_ram[offset] &= 0xFF00;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
302 cd->word_ram[offset] |= value;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
303 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
304 cd->word_ram[address + cd->bank_toggle] &= 0xFF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
305 cd->word_ram[address + cd->bank_toggle] |= value << 8;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
306 }
2138
b6338e18787e Fix some dynarec code invalidation issues
Michael Pavone <pavone@retrodev.com>
parents: 2137
diff changeset
307 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + (address & ~1), cd->base + 0x200000 + (address & ~1) + 1);
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
308 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
309 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
310 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
311
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
312 static uint32_t cell_image_translate_address(uint32_t address)
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
313 {
2087
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
314 uint32_t word_of_cell = address & 2;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
315 if (address < 0x10000) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
316 //64x32 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
317 uint32_t line_of_column = address & 0x3FC;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
318 uint32_t column = address & 0xFC00;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
319 address = (line_of_column << 6) | (column >> 8) | word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
320 } else if (address < 0x18000) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
321 //64x16 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
322 uint32_t line_of_column = address & 0x1FC;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
323 uint32_t column = address & 0x7E00;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
324 address = 0x10000 | (line_of_column << 6) | (column >> 7) | word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
325 } else if (address < 0x1C000) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
326 //64x8 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
327 uint32_t line_of_column = address & 0x00FC;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
328 uint32_t column = address & 0x3F00;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
329 address = 0x18000 | (line_of_column << 6) | (column >> 6) | word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
330 } else {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
331 //64x4 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
332 uint32_t line_of_column = address & 0x007C;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
333 uint32_t column = address & 0x1F80;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
334 address &= 0x1E000;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
335 address |= (line_of_column << 6) | (column >> 5) | word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
336 }
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
337 return address;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
338 }
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
339
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
340 static uint16_t cell_image_read16(uint32_t address, void *vcontext)
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
341 {
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
342 address = cell_image_translate_address(address);
2087
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
343 m68k_context *m68k = vcontext;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
344 genesis_context *gen = m68k->system;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
345 segacd_context *cd = gen->expansion;
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
346 if (!(cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE)) {
2099
b92c998c6742 Add some missing null checks in the Sega CD code dealing with word RAM switching
Michael Pavone <pavone@retrodev.com>
parents: 2094
diff changeset
347 return 0xFFFF;
b92c998c6742 Add some missing null checks in the Sega CD code dealing with word RAM switching
Michael Pavone <pavone@retrodev.com>
parents: 2094
diff changeset
348 }
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
349 return cd->word_ram[address + cd->bank_toggle];
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
350 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
351
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
352 static uint8_t cell_image_read8(uint32_t address, void *vcontext)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
353 {
2087
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
354 uint16_t word = cell_image_read16(address & 0xFFFFFE, vcontext);
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
355 if (address & 1) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
356 return word;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
357 }
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
358 return word >> 8;
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
359 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
360
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
361 static void *cell_image_write16(uint32_t address, void *vcontext, uint16_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
362 {
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
363 m68k_context *m68k = vcontext;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
364 genesis_context *gen = m68k->system;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
365 segacd_context *cd = gen->expansion;
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
366 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
367 address = cell_image_translate_address(address);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
368 cd->word_ram[address + cd->bank_toggle] = value;
2138
b6338e18787e Fix some dynarec code invalidation issues
Michael Pavone <pavone@retrodev.com>
parents: 2137
diff changeset
369 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + address, cd->base + 0x200000 + address + 1);
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
370 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
371 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
372 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
373
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
374 static void *cell_image_write8(uint32_t address, void *vcontext, uint8_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
375 {
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
376 uint32_t byte = address & 1;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
377 address = cell_image_translate_address(address);
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
378 m68k_context *m68k = vcontext;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
379 genesis_context *gen = m68k->system;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
380 segacd_context *cd = gen->expansion;
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
381 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
382 if (byte) {
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
383 cd->word_ram[address + cd->bank_toggle] &= 0xFF00;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
384 cd->word_ram[address + cd->bank_toggle] |= value;
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
385 } else {
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
386 cd->word_ram[address + cd->bank_toggle] &= 0x00FF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
387 cd->word_ram[address + cd->bank_toggle] |= value << 8;
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
388 }
2138
b6338e18787e Fix some dynarec code invalidation issues
Michael Pavone <pavone@retrodev.com>
parents: 2137
diff changeset
389 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + address, cd->base + 0x200000 + address + 1);
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
390 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
391 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
392 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
393
2127
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
394 static void cdd_run(segacd_context *cd, uint32_t cycle)
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
395 {
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
396 cdd_mcu_run(&cd->cdd, cycle, cd->gate_array + GA_CDD_CTRL, &cd->cdc, &cd->fader);
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
397 lc8951_run(&cd->cdc, cycle);
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
398 }
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
399
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
400 static uint8_t pcm_read8(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
401 {
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
402 m68k_context *m68k = vcontext;
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
403 segacd_context *cd = m68k->system;
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
404 if (address & 1) {
2127
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
405 //need to run CD drive because there may be a PCM DMA underway
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
406 cdd_run(cd, m68k->current_cycle);
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
407 rf5c164_run(&cd->pcm, m68k->current_cycle);
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
408 return rf5c164_read(&cd->pcm, address >> 1);
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
409 } else {
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
410 return 0xFF;
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
411 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
412 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
413
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
414 static uint16_t pcm_read16(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
415 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
416 return 0xFF00 | pcm_read8(address+1, vcontext);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
417 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
418
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
419 static void *pcm_write8(uint32_t address, void *vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
420 {
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
421 m68k_context *m68k = vcontext;
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
422 segacd_context *cd = m68k->system;
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
423 if (address & 1) {
2127
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
424 //need to run CD drive because there may be a PCM DMA underway
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
425 cdd_run(cd, m68k->current_cycle);
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
426 rf5c164_run(&cd->pcm, m68k->current_cycle);
2128
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
427 while ((cd->pcm.flags & 0x81) == 1) {
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
428 //not sounding, but pending write
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
429 //DMA write conflict presumably adds wait states
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
430 m68k->current_cycle += 4;
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
431 rf5c164_run(&cd->pcm, m68k->current_cycle);
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
432 }
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
433 rf5c164_write(&cd->pcm, address >> 1, value);
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
434 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
435 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
436 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
437
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
438 static void *pcm_write16(uint32_t address, void *vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
439 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
440 return pcm_write8(address+1, vcontext, value);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
441 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
442
2281
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
443 static uint16_t cart_area_read16(uint32_t address, void *vcontext)
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
444 {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
445 m68k_context *m68k = vcontext;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
446 genesis_context *gen = m68k->system;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
447 segacd_context *cd = gen->expansion;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
448 uint16_t open_bus = read_word(m68k->last_prefetch_address, (void **)m68k->mem_pointers, &m68k->options->gen, m68k);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
449 if (cd->bram_cart_id > 7) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
450 // No cart, just return open bus
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
451 return open_bus;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
452 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
453 address &= 0x3FFFFF;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
454 if (address < 0x200000) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
455 if (address < 0x100000) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
456 return (open_bus & 0xFF00) | cd->bram_cart_id;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
457 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
458 return open_bus;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
459 } else {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
460 address &= 0x1FFFFF;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
461 uint32_t end = 0x2000 << (1 + cd->bram_cart_id);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
462 if (address >= end) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
463 return open_bus;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
464 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
465 return (open_bus & 0xFF00) | cd->bram_cart[address >> 1];
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
466 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
467 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
468
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
469 static uint8_t cart_area_read8(uint32_t address, void *vcontext)
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
470 {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
471 m68k_context *m68k = vcontext;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
472 genesis_context *gen = m68k->system;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
473 segacd_context *cd = gen->expansion;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
474 if (!(address & 1) || cd->bram_cart_id > 7) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
475 //open bus
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
476 return read_byte(m68k->last_prefetch_address | (address & 1), (void **)m68k->mem_pointers, &m68k->options->gen, m68k);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
477 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
478 address &= 0x3FFFFF;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
479 if (address < 0x200000) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
480 if (address < 0x100000) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
481 return cd->bram_cart_id;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
482 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
483 return read_byte(m68k->last_prefetch_address | 1, (void **)m68k->mem_pointers, &m68k->options->gen, m68k);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
484 } else {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
485 address &= 0x1FFFFF;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
486 uint32_t end = 0x2000 << (1 + cd->bram_cart_id);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
487 if (address >= end) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
488 return read_byte(m68k->last_prefetch_address | 1, (void **)m68k->mem_pointers, &m68k->options->gen, m68k);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
489 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
490 return cd->bram_cart[address >> 1];
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
491 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
492 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
493
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
494 static void *cart_area_write8(uint32_t address, void *vcontext, uint8_t value)
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
495 {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
496 m68k_context *m68k = vcontext;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
497 genesis_context *gen = m68k->system;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
498 segacd_context *cd = gen->expansion;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
499 if (!(address & 1) || cd->bram_cart_id > 7 || address < 0x600000) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
500 return vcontext;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
501 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
502 address &= 0x1FFFFF;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
503 uint32_t end = 0x2000 << (1 + cd->bram_cart_id);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
504 if (address < end && cd->bram_cart_write_enabled) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
505 cd->bram_cart[address >> 1] = value;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
506 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
507 if (address == 0x1FFFFF || (cd->bram_cart_id < 7 && address > 0x100000)) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
508 cd->bram_cart_write_enabled = value & 1;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
509 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
510 return vcontext;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
511 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
512
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
513 static void *cart_area_write16(uint32_t address, void *vcontext, uint16_t value)
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
514 {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
515 return cart_area_write8(address | 1, vcontext, value);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
516 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
517
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
518 static void timers_run(segacd_context *cd, uint32_t cycle)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
519 {
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
520 if (cycle <= cd->stopwatch_cycle) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
521 return;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
522 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
523 uint32_t ticks = (cycle - cd->stopwatch_cycle) / TIMER_TICK_CLKS;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
524 cd->stopwatch_cycle += ticks * TIMER_TICK_CLKS;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
525 cd->gate_array[GA_STOP_WATCH] += ticks;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
526 cd->gate_array[GA_STOP_WATCH] &= 0xFFF;
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
527 if (ticks && !cd->timer_value) {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
528 --ticks;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
529 cd->timer_value = cd->gate_array[GA_TIMER];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
530 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
531 if (ticks && cd->timer_value) {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
532 while (ticks >= (cd->timer_value + 1)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
533 ticks -= cd->timer_value + 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
534 cd->timer_value = cd->gate_array[GA_TIMER];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
535 cd->timer_pending = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
536 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
537 cd->timer_value -= ticks;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
538 if (!cd->timer_value) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
539 cd->timer_pending = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
540 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
541 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
542 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
543
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
544 static uint32_t next_timer_int(segacd_context *cd)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
545 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
546 if (cd->timer_pending) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
547 return cd->stopwatch_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
548 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
549 if (cd->timer_value) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
550 return cd->stopwatch_cycle + TIMER_TICK_CLKS * cd->timer_value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
551 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
552 if (cd->gate_array[GA_TIMER]) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
553 return cd->stopwatch_cycle + TIMER_TICK_CLKS * (cd->gate_array[GA_TIMER] + 1);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
554 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
555 return CYCLE_NEVER;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
556 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
557
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
558 static void calculate_target_cycle(m68k_context * context)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
559 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
560 segacd_context *cd = context->system;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
561 context->int_cycle = CYCLE_NEVER;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
562 uint8_t mask = context->status & 0x7;
2094
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
563 uint32_t cdc_cycle = CYCLE_NEVER;
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
564 if (mask < 6) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
565 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN6) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
566 uint32_t subcode_cycle = cd->cdd.subcode_int_pending ? context->current_cycle : cd->cdd.next_subcode_int_cycle;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
567 if (subcode_cycle != CYCLE_NEVER) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
568 context->int_cycle = subcode_cycle;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
569 context->int_num = 6;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
570 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
571 }
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
572 if (mask < 5) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
573 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN5) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
574 cdc_cycle = lc8951_next_interrupt(&cd->cdc);
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
575 //CDC interrupts only generated on falling edge of !INT signal
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
576 if (cd->cdc_int_ack) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
577 if (cdc_cycle > cd->cdc.cycle) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
578 cd->cdc_int_ack = 0;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
579 } else {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
580 cdc_cycle = CYCLE_NEVER;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
581 }
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
582 }
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
583 if (cdc_cycle < context->int_cycle) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
584 context->int_cycle = cdc_cycle;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
585 context->int_num = 5;
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
586 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
587 }
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
588 if (mask < 4) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
589 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN4) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
590 uint32_t cdd_cycle = cd->cdd.int_pending ? context->current_cycle : cd->cdd.next_int_cycle;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
591 if (cdd_cycle < context->int_cycle) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
592 context->int_cycle = cdd_cycle;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
593 context->int_num = 4;
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
594 }
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
595 }
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
596 if (mask < 3) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
597 uint32_t next_timer;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
598 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN3) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
599 uint32_t next_timer_cycle = next_timer_int(cd);
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
600 if (next_timer_cycle < context->int_cycle) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
601 context->int_cycle = next_timer_cycle;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
602 context->int_num = 3;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
603 }
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
604 }
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
605 if (mask < 2) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
606 if (cd->int2_cycle < context->int_cycle && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2)) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
607 context->int_cycle = cd->int2_cycle;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
608 context->int_num = 2;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
609 }
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
610 if (mask < 1) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
611 if (cd->graphics_int_cycle < context->int_cycle && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN1)) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
612 context->int_cycle = cd->graphics_int_cycle;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
613 context->int_num = 1;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
614 }
2069
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
615 }
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
616 }
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
617 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
618 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
619 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
620 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
621 if (context->int_cycle > context->current_cycle && context->int_pending == INT_PENDING_SR_CHANGE) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
622 context->int_pending = INT_PENDING_NONE;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
623 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
624 if (context->current_cycle >= context->sync_cycle) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
625 context->should_return = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
626 context->target_cycle = context->current_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
627 return;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
628 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
629 if (context->status & M68K_STATUS_TRACE || context->trace_pending) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
630 context->target_cycle = context->current_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
631 return;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
632 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
633 context->target_cycle = context->sync_cycle < context->int_cycle ? context->sync_cycle : context->int_cycle;
2136
01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test
Michael Pavone <pavone@retrodev.com>
parents: 2135
diff changeset
634 if (context->int_cycle == cdc_cycle && context->int_num == 5) {
2094
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
635 uint32_t before = context->target_cycle - 2 * cd->cdc.clock_step;
2136
01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test
Michael Pavone <pavone@retrodev.com>
parents: 2135
diff changeset
636 if (before < context->target_cycle) {
2131
d90d92ce5cab Improve CDC decode timing accuracy
Michael Pavone <pavone@retrodev.com>
parents: 2129
diff changeset
637 if (before > context->current_cycle) {
d90d92ce5cab Improve CDC decode timing accuracy
Michael Pavone <pavone@retrodev.com>
parents: 2129
diff changeset
638 context->target_cycle = context->sync_cycle = before;
2136
01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test
Michael Pavone <pavone@retrodev.com>
parents: 2135
diff changeset
639 } else {
01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test
Michael Pavone <pavone@retrodev.com>
parents: 2135
diff changeset
640 before = context->target_cycle - cd->cdc.clock_step;
01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test
Michael Pavone <pavone@retrodev.com>
parents: 2135
diff changeset
641 if (before > context->current_cycle) {
01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test
Michael Pavone <pavone@retrodev.com>
parents: 2135
diff changeset
642 context->target_cycle = context->sync_cycle = before;
01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test
Michael Pavone <pavone@retrodev.com>
parents: 2135
diff changeset
643 }
2131
d90d92ce5cab Improve CDC decode timing accuracy
Michael Pavone <pavone@retrodev.com>
parents: 2129
diff changeset
644 }
2094
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
645 }
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
646 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
647 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
648
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
649 static uint16_t sub_gate_read16(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
650 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
651 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
652 segacd_context *cd = m68k->system;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
653 uint32_t reg = address >> 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
654 switch (reg)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
655 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
656 case GA_SUB_CPU_CTRL: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
657 uint16_t value = cd->gate_array[reg] & 0xFFFE;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
658 if (cd->periph_reset_cycle == CYCLE_NEVER || (m68k->current_cycle - cd->periph_reset_cycle) > SCD_PERIPH_RESET_CLKS) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
659 value |= BIT_PRES;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
660 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
661 return value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
662 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
663 case GA_MEM_MODE:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
664 return cd->gate_array[reg] & 0xFF1F;
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
665 case GA_CDC_CTRL:
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
666 cdd_run(cd, m68k->current_cycle);
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
667 return cd->gate_array[reg] | cd->cdc.ar;
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
668 case GA_CDC_REG_DATA:
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
669 cdd_run(cd, m68k->current_cycle);
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
670 return lc8951_reg_read(&cd->cdc);
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
671 case GA_CDC_HOST_DATA: {
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
672 cdd_run(cd, m68k->current_cycle);
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
673 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
674 if (dst == DST_SUB_CPU) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
675 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
676 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
677 lc8951_resume_transfer(&cd->cdc, cd->cdc.cycle);
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
678 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
679 calculate_target_cycle(cd->m68k);
2068
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
680
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
681 }
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
682 return cd->gate_array[reg];
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
683 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
684 case GA_STOP_WATCH:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
685 case GA_TIMER:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
686 timers_run(cd, m68k->current_cycle);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
687 return cd->gate_array[reg];
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
688 case GA_CDD_STATUS0:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
689 case GA_CDD_STATUS1:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
690 case GA_CDD_STATUS2:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
691 case GA_CDD_STATUS3:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
692 case GA_CDD_STATUS4:
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
693 cdd_run(cd, m68k->current_cycle);
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
694 return cd->gate_array[reg];
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
695 break;
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
696 case GA_FONT_DATA0:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
697 case GA_FONT_DATA1:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
698 case GA_FONT_DATA2:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
699 case GA_FONT_DATA3: {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
700 uint16_t shift = 4 * (3 - (reg - GA_FONT_DATA0));
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
701 uint16_t value = 0;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
702 uint16_t fg = cd->gate_array[GA_FONT_COLOR] >> 4;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
703 uint16_t bg = cd->gate_array[GA_FONT_COLOR] & 0xF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
704 for (int i = 0; i < 4; i++) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
705 uint16_t pixel = 0;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
706 if (cd->gate_array[GA_FONT_BITS] & 1 << (shift + i)) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
707 pixel = fg;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
708 } else {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
709 pixel = bg;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
710 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
711 value |= pixel << (i * 4);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
712 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
713 return value;
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
714 }
2069
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
715 case GA_STAMP_SIZE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
716 case GA_IMAGE_BUFFER_LINES:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
717 //these two have bits that change based on graphics operations
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
718 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
719 return cd->gate_array[reg];
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
720 case GA_TRACE_VECTOR_BASE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
721 //write only
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
722 return 0xFFFF;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
723 default:
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
724 if (reg >= GA_SUBCODE_MIRROR) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
725 return cd->gate_array[GA_SUBCODE_START + (reg & 0x3F)];
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
726 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
727 return cd->gate_array[reg];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
728 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
729 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
730
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
731 static uint8_t sub_gate_read8(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
732 {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
733 uint16_t val = sub_gate_read16(address, vcontext);
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
734 return address & 1 ? val : val >> 8;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
735 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
736
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
737 static void *sub_gate_write16(uint32_t address, void *vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
738 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
739 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
740 segacd_context *cd = m68k->system;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
741 uint32_t reg = address >> 1;
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
742 switch (reg)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
743 {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
744 case GA_SUB_CPU_CTRL:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
745 cd->gate_array[reg] &= 0xF0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
746 cd->gate_array[reg] |= value & (BIT_LEDG|BIT_LEDR);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
747 if (value & BIT_PRES) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
748 cd->periph_reset_cycle = m68k->current_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
749 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
750 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
751 case GA_MEM_MODE: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
752 uint16_t changed = value ^ cd->gate_array[reg];
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
753 uint8_t old_main_has_word2m = cd->main_has_word2m;
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
754 if (value & BIT_RET) {
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
755 cd->main_has_word2m = 1;
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
756 }
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
757 uint8_t old_bank_toggle = cd->bank_toggle;
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
758 cd->bank_toggle = value & BIT_RET;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
759 genesis_context *gen = cd->genesis;
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
760 cd->gate_array[reg] &= 0xFFC0;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
761 if (changed & BIT_MEM_MODE) {
2120
91ed3c4cdfd9 Fix the regression in Stellar Fire while still passing RET/DMNA tests
Michael Pavone <pavone@retrodev.com>
parents: 2119
diff changeset
762 cd->main_swap_request = cd->bank_toggle && !old_bank_toggle;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
763 if (value & BIT_MEM_MODE) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
764 //switch to 1M mode
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
765 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL; //(value & BIT_RET) ? cd->word_ram + 0x10000 : cd->word_ram;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
766 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
767 m68k->mem_pointers[0] = NULL;
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
768 m68k->mem_pointers[1] = cd->bank_toggle ? cd->word_ram : cd->word_ram + 1;
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
769 cd->gate_array[reg] |= value & (MASK_PRIORITY|BIT_RET|BIT_MEM_MODE);
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
770 if (cd->main_swap_request) {
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
771 cd->gate_array[reg] |= BIT_DMNA;
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
772 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
773 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
774 //switch to 2M mode
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
775 if (cd->main_has_word2m) {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
776 //Main CPU will have word ram
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
777 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
778 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
779 m68k->mem_pointers[0] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
780 m68k->mem_pointers[1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
781 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
782 //sub cpu will have word ram
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
783 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
784 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
785 m68k->mem_pointers[0] = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
786 m68k->mem_pointers[1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
787 }
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
788 cd->gate_array[reg] |= value & (MASK_PRIORITY|BIT_MEM_MODE);
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
789 cd->gate_array[reg] |= cd->main_has_word2m ? BIT_RET : BIT_DMNA;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
790 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
791 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
792 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000);
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
793 } else if (value & BIT_MEM_MODE) {
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
794 //1M mode
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
795 if (old_bank_toggle != cd->bank_toggle) {
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
796 m68k->mem_pointers[1] = (value & BIT_RET) ? cd->word_ram : cd->word_ram + 1;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
797 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
798 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000);
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
799 cd->main_swap_request = 0;
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
800 }
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
801 cd->gate_array[reg] |= value & (MASK_PRIORITY|BIT_RET|BIT_MEM_MODE);
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
802 if (cd->main_swap_request) {
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
803 cd->gate_array[reg] |= BIT_DMNA;
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
804 }
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
805 } else {
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
806 //2M mode
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
807 if (old_main_has_word2m != cd->main_has_word2m) {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
808 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
809 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
810 m68k->mem_pointers[0] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
811 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
812 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
813 }
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
814 cd->gate_array[reg] |= value & MASK_PRIORITY;
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
815 cd->gate_array[reg] |= cd->main_has_word2m ? BIT_RET : BIT_DMNA;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
816 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
817 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
818 }
2144
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
819 case GA_CDC_CTRL: {
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
820 cdd_run(cd, m68k->current_cycle);
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
821 lc8951_ar_write(&cd->cdc, value);
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
822 //cd->gate_array[reg] &= 0xC000;
2144
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
823 uint16_t old_dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
824 //apparently this clears EDT, should it also clear DSR?
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
825 cd->gate_array[reg] = value & 0x0700;
2144
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
826 uint16_t dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
827 if (dest != old_dest) {
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
828 if (dest == DST_PCM_RAM) {
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
829 lc8951_set_dma_multiple(&cd->cdc, 21);
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
830 } else {
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
831 lc8951_set_dma_multiple(&cd->cdc, 6);
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
832 }
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
833 if ((old_dest < DST_MAIN_CPU || old_dest == 6) && dest >= DST_MAIN_CPU && dest != 6) {
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
834 lc8951_resume_transfer(&cd->cdc, m68k->current_cycle);
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
835 }
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
836 calculate_target_cycle(m68k);
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
837 }
2135
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
838 cd->gate_array[GA_CDC_DMA_ADDR] = 0;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
839 cd->cdc_dst_low = 0;
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
840 break;
2144
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
841 }
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
842 case GA_CDC_REG_DATA:
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
843 cdd_run(cd, m68k->current_cycle);
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
844 printf("CDC write %X: %X @ %u\n", cd->cdc.ar, value, m68k->current_cycle);
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
845 lc8951_reg_write(&cd->cdc, value);
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
846 calculate_target_cycle(m68k);
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
847 break;
2135
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
848 case GA_CDC_HOST_DATA:
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
849 //writes to this register have the same side effects as reads
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
850 sub_gate_read16(address, vcontext);
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
851 break;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
852 case GA_CDC_DMA_ADDR:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
853 cdd_run(cd, m68k->current_cycle);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
854 cd->gate_array[reg] = value;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
855 cd->cdc_dst_low = 0;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
856 break;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
857 case GA_STOP_WATCH:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
858 //docs say you should only write zero to reset
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
859 //mcd-verificator comments suggest any value will reset
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
860 timers_run(cd, m68k->current_cycle);
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
861 cd->gate_array[reg] = 0;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
862 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
863 case GA_COMM_FLAG:
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
864 cd->gate_array[reg] &= 0xFF00;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
865 cd->gate_array[reg] |= value & 0xFF;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
866 break;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
867 case GA_COMM_STATUS0:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
868 case GA_COMM_STATUS1:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
869 case GA_COMM_STATUS2:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
870 case GA_COMM_STATUS3:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
871 case GA_COMM_STATUS4:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
872 case GA_COMM_STATUS5:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
873 case GA_COMM_STATUS6:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
874 case GA_COMM_STATUS7:
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
875 //no effects for these other than saving the value
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
876 cd->gate_array[reg] = value;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
877 break;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
878 case GA_TIMER:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
879 timers_run(cd, m68k->current_cycle);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
880 cd->gate_array[reg] = value & 0xFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
881 calculate_target_cycle(m68k);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
882 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
883 case GA_INT_MASK:
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
884 if (!(cd->gate_array[reg] & BIT_MASK_IEN6)) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
885 //subcode interrupts can't be made pending when they are disabled in this reg
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
886 cd->cdd.subcode_int_pending = 0;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
887 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
888 cd->gate_array[reg] = value & (BIT_MASK_IEN6|BIT_MASK_IEN5|BIT_MASK_IEN4|BIT_MASK_IEN3|BIT_MASK_IEN2|BIT_MASK_IEN1);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
889 calculate_target_cycle(m68k);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
890 break;
2080
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
891 case GA_CDD_FADER:
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
892 cdd_run(cd, m68k->current_cycle);
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
893 value &= 0x7FFF;
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
894 cdd_fader_attenuation_write(&cd->fader, value);
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
895 cd->gate_array[reg] &= 0x8000;
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
896 cd->gate_array[reg] |= value;
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
897 break;
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
898 case GA_CDD_CTRL: {
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
899 cdd_run(cd, m68k->current_cycle);
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
900 uint16_t changed = cd->gate_array[reg] ^ value;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
901 if (changed & BIT_HOCK) {
2073
c69e42444f96 Fix some cycle adjustment stuff and an off-by one on hte TOCT response
Michael Pavone <pavone@retrodev.com>
parents: 2069
diff changeset
902 cd->gate_array[reg] &= ~BIT_HOCK;
c69e42444f96 Fix some cycle adjustment stuff and an off-by one on hte TOCT response
Michael Pavone <pavone@retrodev.com>
parents: 2069
diff changeset
903 cd->gate_array[reg] |= value & BIT_HOCK;
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
904 if (value & BIT_HOCK) {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
905 cdd_hock_enabled(&cd->cdd);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
906 } else {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
907 cdd_hock_disabled(&cd->cdd);
2080
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
908 cd->gate_array[reg] |= BIT_MUTE;
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
909 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
910 calculate_target_cycle(m68k);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
911 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
912 break;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
913 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
914 case GA_CDD_CMD0:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
915 case GA_CDD_CMD1:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
916 case GA_CDD_CMD2:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
917 case GA_CDD_CMD3:
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
918 cdd_run(cd, m68k->current_cycle);
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
919 cd->gate_array[reg] = value & 0x0F0F;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
920 break;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
921 case GA_CDD_CMD4:
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
922 cdd_run(cd, m68k->current_cycle);
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
923 cd->gate_array[reg] = value & 0x0F0F;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
924 cdd_mcu_start_cmd_recv(&cd->cdd, cd->gate_array + GA_CDD_CTRL);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
925 break;
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
926 case GA_FONT_COLOR:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
927 cd->gate_array[reg] = value & 0xFF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
928 break;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
929 case GA_FONT_BITS:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
930 cd->gate_array[reg] = value;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
931 break;
2069
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
932 case GA_STAMP_SIZE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
933 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
934 cd->gate_array[reg] &= BIT_GRON;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
935 cd->gate_array[reg] |= value & (BIT_SMS|BIT_STS|BIT_RPT);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
936 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
937 case GA_STAMP_MAP_BASE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
938 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
939 cd->gate_array[reg] = value & 0xFFE0;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
940 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
941 case GA_IMAGE_BUFFER_VCELLS:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
942 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
943 cd->gate_array[reg] = value & 0x1F;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
944 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
945 case GA_IMAGE_BUFFER_START:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
946 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
947 cd->gate_array[reg] = value & 0xFFF8;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
948 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
949 case GA_IMAGE_BUFFER_OFFSET:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
950 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
951 cd->gate_array[reg] = value & 0x3F;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
952 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
953 case GA_IMAGE_BUFFER_HDOTS:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
954 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
955 cd->gate_array[reg] = value & 0x1FF;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
956 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
957 case GA_IMAGE_BUFFER_LINES:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
958 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
959 cd->gate_array[reg] = value & 0xFF;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
960 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
961 case GA_TRACE_VECTOR_BASE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
962 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
963 cd->gate_array[reg] = value & 0xFFFE;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
964 cd_graphics_start(cd);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
965 break;
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
966 default:
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
967 printf("Unhandled gate array write %X:%X\n", address, value);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
968 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
969 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
970 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
971
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
972 static void *sub_gate_write8(uint32_t address, void *vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
973 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
974 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
975 segacd_context *cd = m68k->system;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
976 uint32_t reg = (address & 0x1FF) >> 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
977 uint16_t value16;
2056
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
978 switch (address >> 1)
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
979 {
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
980 case GA_MEM_MODE:
2056
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
981 case GA_CDC_HOST_DATA:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
982 case GA_CDC_DMA_ADDR:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
983 case GA_STOP_WATCH:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
984 case GA_COMM_FLAG:
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
985 case GA_TIMER:
2056
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
986 case GA_CDD_FADER:
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
987 case GA_FONT_COLOR:
2056
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
988 //these registers treat all writes as word-wide
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
989 value16 = value | (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
990 break;
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
991 case GA_CDC_CTRL:
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
992 if (address & 1) {
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
993 lc8951_ar_write(&cd->cdc, value);
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
994 return vcontext;
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
995 } else {
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
996 value16 = cd->cdc.ar | (value << 8);
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
997 }
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
998 break;
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
999 case GA_CDD_CMD4:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1000 if (!address) {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1001 //byte write to $FF804A should not trigger transfer
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
1002 cdd_run(cd, m68k->current_cycle);
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1003 cd->gate_array[reg] &= 0x0F;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1004 cd->gate_array[reg] |= (value << 8 & 0x0F00);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1005 return vcontext;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1006 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1007 //intentional fallthrough for $FF804B
2056
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1008 default:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1009 if (address & 1) {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1010 value16 = cd->gate_array[reg] & 0xFF00 | value;
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1011 } else {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1012 value16 = cd->gate_array[reg] & 0xFF | (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1013 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1014 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1015 return sub_gate_write16(address, vcontext, value16);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1016 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1017
2135
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1018 static uint8_t can_main_access_prog(segacd_context *cd)
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1019 {
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1020 //TODO: use actual busack
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1021 return cd->busreq || !cd->reset;
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1022 }
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1023
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1024 static uint8_t handle_cdc_byte(void *vsys, uint8_t value)
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1025 {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1026 segacd_context *cd = vsys;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1027 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1028 //host reg is already full, pause transfer
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1029 return 0;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1030 }
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1031 if (cd->cdc.cycle == cd->cdc.transfer_end) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1032 cd->gate_array[GA_CDC_CTRL] |= BIT_EDT;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1033 printf("EDT set at %u\n", cd->cdc.cycle);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1034 }
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1035 uint16_t dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1036 if (!(cd->cdc_dst_low & 1)) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1037 cd->gate_array[GA_CDC_HOST_DATA] &= 0xFF;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1038 cd->gate_array[GA_CDC_HOST_DATA] |= value << 8;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1039 cd->cdc_dst_low++;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1040 if (dest != DST_PCM_RAM) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1041 //PCM RAM writes a byte at a time
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1042 return 1;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1043 }
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1044 } else {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1045 cd->gate_array[GA_CDC_HOST_DATA] &= 0xFF00;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1046 cd->gate_array[GA_CDC_HOST_DATA] |= value;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1047 }
2068
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1048
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1049 uint32_t dma_addr = cd->gate_array[GA_CDC_DMA_ADDR] << 3;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1050 dma_addr |= cd->cdc_dst_low;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1051 switch (dest)
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1052 {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1053 case DST_MAIN_CPU:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1054 case DST_SUB_CPU:
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1055 cd->cdc_dst_low = 0;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1056 cd->gate_array[GA_CDC_CTRL] |= BIT_DSR;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1057 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1058 case DST_PCM_RAM:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1059 dma_addr &= (1 << 13) - 1;
2094
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
1060 rf5c164_run(&cd->pcm, cd->cdc.cycle);
2128
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
1061 while ((cd->pcm.flags & 0x81) == 1) {
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
1062 //not sounding, but pending write
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
1063 //DMA write conflict with CPU
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
1064 rf5c164_run(&cd->pcm, cd->pcm.cycle + 4);
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
1065 }
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
1066 rf5c164_write(&cd->pcm, 0x1000 | (dma_addr >> 1), value);
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1067 dma_addr += 2;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1068 cd->cdc_dst_low = dma_addr & 7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1069 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3;
2148
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1070 //TODO: determine actual main CPU penalty
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1071 cd->m68k->current_cycle += 2 * cd->m68k->options->gen.bus_cycles;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1072 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1073 case DST_PROG_RAM:
2135
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1074 if (can_main_access_prog(cd)) {
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1075 return 0;
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1076 }
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1077 cd->prog_ram[dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA];
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1078 m68k_invalidate_code_range(cd->m68k, dma_addr - 1, dma_addr + 1);
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1079 dma_addr++;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1080 cd->cdc_dst_low = dma_addr & 7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1081 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3;
2148
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1082 //TODO: determine actual main CPU penalty
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1083 cd->m68k->current_cycle += 2 * cd->m68k->options->gen.bus_cycles;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1084 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1085 case DST_WORD_RAM:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1086 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1087 //1M mode, write to bank assigned to Sub CPU
2135
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1088
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1089 uint32_t masked = dma_addr & (1 << 17) - 2;
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1090 cd->m68k->mem_pointers[1][masked] = cd->gate_array[GA_CDC_HOST_DATA];
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1091 m68k_invalidate_code_range(cd->m68k, 0x0C0000 + masked - 1, 0x0C0000 + masked + 1);
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1092 } else {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1093 //2M mode, check if Sub CPU has access
2129
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2128
diff changeset
1094 if (cd->main_has_word2m) {
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2128
diff changeset
1095 return 0;
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2128
diff changeset
1096 } else {
2094
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
1097 cd_graphics_run(cd, cd->cdc.cycle);
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1098 dma_addr &= (1 << 18) - 1;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1099 cd->word_ram[dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA];
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1100 m68k_invalidate_code_range(cd->m68k, 0x080000 + dma_addr, 0x080000 + dma_addr + 1);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1101 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1102 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1103 dma_addr++;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1104 cd->cdc_dst_low = dma_addr & 7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1105 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1106 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1107 default:
2144
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
1108 return 0;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1109 printf("Invalid CDC transfer destination %d\n", dest);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1110 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1111 return 1;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1112 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1113
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1114 static void scd_peripherals_run(segacd_context *cd, uint32_t cycle)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1115 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1116 timers_run(cd, cycle);
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
1117 cdd_run(cd, cycle);
2069
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1118 cd_graphics_run(cd, cycle);
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
1119 rf5c164_run(&cd->pcm, cycle);
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1120 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1121
2148
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1122 //TODO: do some logic analyzer captuers to get actual values
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1123 #define REFRESH_INTERVAL 256
2233
54cd40fc0da5 Fix regression in mcd-verificator "VAR" tests
Michael Pavone <pavone@retrodev.com>
parents: 2164
diff changeset
1124 #define REFRESH_DELAY 2
2148
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1125
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1126 static m68k_context *sync_components(m68k_context * context, uint32_t address)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1127 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1128 segacd_context *cd = context->system;
2148
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1129
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1130 uint32_t num_refresh = (context->current_cycle - cd->last_refresh_cycle) / REFRESH_INTERVAL;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1131 cd->last_refresh_cycle = cd->last_refresh_cycle + num_refresh * REFRESH_INTERVAL;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1132 context->current_cycle += num_refresh * REFRESH_DELAY;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1133
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1134 scd_peripherals_run(cd, context->current_cycle);
2280
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1135 if (address) {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1136 if (cd->enter_debugger) {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1137 genesis_context *gen = cd->genesis;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1138 cd->enter_debugger = 0;
2302
0343f0d5add0 Fix libretro build for real
Michael Pavone <pavone@retrodev.com>
parents: 2282
diff changeset
1139 #ifndef IS_LIB
2280
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1140 if (gen->header.debugger_type == DEBUGGER_NATIVE) {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1141 debugger(context, address);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1142 } else {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1143 gdb_debug_enter(context, address);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1144 }
2302
0343f0d5add0 Fix libretro build for real
Michael Pavone <pavone@retrodev.com>
parents: 2282
diff changeset
1145 #endif
2104
ff32a90260c9 Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents: 2099
diff changeset
1146 }
2280
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1147 cd->m68k_pc = address;
2080
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
1148 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1149 switch (context->int_ack)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1150 {
2069
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1151 case 1:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1152 cd->graphics_int_cycle = CYCLE_NEVER;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1153 break;
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1154 case 2:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1155 cd->int2_cycle = CYCLE_NEVER;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1156 break;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1157 case 3:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1158 cd->timer_pending = 0;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1159 break;
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1160 case 4:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1161 cd->cdd.int_pending = 0;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1162 break;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1163 case 5:
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1164 cd->cdc_int_ack = 1;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1165 break;
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
1166 case 6:
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
1167 cd->cdd.subcode_int_pending = 0;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
1168 break;
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1169 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1170 context->int_ack = 0;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1171 calculate_target_cycle(context);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1172 return context;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1173 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1174
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1175 void scd_run(segacd_context *cd, uint32_t cycle)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1176 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1177 uint8_t m68k_run = !can_main_access_prog(cd);
2094
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
1178 while (cycle > cd->m68k->current_cycle) {
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
1179 if (m68k_run && !cd->sub_paused_wordram) {
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1180 uint32_t start = cd->m68k->current_cycle;
2148
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1181
2104
ff32a90260c9 Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents: 2099
diff changeset
1182 cd->m68k->sync_cycle = cd->enter_debugger ? cd->m68k->current_cycle + 1 : cycle;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1183 if (cd->need_reset) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1184 cd->need_reset = 0;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1185 m68k_reset(cd->m68k);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1186 } else {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1187 calculate_target_cycle(cd->m68k);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1188 resume_68k(cd->m68k);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1189 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1190 } else {
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1191 cd->m68k->current_cycle = cycle;
2148
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1192 cd->last_refresh_cycle = cycle;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1193 }
2094
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
1194 scd_peripherals_run(cd, cd->m68k->current_cycle);
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1195 }
2094
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
1196
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1197 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1198
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1199 uint32_t gen_cycle_to_scd(uint32_t cycle, genesis_context *gen)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1200 {
2055
c4d066d798c4 Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works
Michael Pavone <pavone@retrodev.com>
parents: 2054
diff changeset
1201 return ((uint64_t)cycle) * ((uint64_t)SCD_MCLKS) / ((uint64_t)gen->normal_clock);
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1202 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1203
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1204 void scd_adjust_cycle(segacd_context *cd, uint32_t deduction)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1205 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1206 deduction = gen_cycle_to_scd(deduction, cd->genesis);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1207 cd->m68k->current_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1208 cd->stopwatch_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1209 if (deduction >= cd->int2_cycle) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1210 cd->int2_cycle = 0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1211 } else if (cd->int2_cycle != CYCLE_NEVER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1212 cd->int2_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1213 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1214 if (deduction >= cd->periph_reset_cycle) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1215 cd->periph_reset_cycle = CYCLE_NEVER;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1216 } else if (cd->periph_reset_cycle != CYCLE_NEVER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1217 cd->periph_reset_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1218 }
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1219 cdd_mcu_adjust_cycle(&cd->cdd, deduction);
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1220 lc8951_adjust_cycles(&cd->cdc, deduction);
2069
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1221 cd->graphics_cycle -= deduction;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1222 if (cd->graphics_int_cycle != CYCLE_NEVER) {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1223 if (cd->graphics_int_cycle > deduction) {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1224 cd->graphics_int_cycle -= deduction;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1225 } else {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1226 cd->graphics_int_cycle = 0;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1227 }
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1228 }
2148
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1229 if (deduction >= cd->last_refresh_cycle) {
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1230 cd->last_refresh_cycle -= deduction;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1231 } else {
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1232 cd->last_refresh_cycle = 0;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1233 }
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
1234 cd->pcm.cycle -= deduction;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1235 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1236
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1237 static uint16_t main_gate_read16(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1238 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1239 m68k_context *m68k = vcontext;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1240 genesis_context *gen = m68k->system;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1241 segacd_context *cd = gen->expansion;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1242 uint32_t scd_cycle = gen_cycle_to_scd(m68k->current_cycle, gen);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1243 scd_run(cd, scd_cycle);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1244 uint32_t offset = (address & 0x1FF) >> 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1245 switch (offset)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1246 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1247 case GA_SUB_CPU_CTRL: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1248 uint16_t value = 0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1249 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1250 value |= BIT_IEN2;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1251 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1252 if (cd->int2_cycle != CYCLE_NEVER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1253 value |= BIT_IFL2;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1254 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1255 if (can_main_access_prog(cd)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1256 value |= BIT_SBRQ;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1257 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1258 if (cd->reset) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1259 value |= BIT_SRES;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1260 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1261 return value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1262 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1263 case GA_MEM_MODE:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1264 //Main CPU can't read priority mode bits
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1265 return cd->gate_array[offset] & 0xFFE7;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1266 case GA_HINT_VECTOR:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1267 return cd->rom_mut[0x72/2];
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1268 case GA_CDC_HOST_DATA: {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1269 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1270 if (dst == DST_MAIN_CPU) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1271 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1272 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1273 lc8951_resume_transfer(&cd->cdc, scd_cycle);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1274 } else {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1275 printf("Read of CDC host data with DSR clear at %u\n", scd_cycle);
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1276 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1277 calculate_target_cycle(cd->m68k);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1278 }
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1279 return cd->gate_array[offset];
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1280 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1281 case GA_CDC_DMA_ADDR:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1282 //TODO: open bus maybe?
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1283 return 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1284 default:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1285 if (offset < GA_TIMER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1286 return cd->gate_array[offset];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1287 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1288 //TODO: open bus maybe?
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1289 return 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1290 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1291 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1292
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1293 static uint8_t main_gate_read8(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1294 {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1295 uint16_t val = main_gate_read16(address & 0xFE, vcontext);
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1296 return address & 1 ? val : val >> 8;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1297 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1298
2068
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1299 static void dump_prog_ram(segacd_context *cd)
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1300 {
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1301 static int dump_count;
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1302 char fname[256];
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1303 sprintf(fname, "prog_ram_%d.bin", dump_count++);
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1304 FILE *f = fopen(fname, "wb");
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1305 if (f) {
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1306 uint32_t last = 256*1024-1;
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1307 for(; last > 0; --last)
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1308 {
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1309 if (cd->prog_ram[last]) {
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1310 break;
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1311 }
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1312 }
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1313 for (uint32_t i = 0; i <= last; i++)
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1314 {
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1315 uint8_t pair[2];
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1316 pair[0] = cd->prog_ram[i] >> 8;
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1317 pair[1] = cd->prog_ram[i];
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1318 fwrite(pair, 1, sizeof(pair), f);
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1319 }
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1320
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1321 fclose(f);
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1322 }
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1323 }
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1324
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1325 static void *main_gate_write16(uint32_t address, void *vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1326 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1327 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1328 genesis_context *gen = m68k->system;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1329 segacd_context *cd = gen->expansion;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1330 uint32_t scd_cycle = gen_cycle_to_scd(m68k->current_cycle, gen);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1331 scd_run(cd, scd_cycle);
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1332 uint32_t reg = (address & 0x1FF) >> 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1333 switch (reg)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1334 {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1335 case GA_SUB_CPU_CTRL: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1336 uint8_t old_access = can_main_access_prog(cd);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1337 cd->busreq = value & BIT_SBRQ;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1338 uint8_t old_reset = cd->reset;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1339 cd->reset = value & BIT_SRES;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1340 if (cd->reset && !old_reset) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1341 cd->need_reset = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1342 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1343 if (value & BIT_IFL2) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1344 cd->int2_cycle = scd_cycle;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1345 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1346 /*cd->gate_array[reg] &= 0x7FFF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1347 cd->gate_array[reg] |= value & 0x8000;*/
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1348 uint8_t new_access = can_main_access_prog(cd);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1349 uint32_t bank = cd->gate_array[GA_MEM_MODE] >> 6 & 0x3;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1350 if (new_access) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1351 if (!old_access) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1352 m68k->mem_pointers[cd->memptr_start_index] = cd->prog_ram + bank * 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1353 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1354 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1355 } else if (old_access) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1356 m68k->mem_pointers[cd->memptr_start_index] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1357 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1358 m68k_invalidate_code_range(cd->m68k, bank * 0x20000, (bank + 1) * 0x20000);
2135
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1359 dump_prog_ram(cd);
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1360 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1361 if (dst == DST_PROG_RAM) {
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1362 lc8951_resume_transfer(&cd->cdc, cd->cdc.cycle);
2068
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1363 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1364 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1365 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1366 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1367 case GA_MEM_MODE: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1368 uint16_t changed = cd->gate_array[reg] ^ value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1369 //Main CPU can't write priority mode bits, MODE or RET
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1370 cd->gate_array[reg] &= 0x001F;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1371 cd->gate_array[reg] |= value & 0xFFC0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1372 if ((cd->gate_array[reg] & BIT_MEM_MODE)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1373 //1M mode
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1374 if (!(value & BIT_DMNA)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1375 cd->gate_array[reg] |= BIT_DMNA;
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
1376 cd->main_swap_request = 1;
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
1377 } else {
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
1378 cd->main_has_word2m = 0;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1379 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1380 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1381 //2M mode
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1382 if (changed & value & BIT_DMNA) {
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1383 cd->gate_array[reg] |= BIT_DMNA;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1384 m68k->mem_pointers[cd->memptr_start_index + 1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1385 m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1386 cd->m68k->mem_pointers[0] = cd->word_ram;
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1387 cd->gate_array[reg] &= ~BIT_RET;
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
1388 cd->main_has_word2m = 0;
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
1389 if (cd->sub_paused_wordram) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
1390 cd->sub_paused_wordram = 0;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
1391 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1392
2129
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2128
diff changeset
1393 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2128
diff changeset
1394 if (dst == DST_WORD_RAM) {
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2128
diff changeset
1395 lc8951_resume_transfer(&cd->cdc, cd->cdc.cycle);
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2128
diff changeset
1396 }
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2128
diff changeset
1397
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1398 m68k_invalidate_code_range(m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1399 m68k_invalidate_code_range(cd->m68k, 0x080000, 0x0C0000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1400 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1401 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1402 if (changed & MASK_PROG_BANK && can_main_access_prog(cd)) {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1403 uint32_t bank = cd->gate_array[GA_MEM_MODE] >> 6 & 0x3;
2055
c4d066d798c4 Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works
Michael Pavone <pavone@retrodev.com>
parents: 2054
diff changeset
1404 m68k->mem_pointers[cd->memptr_start_index] = cd->prog_ram + bank * 0x10000;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1405 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1406 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1407 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1408 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1409 case GA_HINT_VECTOR:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1410 cd->rom_mut[0x72/2] = value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1411 break;
2135
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1412 case GA_CDC_HOST_DATA:
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1413 //writes to this register have the same side effects as reads
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1414 main_gate_read16(address, vcontext);
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1415 break;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1416 case GA_COMM_FLAG:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1417 //Main CPU can only write the upper byte;
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1418 cd->gate_array[reg] &= 0xFF;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1419 cd->gate_array[reg] |= value & 0xFF00;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1420 break;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1421 case GA_COMM_CMD0:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1422 case GA_COMM_CMD1:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1423 case GA_COMM_CMD2:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1424 case GA_COMM_CMD3:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1425 case GA_COMM_CMD4:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1426 case GA_COMM_CMD5:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1427 case GA_COMM_CMD6:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1428 case GA_COMM_CMD7:
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1429 //no effects for these other than saving the value
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1430 cd->gate_array[reg] = value;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1431 break;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1432 default:
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1433 printf("Unhandled gate array write %X:%X\n", address, value);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1434 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1435 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1436 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1437
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1438 static void *main_gate_write8(uint32_t address, void *vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1439 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1440 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1441 genesis_context *gen = m68k->system;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1442 segacd_context *cd = gen->expansion;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1443 uint32_t reg = (address & 0x1FF) >> 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1444 uint16_t value16;
2108
68d61ba1b762 Fix handling of byte writes to gate array regs from main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2106
diff changeset
1445 switch (reg)
2056
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1446 {
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1447 case GA_SUB_CPU_CTRL:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1448 if (address & 1) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1449 value16 = value;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1450 } else {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1451 value16 = value << 8;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1452 if (cd->reset) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1453 value16 |= BIT_SRES;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1454 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1455 if (cd->busreq) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1456 value16 |= BIT_SBRQ;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1457 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1458 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1459 break;
2056
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1460 case GA_HINT_VECTOR:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1461 case GA_COMM_FLAG:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1462 //writes to these regs are always treated as word wide
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1463 value16 = value | (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1464 break;
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1465 default:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1466 if (address & 1) {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1467 value16 = cd->gate_array[reg] & 0xFF00 | value;
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1468 } else {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1469 value16 = cd->gate_array[reg] & 0xFF | (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1470 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1471 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1472 return main_gate_write16(address, vcontext, value16);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1473 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1474
2329
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1475 uint8_t laseractive_regs[256];
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1476
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1477 static uint16_t laseractive_read16(uint32_t address, void *vcontext)
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1478 {
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1479 printf("LaserActive 16-bit register read %X\n", address);
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1480 return 0xFFFF;
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1481 }
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1482
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1483 static uint8_t laseractive_read8(uint32_t address, void *vcontext)
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1484 {
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1485 printf("LaserActive 8-bit register read %X\n", address);
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1486 if (address == 0xFDFE81) {
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1487 return 0x80 | (laseractive_regs[0x41] & 1);
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1488 } else if (address >= 0xFDFE41 && address < 0xFDFE80 && (address & 1)) {
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1489 return laseractive_regs[address & 0xFF];
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1490 }
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1491 return 0xFF;
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1492 }
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1493
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1494 static void *laseractive_write16(uint32_t address, void *vcontext, uint16_t value)
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1495 {
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1496 printf("LaserActive 16-bit register write %X: %X\n", address, value);
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1497 return vcontext;
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1498 }
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1499
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1500 static void *laseractive_write8(uint32_t address, void *vcontext, uint8_t value)
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1501 {
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1502 printf("LaserActive 8-bit register write %X: %X\n", address, value);
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1503 laseractive_regs[address & 0xFF] = value;
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1504 return vcontext;
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1505 }
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1506
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1507 segacd_context *alloc_configure_segacd(system_media *media, uint32_t opts, uint8_t force_region, rom_info *info)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1508 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1509 static memmap_chunk sub_cpu_map[] = {
2111
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1510 {0x000000, 0x01FF00, 0xFFFFFF, .flags=MMAP_READ | MMAP_CODE, .write_16 = prog_ram_wp_write16, .write_8 = prog_ram_wp_write8},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1511 {0x01FF00, 0x080000, 0xFFFFFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_CODE},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1512 {0x080000, 0x0C0000, 0x03FFFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_CODE | MMAP_PTR_IDX | MMAP_FUNC_NULL, .ptr_index = 0,
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1513 .read_16 = word_ram_2M_read16, .write_16 = word_ram_2M_write16, .read_8 = word_ram_2M_read8, .write_8 = word_ram_2M_write8},
2111
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1514 {0x0C0000, 0x0E0000, 0x01FFFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_CODE | MMAP_PTR_IDX | MMAP_FUNC_NULL, .ptr_index = 1,
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
1515 .read_16 = word_ram_1M_read16, .write_16 = word_ram_1M_write16, .read_8 = word_ram_1M_read8, .write_8 = word_ram_1M_write8, .shift = 1},
2111
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1516 {0xFE0000, 0xFF0000, 0x003FFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_ONLY_ODD},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1517 {0xFF0000, 0xFF8000, 0x003FFF, .read_16 = pcm_read16, .write_16 = pcm_write16, .read_8 = pcm_read8, .write_8 = pcm_write8},
2329
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1518 {0xFF8000, 0xFF8200, 0x0001FF, .read_16 = sub_gate_read16, .write_16 = sub_gate_write16, .read_8 = sub_gate_read8, .write_8 = sub_gate_write8},
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1519 {0xFD0000, 0xFE0000, 0xFFFFFF, .read_16 = laseractive_read16, .write_16 = laseractive_write16, .read_8 = laseractive_read8, .write_8 = laseractive_write8}
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1520 };
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1521
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1522 segacd_context *cd = calloc(sizeof(segacd_context), 1);
2083
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents: 2081
diff changeset
1523 uint32_t firmware_size;
2123
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1524 uint8_t region = force_region;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1525 if (!region) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1526 char * def_region = tern_find_path_default(config, "system\0default_region\0", (tern_val){.ptrval = "U"}, TVAL_PTR).ptrval;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1527 if (!info->regions || (info->regions & translate_region_char(toupper(*def_region)))) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1528 region = translate_region_char(toupper(*def_region));
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1529 } else {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1530 region = info->regions;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1531 }
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1532 }
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1533 const char *key;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1534 if (region & REGION_E) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1535 key = "system\0scd_bios_eu\0";
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1536 } else if (region & REGION_J) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1537 key = "system\0scd_bios_jp\0";
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1538 } else {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1539 key = "system\0scd_bios_us\0";
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1540 }
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1541 char *bios_path = tern_find_path_default(config, key, (tern_val){.ptrval = "cdbios.bin"}, TVAL_PTR).ptrval;
2160
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1542 if (is_absolute_path(bios_path)) {
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1543 FILE *f = fopen(bios_path, "rb");
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1544 if (f) {
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1545 long to_read = file_size(f);
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1546 cd->rom = malloc(to_read);
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1547 firmware_size = fread(cd->rom, 1, to_read, f);
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1548 if (!firmware_size) {
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1549 free(cd->rom);
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1550 cd->rom = NULL;
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1551 }
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1552 fclose(f);
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1553 }
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1554 } else {
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1555 cd->rom = (uint16_t *)read_bundled_file(bios_path, &firmware_size);
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1556 }
2123
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1557 if (!cd->rom) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1558 fatal_error("Failed to load Sega CD BIOS from %s\n", bios_path);
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1559 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1560 uint32_t adjusted_size = nearest_pow2(firmware_size);
2083
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents: 2081
diff changeset
1561 if (adjusted_size != firmware_size) {
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents: 2081
diff changeset
1562 cd->rom = realloc(cd->rom, adjusted_size);
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1563 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1564 cd->rom_mut = malloc(adjusted_size);
1503
a763523dadf4 Added code for initializing a combined Genesis + Sega CD system when a Sega CD ISO is loaded
Michael Pavone <pavone@retrodev.com>
parents: 1502
diff changeset
1565 byteswap_rom(adjusted_size, cd->rom);
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1566 memcpy(cd->rom_mut, cd->rom, adjusted_size);
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1567 cd->rom_mut[0x72/2] = 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1568
2083
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents: 2081
diff changeset
1569 cd->prog_ram = calloc(512*1024, 1);
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents: 2081
diff changeset
1570 cd->word_ram = calloc(256*1024, 1);
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents: 2081
diff changeset
1571 cd->bram = calloc(8*1024, 1);
2281
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1572 char *bram_size_id = tern_find_path_default(config, "system\0bram_cart_size_id\0", (tern_val){.ptrval = "4"}, TVAL_PTR).ptrval;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1573 cd->bram_cart_id = 0xFF;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1574 cd->bram_cart = NULL;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1575 if (strcmp(bram_size_id, "none")) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1576 char *end;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1577 long id = strtol(bram_size_id, &end, 10);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1578 if (end != bram_size_id && id < 8) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1579 cd->bram_cart_id = id;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1580 cd->bram_cart = calloc(0x2000 << id, 1);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1581 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1582 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1583
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1584 sub_cpu_map[0].buffer = sub_cpu_map[1].buffer = cd->prog_ram;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1585 sub_cpu_map[4].buffer = cd->bram;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1586 m68k_options *mopts = malloc(sizeof(m68k_options));
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1587 init_m68k_opts(mopts, sub_cpu_map, sizeof(sub_cpu_map) / sizeof(*sub_cpu_map), 4, sync_components);
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1588 cd->m68k = init_68k_context(mopts, NULL);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1589 cd->m68k->system = cd;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1590 cd->int2_cycle = CYCLE_NEVER;
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1591 cd->busreq = 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1592 cd->busack = 1;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1593 cd->need_reset = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1594 cd->reset = 1; //active low, so reset is not active on start
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1595 cd->memptr_start_index = 0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1596 cd->gate_array[1] = 1;
2080
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
1597 cd->gate_array[GA_CDD_CTRL] = BIT_MUTE; //Data/mute flag is set on start
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
1598 cd->main_has_word2m = 1;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1599 lc8951_init(&cd->cdc, handle_cdc_byte, cd);
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1600 if (media->chain && media->type != MEDIA_CDROM) {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1601 media = media->chain;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1602 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1603 cdd_mcu_init(&cd->cdd, media);
2069
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1604 cd_graphics_init(cd);
2080
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
1605 cdd_fader_init(&cd->fader);
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
1606 rf5c164_init(&cd->pcm, SCD_MCLKS, 4);
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1607 return cd;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1608 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1609
2164
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1610 void free_segacd(segacd_context *cd)
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1611 {
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1612 cdd_fader_deinit(&cd->fader);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1613 rf5c164_deinit(&cd->pcm);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1614 m68k_options_free(cd->m68k->options);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1615 free(cd->m68k);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1616 free(cd->bram);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1617 free(cd->word_ram);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1618 free(cd->prog_ram);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1619 free(cd->rom_mut);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1620 }
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1621
2280
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1622 void segacd_serialize(segacd_context *cd, serialize_buffer *buf, uint8_t all)
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1623 {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1624 if (all) {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1625 start_section(buf, SECTION_SUB_68000);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1626 m68k_serialize(cd->m68k, cd->m68k_pc, buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1627 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1628
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1629 start_section(buf, SECTION_GATE_ARRAY);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1630 save_buffer16(buf, cd->gate_array, sizeof(cd->gate_array)/sizeof(*cd->gate_array));
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1631 save_buffer16(buf, cd->prog_ram, 256*1024);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1632 save_buffer16(buf, cd->word_ram, 128*1024);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1633 save_int16(buf, cd->rom_mut[0x72/2]);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1634 save_int32(buf, cd->stopwatch_cycle);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1635 save_int32(buf, cd->int2_cycle);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1636 save_int32(buf, cd->graphics_int_cycle);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1637 save_int32(buf, cd->periph_reset_cycle);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1638 save_int32(buf, cd->last_refresh_cycle);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1639 save_int32(buf, cd->graphics_cycle);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1640 save_int32(buf, cd->base);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1641 save_int32(buf, cd->graphics_x);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1642 save_int32(buf, cd->graphics_y);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1643 save_int32(buf, cd->graphics_dx);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1644 save_int32(buf, cd->graphics_dy);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1645 save_int32(buf, cd->graphics_dst_x);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1646 save_buffer8(buf, cd->graphics_pixels, sizeof(cd->graphics_pixels));
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1647 save_int8(buf, cd->timer_pending);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1648 save_int8(buf, cd->timer_value);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1649 save_int8(buf, cd->busreq);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1650 save_int8(buf, cd->reset);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1651 save_int8(buf, cd->need_reset);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1652 save_int8(buf, cd->cdc_dst_low);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1653 save_int8(buf, cd->cdc_int_ack);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1654 save_int8(buf, cd->graphics_step);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1655 save_int8(buf, cd->graphics_dst_y);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1656 save_int8(buf, cd->main_has_word2m);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1657 save_int8(buf, cd->main_swap_request);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1658 save_int8(buf, cd->bank_toggle);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1659 save_int8(buf, cd->sub_paused_wordram);
2281
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1660 save_int8(buf, cd->bram_cart_write_enabled);
2280
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1661 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1662
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1663 start_section(buf, SECTION_CDD_MCU);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1664 cdd_mcu_serialize(&cd->cdd, buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1665 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1666
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1667 start_section(buf, SECTION_LC8951);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1668 lc8951_serialize(&cd->cdc, buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1669 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1670
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1671 start_section(buf, SECTION_CDROM);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1672 cdimage_serialize(cd->cdd.media, buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1673 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1674 }
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1675 start_section(buf, SECTION_RF5C164);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1676 rf5c164_serialize(&cd->pcm, buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1677 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1678
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1679 start_section(buf, SECTION_CDD_FADER);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1680 cdd_fader_serialize(&cd->fader, buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1681 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1682 }
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1683
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1684 static void gate_array_deserialize(deserialize_buffer *buf, void *vcd)
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1685 {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1686 segacd_context *cd = vcd;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1687 load_buffer16(buf, cd->gate_array, sizeof(cd->gate_array)/sizeof(*cd->gate_array));
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1688 load_buffer16(buf, cd->prog_ram, 256*1024);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1689 load_buffer16(buf, cd->word_ram, 128*1024);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1690 cd->rom_mut[0x72/2] = load_int16(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1691 cd->stopwatch_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1692 cd->int2_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1693 cd->graphics_int_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1694 cd->periph_reset_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1695 cd->last_refresh_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1696 cd->graphics_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1697 cd->base = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1698 cd->graphics_x = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1699 cd->graphics_y = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1700 cd->graphics_dx = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1701 cd->graphics_dy = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1702 cd->graphics_dst_x = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1703 load_buffer8(buf, cd->graphics_pixels, sizeof(cd->graphics_pixels));
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1704 cd->timer_pending = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1705 cd->timer_value = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1706 cd->busreq = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1707 cd->reset = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1708 cd->need_reset = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1709 cd->cdc_dst_low = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1710 cd->cdc_int_ack = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1711 cd->graphics_step = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1712 cd->graphics_dst_y = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1713 cd->main_has_word2m = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1714 cd->main_swap_request = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1715 cd->bank_toggle = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1716 cd->sub_paused_wordram = load_int8(buf);
2281
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1717 cd->bram_cart_write_enabled = load_int8(buf);
2280
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1718
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1719 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1720 //1M mode
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1721 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1722 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1723 cd->m68k->mem_pointers[0] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1724 cd->m68k->mem_pointers[1] = cd->bank_toggle ? cd->word_ram : cd->word_ram + 1;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1725 } else {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1726 //2M mode
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1727 if (cd->main_has_word2m) {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1728 //main CPU has word ram
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1729 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1730 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1731 cd->m68k->mem_pointers[0] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1732 cd->m68k->mem_pointers[1] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1733 } else {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1734 //sub cpu has word ram
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1735 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1736 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1737 cd->m68k->mem_pointers[0] = cd->word_ram;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1738 cd->m68k->mem_pointers[1] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1739 }
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1740 }
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1741
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1742 m68k_invalidate_code_range(cd->m68k, 0, 0x0E0000);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1743 m68k_invalidate_code_range(cd->genesis->m68k, cd->base + 0x200000, cd->base + 0x240000);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1744 }
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1745
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1746 void segacd_register_section_handlers(segacd_context *cd, deserialize_buffer *buf)
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1747 {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1748 register_section_handler(buf, (section_handler){.fun = m68k_deserialize, .data = cd->m68k}, SECTION_SUB_68000);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1749 register_section_handler(buf, (section_handler){.fun = gate_array_deserialize, .data = cd}, SECTION_GATE_ARRAY);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1750 register_section_handler(buf, (section_handler){.fun = cdd_mcu_deserialize, .data = &cd->cdd}, SECTION_CDD_MCU);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1751 register_section_handler(buf, (section_handler){.fun = lc8951_deserialize, .data = &cd->cdc}, SECTION_LC8951);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1752 register_section_handler(buf, (section_handler){.fun = rf5c164_deserialize, .data = &cd->pcm}, SECTION_RF5C164);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1753 register_section_handler(buf, (section_handler){.fun = cdd_fader_deserialize, .data = &cd->fader}, SECTION_CDD_FADER);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1754 register_section_handler(buf, (section_handler){.fun = cdimage_deserialize, .data = cd->cdd.media}, SECTION_CDROM);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1755 }
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1756
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1757 memmap_chunk *segacd_main_cpu_map(segacd_context *cd, uint8_t cart_boot, uint32_t *num_chunks)
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1758 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1759 static memmap_chunk main_cpu_map[] = {
2111
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1760 {0x000000, 0x020000, 0x01FFFF, .flags=MMAP_READ},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1761 {0x020000, 0x040000, 0x01FFFF, .flags=MMAP_READ|MMAP_WRITE|MMAP_PTR_IDX|MMAP_FUNC_NULL|MMAP_CODE, .ptr_index = 0,
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1762 .read_16 = unmapped_prog_read16, .write_16 = unmapped_prog_write16, .read_8 = unmapped_prog_read8, .write_8 = unmapped_prog_write8},
2111
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1763 {0x040000, 0x060000, 0x01FFFF, .flags=MMAP_READ}, //first ROM alias
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1764 //TODO: additional ROM/prog RAM aliases
2111
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1765 {0x200000, 0x220000, 0x01FFFF, .flags=MMAP_READ|MMAP_WRITE|MMAP_PTR_IDX|MMAP_FUNC_NULL|MMAP_CODE, .ptr_index = 1,
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1766 .read_16 = unmapped_word_read16, .write_16 = unmapped_word_write16, .read_8 = unmapped_word_read8, .write_8 = unmapped_word_write8},
2111
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1767 {0x220000, 0x240000, 0x01FFFF, .flags=MMAP_READ|MMAP_WRITE|MMAP_PTR_IDX|MMAP_FUNC_NULL|MMAP_CODE, .ptr_index = 2,
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1768 .read_16 = cell_image_read16, .write_16 = cell_image_write16, .read_8 = cell_image_read8, .write_8 = cell_image_write8},
2281
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1769 {0xA12000, 0xA13000, 0xFFFFFF, .read_16 = main_gate_read16, .write_16 = main_gate_write16, .read_8 = main_gate_read8, .write_8 = main_gate_write8},
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1770 {0x400000, 0x800000, 0xFFFFFF, .read_16 = cart_area_read16, .write_16 = cart_area_write16, .read_8 = cart_area_read8, .write_8 = cart_area_write8}
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1771 };
2281
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1772 *num_chunks = sizeof(main_cpu_map) / sizeof(*main_cpu_map);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1773 if (cart_boot) {
2282
a6a68c33cce7 Fix regression in Mode 1 boot
Michael Pavone <pavone@retrodev.com>
parents: 2281
diff changeset
1774 (*num_chunks)--;
2281
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1775 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1776 for (int i = 0; i < *num_chunks; i++)
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1777 {
2281
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1778 if (main_cpu_map[i].start < 0x400000) {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1779 if (cart_boot) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1780 main_cpu_map[i].start |= 0x400000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1781 main_cpu_map[i].end |= 0x400000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1782 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1783 main_cpu_map[i].start &= 0x3FFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1784 main_cpu_map[i].end &= 0x3FFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1785 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1786 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1787 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1788 main_cpu_map[0].buffer = cd->rom_mut;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1789 main_cpu_map[2].buffer = cd->rom;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1790 main_cpu_map[1].buffer = cd->prog_ram;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1791 main_cpu_map[3].buffer = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1792 main_cpu_map[4].buffer = cd->word_ram + 0x10000;
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1793 return main_cpu_map;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1794 }
2278
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1795
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1796 void segacd_set_speed_percent(segacd_context *cd, uint32_t percent)
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1797 {
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1798 uint32_t scd_cycle = gen_cycle_to_scd(cd->genesis->ym->current_cycle, cd->genesis);
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1799 scd_run(cd, scd_cycle);
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1800 uint32_t new_clock = ((uint64_t)SCD_MCLKS * (uint64_t)percent) / 100;
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1801 rf5c164_adjust_master_clock(&cd->pcm, new_clock);
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1802 cdd_fader_set_speed_percent(&cd->fader, percent);
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1803 }