repos/blastem: segacd.c annotate

annotate segacd.c @ 2688:b42f00a3a937 default tip

Fix default target. Ensure m68k.h and z80.h are built before anything else when no dep info is available

author	Michael Pavone <pavone@retrodev.com>
date	Mon, 31 Mar 2025 21:06:18 -0700
parents	07cc0f7109f0
children

rev	line source
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1 #include <stdlib.h>
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	2 #include <string.h>
2126 da1fae7d5407 Fix embarassing typo Michael Pavone <pavone@retrodev.com> parents: 2125 diff changeset	3 #include <ctype.h>
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	4 #include "cd_graphics.h"
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	5 #include "genesis.h"
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	6 #include "util.h"
2104 ff32a90260c9 Initial support for using debugger on sub CPU Michael Pavone <pavone@retrodev.com> parents: 2099 diff changeset	7 #include "debug.h"
ff32a90260c9 Initial support for using debugger on sub CPU Michael Pavone <pavone@retrodev.com> parents: 2099 diff changeset	8 #include "gdb_remote.h"
2123 50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	9 #include "blastem.h"
2280 9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	10 #include "cdimage.h"
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	11
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	12 #define SCD_MCLKS 50000000
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	13 #define SCD_PERIPH_RESET_CLKS (SCD_MCLKS / 10)
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	14 #define TIMER_TICK_CLKS 1536/1792/
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	15
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	16 //TODO: do some logic analyzer captuers to get actual values
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	17 #define REFRESH_INTERVAL 259
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	18 #define REFRESH_DELAY 2
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	19
2669 c6bc66b16392 Less broken Sega CD emulation with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2519 diff changeset	20 #ifdef NEW_CORE
c6bc66b16392 Less broken Sega CD emulation with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2519 diff changeset	21 #define int_num int_priority
c6bc66b16392 Less broken Sega CD emulation with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2519 diff changeset	22 #endif
c6bc66b16392 Less broken Sega CD emulation with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2519 diff changeset	23
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	24 enum {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	25 GA_SUB_CPU_CTRL,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	26 GA_MEM_MODE,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	27 GA_CDC_CTRL,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	28 GA_CDC_REG_DATA,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	29 GA_CDC_HOST_DATA,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	30 GA_CDC_DMA_ADDR,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	31 GA_STOP_WATCH,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	32 GA_COMM_FLAG,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	33 GA_COMM_CMD0,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	34 GA_COMM_CMD1,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	35 GA_COMM_CMD2,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	36 GA_COMM_CMD3,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	37 GA_COMM_CMD4,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	38 GA_COMM_CMD5,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	39 GA_COMM_CMD6,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	40 GA_COMM_CMD7,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	41 GA_COMM_STATUS0,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	42 GA_COMM_STATUS1,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	43 GA_COMM_STATUS2,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	44 GA_COMM_STATUS3,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	45 GA_COMM_STATUS4,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	46 GA_COMM_STATUS5,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	47 GA_COMM_STATUS6,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	48 GA_COMM_STATUS7,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	49 GA_TIMER,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	50 GA_INT_MASK,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	51 GA_CDD_FADER,
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	52 GA_CDD_CTRL,
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	53 GA_CDD_STATUS0,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	54 GA_CDD_STATUS1,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	55 GA_CDD_STATUS2,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	56 GA_CDD_STATUS3,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	57 GA_CDD_STATUS4,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	58 GA_CDD_CMD0,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	59 GA_CDD_CMD1,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	60 GA_CDD_CMD2,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	61 GA_CDD_CMD3,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	62 GA_CDD_CMD4,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	63 GA_FONT_COLOR,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	64 GA_FONT_BITS,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	65 GA_FONT_DATA0,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	66 GA_FONT_DATA1,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	67 GA_FONT_DATA2,
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	68 GA_FONT_DATA3,
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	69 GA_SUBCODE_START = 0x80,
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	70 GA_SUBCODE_MIRROR = 0xC0,
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	71
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	72 GA_HINT_VECTOR = GA_CDC_REG_DATA
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	73 };
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	74 //GA_SUB_CPU_CTRL
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	75 #define BIT_IEN2 0x8000
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	76 #define BIT_IFL2 0x0100
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	77 #define BIT_LEDG 0x0200
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	78 #define BIT_LEDR 0x0100
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	79 #define BIT_SBRQ 0x0002
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	80 #define BIT_SRES 0x0001
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	81 #define BIT_PRES 0x0001
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	82 //GA_MEM_MODE
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	83 #define MASK_PROG_BANK 0x00C0
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	84 #define BIT_OVERWRITE 0x0010
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	85 #define BIT_UNDERWRITE 0x0008
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	86 #define MASK_PRIORITY (BIT_OVERWRITE\|BIT_UNDERWRITE)
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	87 #define BIT_MEM_MODE 0x0004
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	88 #define BIT_DMNA 0x0002
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	89 #define BIT_RET 0x0001
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	90
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	91 //GA_CDC_CTRL
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	92 #define BIT_EDT 0x8000
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	93 #define BIT_DSR 0x4000
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	94
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	95 //GA_CDD_CTRL
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	96 #define BIT_MUTE 0x0100
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	97
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	98 enum {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	99 DST_MAIN_CPU = 2,
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	100 DST_SUB_CPU,
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	101 DST_PCM_RAM,
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	102 DST_PROG_RAM,
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	103 DST_WORD_RAM = 7
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	104 };
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	105
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	106 //GA_INT_MASK
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	107 #define BIT_MASK_IEN1 0x0002
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	108 #define BIT_MASK_IEN2 0x0004
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	109 #define BIT_MASK_IEN3 0x0008
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	110 #define BIT_MASK_IEN4 0x0010
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	111 #define BIT_MASK_IEN5 0x0020
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	112 #define BIT_MASK_IEN6 0x0040
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	113
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	114 //GA_CDD_CTRL
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	115 #define BIT_HOCK 0x0004
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	116
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	117 static void prog_ram_wp_write16(uint32_t address, void vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	118 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	119 m68k_context *m68k = vcontext;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	120 segacd_context *cd = m68k->system;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	121 //if (!(cd->gate_array[GA_MEM_MODE] & (1 << ((address >> 9) + 8)))) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	122 if (address >= ((cd->gate_array[GA_MEM_MODE] & 0xFF00) << 1)) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	123 cd->prog_ram[address >> 1] = value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	124 m68k_invalidate_code_range(m68k, address, address + 2);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	125 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	126 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	127 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	128
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	129 static void prog_ram_wp_write8(uint32_t address, void vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	130 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	131 m68k_context *m68k = vcontext;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	132 segacd_context *cd = m68k->system;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	133 if (address >= ((cd->gate_array[GA_MEM_MODE] & 0xFF00) << 1)) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	134 ((uint8_t *)cd->prog_ram)[address ^ 1] = value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	135 m68k_invalidate_code_range(m68k, address, address + 1);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	136 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	137 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	138 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	139
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	140 static uint16_t word_ram_2M_read16(uint32_t address, void *vcontext)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	141 {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	142 m68k_context *m68k = vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	143 uint16_t* bank = m68k->mem_pointers[1];
2099 b92c998c6742 Add some missing null checks in the Sega CD code dealing with word RAM switching Michael Pavone <pavone@retrodev.com> parents: 2094 diff changeset	144 if (!bank) {
b92c998c6742 Add some missing null checks in the Sega CD code dealing with word RAM switching Michael Pavone <pavone@retrodev.com> parents: 2094 diff changeset	145 return 0xFFFF;
b92c998c6742 Add some missing null checks in the Sega CD code dealing with word RAM switching Michael Pavone <pavone@retrodev.com> parents: 2094 diff changeset	146 }
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	147 uint16_t raw = bank[address >> 1 & ~1];
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	148 if (address & 2) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	149 return (raw & 0xF) \| (raw << 4 & 0xF00);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	150 } else {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	151 return (raw >> 4 & 0xF00) \| (raw >> 8 & 0xF);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	152 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	153 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	154
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	155 static uint8_t word_ram_2M_read8(uint32_t address, void *vcontext)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	156 {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	157 uint16_t word = word_ram_2M_read16(address, vcontext);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	158 if (address & 1) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	159 return word;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	160 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	161 return word >> 8;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	162 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	163
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	164 static void word_ram_2M_write8(uint32_t address, void vcontext, uint8_t value)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	165 {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	166 m68k_context *m68k = vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	167 segacd_context *cd = m68k->system;
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	168 if (!(cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE)) {
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2137 diff changeset	169 //TODO: Confirm this first write goes through (seemed like it in initial testing)
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	170 if (address & 1) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	171 address >>= 1;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	172 cd->word_ram[address] &= 0xFF00;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	173 cd->word_ram[address] \|= value;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	174 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	175 address >>= 1;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	176 cd->word_ram[address] &= 0x00FF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	177 cd->word_ram[address] \|= value << 8;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	178 }
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2137 diff changeset	179 m68k_invalidate_code_range(cd->genesis->m68k, cd->base + 0x200000 + (address & ~1), cd->base + 0x200000 + (address & ~1) + 1);
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	180 cd->sub_paused_wordram = 1;
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	181 m68k->sync_cycle = m68k->target_cycle = m68k->cycles;
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	182 m68k->should_return = 1;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	183 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	184 value &= 0xF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	185 uint16_t priority = cd->gate_array[GA_MEM_MODE] & MASK_PRIORITY;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	186
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	187 if (priority == BIT_OVERWRITE && !value) {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	188 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	189 }
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	190 if (priority == BIT_UNDERWRITE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	191 if (!value) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	192 return vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	193 }
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	194 uint8_t old = word_ram_2M_read8(address, vcontext);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	195 if (old) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	196 return vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	197 }
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	198 }
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	199 uint16_t* bank = m68k->mem_pointers[1];
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	200 if (!bank) {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	201 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	202 }
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	203 uint16_t raw = bank[address >> 1 & ~1];
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	204 uint16_t shift = ((address & 3) * 4);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	205 raw &= ~(0xF000 >> shift);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	206 raw \|= value << (12 - shift);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	207 bank[address >> 1 & ~1] = raw;
2099 b92c998c6742 Add some missing null checks in the Sega CD code dealing with word RAM switching Michael Pavone <pavone@retrodev.com> parents: 2094 diff changeset	208 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	209 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	210 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	211
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	212
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	213 static void word_ram_2M_write16(uint32_t address, void vcontext, uint16_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	214 {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	215 word_ram_2M_write8(address, vcontext, value >> 8);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	216 return word_ram_2M_write8(address + 1, vcontext, value);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	217 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	218
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	219 static uint16_t word_ram_1M_read16(uint32_t address, void *vcontext)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	220 {
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2137 diff changeset	221 //TODO: check behavior for these on hardware
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	222 return 0;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	223 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	224
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	225 static uint8_t word_ram_1M_read8(uint32_t address, void *vcontext)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	226 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	227 return 0;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	228 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	229
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	230 static void word_ram_1M_write16(uint32_t address, void vcontext, uint16_t value)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	231 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	232 return vcontext;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	233 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	234
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	235 static void word_ram_1M_write8(uint32_t address, void vcontext, uint8_t value)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	236 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	237 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	238 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	239
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	240
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	241 static uint16_t unmapped_prog_read16(uint32_t address, void *vcontext)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	242 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	243 return 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	244 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	245
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	246 static uint8_t unmapped_prog_read8(uint32_t address, void *vcontext)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	247 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	248 return 0xFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	249 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	250
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	251 static void unmapped_prog_write16(uint32_t address, void vcontext, uint16_t value)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	252 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	253 return vcontext;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	254 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	255
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	256 static void unmapped_prog_write8(uint32_t address, void vcontext, uint8_t value)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	257 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	258 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	259 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	260
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	261 static uint16_t unmapped_word_read16(uint32_t address, void *vcontext)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	262 {
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	263 m68k_context *m68k = vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	264 genesis_context *gen = m68k->system;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	265 segacd_context *cd = gen->expansion;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	266 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	267 return cd->word_ram[address + cd->bank_toggle];
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	268 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	269 return 0xFFFF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	270 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	271 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	272
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	273 static uint8_t unmapped_word_read8(uint32_t address, void *vcontext)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	274 {
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	275 m68k_context *m68k = vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	276 genesis_context *gen = m68k->system;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	277 segacd_context *cd = gen->expansion;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	278 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	279 if (address & 1) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	280 return cd->word_ram[(address & ~1) + cd->bank_toggle];
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	281 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	282 return cd->word_ram[address + cd->bank_toggle] >> 8;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	283 }
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	284 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	285 return 0xFF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	286 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	287 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	288
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	289 static void unmapped_word_write16(uint32_t address, void vcontext, uint16_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	290 {
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	291 m68k_context *m68k = vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	292 genesis_context *gen = m68k->system;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	293 segacd_context *cd = gen->expansion;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	294 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	295 cd->word_ram[address + cd->bank_toggle] = value;
2137 3ef9456b76cf Fix a crash regression from word RAM interleave changes Michael Pavone <pavone@retrodev.com> parents: 2136 diff changeset	296 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + address, cd->base + 0x200000 + address + 1);
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	297 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	298 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	299 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	300
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	301 static void unmapped_word_write8(uint32_t address, void vcontext, uint8_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	302 {
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	303 m68k_context *m68k = vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	304 genesis_context *gen = m68k->system;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	305 segacd_context *cd = gen->expansion;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	306 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	307 if (address & 1) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	308 uint32_t offset = (address & ~1) + cd->bank_toggle;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	309 cd->word_ram[offset] &= 0xFF00;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	310 cd->word_ram[offset] \|= value;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	311 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	312 cd->word_ram[address + cd->bank_toggle] &= 0xFF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	313 cd->word_ram[address + cd->bank_toggle] \|= value << 8;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	314 }
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2137 diff changeset	315 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + (address & ~1), cd->base + 0x200000 + (address & ~1) + 1);
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	316 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	317 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	318 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	319
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	320 static uint32_t cell_image_translate_address(uint32_t address)
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	321 {
2087 3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	322 uint32_t word_of_cell = address & 2;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	323 if (address < 0x10000) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	324 //64x32 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	325 uint32_t line_of_column = address & 0x3FC;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	326 uint32_t column = address & 0xFC00;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	327 address = (line_of_column << 6) \| (column >> 8) \| word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	328 } else if (address < 0x18000) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	329 //64x16 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	330 uint32_t line_of_column = address & 0x1FC;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	331 uint32_t column = address & 0x7E00;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	332 address = 0x10000 \| (line_of_column << 6) \| (column >> 7) \| word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	333 } else if (address < 0x1C000) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	334 //64x8 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	335 uint32_t line_of_column = address & 0x00FC;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	336 uint32_t column = address & 0x3F00;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	337 address = 0x18000 \| (line_of_column << 6) \| (column >> 6) \| word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	338 } else {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	339 //64x4 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	340 uint32_t line_of_column = address & 0x007C;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	341 uint32_t column = address & 0x1F80;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	342 address &= 0x1E000;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	343 address \|= (line_of_column << 6) \| (column >> 5) \| word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	344 }
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	345 return address;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	346 }
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	347
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	348 static uint16_t cell_image_read16(uint32_t address, void *vcontext)
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	349 {
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	350 address = cell_image_translate_address(address);
2087 3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	351 m68k_context *m68k = vcontext;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	352 genesis_context *gen = m68k->system;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	353 segacd_context *cd = gen->expansion;
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	354 if (!(cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE)) {
2099 b92c998c6742 Add some missing null checks in the Sega CD code dealing with word RAM switching Michael Pavone <pavone@retrodev.com> parents: 2094 diff changeset	355 return 0xFFFF;
b92c998c6742 Add some missing null checks in the Sega CD code dealing with word RAM switching Michael Pavone <pavone@retrodev.com> parents: 2094 diff changeset	356 }
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	357 return cd->word_ram[address + cd->bank_toggle];
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	358 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	359
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	360 static uint8_t cell_image_read8(uint32_t address, void *vcontext)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	361 {
2087 3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	362 uint16_t word = cell_image_read16(address & 0xFFFFFE, vcontext);
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	363 if (address & 1) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	364 return word;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	365 }
3e0801280bef Implement bitmap to cell mapping feature of 1M mode Michael Pavone <pavone@retrodev.com> parents: 2083 diff changeset	366 return word >> 8;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	367 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	368
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	369 static void cell_image_write16(uint32_t address, void vcontext, uint16_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	370 {
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	371 m68k_context *m68k = vcontext;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	372 genesis_context *gen = m68k->system;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	373 segacd_context *cd = gen->expansion;
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	374 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	375 address = cell_image_translate_address(address);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	376 cd->word_ram[address + cd->bank_toggle] = value;
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2137 diff changeset	377 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + address, cd->base + 0x200000 + address + 1);
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	378 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	379 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	380 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	381
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	382 static void cell_image_write8(uint32_t address, void vcontext, uint8_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	383 {
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	384 uint32_t byte = address & 1;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	385 address = cell_image_translate_address(address);
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	386 m68k_context *m68k = vcontext;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	387 genesis_context *gen = m68k->system;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	388 segacd_context *cd = gen->expansion;
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	389 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	390 if (byte) {
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	391 cd->word_ram[address + cd->bank_toggle] &= 0xFF00;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	392 cd->word_ram[address + cd->bank_toggle] \|= value;
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	393 } else {
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	394 cd->word_ram[address + cd->bank_toggle] &= 0x00FF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	395 cd->word_ram[address + cd->bank_toggle] \|= value << 8;
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	396 }
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2137 diff changeset	397 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + address, cd->base + 0x200000 + address + 1);
2121 76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire Michael Pavone <pavone@retrodev.com> parents: 2120 diff changeset	398 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	399 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	400 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	401
2127 1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	402 static void cdd_run(segacd_context *cd, uint32_t cycle)
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	403 {
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	404 cdd_mcu_run(&cd->cdd, cycle, cd->gate_array + GA_CDD_CTRL, &cd->cdc, &cd->fader);
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	405 lc8951_run(&cd->cdc, cycle);
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	406 }
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	407
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	408 static uint8_t pcm_read8(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	409 {
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	410 m68k_context *m68k = vcontext;
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	411 segacd_context *cd = m68k->system;
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	412 if (address & 1) {
2127 1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	413 //need to run CD drive because there may be a PCM DMA underway
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	414 cdd_run(cd, m68k->cycles);
d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	415 rf5c164_run(&cd->pcm, m68k->cycles);
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	416 return rf5c164_read(&cd->pcm, address >> 1);
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	417 } else {
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	418 return 0xFF;
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	419 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	420 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	421
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	422 static uint16_t pcm_read16(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	423 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	424 return 0xFF00 \| pcm_read8(address+1, vcontext);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	425 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	426
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	427 static void pcm_write8(uint32_t address, void vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	428 {
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	429 m68k_context *m68k = vcontext;
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	430 segacd_context *cd = m68k->system;
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	431 if (address & 1) {
2127 1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1 Michael Pavone <pavone@retrodev.com> parents: 2126 diff changeset	432 //need to run CD drive because there may be a PCM DMA underway
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	433 cdd_run(cd, m68k->cycles);
d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	434 rf5c164_run(&cd->pcm, m68k->cycles);
2128 b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	435 while ((cd->pcm.flags & 0x81) == 1) {
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	436 //not sounding, but pending write
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	437 //DMA write conflict presumably adds wait states
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	438 m68k->cycles += 4;
d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	439 rf5c164_run(&cd->pcm, m68k->cycles);
2128 b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	440 }
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	441 rf5c164_write(&cd->pcm, address >> 1, value);
cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	442 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	443 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	444 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	445
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	446 static void pcm_write16(uint32_t address, void vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	447 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	448 return pcm_write8(address+1, vcontext, value);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	449 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	450
2281 b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	451 static uint16_t cart_area_read16(uint32_t address, void *vcontext)
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	452 {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	453 m68k_context *m68k = vcontext;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	454 genesis_context *gen = m68k->system;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	455 segacd_context *cd = gen->expansion;
2500 d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	456 #ifdef NEW_CORE
d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	457 uint16_t open_bus = m68k->prefetch;
d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	458 #else
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	459 uint16_t open_bus = read_word(m68k->last_prefetch_address, (void **)m68k->mem_pointers, &m68k->opts->gen, m68k);
2500 d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	460 #endif
2281 b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	461 if (cd->bram_cart_id > 7) {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	462 // No cart, just return open bus
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	463 return open_bus;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	464 }
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	465 address &= 0x3FFFFF;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	466 if (address < 0x200000) {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	467 if (address < 0x100000) {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	468 return (open_bus & 0xFF00) \| cd->bram_cart_id;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	469 }
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	470 return open_bus;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	471 } else {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	472 address &= 0x1FFFFF;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	473 uint32_t end = 0x2000 << (1 + cd->bram_cart_id);
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	474 if (address >= end) {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	475 return open_bus;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	476 }
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	477 return (open_bus & 0xFF00) \| cd->bram_cart[address >> 1];
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	478 }
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	479 }
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	480
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	481 static uint8_t cart_area_read8(uint32_t address, void *vcontext)
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	482 {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	483 m68k_context *m68k = vcontext;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	484 genesis_context *gen = m68k->system;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	485 segacd_context *cd = gen->expansion;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	486 if (!(address & 1) \|\| cd->bram_cart_id > 7) {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	487 //open bus
2500 d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	488 #ifdef NEW_CORE
d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	489 return (address & 1) ? m68k->prefetch : m68k->prefetch >> 8;
d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	490 #else
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	491 return read_byte(m68k->last_prefetch_address \| (address & 1), (void **)m68k->mem_pointers, &m68k->opts->gen, m68k);
2500 d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	492 #endif
2281 b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	493 }
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	494 address &= 0x3FFFFF;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	495 if (address < 0x200000) {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	496 if (address < 0x100000) {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	497 return cd->bram_cart_id;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	498 }
2500 d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	499 #ifdef NEW_CORE
d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	500 return m68k->prefetch;
d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	501 #else
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	502 return read_byte(m68k->last_prefetch_address \| 1, (void **)m68k->mem_pointers, &m68k->opts->gen, m68k);
2500 d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	503 #endif
2281 b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	504 } else {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	505 address &= 0x1FFFFF;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	506 uint32_t end = 0x2000 << (1 + cd->bram_cart_id);
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	507 if (address >= end) {
2500 d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	508 #ifdef NEW_CORE
d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	509 return m68k->prefetch;
d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	510 #else
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	511 return read_byte(m68k->last_prefetch_address \| 1, (void **)m68k->mem_pointers, &m68k->opts->gen, m68k);
2500 d44fe974fb85 Get blastem compiling with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2499 diff changeset	512 #endif
2281 b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	513 }
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	514 return cd->bram_cart[address >> 1];
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	515 }
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	516 }
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	517
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	518 static void cart_area_write8(uint32_t address, void vcontext, uint8_t value)
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	519 {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	520 m68k_context *m68k = vcontext;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	521 genesis_context *gen = m68k->system;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	522 segacd_context *cd = gen->expansion;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	523 if (!(address & 1) \|\| cd->bram_cart_id > 7 \|\| address < 0x600000) {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	524 return vcontext;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	525 }
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	526 address &= 0x1FFFFF;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	527 uint32_t end = 0x2000 << (1 + cd->bram_cart_id);
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	528 if (address < end && cd->bram_cart_write_enabled) {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	529 cd->bram_cart[address >> 1] = value;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	530 }
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	531 if (address == 0x1FFFFF \|\| (cd->bram_cart_id < 7 && address > 0x100000)) {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	532 cd->bram_cart_write_enabled = value & 1;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	533 }
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	534 return vcontext;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	535 }
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	536
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	537 static void cart_area_write16(uint32_t address, void vcontext, uint16_t value)
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	538 {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	539 return cart_area_write8(address \| 1, vcontext, value);
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	540 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	541
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	542 static void timers_run(segacd_context *cd, uint32_t cycle)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	543 {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	544 if (cycle <= cd->stopwatch_cycle) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	545 return;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	546 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	547 uint32_t ticks = (cycle - cd->stopwatch_cycle) / TIMER_TICK_CLKS;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	548 cd->stopwatch_cycle += ticks * TIMER_TICK_CLKS;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	549 cd->gate_array[GA_STOP_WATCH] += ticks;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	550 cd->gate_array[GA_STOP_WATCH] &= 0xFFF;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	551 if (ticks && !cd->timer_value) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	552 --ticks;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	553 cd->timer_value = cd->gate_array[GA_TIMER];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	554 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	555 if (ticks && cd->timer_value) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	556 while (ticks >= (cd->timer_value + 1)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	557 ticks -= cd->timer_value + 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	558 cd->timer_value = cd->gate_array[GA_TIMER];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	559 cd->timer_pending = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	560 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	561 cd->timer_value -= ticks;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	562 if (!cd->timer_value) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	563 cd->timer_pending = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	564 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	565 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	566 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	567
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	568 static uint32_t next_timer_int(segacd_context *cd)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	569 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	570 if (cd->timer_pending) {
2674 07cc0f7109f0 Fix an issue in which CD timer interrupts could get missed, at least with the new interpreter Michael Pavone <pavone@retrodev.com> parents: 2669 diff changeset	571 return cd->m68k->cycles;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	572 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	573 if (cd->timer_value) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	574 return cd->stopwatch_cycle + TIMER_TICK_CLKS * cd->timer_value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	575 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	576 if (cd->gate_array[GA_TIMER]) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	577 return cd->stopwatch_cycle + TIMER_TICK_CLKS * (cd->gate_array[GA_TIMER] + 1);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	578 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	579 return CYCLE_NEVER;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	580 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	581
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	582 static void calculate_target_cycle(m68k_context * context)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	583 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	584 segacd_context *cd = context->system;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	585 context->int_cycle = CYCLE_NEVER;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	586 uint8_t mask = context->status & 0x7;
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	587 uint32_t cdc_cycle = CYCLE_NEVER;
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	588 if (mask < 6) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	589 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN6) {
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	590 uint32_t subcode_cycle = cd->cdd.subcode_int_pending ? context->cycles : cd->cdd.next_subcode_int_cycle;
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	591 if (subcode_cycle != CYCLE_NEVER) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	592 context->int_cycle = subcode_cycle;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	593 context->int_num = 6;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	594 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	595 }
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	596 if (mask < 5) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	597 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN5) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	598 cdc_cycle = lc8951_next_interrupt(&cd->cdc);
2669 c6bc66b16392 Less broken Sega CD emulation with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2519 diff changeset	599 #ifdef NEW_CORE
c6bc66b16392 Less broken Sega CD emulation with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2519 diff changeset	600 //should this maybe happen with the old core too?
c6bc66b16392 Less broken Sega CD emulation with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2519 diff changeset	601 if (cdc_cycle == cd->cdc.cycle) {
c6bc66b16392 Less broken Sega CD emulation with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2519 diff changeset	602 cdc_cycle = context->cycles;
c6bc66b16392 Less broken Sega CD emulation with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2519 diff changeset	603 }
c6bc66b16392 Less broken Sega CD emulation with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2519 diff changeset	604 #endif
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	605 //CDC interrupts only generated on falling edge of !INT signal
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	606 if (cd->cdc_int_ack) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	607 if (cdc_cycle > cd->cdc.cycle) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	608 cd->cdc_int_ack = 0;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	609 } else {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	610 cdc_cycle = CYCLE_NEVER;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	611 }
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	612 }
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	613 if (cdc_cycle < context->int_cycle) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	614 context->int_cycle = cdc_cycle;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	615 context->int_num = 5;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	616 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	617 }
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	618 if (mask < 4) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	619 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN4) {
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	620 uint32_t cdd_cycle = cd->cdd.int_pending ? context->cycles : cd->cdd.next_int_cycle;
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	621 if (cdd_cycle < context->int_cycle) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	622 context->int_cycle = cdd_cycle;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	623 context->int_num = 4;
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	624 }
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	625 }
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	626 if (mask < 3) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	627 uint32_t next_timer;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	628 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN3) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	629 uint32_t next_timer_cycle = next_timer_int(cd);
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	630 if (next_timer_cycle < context->int_cycle) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	631 context->int_cycle = next_timer_cycle;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	632 context->int_num = 3;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	633 }
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	634 }
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	635 if (mask < 2) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	636 if (cd->int2_cycle < context->int_cycle && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2)) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	637 context->int_cycle = cd->int2_cycle;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	638 context->int_num = 2;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	639 }
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	640 if (mask < 1) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	641 if (cd->graphics_int_cycle < context->int_cycle && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN1)) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	642 context->int_cycle = cd->graphics_int_cycle;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	643 context->int_num = 1;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	644 }
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	645 }
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	646 }
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	647 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	648 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	649 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	650 }
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	651 if (context->int_cycle > context->cycles && context->int_pending == INT_PENDING_SR_CHANGE) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	652 context->int_pending = INT_PENDING_NONE;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	653 }
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	654 if (context->cycles >= context->sync_cycle) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	655 context->should_return = 1;
2669 c6bc66b16392 Less broken Sega CD emulation with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2519 diff changeset	656 context->target_cycle = context->cycles + 1;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	657 return;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	658 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	659 if (context->status & M68K_STATUS_TRACE \|\| context->trace_pending) {
2669 c6bc66b16392 Less broken Sega CD emulation with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2519 diff changeset	660 context->target_cycle = context->cycles + 1;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	661 return;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	662 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	663 context->target_cycle = context->sync_cycle < context->int_cycle ? context->sync_cycle : context->int_cycle;
2136 01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test Michael Pavone <pavone@retrodev.com> parents: 2135 diff changeset	664 if (context->int_cycle == cdc_cycle && context->int_num == 5) {
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	665 uint32_t before = cdc_cycle - cd->m68k->opts->gen.clock_divider * 158; //divs worst case
2136 01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test Michael Pavone <pavone@retrodev.com> parents: 2135 diff changeset	666 if (before < context->target_cycle) {
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	667 while (before <= context->cycles) {
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	668 before += cd->cdc.clock_step;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	669 }
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	670 if (before < context->target_cycle) {
2131 d90d92ce5cab Improve CDC decode timing accuracy Michael Pavone <pavone@retrodev.com> parents: 2129 diff changeset	671 context->target_cycle = context->sync_cycle = before;
d90d92ce5cab Improve CDC decode timing accuracy Michael Pavone <pavone@retrodev.com> parents: 2129 diff changeset	672 }
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	673 }
ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	674 }
2669 c6bc66b16392 Less broken Sega CD emulation with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2519 diff changeset	675 if (context->target_cycle <= context->cycles) {
c6bc66b16392 Less broken Sega CD emulation with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2519 diff changeset	676 context->target_cycle = context->cycles + 1;
c6bc66b16392 Less broken Sega CD emulation with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2519 diff changeset	677 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	678 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	679
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	680 static uint16_t sub_gate_read16(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	681 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	682 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	683 segacd_context *cd = m68k->system;
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	684 uint32_t before_cycle = m68k->cycles - m68k->opts->gen.clock_divider * 4;
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	685 if (before_cycle >= cd->last_refresh_cycle) {
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	686 uint32_t num_refresh = (before_cycle - cd->last_refresh_cycle) / REFRESH_INTERVAL;
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	687 uint32_t num_full = (m68k->cycles - cd->last_refresh_cycle) / REFRESH_INTERVAL;
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	688 cd->last_refresh_cycle = cd->last_refresh_cycle + num_full * REFRESH_INTERVAL;
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	689 m68k->cycles += num_refresh * REFRESH_DELAY;
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	690 }
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	691
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	692
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	693 uint32_t reg = address >> 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	694 switch (reg)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	695 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	696 case GA_SUB_CPU_CTRL: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	697 uint16_t value = cd->gate_array[reg] & 0xFFFE;
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	698 if (cd->periph_reset_cycle == CYCLE_NEVER \|\| (m68k->cycles - cd->periph_reset_cycle) > SCD_PERIPH_RESET_CLKS) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	699 value \|= BIT_PRES;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	700 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	701 return value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	702 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	703 case GA_MEM_MODE:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	704 return cd->gate_array[reg] & 0xFF1F;
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	705 case GA_CDC_CTRL:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	706 cdd_run(cd, m68k->cycles);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	707 return cd->gate_array[reg] \| cd->cdc.ar;
70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	708 case GA_CDC_REG_DATA:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	709 cdd_run(cd, m68k->cycles);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	710 return lc8951_reg_read(&cd->cdc);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	711 case GA_CDC_HOST_DATA: {
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	712 cdd_run(cd, m68k->cycles);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	713 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	714 if (dst == DST_SUB_CPU) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	715 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	716 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	717 lc8951_resume_transfer(&cd->cdc);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	718 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	719 calculate_target_cycle(cd->m68k);
2068 f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	720
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	721 }
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	722 return cd->gate_array[reg];
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	723 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	724 case GA_STOP_WATCH:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	725 case GA_TIMER:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	726 timers_run(cd, m68k->cycles);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	727 return cd->gate_array[reg];
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	728 case GA_CDD_STATUS0:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	729 case GA_CDD_STATUS1:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	730 case GA_CDD_STATUS2:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	731 case GA_CDD_STATUS3:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	732 case GA_CDD_STATUS4:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	733 cdd_run(cd, m68k->cycles);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	734 return cd->gate_array[reg];
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	735 break;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	736 case GA_FONT_DATA0:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	737 case GA_FONT_DATA1:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	738 case GA_FONT_DATA2:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	739 case GA_FONT_DATA3: {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	740 uint16_t shift = 4 * (3 - (reg - GA_FONT_DATA0));
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	741 uint16_t value = 0;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	742 uint16_t fg = cd->gate_array[GA_FONT_COLOR] >> 4;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	743 uint16_t bg = cd->gate_array[GA_FONT_COLOR] & 0xF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	744 for (int i = 0; i < 4; i++) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	745 uint16_t pixel = 0;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	746 if (cd->gate_array[GA_FONT_BITS] & 1 << (shift + i)) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	747 pixel = fg;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	748 } else {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	749 pixel = bg;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	750 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	751 value \|= pixel << (i * 4);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	752 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	753 return value;
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	754 }
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	755 case GA_STAMP_SIZE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	756 case GA_IMAGE_BUFFER_LINES:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	757 //these two have bits that change based on graphics operations
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	758 cd_graphics_run(cd, m68k->cycles);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	759 return cd->gate_array[reg];
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	760 case GA_TRACE_VECTOR_BASE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	761 //write only
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	762 return 0xFFFF;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	763 default:
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	764 if (reg >= GA_SUBCODE_MIRROR) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	765 return cd->gate_array[GA_SUBCODE_START + (reg & 0x3F)];
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	766 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	767 return cd->gate_array[reg];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	768 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	769 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	770
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	771 static uint8_t sub_gate_read8(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	772 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	773 uint16_t val = sub_gate_read16(address, vcontext);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	774 return address & 1 ? val : val >> 8;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	775 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	776
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	777 static void sub_gate_write16(uint32_t address, void vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	778 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	779 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	780 segacd_context *cd = m68k->system;
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	781 uint32_t before_cycle = m68k->cycles - m68k->opts->gen.clock_divider * 4;
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	782 if (before_cycle >= cd->last_refresh_cycle) {
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	783 uint32_t num_refresh = (before_cycle - cd->last_refresh_cycle) / REFRESH_INTERVAL;
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	784 uint32_t num_full = (m68k->cycles - cd->last_refresh_cycle) / REFRESH_INTERVAL;
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	785 cd->last_refresh_cycle = cd->last_refresh_cycle + num_full * REFRESH_INTERVAL;
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	786 m68k->cycles += num_refresh * REFRESH_DELAY;
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	787 }
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	788
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	789 uint32_t reg = address >> 1;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	790 switch (reg)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	791 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	792 case GA_SUB_CPU_CTRL:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	793 cd->gate_array[reg] &= 0xF0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	794 cd->gate_array[reg] \|= value & (BIT_LEDG\|BIT_LEDR);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	795 if (value & BIT_PRES) {
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	796 cd->periph_reset_cycle = m68k->cycles;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	797 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	798 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	799 case GA_MEM_MODE: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	800 uint16_t changed = value ^ cd->gate_array[reg];
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	801 uint8_t old_main_has_word2m = cd->main_has_word2m;
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	802 if (value & BIT_RET) {
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	803 cd->main_has_word2m = 1;
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	804 }
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	805 uint8_t old_bank_toggle = cd->bank_toggle;
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	806 cd->bank_toggle = value & BIT_RET;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	807 genesis_context *gen = cd->genesis;
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	808 cd->gate_array[reg] &= 0xFFC0;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	809 if (changed & BIT_MEM_MODE) {
2120 91ed3c4cdfd9 Fix the regression in Stellar Fire while still passing RET/DMNA tests Michael Pavone <pavone@retrodev.com> parents: 2119 diff changeset	810 cd->main_swap_request = cd->bank_toggle && !old_bank_toggle;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	811 if (value & BIT_MEM_MODE) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	812 //switch to 1M mode
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	813 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL; //(value & BIT_RET) ? cd->word_ram + 0x10000 : cd->word_ram;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	814 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	815 m68k->mem_pointers[0] = NULL;
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	816 m68k->mem_pointers[1] = cd->bank_toggle ? cd->word_ram : cd->word_ram + 1;
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	817 cd->gate_array[reg] \|= value & (MASK_PRIORITY\|BIT_RET\|BIT_MEM_MODE);
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	818 if (cd->main_swap_request) {
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	819 cd->gate_array[reg] \|= BIT_DMNA;
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	820 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	821 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	822 //switch to 2M mode
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	823 if (cd->main_has_word2m) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	824 //Main CPU will have word ram
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	825 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	826 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	827 m68k->mem_pointers[0] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	828 m68k->mem_pointers[1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	829 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	830 //sub cpu will have word ram
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	831 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	832 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	833 m68k->mem_pointers[0] = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	834 m68k->mem_pointers[1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	835 }
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	836 cd->gate_array[reg] \|= value & (MASK_PRIORITY\|BIT_MEM_MODE);
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	837 cd->gate_array[reg] \|= cd->main_has_word2m ? BIT_RET : BIT_DMNA;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	838 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	839 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	840 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000);
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	841 } else if (value & BIT_MEM_MODE) {
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	842 //1M mode
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	843 if (old_bank_toggle != cd->bank_toggle) {
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	844 m68k->mem_pointers[1] = (value & BIT_RET) ? cd->word_ram : cd->word_ram + 1;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	845 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	846 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000);
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	847 cd->main_swap_request = 0;
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	848 }
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	849 cd->gate_array[reg] \|= value & (MASK_PRIORITY\|BIT_RET\|BIT_MEM_MODE);
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	850 if (cd->main_swap_request) {
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	851 cd->gate_array[reg] \|= BIT_DMNA;
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	852 }
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	853 } else {
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	854 //2M mode
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	855 if (old_main_has_word2m != cd->main_has_word2m) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	856 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	857 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	858 m68k->mem_pointers[0] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	859 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	860 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	861 }
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	862 cd->gate_array[reg] \|= value & MASK_PRIORITY;
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	863 cd->gate_array[reg] \|= cd->main_has_word2m ? BIT_RET : BIT_DMNA;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	864 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	865 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	866 }
2144 10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	867 case GA_CDC_CTRL: {
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	868 cdd_run(cd, m68k->cycles);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	869 lc8951_ar_write(&cd->cdc, value);
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	870 //cd->gate_array[reg] &= 0xC000;
2144 10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	871 uint16_t old_dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
2515 0775f5e0c468 Clear EDT on DTTRG. Fixes Cliffhanger and OrionNavattan's Mode 1 demo Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	872 //clears both EDT and DSR
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	873 cd->gate_array[reg] = value & 0x0700;
2144 10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	874 uint16_t dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	875 if (dest != old_dest) {
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	876 if (dest == DST_PCM_RAM) {
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	877 lc8951_set_dma_multiple(&cd->cdc, 21);
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	878 } else {
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	879 lc8951_set_dma_multiple(&cd->cdc, 6);
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	880 }
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	881 if ((old_dest < DST_MAIN_CPU \|\| old_dest == 6) && dest >= DST_MAIN_CPU && dest != 6) {
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	882 lc8951_resume_transfer(&cd->cdc);
2144 10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	883 }
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	884 calculate_target_cycle(m68k);
10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	885 }
2135 95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	886 cd->gate_array[GA_CDC_DMA_ADDR] = 0;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	887 cd->cdc_dst_low = 0;
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	888 break;
2144 10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	889 }
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	890 case GA_CDC_REG_DATA:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	891 cdd_run(cd, m68k->cycles);
d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	892 printf("CDC write %X: %X @ %u\n", cd->cdc.ar, value, m68k->cycles);
2426 cde4ea2b4929 Clear DSR in certain gate array writes. Fixes issue in Penn & Teller's Smoke and Mirrors Michael Pavone <pavone@retrodev.com> parents: 2384 diff changeset	893 if (cd->cdc.ar == 6) {
2515 0775f5e0c468 Clear EDT on DTTRG. Fixes Cliffhanger and OrionNavattan's Mode 1 demo Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	894 //this next bit needs hardware confirmation
2426 cde4ea2b4929 Clear DSR in certain gate array writes. Fixes issue in Penn & Teller's Smoke and Mirrors Michael Pavone <pavone@retrodev.com> parents: 2384 diff changeset	895 cd->cdc_dst_low = 0;
2515 0775f5e0c468 Clear EDT on DTTRG. Fixes Cliffhanger and OrionNavattan's Mode 1 demo Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	896 }
0775f5e0c468 Clear EDT on DTTRG. Fixes Cliffhanger and OrionNavattan's Mode 1 demo Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	897 lc8951_reg_write(&cd->cdc, value);
0775f5e0c468 Clear EDT on DTTRG. Fixes Cliffhanger and OrionNavattan's Mode 1 demo Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	898 if (!lc8951_dtbsy_state(&cd->cdc)) {
0775f5e0c468 Clear EDT on DTTRG. Fixes Cliffhanger and OrionNavattan's Mode 1 demo Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	899 //new transfer has started, this clears EDT
0775f5e0c468 Clear EDT on DTTRG. Fixes Cliffhanger and OrionNavattan's Mode 1 demo Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	900 cd->gate_array[GA_CDC_CTRL] &= ~BIT_EDT;
0775f5e0c468 Clear EDT on DTTRG. Fixes Cliffhanger and OrionNavattan's Mode 1 demo Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	901 //DSR does not seem to be cleared on hardware
0775f5e0c468 Clear EDT on DTTRG. Fixes Cliffhanger and OrionNavattan's Mode 1 demo Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	902 //but doing this seems to fix Penn & Teller's Smoke and Mirrors
0775f5e0c468 Clear EDT on DTTRG. Fixes Cliffhanger and OrionNavattan's Mode 1 demo Michael Pavone <pavone@retrodev.com> parents: 2500 diff changeset	903 //needs more research
2426 cde4ea2b4929 Clear DSR in certain gate array writes. Fixes issue in Penn & Teller's Smoke and Mirrors Michael Pavone <pavone@retrodev.com> parents: 2384 diff changeset	904 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
cde4ea2b4929 Clear DSR in certain gate array writes. Fixes issue in Penn & Teller's Smoke and Mirrors Michael Pavone <pavone@retrodev.com> parents: 2384 diff changeset	905 }
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	906 calculate_target_cycle(m68k);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	907 break;
2135 95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	908 case GA_CDC_HOST_DATA:
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	909 //writes to this register have the same side effects as reads
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	910 sub_gate_read16(address, vcontext);
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	911 break;
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	912 case GA_CDC_DMA_ADDR:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	913 cdd_run(cd, m68k->cycles);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	914 cd->gate_array[reg] = value;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	915 cd->cdc_dst_low = 0;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	916 break;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	917 case GA_STOP_WATCH:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	918 //docs say you should only write zero to reset
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	919 //mcd-verificator comments suggest any value will reset
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	920 timers_run(cd, m68k->cycles);
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	921 cd->gate_array[reg] = 0;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	922 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	923 case GA_COMM_FLAG:
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	924 cd->gate_array[reg] &= 0xFF00;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	925 cd->gate_array[reg] \|= value & 0xFF;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	926 break;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	927 case GA_COMM_STATUS0:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	928 case GA_COMM_STATUS1:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	929 case GA_COMM_STATUS2:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	930 case GA_COMM_STATUS3:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	931 case GA_COMM_STATUS4:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	932 case GA_COMM_STATUS5:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	933 case GA_COMM_STATUS6:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	934 case GA_COMM_STATUS7:
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	935 //no effects for these other than saving the value
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	936 cd->gate_array[reg] = value;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	937 break;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	938 case GA_TIMER:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	939 timers_run(cd, m68k->cycles);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	940 cd->gate_array[reg] = value & 0xFF;
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	941 cd->timer_value = 0;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	942 calculate_target_cycle(m68k);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	943 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	944 case GA_INT_MASK:
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	945 if (!(cd->gate_array[reg] & BIT_MASK_IEN6)) {
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	946 //subcode interrupts can't be made pending when they are disabled in this reg
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	947 cd->cdd.subcode_int_pending = 0;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	948 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	949 cd->gate_array[reg] = value & (BIT_MASK_IEN6\|BIT_MASK_IEN5\|BIT_MASK_IEN4\|BIT_MASK_IEN3\|BIT_MASK_IEN2\|BIT_MASK_IEN1);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	950 calculate_target_cycle(m68k);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	951 break;
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	952 case GA_CDD_FADER:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	953 cdd_run(cd, m68k->cycles);
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	954 value &= 0x7FFF;
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	955 cdd_fader_attenuation_write(&cd->fader, value);
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	956 cd->gate_array[reg] &= 0x8000;
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	957 cd->gate_array[reg] \|= value;
bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	958 break;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	959 case GA_CDD_CTRL: {
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	960 cdd_run(cd, m68k->cycles);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	961 uint16_t changed = cd->gate_array[reg] ^ value;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	962 if (changed & BIT_HOCK) {
2073 c69e42444f96 Fix some cycle adjustment stuff and an off-by one on hte TOCT response Michael Pavone <pavone@retrodev.com> parents: 2069 diff changeset	963 cd->gate_array[reg] &= ~BIT_HOCK;
c69e42444f96 Fix some cycle adjustment stuff and an off-by one on hte TOCT response Michael Pavone <pavone@retrodev.com> parents: 2069 diff changeset	964 cd->gate_array[reg] \|= value & BIT_HOCK;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	965 if (value & BIT_HOCK) {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	966 cdd_hock_enabled(&cd->cdd);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	967 } else {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	968 cdd_hock_disabled(&cd->cdd);
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	969 cd->gate_array[reg] \|= BIT_MUTE;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	970 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	971 calculate_target_cycle(m68k);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	972 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	973 break;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	974 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	975 case GA_CDD_CMD0:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	976 case GA_CDD_CMD1:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	977 case GA_CDD_CMD2:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	978 case GA_CDD_CMD3:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	979 cdd_run(cd, m68k->cycles);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	980 cd->gate_array[reg] = value & 0x0F0F;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	981 break;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	982 case GA_CDD_CMD4:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	983 cdd_run(cd, m68k->cycles);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	984 cd->gate_array[reg] = value & 0x0F0F;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	985 cdd_mcu_start_cmd_recv(&cd->cdd, cd->gate_array + GA_CDD_CTRL);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	986 break;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	987 case GA_FONT_COLOR:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	988 cd->gate_array[reg] = value & 0xFF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	989 break;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	990 case GA_FONT_BITS:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	991 cd->gate_array[reg] = value;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	992 break;
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	993 case GA_STAMP_SIZE:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	994 cd_graphics_run(cd, m68k->cycles);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	995 cd->gate_array[reg] &= BIT_GRON;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	996 cd->gate_array[reg] \|= value & (BIT_SMS\|BIT_STS\|BIT_RPT);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	997 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	998 case GA_STAMP_MAP_BASE:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	999 cd_graphics_run(cd, m68k->cycles);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1000 cd->gate_array[reg] = value & 0xFFE0;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1001 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1002 case GA_IMAGE_BUFFER_VCELLS:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1003 cd_graphics_run(cd, m68k->cycles);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1004 cd->gate_array[reg] = value & 0x1F;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1005 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1006 case GA_IMAGE_BUFFER_START:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1007 cd_graphics_run(cd, m68k->cycles);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1008 cd->gate_array[reg] = value & 0xFFF8;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1009 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1010 case GA_IMAGE_BUFFER_OFFSET:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1011 cd_graphics_run(cd, m68k->cycles);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1012 cd->gate_array[reg] = value & 0x3F;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1013 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1014 case GA_IMAGE_BUFFER_HDOTS:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1015 cd_graphics_run(cd, m68k->cycles);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1016 cd->gate_array[reg] = value & 0x1FF;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1017 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1018 case GA_IMAGE_BUFFER_LINES:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1019 cd_graphics_run(cd, m68k->cycles);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1020 cd->gate_array[reg] = value & 0xFF;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1021 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1022 case GA_TRACE_VECTOR_BASE:
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1023 cd_graphics_run(cd, m68k->cycles);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1024 cd->gate_array[reg] = value & 0xFFFE;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1025 cd_graphics_start(cd);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1026 break;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1027 default:
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1028 printf("Unhandled gate array write %X:%X\n", address, value);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1029 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1030 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1031 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1032
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1033 static void sub_gate_write8(uint32_t address, void vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1034 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1035 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1036 segacd_context *cd = m68k->system;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1037 uint32_t reg = (address & 0x1FF) >> 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1038 uint16_t value16;
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1039 switch (address >> 1)
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1040 {
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	1041 case GA_MEM_MODE:
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1042 case GA_CDC_HOST_DATA:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1043 case GA_CDC_DMA_ADDR:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1044 case GA_STOP_WATCH:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1045 case GA_COMM_FLAG:
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1046 case GA_TIMER:
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1047 case GA_CDD_FADER:
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1048 case GA_FONT_COLOR:
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1049 //these registers treat all writes as word-wide
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1050 value16 = value \| (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1051 break;
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	1052 case GA_CDC_CTRL:
70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	1053 if (address & 1) {
70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	1054 lc8951_ar_write(&cd->cdc, value);
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1055 return vcontext;
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	1056 } else {
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1057 value16 = cd->cdc.ar \| (value << 8);
2058 70260f6051dd Initial work on CDC emulation Michael Pavone <pavone@retrodev.com> parents: 2057 diff changeset	1058 }
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1059 break;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1060 case GA_CDD_CMD4:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1061 if (!address) {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1062 //byte write to $FF804A should not trigger transfer
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1063 cdd_run(cd, m68k->cycles);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1064 cd->gate_array[reg] &= 0x0F;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1065 cd->gate_array[reg] \|= (value << 8 & 0x0F00);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1066 return vcontext;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1067 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1068 //intentional fallthrough for $FF804B
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1069 default:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1070 if (address & 1) {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1071 value16 = cd->gate_array[reg] & 0xFF00 \| value;
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1072 } else {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1073 value16 = cd->gate_array[reg] & 0xFF \| (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1074 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1075 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1076 return sub_gate_write16(address, vcontext, value16);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1077 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1078
2135 95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1079 static uint8_t can_main_access_prog(segacd_context *cd)
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1080 {
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1081 //TODO: use actual busack
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1082 return cd->busreq \|\| !cd->reset;
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1083 }
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1084
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1085 static uint8_t handle_cdc_byte(void *vsys, uint8_t value)
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1086 {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1087 segacd_context *cd = vsys;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1088 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1089 //host reg is already full, pause transfer
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1090 return 0;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1091 }
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1092 if (cd->cdc.cycle == cd->cdc.transfer_end) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1093 cd->gate_array[GA_CDC_CTRL] \|= BIT_EDT;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1094 printf("EDT set at %u\n", cd->cdc.cycle);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1095 }
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1096 uint16_t dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1097 if (!(cd->cdc_dst_low & 1)) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1098 cd->gate_array[GA_CDC_HOST_DATA] &= 0xFF;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1099 cd->gate_array[GA_CDC_HOST_DATA] \|= value << 8;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1100 cd->cdc_dst_low++;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1101 if (dest != DST_PCM_RAM) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1102 //PCM RAM writes a byte at a time
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1103 return 1;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1104 }
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1105 } else {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1106 cd->gate_array[GA_CDC_HOST_DATA] &= 0xFF00;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1107 cd->gate_array[GA_CDC_HOST_DATA] \|= value;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1108 }
2068 f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1109
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1110 uint32_t dma_addr = cd->gate_array[GA_CDC_DMA_ADDR] << 3;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1111 dma_addr \|= cd->cdc_dst_low;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1112 switch (dest)
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1113 {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1114 case DST_MAIN_CPU:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1115 case DST_SUB_CPU:
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1116 cd->cdc_dst_low = 0;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1117 cd->gate_array[GA_CDC_CTRL] \|= BIT_DSR;
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1118 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1119 case DST_PCM_RAM:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1120 dma_addr &= (1 << 13) - 1;
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	1121 rf5c164_run(&cd->pcm, cd->cdc.cycle);
2128 b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	1122 while ((cd->pcm.flags & 0x81) == 1) {
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	1123 //not sounding, but pending write
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	1124 //DMA write conflict with CPU
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	1125 rf5c164_run(&cd->pcm, cd->pcm.cycle + 4);
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts Michael Pavone <pavone@retrodev.com> parents: 2127 diff changeset	1126 }
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	1127 rf5c164_write(&cd->pcm, 0x1000 \| (dma_addr >> 1), value);
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1128 dma_addr += 2;
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1129 cd->cdc_dst_low = dma_addr & 7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1130 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3;
2148 2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1131 //TODO: determine actual main CPU penalty
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1132 cd->m68k->cycles += 2 * cd->m68k->opts->gen.bus_cycles;
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1133 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1134 case DST_PROG_RAM:
2135 95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1135 if (can_main_access_prog(cd)) {
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1136 return 0;
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1137 }
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1138 cd->prog_ram[dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA];
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1139 m68k_invalidate_code_range(cd->m68k, dma_addr - 1, dma_addr + 1);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1140 dma_addr++;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1141 cd->cdc_dst_low = dma_addr & 7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1142 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3;
2148 2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1143 //TODO: determine actual main CPU penalty
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1144 cd->m68k->cycles += 2 * cd->m68k->opts->gen.bus_cycles;
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1145 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1146 case DST_WORD_RAM:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1147 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1148 //1M mode, write to bank assigned to Sub CPU
2135 95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1149
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1150 uint32_t masked = dma_addr & (1 << 17) - 2;
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1151 cd->m68k->mem_pointers[1][masked] = cd->gate_array[GA_CDC_HOST_DATA];
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1152 m68k_invalidate_code_range(cd->m68k, 0x0C0000 + masked - 1, 0x0C0000 + masked + 1);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1153 } else {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1154 //2M mode, check if Sub CPU has access
2129 4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU Michael Pavone <pavone@retrodev.com> parents: 2128 diff changeset	1155 if (cd->main_has_word2m) {
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU Michael Pavone <pavone@retrodev.com> parents: 2128 diff changeset	1156 return 0;
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU Michael Pavone <pavone@retrodev.com> parents: 2128 diff changeset	1157 } else {
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	1158 cd_graphics_run(cd, cd->cdc.cycle);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1159 dma_addr &= (1 << 18) - 1;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1160 cd->word_ram[dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA];
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1161 m68k_invalidate_code_range(cd->m68k, 0x080000 + dma_addr, 0x080000 + dma_addr + 1);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1162 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1163 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1164 dma_addr++;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1165 cd->cdc_dst_low = dma_addr & 7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1166 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1167 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1168 default:
2144 10e4439d8f13 Fix speed of CDC to PCM RAM DMA Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	1169 return 0;
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1170 printf("Invalid CDC transfer destination %d\n", dest);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1171 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1172 return 1;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1173 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1174
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1175 static void scd_peripherals_run(segacd_context *cd, uint32_t cycle)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1176 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1177 timers_run(cd, cycle);
2062 07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2061 diff changeset	1178 cdd_run(cd, cycle);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1179 cd_graphics_run(cd, cycle);
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	1180 rf5c164_run(&cd->pcm, cycle);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1181 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1182
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1183 static m68k_context sync_components(m68k_context context, uint32_t address)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1184 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1185 segacd_context *cd = context->system;
2148 2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1186
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1187 uint32_t num_refresh = (context->cycles - cd->last_refresh_cycle) / REFRESH_INTERVAL;
2148 2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1188 cd->last_refresh_cycle = cd->last_refresh_cycle + num_refresh * REFRESH_INTERVAL;
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1189 context->cycles += num_refresh * REFRESH_DELAY;
2148 2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1190
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1191 scd_peripherals_run(cd, context->cycles);
2280 9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1192 if (address) {
2519 0fae9d6a77c4 Fix sub cpu watchpoints Michael Pavone <pavone@retrodev.com> parents: 2515 diff changeset	1193 if (cd->enter_debugger \|\| context->wp_hit) {
2280 9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1194 genesis_context *gen = cd->genesis;
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1195 cd->enter_debugger = 0;
2302 0343f0d5add0 Fix libretro build for real Michael Pavone <pavone@retrodev.com> parents: 2282 diff changeset	1196 #ifndef IS_LIB
2280 9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1197 if (gen->header.debugger_type == DEBUGGER_NATIVE) {
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1198 debugger(context, address);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1199 } else {
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1200 gdb_debug_enter(context, address);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1201 }
2302 0343f0d5add0 Fix libretro build for real Michael Pavone <pavone@retrodev.com> parents: 2282 diff changeset	1202 #endif
2104 ff32a90260c9 Initial support for using debugger on sub CPU Michael Pavone <pavone@retrodev.com> parents: 2099 diff changeset	1203 }
2280 9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1204 cd->m68k_pc = address;
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	1205 }
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1206 calculate_target_cycle(context);
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1207 return context;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1208 }
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1209
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1210 static m68k_context int_ack(m68k_context context)
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1211 {
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1212 segacd_context *cd = context->system;
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1213 scd_peripherals_run(cd, context->cycles);
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1214 switch (context->int_pending)
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1215 {
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1216 case 1:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1217 cd->graphics_int_cycle = CYCLE_NEVER;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1218 break;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1219 case 2:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1220 cd->int2_cycle = CYCLE_NEVER;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1221 break;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1222 case 3:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1223 cd->timer_pending = 0;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1224 break;
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1225 case 4:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1226 cd->cdd.int_pending = 0;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1227 break;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1228 case 5:
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1229 cd->cdc_int_ack = 1;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1230 break;
2116 cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	1231 case 6:
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	1232 cd->cdd.subcode_int_pending = 0;
cd057d6fe030 Initial stab at subcode emulation Michael Pavone <pavone@retrodev.com> parents: 2111 diff changeset	1233 break;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1234 }
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1235 //the Sega CD responds to these exclusively with !VPA which means its a slow
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1236 //6800 operation. documentation says these can take between 10 and 19 cycles.
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1237 //actual results measurements seem to suggest it's actually between 9 and 18
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1238 //Base 68K core has added 4 cycles for a normal int ack cycle already
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1239 //We add 5 + the current cycle count (in 68K cycles) mod 10 to simulate the
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1240 //additional variable delay from the use of the 6800 cycle
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1241 uint32_t cycle_count = context->cycles / context->opts->gen.clock_divider;
d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1242 context->cycles += 5 + (cycle_count % 10);
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1243
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1244 return context;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1245 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1246
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1247 void scd_run(segacd_context *cd, uint32_t cycle)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1248 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1249 uint8_t m68k_run = !can_main_access_prog(cd);
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1250 while (cycle > cd->m68k->cycles) {
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	1251 if (m68k_run && !cd->sub_paused_wordram) {
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1252 uint32_t num_refresh = (cd->m68k->cycles - cd->last_refresh_cycle) / REFRESH_INTERVAL;
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1253 cd->last_refresh_cycle = cd->last_refresh_cycle + num_refresh * REFRESH_INTERVAL;
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1254 cd->m68k->cycles += num_refresh * REFRESH_DELAY;
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1255
2148 2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1256
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1257 cd->m68k->sync_cycle = cd->enter_debugger ? cd->m68k->cycles + 1 : cycle;
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1258 if (cd->need_reset) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1259 cd->need_reset = 0;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1260 m68k_reset(cd->m68k);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1261 } else {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1262 calculate_target_cycle(cd->m68k);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1263 resume_68k(cd->m68k);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1264 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1265 } else {
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1266 cd->m68k->cycles = cycle;
2148 2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1267 cd->last_refresh_cycle = cycle;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1268 }
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1269 scd_peripherals_run(cd, cd->m68k->cycles);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1270 }
2094 ca6fc8c8dc60 Pass some more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2087 diff changeset	1271
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1272 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1273
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1274 uint32_t gen_cycle_to_scd(uint32_t cycle, genesis_context *gen)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1275 {
2055 c4d066d798c4 Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works Michael Pavone <pavone@retrodev.com> parents: 2054 diff changeset	1276 return ((uint64_t)cycle) * ((uint64_t)SCD_MCLKS) / ((uint64_t)gen->normal_clock);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1277 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1278
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1279 void scd_adjust_cycle(segacd_context *cd, uint32_t deduction)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1280 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1281 deduction = gen_cycle_to_scd(deduction, cd->genesis);
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1282 cd->m68k->cycles -= deduction;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1283 cd->stopwatch_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1284 if (deduction >= cd->int2_cycle) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1285 cd->int2_cycle = 0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1286 } else if (cd->int2_cycle != CYCLE_NEVER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1287 cd->int2_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1288 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1289 if (deduction >= cd->periph_reset_cycle) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1290 cd->periph_reset_cycle = CYCLE_NEVER;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1291 } else if (cd->periph_reset_cycle != CYCLE_NEVER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1292 cd->periph_reset_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1293 }
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1294 cdd_mcu_adjust_cycle(&cd->cdd, deduction);
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1295 lc8951_adjust_cycles(&cd->cdc, deduction);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1296 cd->graphics_cycle -= deduction;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1297 if (cd->graphics_int_cycle != CYCLE_NEVER) {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1298 if (cd->graphics_int_cycle > deduction) {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1299 cd->graphics_int_cycle -= deduction;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1300 } else {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1301 cd->graphics_int_cycle = 0;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1302 }
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1303 }
2148 2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1304 if (deduction >= cd->last_refresh_cycle) {
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1305 cd->last_refresh_cycle -= deduction;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1306 } else {
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1307 cd->last_refresh_cycle = 0;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays Michael Pavone <pavone@retrodev.com> parents: 2144 diff changeset	1308 }
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	1309 cd->pcm.cycle -= deduction;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1310 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1311
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1312 static uint16_t main_gate_read16(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1313 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1314 m68k_context *m68k = vcontext;
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1315 gen_update_refresh_free_access(m68k);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1316 genesis_context *gen = m68k->system;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1317 segacd_context *cd = gen->expansion;
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1318 uint32_t scd_cycle = gen_cycle_to_scd(m68k->cycles, gen);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1319 scd_run(cd, scd_cycle);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1320 uint32_t offset = (address & 0x1FF) >> 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1321 switch (offset)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1322 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1323 case GA_SUB_CPU_CTRL: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1324 uint16_t value = 0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1325 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1326 value \|= BIT_IEN2;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1327 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1328 if (cd->int2_cycle != CYCLE_NEVER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1329 value \|= BIT_IFL2;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1330 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1331 if (can_main_access_prog(cd)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1332 value \|= BIT_SBRQ;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1333 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1334 if (cd->reset) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1335 value \|= BIT_SRES;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1336 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1337 return value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1338 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1339 case GA_MEM_MODE:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1340 //Main CPU can't read priority mode bits
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1341 return cd->gate_array[offset] & 0xFFE7;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1342 case GA_HINT_VECTOR:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1343 return cd->rom_mut[0x72/2];
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1344 case GA_CDC_HOST_DATA: {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1345 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1346 if (dst == DST_MAIN_CPU) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1347 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1348 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1349 lc8951_resume_transfer(&cd->cdc);
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1350 } else {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1351 printf("Read of CDC host data with DSR clear at %u\n", scd_cycle);
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1352 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1353 calculate_target_cycle(cd->m68k);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1354 }
2066 a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures Michael Pavone <pavone@retrodev.com> parents: 2065 diff changeset	1355 return cd->gate_array[offset];
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1356 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1357 case GA_CDC_DMA_ADDR:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1358 //TODO: open bus maybe?
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1359 return 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1360 default:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1361 if (offset < GA_TIMER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1362 return cd->gate_array[offset];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1363 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1364 //TODO: open bus maybe?
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1365 return 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1366 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1367 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1368
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1369 static uint8_t main_gate_read8(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1370 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1371 uint16_t val = main_gate_read16(address & 0xFE, vcontext);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1372 return address & 1 ? val : val >> 8;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1373 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1374
2068 f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1375 static void dump_prog_ram(segacd_context *cd)
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1376 {
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1377 static int dump_count;
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1378 char fname[256];
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1379 sprintf(fname, "prog_ram_%d.bin", dump_count++);
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1380 FILE *f = fopen(fname, "wb");
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1381 if (f) {
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1382 uint32_t last = 256*1024-1;
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1383 for(; last > 0; --last)
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1384 {
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1385 if (cd->prog_ram[last]) {
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1386 break;
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1387 }
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1388 }
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1389 for (uint32_t i = 0; i <= last; i++)
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1390 {
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1391 uint8_t pair[2];
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1392 pair[0] = cd->prog_ram[i] >> 8;
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1393 pair[1] = cd->prog_ram[i];
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1394 fwrite(pair, 1, sizeof(pair), f);
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1395 }
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1396
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1397 fclose(f);
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1398 }
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1399 }
f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1400
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1401 static void main_gate_write16(uint32_t address, void vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1402 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1403 m68k_context *m68k = vcontext;
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1404 gen_update_refresh_free_access(m68k);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1405 genesis_context *gen = m68k->system;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1406 segacd_context *cd = gen->expansion;
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1407 uint32_t scd_cycle = gen_cycle_to_scd(m68k->cycles, gen);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1408 uint32_t reg = (address & 0x1FF) >> 1;
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1409 if (reg != GA_SUB_CPU_CTRL) {
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1410 scd_run(cd, scd_cycle);
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1411 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1412 switch (reg)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1413 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1414 case GA_SUB_CPU_CTRL: {
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1415 if ((value & BIT_IFL2) && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2)) {
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1416 if (cd->int2_cycle != CYCLE_NEVER) {
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1417 scd_run(cd, scd_cycle - 4 * cd->m68k->opts->gen.clock_divider);
d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1418 while (cd->int2_cycle != CYCLE_NEVER && cd->m68k->cycles < scd_cycle) {
d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1419 scd_run(cd, cd->m68k->cycles + cd->m68k->opts->gen.clock_divider);
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1420 }
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1421 }
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1422 cd->int2_cycle = scd_cycle;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1423
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1424 }
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1425 scd_run(cd, scd_cycle);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1426 uint8_t old_access = can_main_access_prog(cd);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1427 cd->busreq = value & BIT_SBRQ;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1428 uint8_t old_reset = cd->reset;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1429 cd->reset = value & BIT_SRES;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1430 if (cd->reset && !old_reset) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1431 cd->need_reset = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1432 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1433 /*cd->gate_array[reg] &= 0x7FFF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1434 cd->gate_array[reg] \|= value & 0x8000;*/
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1435 uint8_t new_access = can_main_access_prog(cd);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1436 uint32_t bank = cd->gate_array[GA_MEM_MODE] >> 6 & 0x3;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1437 if (new_access) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1438 if (!old_access) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1439 m68k->mem_pointers[cd->memptr_start_index] = cd->prog_ram + bank * 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1440 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1441 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1442 } else if (old_access) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1443 m68k->mem_pointers[cd->memptr_start_index] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1444 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1445 m68k_invalidate_code_range(cd->m68k, bank * 0x20000, (bank + 1) * 0x20000);
2135 95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1446 dump_prog_ram(cd);
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1447 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1448 if (dst == DST_PROG_RAM) {
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1449 lc8951_resume_transfer(&cd->cdc);
2068 f573f2c31bc9 Dump PROG RAM to file for debugging Michael Pavone <pavone@retrodev.com> parents: 2066 diff changeset	1450 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1451 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1452 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1453 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1454 case GA_MEM_MODE: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1455 uint16_t changed = cd->gate_array[reg] ^ value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1456 //Main CPU can't write priority mode bits, MODE or RET
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1457 cd->gate_array[reg] &= 0x001F;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1458 cd->gate_array[reg] \|= value & 0xFFC0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1459 if ((cd->gate_array[reg] & BIT_MEM_MODE)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1460 //1M mode
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1461 if (!(value & BIT_DMNA)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1462 cd->gate_array[reg] \|= BIT_DMNA;
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	1463 cd->main_swap_request = 1;
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	1464 } else {
5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	1465 cd->main_has_word2m = 0;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1466 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1467 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1468 //2M mode
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1469 if (changed & value & BIT_DMNA) {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1470 cd->gate_array[reg] \|= BIT_DMNA;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1471 m68k->mem_pointers[cd->memptr_start_index + 1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1472 m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1473 cd->m68k->mem_pointers[0] = cd->word_ram;
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1474 cd->gate_array[reg] &= ~BIT_RET;
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	1475 cd->main_has_word2m = 0;
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	1476 if (cd->sub_paused_wordram) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	1477 cd->sub_paused_wordram = 0;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	1478 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1479
2129 4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU Michael Pavone <pavone@retrodev.com> parents: 2128 diff changeset	1480 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU Michael Pavone <pavone@retrodev.com> parents: 2128 diff changeset	1481 if (dst == DST_WORD_RAM) {
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1482 lc8951_resume_transfer(&cd->cdc);
2129 4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU Michael Pavone <pavone@retrodev.com> parents: 2128 diff changeset	1483 }
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU Michael Pavone <pavone@retrodev.com> parents: 2128 diff changeset	1484
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1485 m68k_invalidate_code_range(m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1486 m68k_invalidate_code_range(cd->m68k, 0x080000, 0x0C0000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1487 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1488 }
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1489 if (changed & MASK_PROG_BANK && can_main_access_prog(cd)) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1490 uint32_t bank = cd->gate_array[GA_MEM_MODE] >> 6 & 0x3;
2055 c4d066d798c4 Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works Michael Pavone <pavone@retrodev.com> parents: 2054 diff changeset	1491 m68k->mem_pointers[cd->memptr_start_index] = cd->prog_ram + bank * 0x10000;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1492 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1493 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1494 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1495 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1496 case GA_HINT_VECTOR:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1497 cd->rom_mut[0x72/2] = value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1498 break;
2135 95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1499 case GA_CDC_HOST_DATA:
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1500 //writes to this register have the same side effects as reads
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1501 main_gate_read16(address, vcontext);
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	1502 break;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1503 case GA_COMM_FLAG:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1504 //Main CPU can only write the upper byte;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1505 cd->gate_array[reg] &= 0xFF;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1506 cd->gate_array[reg] \|= value & 0xFF00;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1507 break;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1508 case GA_COMM_CMD0:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1509 case GA_COMM_CMD1:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1510 case GA_COMM_CMD2:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1511 case GA_COMM_CMD3:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1512 case GA_COMM_CMD4:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1513 case GA_COMM_CMD5:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1514 case GA_COMM_CMD6:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1515 case GA_COMM_CMD7:
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1516 //no effects for these other than saving the value
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1517 cd->gate_array[reg] = value;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1518 break;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1519 default:
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1520 printf("Unhandled gate array write %X:%X\n", address, value);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1521 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1522 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1523 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1524
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1525 static void main_gate_write8(uint32_t address, void vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1526 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1527 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1528 genesis_context *gen = m68k->system;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1529 segacd_context *cd = gen->expansion;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1530 uint32_t reg = (address & 0x1FF) >> 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1531 uint16_t value16;
2108 68d61ba1b762 Fix handling of byte writes to gate array regs from main CPU Michael Pavone <pavone@retrodev.com> parents: 2106 diff changeset	1532 switch (reg)
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1533 {
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1534 case GA_SUB_CPU_CTRL:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1535 if (address & 1) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1536 value16 = value;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1537 } else {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1538 value16 = value << 8;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1539 if (cd->reset) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1540 value16 \|= BIT_SRES;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1541 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1542 if (cd->busreq) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1543 value16 \|= BIT_SBRQ;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1544 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1545 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1546 break;
2056 27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1547 case GA_HINT_VECTOR:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1548 case GA_COMM_FLAG:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1549 //writes to these regs are always treated as word wide
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1550 value16 = value \| (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1551 break;
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1552 default:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1553 if (address & 1) {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1554 value16 = cd->gate_array[reg] & 0xFF00 \| value;
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1555 } else {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1556 value16 = cd->gate_array[reg] & 0xFF \| (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator Michael Pavone <pavone@retrodev.com> parents: 2055 diff changeset	1557 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1558 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1559 return main_gate_write16(address, vcontext, value16);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1560 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1561
2329 06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1562 uint8_t laseractive_regs[256];
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1563
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1564 static uint16_t laseractive_read16(uint32_t address, void *vcontext)
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1565 {
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1566 printf("LaserActive 16-bit register read %X\n", address);
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1567 return 0xFFFF;
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1568 }
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1569
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1570 static uint8_t laseractive_read8(uint32_t address, void *vcontext)
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1571 {
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1572 printf("LaserActive 8-bit register read %X\n", address);
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1573 if (address == 0xFDFE81) {
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1574 return 0x80 \| (laseractive_regs[0x41] & 1);
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1575 } else if (address >= 0xFDFE41 && address < 0xFDFE80 && (address & 1)) {
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1576 return laseractive_regs[address & 0xFF];
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1577 }
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1578 return 0xFF;
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1579 }
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1580
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1581 static void laseractive_write16(uint32_t address, void vcontext, uint16_t value)
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1582 {
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1583 printf("LaserActive 16-bit register write %X: %X\n", address, value);
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1584 return vcontext;
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1585 }
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1586
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1587 static void laseractive_write8(uint32_t address, void vcontext, uint8_t value)
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1588 {
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1589 printf("LaserActive 8-bit register write %X: %X\n", address, value);
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1590 laseractive_regs[address & 0xFF] = value;
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1591 return vcontext;
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1592 }
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1593
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1594 segacd_context alloc_configure_segacd(system_media media, uint32_t opts, uint8_t force_region, rom_info *info)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1595 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1596 static memmap_chunk sub_cpu_map[] = {
2111 4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1597 {0x000000, 0x01FF00, 0xFFFFFF, .flags=MMAP_READ \| MMAP_CODE, .write_16 = prog_ram_wp_write16, .write_8 = prog_ram_wp_write8},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1598 {0x01FF00, 0x080000, 0xFFFFFF, .flags=MMAP_READ \| MMAP_WRITE \| MMAP_CODE},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1599 {0x080000, 0x0C0000, 0x03FFFF, .flags=MMAP_READ \| MMAP_WRITE \| MMAP_CODE \| MMAP_PTR_IDX \| MMAP_FUNC_NULL, .ptr_index = 0,
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1600 .read_16 = word_ram_2M_read16, .write_16 = word_ram_2M_write16, .read_8 = word_ram_2M_read8, .write_8 = word_ram_2M_write8},
2111 4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1601 {0x0C0000, 0x0E0000, 0x01FFFF, .flags=MMAP_READ \| MMAP_WRITE \| MMAP_CODE \| MMAP_PTR_IDX \| MMAP_FUNC_NULL, .ptr_index = 1,
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2131 diff changeset	1602 .read_16 = word_ram_1M_read16, .write_16 = word_ram_1M_write16, .read_8 = word_ram_1M_read8, .write_8 = word_ram_1M_write8, .shift = 1},
2111 4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1603 {0xFE0000, 0xFF0000, 0x003FFF, .flags=MMAP_READ \| MMAP_WRITE \| MMAP_ONLY_ODD},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1604 {0xFF0000, 0xFF8000, 0x003FFF, .read_16 = pcm_read16, .write_16 = pcm_write16, .read_8 = pcm_read8, .write_8 = pcm_write8},
2329 06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1605 {0xFF8000, 0xFF8200, 0x0001FF, .read_16 = sub_gate_read16, .write_16 = sub_gate_write16, .read_8 = sub_gate_read8, .write_8 = sub_gate_write8},
06d5e9b08bdb Add NTSC composite shader by Sik Michael Pavone <pavone@retrodev.com> parents: 2302 diff changeset	1606 {0xFD0000, 0xFE0000, 0xFFFFFF, .read_16 = laseractive_read16, .write_16 = laseractive_write16, .read_8 = laseractive_read8, .write_8 = laseractive_write8}
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1607 };
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1608
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1609 segacd_context *cd = calloc(sizeof(segacd_context), 1);
2384 03e6ac327ba0 Handle changes to sample rate while content is running Michael Pavone <pavone@retrodev.com> parents: 2350 diff changeset	1610 cd->speed_percent = 100;
2083 372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1611 uint32_t firmware_size;
2123 50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1612 uint8_t region = force_region;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1613 if (!region) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1614 char * def_region = tern_find_path_default(config, "system\0default_region\0", (tern_val){.ptrval = "U"}, TVAL_PTR).ptrval;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1615 if (!info->regions \|\| (info->regions & translate_region_char(toupper(*def_region)))) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1616 region = translate_region_char(toupper(*def_region));
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1617 } else {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1618 region = info->regions;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1619 }
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1620 }
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1621 const char *key;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1622 if (region & REGION_E) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1623 key = "system\0scd_bios_eu\0";
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1624 } else if (region & REGION_J) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1625 key = "system\0scd_bios_jp\0";
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1626 } else {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1627 key = "system\0scd_bios_us\0";
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1628 }
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1629 char *bios_path = tern_find_path_default(config, key, (tern_val){.ptrval = "cdbios.bin"}, TVAL_PTR).ptrval;
2160 3f09312685e3 Fix loading CD bios from absolute path Michael Pavone <pavone@retrodev.com> parents: 2148 diff changeset	1630 if (is_absolute_path(bios_path)) {
3f09312685e3 Fix loading CD bios from absolute path Michael Pavone <pavone@retrodev.com> parents: 2148 diff changeset	1631 FILE *f = fopen(bios_path, "rb");
3f09312685e3 Fix loading CD bios from absolute path Michael Pavone <pavone@retrodev.com> parents: 2148 diff changeset	1632 if (f) {
3f09312685e3 Fix loading CD bios from absolute path Michael Pavone <pavone@retrodev.com> parents: 2148 diff changeset	1633 long to_read = file_size(f);
3f09312685e3 Fix loading CD bios from absolute path Michael Pavone <pavone@retrodev.com> parents: 2148 diff changeset	1634 cd->rom = malloc(to_read);
3f09312685e3 Fix loading CD bios from absolute path Michael Pavone <pavone@retrodev.com> parents: 2148 diff changeset	1635 firmware_size = fread(cd->rom, 1, to_read, f);
3f09312685e3 Fix loading CD bios from absolute path Michael Pavone <pavone@retrodev.com> parents: 2148 diff changeset	1636 if (!firmware_size) {
3f09312685e3 Fix loading CD bios from absolute path Michael Pavone <pavone@retrodev.com> parents: 2148 diff changeset	1637 free(cd->rom);
3f09312685e3 Fix loading CD bios from absolute path Michael Pavone <pavone@retrodev.com> parents: 2148 diff changeset	1638 cd->rom = NULL;
3f09312685e3 Fix loading CD bios from absolute path Michael Pavone <pavone@retrodev.com> parents: 2148 diff changeset	1639 }
3f09312685e3 Fix loading CD bios from absolute path Michael Pavone <pavone@retrodev.com> parents: 2148 diff changeset	1640 fclose(f);
3f09312685e3 Fix loading CD bios from absolute path Michael Pavone <pavone@retrodev.com> parents: 2148 diff changeset	1641 }
3f09312685e3 Fix loading CD bios from absolute path Michael Pavone <pavone@retrodev.com> parents: 2148 diff changeset	1642 } else {
3f09312685e3 Fix loading CD bios from absolute path Michael Pavone <pavone@retrodev.com> parents: 2148 diff changeset	1643 cd->rom = (uint16_t *)read_bundled_file(bios_path, &firmware_size);
3f09312685e3 Fix loading CD bios from absolute path Michael Pavone <pavone@retrodev.com> parents: 2148 diff changeset	1644 }
2123 50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1645 if (!cd->rom) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1646 fatal_error("Failed to load Sega CD BIOS from %s\n", bios_path);
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config Michael Pavone <pavone@retrodev.com> parents: 2122 diff changeset	1647 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1648 uint32_t adjusted_size = nearest_pow2(firmware_size);
2083 372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1649 if (adjusted_size != firmware_size) {
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1650 cd->rom = realloc(cd->rom, adjusted_size);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1651 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1652 cd->rom_mut = malloc(adjusted_size);
1503 a763523dadf4 Added code for initializing a combined Genesis + Sega CD system when a Sega CD ISO is loaded Michael Pavone <pavone@retrodev.com> parents: 1502 diff changeset	1653 byteswap_rom(adjusted_size, cd->rom);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1654 memcpy(cd->rom_mut, cd->rom, adjusted_size);
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1655 cd->rom_mut[0x72/2] = 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1656
2083 372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1657 cd->prog_ram = calloc(512*1024, 1);
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1658 cd->word_ram = calloc(256*1024, 1);
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory Michael Pavone <pavone@retrodev.com> parents: 2081 diff changeset	1659 cd->bram = calloc(8*1024, 1);
2281 b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1660 char *bram_size_id = tern_find_path_default(config, "system\0bram_cart_size_id\0", (tern_val){.ptrval = "4"}, TVAL_PTR).ptrval;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1661 cd->bram_cart_id = 0xFF;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1662 cd->bram_cart = NULL;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1663 if (strcmp(bram_size_id, "none")) {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1664 char *end;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1665 long id = strtol(bram_size_id, &end, 10);
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1666 if (end != bram_size_id && id < 8) {
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1667 cd->bram_cart_id = id;
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1668 cd->bram_cart = calloc(0x2000 << id, 1);
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1669 }
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1670 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1671
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1672 sub_cpu_map[0].buffer = sub_cpu_map[1].buffer = cd->prog_ram;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1673 sub_cpu_map[4].buffer = cd->bram;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1674 m68k_options *mopts = malloc(sizeof(m68k_options));
2350 f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues Michael Pavone <pavone@retrodev.com> parents: 2344 diff changeset	1675 init_m68k_opts(mopts, sub_cpu_map, sizeof(sub_cpu_map) / sizeof(*sub_cpu_map), 4, sync_components, int_ack);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1676 cd->m68k = init_68k_context(mopts, NULL);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1677 cd->m68k->system = cd;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1678 cd->int2_cycle = CYCLE_NEVER;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1679 cd->busreq = 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1680 cd->busack = 1;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1681 cd->need_reset = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1682 cd->reset = 1; //active low, so reset is not active on start
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1683 cd->memptr_start_index = 0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1684 cd->gate_array[1] = 1;
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	1685 cd->gate_array[GA_CDD_CTRL] = BIT_MUTE; //Data/mute flag is set on start
2119 5ec2f97365a2 More accurate RET/DMNA implementation Michael Pavone <pavone@retrodev.com> parents: 2116 diff changeset	1686 cd->main_has_word2m = 1;
2065 02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements Michael Pavone <pavone@retrodev.com> parents: 2062 diff changeset	1687 lc8951_init(&cd->cdc, handle_cdc_byte, cd);
2061 7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1688 if (media->chain && media->type != MEDIA_CDROM) {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1689 media = media->chain;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1690 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU Michael Pavone <pavone@retrodev.com> parents: 2058 diff changeset	1691 cdd_mcu_init(&cd->cdd, media);
2069 8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware Michael Pavone <pavone@retrodev.com> parents: 2068 diff changeset	1692 cd_graphics_init(cd);
2080 bafb757e1cd2 Implement CD audio Michael Pavone <pavone@retrodev.com> parents: 2073 diff changeset	1693 cdd_fader_init(&cd->fader);
2081 cfd53c94fffb Initial stab at RF5C164 emulation Michael Pavone <pavone@retrodev.com> parents: 2080 diff changeset	1694 rf5c164_init(&cd->pcm, SCD_MCLKS, 4);
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1695 return cd;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1696 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1697
2164 4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance Michael Pavone <pavone@retrodev.com> parents: 2160 diff changeset	1698 void free_segacd(segacd_context *cd)
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance Michael Pavone <pavone@retrodev.com> parents: 2160 diff changeset	1699 {
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance Michael Pavone <pavone@retrodev.com> parents: 2160 diff changeset	1700 cdd_fader_deinit(&cd->fader);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance Michael Pavone <pavone@retrodev.com> parents: 2160 diff changeset	1701 rf5c164_deinit(&cd->pcm);
2499 d74d3998482c Make some progress on compiling full emulator with new 68K core Michael Pavone <pavone@retrodev.com> parents: 2427 diff changeset	1702 m68k_options_free(cd->m68k->opts);
2164 4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance Michael Pavone <pavone@retrodev.com> parents: 2160 diff changeset	1703 free(cd->m68k);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance Michael Pavone <pavone@retrodev.com> parents: 2160 diff changeset	1704 free(cd->bram);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance Michael Pavone <pavone@retrodev.com> parents: 2160 diff changeset	1705 free(cd->word_ram);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance Michael Pavone <pavone@retrodev.com> parents: 2160 diff changeset	1706 free(cd->prog_ram);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance Michael Pavone <pavone@retrodev.com> parents: 2160 diff changeset	1707 free(cd->rom_mut);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance Michael Pavone <pavone@retrodev.com> parents: 2160 diff changeset	1708 }
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance Michael Pavone <pavone@retrodev.com> parents: 2160 diff changeset	1709
2280 9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1710 void segacd_serialize(segacd_context cd, serialize_buffer buf, uint8_t all)
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1711 {
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1712 if (all) {
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1713 start_section(buf, SECTION_SUB_68000);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1714 m68k_serialize(cd->m68k, cd->m68k_pc, buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1715 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1716
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1717 start_section(buf, SECTION_GATE_ARRAY);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1718 save_buffer16(buf, cd->gate_array, sizeof(cd->gate_array)/sizeof(*cd->gate_array));
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1719 save_buffer16(buf, cd->prog_ram, 256*1024);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1720 save_buffer16(buf, cd->word_ram, 128*1024);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1721 save_int16(buf, cd->rom_mut[0x72/2]);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1722 save_int32(buf, cd->stopwatch_cycle);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1723 save_int32(buf, cd->int2_cycle);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1724 save_int32(buf, cd->graphics_int_cycle);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1725 save_int32(buf, cd->periph_reset_cycle);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1726 save_int32(buf, cd->last_refresh_cycle);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1727 save_int32(buf, cd->graphics_cycle);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1728 save_int32(buf, cd->base);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1729 save_int32(buf, cd->graphics_x);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1730 save_int32(buf, cd->graphics_y);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1731 save_int32(buf, cd->graphics_dx);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1732 save_int32(buf, cd->graphics_dy);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1733 save_int32(buf, cd->graphics_dst_x);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1734 save_buffer8(buf, cd->graphics_pixels, sizeof(cd->graphics_pixels));
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1735 save_int8(buf, cd->timer_pending);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1736 save_int8(buf, cd->timer_value);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1737 save_int8(buf, cd->busreq);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1738 save_int8(buf, cd->reset);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1739 save_int8(buf, cd->need_reset);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1740 save_int8(buf, cd->cdc_dst_low);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1741 save_int8(buf, cd->cdc_int_ack);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1742 save_int8(buf, cd->graphics_step);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1743 save_int8(buf, cd->graphics_dst_y);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1744 save_int8(buf, cd->main_has_word2m);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1745 save_int8(buf, cd->main_swap_request);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1746 save_int8(buf, cd->bank_toggle);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1747 save_int8(buf, cd->sub_paused_wordram);
2281 b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1748 save_int8(buf, cd->bram_cart_write_enabled);
2280 9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1749 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1750
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1751 start_section(buf, SECTION_CDD_MCU);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1752 cdd_mcu_serialize(&cd->cdd, buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1753 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1754
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1755 start_section(buf, SECTION_LC8951);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1756 lc8951_serialize(&cd->cdc, buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1757 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1758
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1759 start_section(buf, SECTION_CDROM);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1760 cdimage_serialize(cd->cdd.media, buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1761 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1762 }
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1763 start_section(buf, SECTION_RF5C164);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1764 rf5c164_serialize(&cd->pcm, buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1765 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1766
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1767 start_section(buf, SECTION_CDD_FADER);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1768 cdd_fader_serialize(&cd->fader, buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1769 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1770 }
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1771
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1772 static void gate_array_deserialize(deserialize_buffer buf, void vcd)
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1773 {
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1774 segacd_context *cd = vcd;
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1775 load_buffer16(buf, cd->gate_array, sizeof(cd->gate_array)/sizeof(*cd->gate_array));
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1776 load_buffer16(buf, cd->prog_ram, 256*1024);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1777 load_buffer16(buf, cd->word_ram, 128*1024);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1778 cd->rom_mut[0x72/2] = load_int16(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1779 cd->stopwatch_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1780 cd->int2_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1781 cd->graphics_int_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1782 cd->periph_reset_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1783 cd->last_refresh_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1784 cd->graphics_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1785 cd->base = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1786 cd->graphics_x = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1787 cd->graphics_y = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1788 cd->graphics_dx = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1789 cd->graphics_dy = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1790 cd->graphics_dst_x = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1791 load_buffer8(buf, cd->graphics_pixels, sizeof(cd->graphics_pixels));
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1792 cd->timer_pending = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1793 cd->timer_value = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1794 cd->busreq = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1795 cd->reset = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1796 cd->need_reset = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1797 cd->cdc_dst_low = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1798 cd->cdc_int_ack = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1799 cd->graphics_step = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1800 cd->graphics_dst_y = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1801 cd->main_has_word2m = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1802 cd->main_swap_request = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1803 cd->bank_toggle = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1804 cd->sub_paused_wordram = load_int8(buf);
2281 b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1805 cd->bram_cart_write_enabled = load_int8(buf);
2280 9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1806
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1807 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1808 //1M mode
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1809 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1810 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1811 cd->m68k->mem_pointers[0] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1812 cd->m68k->mem_pointers[1] = cd->bank_toggle ? cd->word_ram : cd->word_ram + 1;
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1813 } else {
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1814 //2M mode
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1815 if (cd->main_has_word2m) {
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1816 //main CPU has word ram
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1817 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram;
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1818 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000;
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1819 cd->m68k->mem_pointers[0] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1820 cd->m68k->mem_pointers[1] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1821 } else {
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1822 //sub cpu has word ram
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1823 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1824 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1825 cd->m68k->mem_pointers[0] = cd->word_ram;
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1826 cd->m68k->mem_pointers[1] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1827 }
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1828 }
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1829
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1830 m68k_invalidate_code_range(cd->m68k, 0, 0x0E0000);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1831 m68k_invalidate_code_range(cd->genesis->m68k, cd->base + 0x200000, cd->base + 0x240000);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1832 }
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1833
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1834 void segacd_register_section_handlers(segacd_context cd, deserialize_buffer buf)
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1835 {
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1836 register_section_handler(buf, (section_handler){.fun = m68k_deserialize, .data = cd->m68k}, SECTION_SUB_68000);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1837 register_section_handler(buf, (section_handler){.fun = gate_array_deserialize, .data = cd}, SECTION_GATE_ARRAY);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1838 register_section_handler(buf, (section_handler){.fun = cdd_mcu_deserialize, .data = &cd->cdd}, SECTION_CDD_MCU);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1839 register_section_handler(buf, (section_handler){.fun = lc8951_deserialize, .data = &cd->cdc}, SECTION_LC8951);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1840 register_section_handler(buf, (section_handler){.fun = rf5c164_deserialize, .data = &cd->pcm}, SECTION_RF5C164);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1841 register_section_handler(buf, (section_handler){.fun = cdd_fader_deserialize, .data = &cd->fader}, SECTION_CDD_FADER);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1842 register_section_handler(buf, (section_handler){.fun = cdimage_deserialize, .data = cd->cdd.media}, SECTION_CDROM);
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1843 }
9ead0fe69d9b Implement savestate support for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2278 diff changeset	1844
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1845 memmap_chunk segacd_main_cpu_map(segacd_context cd, uint8_t cart_boot, uint32_t *num_chunks)
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1846 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1847 static memmap_chunk main_cpu_map[] = {
2111 4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1848 {0x000000, 0x020000, 0x01FFFF, .flags=MMAP_READ},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1849 {0x020000, 0x040000, 0x01FFFF, .flags=MMAP_READ\|MMAP_WRITE\|MMAP_PTR_IDX\|MMAP_FUNC_NULL\|MMAP_CODE, .ptr_index = 0,
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1850 .read_16 = unmapped_prog_read16, .write_16 = unmapped_prog_write16, .read_8 = unmapped_prog_read8, .write_8 = unmapped_prog_write8},
2111 4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1851 {0x040000, 0x060000, 0x01FFFF, .flags=MMAP_READ}, //first ROM alias
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1852 //TODO: additional ROM/prog RAM aliases
2111 4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1853 {0x200000, 0x220000, 0x01FFFF, .flags=MMAP_READ\|MMAP_WRITE\|MMAP_PTR_IDX\|MMAP_FUNC_NULL\|MMAP_CODE, .ptr_index = 1,
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1854 .read_16 = unmapped_word_read16, .write_16 = unmapped_word_write16, .read_8 = unmapped_word_read8, .write_8 = unmapped_word_write8},
2111 4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware Michael Pavone <pavone@retrodev.com> parents: 2108 diff changeset	1855 {0x220000, 0x240000, 0x01FFFF, .flags=MMAP_READ\|MMAP_WRITE\|MMAP_PTR_IDX\|MMAP_FUNC_NULL\|MMAP_CODE, .ptr_index = 2,
2057 88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests Michael Pavone <pavone@retrodev.com> parents: 2056 diff changeset	1856 .read_16 = cell_image_read16, .write_16 = cell_image_write16, .read_8 = cell_image_read8, .write_8 = cell_image_write8},
2281 b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1857 {0xA12000, 0xA13000, 0xFFFFFF, .read_16 = main_gate_read16, .write_16 = main_gate_write16, .read_8 = main_gate_read8, .write_8 = main_gate_write8},
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1858 {0x400000, 0x800000, 0xFFFFFF, .read_16 = cart_area_read16, .write_16 = cart_area_write16, .read_8 = cart_area_read8, .write_8 = cart_area_write8}
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1859 };
2281 b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1860 num_chunks = sizeof(main_cpu_map) / sizeof(main_cpu_map);
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1861 if (cart_boot) {
2282 a6a68c33cce7 Fix regression in Mode 1 boot Michael Pavone <pavone@retrodev.com> parents: 2281 diff changeset	1862 (*num_chunks)--;
2281 b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1863 }
b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1864 for (int i = 0; i < *num_chunks; i++)
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1865 {
2281 b9fed07f19e4 Implement BRAM cart support Michael Pavone <pavone@retrodev.com> parents: 2280 diff changeset	1866 if (main_cpu_map[i].start < 0x400000) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1867 if (cart_boot) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1868 main_cpu_map[i].start \|= 0x400000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1869 main_cpu_map[i].end \|= 0x400000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1870 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1871 main_cpu_map[i].start &= 0x3FFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1872 main_cpu_map[i].end &= 0x3FFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1873 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1874 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1875 }
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1876 main_cpu_map[0].buffer = cd->rom_mut;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1877 main_cpu_map[2].buffer = cd->rom;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1878 main_cpu_map[1].buffer = cd->prog_ram;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1879 main_cpu_map[3].buffer = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 1504 diff changeset	1880 main_cpu_map[4].buffer = cd->word_ram + 0x10000;
1502 2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1881 return main_cpu_map;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers Michael Pavone <pavone@retrodev.com> parents: 1467 diff changeset	1882 }
2278 5a21bc0ec583 Implement turbo/slo mo for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2233 diff changeset	1883
5a21bc0ec583 Implement turbo/slo mo for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2233 diff changeset	1884 void segacd_set_speed_percent(segacd_context *cd, uint32_t percent)
5a21bc0ec583 Implement turbo/slo mo for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2233 diff changeset	1885 {
5a21bc0ec583 Implement turbo/slo mo for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2233 diff changeset	1886 uint32_t scd_cycle = gen_cycle_to_scd(cd->genesis->ym->current_cycle, cd->genesis);
5a21bc0ec583 Implement turbo/slo mo for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2233 diff changeset	1887 scd_run(cd, scd_cycle);
2384 03e6ac327ba0 Handle changes to sample rate while content is running Michael Pavone <pavone@retrodev.com> parents: 2350 diff changeset	1888 cd->speed_percent = percent;
03e6ac327ba0 Handle changes to sample rate while content is running Michael Pavone <pavone@retrodev.com> parents: 2350 diff changeset	1889 uint32_t new_clock = ((uint64_t)SCD_MCLKS * (uint64_t)cd->speed_percent) / 100;
2278 5a21bc0ec583 Implement turbo/slo mo for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2233 diff changeset	1890 rf5c164_adjust_master_clock(&cd->pcm, new_clock);
5a21bc0ec583 Implement turbo/slo mo for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2233 diff changeset	1891 cdd_fader_set_speed_percent(&cd->fader, percent);
5a21bc0ec583 Implement turbo/slo mo for Sega CD Michael Pavone <pavone@retrodev.com> parents: 2233 diff changeset	1892 }
2335 c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1893
2384 03e6ac327ba0 Handle changes to sample rate while content is running Michael Pavone <pavone@retrodev.com> parents: 2350 diff changeset	1894 void segacd_config_updated(segacd_context *cd)
03e6ac327ba0 Handle changes to sample rate while content is running Michael Pavone <pavone@retrodev.com> parents: 2350 diff changeset	1895 {
03e6ac327ba0 Handle changes to sample rate while content is running Michael Pavone <pavone@retrodev.com> parents: 2350 diff changeset	1896 //sample rate may have changed
03e6ac327ba0 Handle changes to sample rate while content is running Michael Pavone <pavone@retrodev.com> parents: 2350 diff changeset	1897 uint32_t new_clock = ((uint64_t)SCD_MCLKS * (uint64_t)cd->speed_percent) / 100;
03e6ac327ba0 Handle changes to sample rate while content is running Michael Pavone <pavone@retrodev.com> parents: 2350 diff changeset	1898 rf5c164_adjust_master_clock(&cd->pcm, new_clock);
03e6ac327ba0 Handle changes to sample rate while content is running Michael Pavone <pavone@retrodev.com> parents: 2350 diff changeset	1899 cdd_fader_set_speed_percent(&cd->fader, cd->speed_percent);
03e6ac327ba0 Handle changes to sample rate while content is running Michael Pavone <pavone@retrodev.com> parents: 2350 diff changeset	1900 }
03e6ac327ba0 Handle changes to sample rate while content is running Michael Pavone <pavone@retrodev.com> parents: 2350 diff changeset	1901
2335 c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1902 static uint8_t copy_chars(uint8_t dst, uint8_t *str)
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1903 {
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1904 size_t len = strlen(str);
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1905 memcpy(dst, str, len);
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1906 return dst + len;
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1907 }
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1908
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1909 void segacd_format_bram(uint8_t *buffer, size_t size)
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1910 {
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1911 memset(buffer, 0, size);
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1912 uint16_t free_blocks = (size / 64) - 3;
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1913 uint8_t *cur = buffer + size - 0x40;
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1914 cur = copy_chars(cur, "___________");
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1915 cur += 4;
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1916 *(cur++) = 0x40;
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1917 for (int i = 0; i < 4; i++)
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1918 {
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1919 *(cur++) = free_blocks >> 8;
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1920 *(cur++) = free_blocks;
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1921 }
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1922 cur += 8;
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1923 cur = copy_chars(cur, "SEGA_CD_ROM");
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1924 ++cur;
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1925 *(cur++) = 1;
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1926 cur += 3;
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1927 copy_chars(cur, "RAM_CARTRIDGE___");
c05b7c5e6f11 Automatically format Sega CD backup RAM Michael Pavone <pavone@retrodev.com> parents: 2329 diff changeset	1928 }

Mercurial > repos > blastem

annotate segacd.c @ 2688:b42f00a3a937 default tip