Mercurial > repos > blastem
annotate 68kinst.c @ 1458:b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
author | Michael Pavone <pavone@retrodev.com> |
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date | Wed, 06 Sep 2017 22:14:51 -0700 |
parents | 696a029d09e9 |
children | d276ec2fff11 |
rev | line source |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "68kinst.h" |
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7 #include <string.h> |
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8 #include <stdio.h> |
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9 |
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10 uint32_t sign_extend16(uint32_t val) |
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11 { |
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12 return (val & 0x8000) ? val | 0xFFFF0000 : val; |
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13 } |
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14 |
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15 uint32_t sign_extend8(uint32_t val) |
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16 { |
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17 return (val & 0x80) ? val | 0xFFFFFF00 : val; |
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18 } |
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19 |
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20 uint16_t *m68k_decode_op_ex(uint16_t *cur, uint8_t mode, uint8_t reg, uint8_t size, m68k_op_info *dst) |
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21 { |
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22 uint16_t ext, tmp; |
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23 dst->addr_mode = mode; |
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24 switch(mode) |
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25 { |
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26 case MODE_REG: |
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27 case MODE_AREG: |
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28 case MODE_AREG_INDIRECT: |
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29 case MODE_AREG_POSTINC: |
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30 case MODE_AREG_PREDEC: |
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31 dst->params.regs.pri = reg; |
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32 break; |
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33 case MODE_AREG_DISPLACE: |
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34 ext = *(++cur); |
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35 dst->params.regs.pri = reg; |
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36 dst->params.regs.displacement = sign_extend16(ext); |
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37 break; |
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38 case MODE_AREG_INDEX_MEM: |
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39 dst->params.regs.pri = reg; |
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40 ext = *(++cur); |
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41 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit |
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42 #ifdef M68020 |
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43 dst->params.regs.scale = ext >> 9 & 3; |
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44 if (ext & 0x100) |
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45 { |
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46 dst->params.regs.disp_sizes = ext >> 4 & 3; |
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47 switch (dst->params.regs.disp_sizes) |
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48 { |
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49 case 0: |
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50 //reserved |
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51 return NULL; |
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52 case 1: |
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53 dst->params.regs.displacement = 0; |
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54 break; |
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55 case 2: |
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56 dst->params.regs.displacement = sign_extend16(*(cur++)); |
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57 break; |
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58 case 3: |
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59 tmp = *(cur++); |
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60 dst->params.regs.displacement = tmp << 16 | *(cur++); |
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61 break; |
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62 } |
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63 if (ext & 0x3) |
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64 { |
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65 //memory indirect |
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66 switch (ext & 0xC4) |
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67 { |
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68 case 0x00: |
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69 dst->addr_mode = MODE_AREG_PREINDEX; |
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70 break; |
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71 case 0x04: |
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72 dst->addr_mode = MODE_AREG_POSTINDEX; |
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73 break; |
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74 case 0x40: |
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75 dst->addr_mode = MODE_AREG_MEM_INDIRECT; |
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76 break; |
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77 case 0x80: |
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78 dst->addr_mode = MODE_PREINDEX; |
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79 break; |
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80 case 0x84: |
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81 dst->addr_mode = MODE_POSTINDEX; |
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82 break; |
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83 case 0xC0: |
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84 dst->addr_mode = MODE_MEM_INDIRECT; |
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85 break; |
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86 } |
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87 dst->params.regs.disp_sizes |= ext << 4 & 0x30; |
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88 switch (ext & 0x3) |
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89 { |
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90 case 0: |
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91 //reserved |
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92 return NULL; |
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93 case 1: |
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94 dst->params.regs.outer_disp = 0; |
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95 break; |
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96 case 2: |
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97 dst->params.regs.outer_disp = sign_extend16(*(cur++)); |
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98 break; |
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99 case 3: |
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100 tmp = *(cur++); |
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101 dst->params.regs.outer_disp = tmp << 16 | *(cur++); |
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102 break; |
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103 } |
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104 } else { |
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105 switch (ext >> 6 & 3) |
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106 { |
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107 case 0: |
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108 dst->addr_mode = MODE_AREG_INDEX_BASE_DISP; |
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109 break; |
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110 case 1: |
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111 dst->addr_mode = MODE_AREG_BASE_DISP; |
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112 break; |
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113 case 2: |
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114 dst->addr_mode = MODE_INDEX_BASE_DISP; |
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115 break; |
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116 case 3: |
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117 dst->addr_mode = MODE_BASE_DISP; |
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118 break; |
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119 } |
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120 } |
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121 } else { |
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122 #endif |
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123 dst->addr_mode = MODE_AREG_INDEX_DISP8; |
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124 dst->params.regs.displacement = sign_extend8(ext&0xFF); |
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125 #ifdef M68020 |
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126 } |
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127 #endif |
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128 break; |
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129 case MODE_PC_INDIRECT_ABS_IMMED: |
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130 switch(reg) |
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131 { |
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132 case 0: |
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133 dst->addr_mode = MODE_ABSOLUTE_SHORT; |
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134 ext = *(++cur); |
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135 dst->params.immed = sign_extend16(ext); |
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136 break; |
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137 case 1: |
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138 dst->addr_mode = MODE_ABSOLUTE; |
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139 ext = *(++cur); |
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140 dst->params.immed = ext << 16 | *(++cur); |
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141 break; |
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142 case 3: |
638
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143 ext = *(++cur); |
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144 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit |
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145 #ifdef M68020 |
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146 dst->params.regs.scale = ext >> 9 & 3; |
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147 if (ext & 0x100) |
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148 { |
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149 dst->params.regs.disp_sizes = ext >> 4 & 3; |
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150 switch (dst->params.regs.disp_sizes) |
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151 { |
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152 case 0: |
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153 //reserved |
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154 return NULL; |
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155 case 1: |
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156 dst->params.regs.displacement = 0; |
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157 break; |
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158 case 2: |
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159 dst->params.regs.displacement = sign_extend16(*(cur++)); |
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160 break; |
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161 case 3: |
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162 tmp = *(cur++); |
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163 dst->params.regs.displacement = tmp << 16 | *(cur++); |
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164 break; |
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165 } |
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166 if (ext & 0x3) |
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167 { |
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168 //memory indirect |
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169 switch (ext & 0xC4) |
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170 { |
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171 case 0x00: |
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172 dst->addr_mode = MODE_PC_PREINDEX; |
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173 break; |
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174 case 0x04: |
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175 dst->addr_mode = MODE_PC_POSTINDEX; |
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176 break; |
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177 case 0x40: |
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178 dst->addr_mode = MODE_PC_MEM_INDIRECT; |
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179 break; |
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180 case 0x80: |
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181 dst->addr_mode = MODE_ZPC_PREINDEX; |
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182 break; |
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183 case 0x84: |
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184 dst->addr_mode = MODE_ZPC_POSTINDEX; |
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185 break; |
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186 case 0xC0: |
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187 dst->addr_mode = MODE_ZPC_MEM_INDIRECT; |
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188 break; |
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189 } |
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190 dst->params.regs.disp_sizes |= ext << 4 & 0x30; |
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191 switch (ext & 0x3) |
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192 { |
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193 case 0: |
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194 //reserved |
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195 return NULL; |
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196 case 1: |
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197 dst->params.regs.outer_disp = 0; |
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198 break; |
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199 case 2: |
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200 dst->params.regs.outer_disp = sign_extend16(*(cur++)); |
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201 break; |
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202 case 3: |
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203 tmp = *(cur++); |
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204 dst->params.regs.outer_disp = tmp << 16 | *(cur++); |
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205 break; |
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206 } |
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207 } else { |
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208 switch (ext >> 6 & 3) |
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209 { |
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210 case 0: |
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211 dst->addr_mode = MODE_PC_INDEX_BASE_DISP; |
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212 break; |
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213 case 1: |
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214 dst->addr_mode = MODE_PC_BASE_DISP; |
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215 break; |
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216 case 2: |
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217 dst->addr_mode = MODE_ZPC_INDEX_BASE_DISP; |
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218 break; |
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219 case 3: |
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220 dst->addr_mode = MODE_ZPC_BASE_DISP; |
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221 break; |
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222 } |
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223 } |
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224 } else { |
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225 #endif |
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226 dst->addr_mode = MODE_PC_INDEX_DISP8; |
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227 dst->params.regs.displacement = sign_extend8(ext&0xFF); |
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228 #ifdef M68020 |
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229 } |
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230 #endif |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
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231 break; |
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232 case 2: |
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233 dst->addr_mode = MODE_PC_DISPLACE; |
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234 ext = *(++cur); |
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235 dst->params.regs.displacement = sign_extend16(ext); |
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236 break; |
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237 case 4: |
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238 dst->addr_mode = MODE_IMMEDIATE; |
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239 ext = *(++cur); |
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240 switch (size) |
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241 { |
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242 case OPSIZE_BYTE: |
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243 dst->params.immed = ext & 0xFF; |
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244 break; |
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245 case OPSIZE_WORD: |
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246 dst->params.immed = ext; |
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247 break; |
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248 case OPSIZE_LONG: |
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249 dst->params.immed = ext << 16 | *(++cur); |
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250 break; |
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251 } |
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252 break; |
176
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253 default: |
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254 return NULL; |
2
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255 } |
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256 break; |
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257 } |
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258 return cur; |
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259 } |
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260 |
823
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261 uint8_t m68k_valid_immed_dst(m68k_op_info *dst) |
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262 { |
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263 if (dst->addr_mode == MODE_AREG || dst->addr_mode == MODE_IMMEDIATE) { |
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264 return 0; |
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265 } |
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266 return 1; |
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267 } |
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268 |
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269 uint8_t m68k_valid_immed_limited_dst(m68k_op_info *dst) |
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270 { |
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271 if (dst->addr_mode == MODE_AREG || dst->addr_mode > MODE_ABSOLUTE) { |
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272 return 0; |
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273 } |
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274 return 1; |
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275 } |
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276 |
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277 uint8_t m68k_valid_movem_dst(m68k_op_info *dst) |
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278 { |
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279 if (dst->addr_mode == MODE_REG || dst->addr_mode == MODE_AREG_POSTINC) { |
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280 return 0; |
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281 } |
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282 return m68k_valid_immed_limited_dst(dst); |
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283 } |
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284 |
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285 uint16_t *m68k_decode_op(uint16_t *cur, uint8_t size, m68k_op_info *dst) |
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286 { |
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287 uint8_t mode = (*cur >> 3) & 0x7; |
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288 uint8_t reg = *cur & 0x7; |
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289 return m68k_decode_op_ex(cur, mode, reg, size, dst); |
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290 } |
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291 |
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292 void m68k_decode_cond(uint16_t op, m68kinst * decoded) |
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293 { |
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294 decoded->extra.cond = (op >> 0x8) & 0xF; |
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295 } |
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296 |
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297 uint8_t m68k_reg_quick_field(uint16_t op) |
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298 { |
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299 return (op >> 9) & 0x7; |
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300 } |
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301 |
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302 uint16_t * m68k_decode(uint16_t * istream, m68kinst * decoded, uint32_t address) |
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303 { |
176
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304 uint16_t *start = istream; |
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305 uint8_t optype = *istream >> 12; |
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306 uint8_t size; |
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307 uint8_t reg; |
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308 uint8_t opmode; |
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309 uint32_t immed; |
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310 decoded->op = M68K_INVALID; |
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311 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_UNUSED; |
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312 decoded->variant = VAR_NORMAL; |
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313 decoded->address = address; |
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314 switch(optype) |
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315 { |
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316 case BIT_MOVEP_IMMED: |
163 | 317 if ((*istream & 0x138) == 0x108) { |
318 //MOVEP | |
319 decoded->op = M68K_MOVEP; | |
320 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD; | |
321 if (*istream & 0x80) { | |
322 //memory dest | |
323 decoded->src.addr_mode = MODE_REG; | |
324 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); | |
325 decoded->dst.addr_mode = MODE_AREG_DISPLACE; | |
326 decoded->dst.params.regs.pri = *istream & 0x7; | |
327 decoded->dst.params.regs.displacement = *(++istream); | |
328 } else { | |
329 //memory source | |
330 decoded->dst.addr_mode = MODE_REG; | |
331 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); | |
332 decoded->src.addr_mode = MODE_AREG_DISPLACE; | |
333 decoded->src.params.regs.pri = *istream & 0x7; | |
334 decoded->src.params.regs.displacement = *(++istream); | |
335 } | |
336 } else if (*istream & 0x100) { | |
4
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337 //BTST, BCHG, BCLR, BSET |
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338 switch ((*istream >> 6) & 0x3) |
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339 { |
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340 case 0: |
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341 decoded->op = M68K_BTST; |
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342 break; |
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343 case 1: |
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344 decoded->op = M68K_BCHG; |
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345 break; |
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346 case 2: |
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347 decoded->op = M68K_BCLR; |
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348 break; |
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349 case 3: |
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350 decoded->op = M68K_BSET; |
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351 break; |
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352 } |
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353 decoded->src.addr_mode = MODE_REG; |
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354 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
61
918468c623e9
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355 decoded->extra.size = OPSIZE_BYTE; |
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356 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst)); |
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357 if ( |
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358 !istream || decoded->dst.addr_mode == MODE_AREG |
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359 || (decoded->op != M68K_BTST && !m68k_valid_immed_limited_dst(&decoded->dst)) |
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360 ) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
361 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
362 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
363 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
364 if (decoded->dst.addr_mode == MODE_REG) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
365 decoded->extra.size = OPSIZE_LONG; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
366 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
367 } else if ((*istream & 0xF00) == 0x800) { |
12
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
368 //BTST, BCHG, BCLR, BSET |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
369 switch ((*istream >> 6) & 0x3) |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
370 { |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
371 case 0: |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
372 decoded->op = M68K_BTST; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
373 break; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
374 case 1: |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
375 decoded->op = M68K_BCHG; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
376 break; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
377 case 2: |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
378 decoded->op = M68K_BCLR; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
379 break; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
380 case 3: |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
381 decoded->op = M68K_BSET; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
382 break; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
383 } |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
384 opmode = (*istream >> 3) & 0x7; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
385 reg = *istream & 0x7; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
386 decoded->src.addr_mode = MODE_IMMEDIATE_WORD; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
387 decoded->src.params.immed = *(++istream) & 0xFF; |
12
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
388 decoded->extra.size = OPSIZE_BYTE; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
389 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
390 if (!istream || !m68k_valid_immed_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
391 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
392 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
393 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
394 if (decoded->dst.addr_mode == MODE_REG) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
395 decoded->extra.size = OPSIZE_LONG; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
396 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
397 } else if ((*istream & 0xC0) == 0xC0) { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
398 #ifdef M68020 |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
399 //CMP2, CHK2, CAS, CAS2, RTM, CALLM |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
400 #endif |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
401 } else { |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
402 switch ((*istream >> 9) & 0x7) |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
403 { |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
404 case 0: |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
405 if ((*istream & 0xFF) == 0x3C) { |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
406 decoded->op = M68K_ORI_CCR; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
407 decoded->extra.size = OPSIZE_BYTE; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
408 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
409 decoded->src.params.immed = *(++istream) & 0xFF; |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
410 } else if((*istream & 0xFF) == 0x7C) { |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
411 decoded->op = M68K_ORI_SR; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
412 decoded->extra.size = OPSIZE_WORD; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
413 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
414 decoded->src.params.immed = *(++istream); |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
415 } else { |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
416 decoded->op = M68K_OR; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
417 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
418 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
419 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
420 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
421 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
422 switch (size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
423 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
424 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
425 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
426 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
427 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
428 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
429 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
430 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
431 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
432 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
433 break; |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
434 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
435 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
823
b1b5a7e7d955
Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
436 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
437 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
438 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
439 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
440 } |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
441 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
442 case 1: |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
443 //ANDI, ANDI to CCR, ANDI to SR |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
444 if ((*istream & 0xFF) == 0x3C) { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
445 decoded->op = M68K_ANDI_CCR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
446 decoded->extra.size = OPSIZE_BYTE; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
447 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
448 decoded->src.params.immed = *(++istream) & 0xFF; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
449 } else if((*istream & 0xFF) == 0x7C) { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
450 decoded->op = M68K_ANDI_SR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
451 decoded->extra.size = OPSIZE_WORD; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
452 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
453 decoded->src.params.immed = *(++istream); |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
454 } else { |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
455 decoded->op = M68K_AND; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
456 decoded->variant = VAR_IMMEDIATE; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
457 decoded->src.addr_mode = MODE_IMMEDIATE; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
458 decoded->extra.size = size = (*istream >> 6) & 3; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
459 reg = *istream & 0x7; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
460 opmode = (*istream >> 3) & 0x7; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
461 switch (size) |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
462 { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
463 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
464 decoded->src.params.immed = *(++istream) & 0xFF; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
465 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
466 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
467 decoded->src.params.immed = *(++istream); |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
468 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
469 case OPSIZE_LONG: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
470 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
471 decoded->src.params.immed = immed << 16 | *(++istream); |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
472 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
473 } |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
474 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
823
b1b5a7e7d955
Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
475 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
476 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
477 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
478 } |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
479 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
480 break; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
481 case 2: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
482 decoded->op = M68K_SUB; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
483 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
484 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
485 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
486 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
487 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
488 switch (size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
489 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
490 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
491 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
492 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
493 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
494 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
495 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
496 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
497 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
498 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
499 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
500 } |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
501 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
823
b1b5a7e7d955
Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
502 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
503 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
504 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
505 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
506 break; |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
507 case 3: |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
508 decoded->op = M68K_ADD; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
509 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
510 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
511 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
512 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
513 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
514 switch (size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
515 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
516 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
517 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
518 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
519 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
520 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
521 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
522 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
523 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
524 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
525 break; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
526 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
527 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
823
b1b5a7e7d955
Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
528 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
529 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
530 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
531 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
532 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
533 case 4: |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
534 //BTST, BCHG, BCLR, BSET |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
535 //Seems like this should be unnecessary since bit instructions are explicitly handled above |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
536 //Possible this is redundant or the case above is overly restrictive |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
537 //TODO: Investigate whether this can be removed |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
538 switch ((*istream >> 6) & 0x3) |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
539 { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
540 case 0: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
541 decoded->op = M68K_BTST; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
542 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
543 case 1: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
544 decoded->op = M68K_BCHG; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
545 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
546 case 2: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
547 decoded->op = M68K_BCLR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
548 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
549 case 3: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
550 decoded->op = M68K_BSET; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
551 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
552 } |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
553 decoded->src.addr_mode = MODE_IMMEDIATE_WORD; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
554 decoded->src.params.immed = *(++istream) & 0xFF; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
555 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
556 if ( |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
557 !istream || !m68k_valid_immed_dst(&decoded->dst) |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
558 || (decoded->op != M68K_BTST && !m68k_valid_immed_limited_dst(&decoded->dst)) |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
559 ) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
560 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
561 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
562 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
563 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
564 case 5: |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
565 //EORI, EORI to CCR, EORI to SR |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
566 if ((*istream & 0xFF) == 0x3C) { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
567 decoded->op = M68K_EORI_CCR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
568 decoded->extra.size = OPSIZE_BYTE; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
569 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
570 decoded->src.params.immed = *(++istream) & 0xFF; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
571 } else if((*istream & 0xFF) == 0x7C) { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
572 decoded->op = M68K_EORI_SR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
573 decoded->extra.size = OPSIZE_WORD; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
574 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
575 decoded->src.params.immed = *(++istream); |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
576 } else { |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
577 decoded->op = M68K_EOR; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
578 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
579 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
580 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
581 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
582 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
583 switch (size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
584 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
585 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
586 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
587 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
588 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
589 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
590 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
591 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
592 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
593 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
594 break; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
595 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
596 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
823
b1b5a7e7d955
Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
597 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
598 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
599 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
600 } |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
601 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
602 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
603 case 6: |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
604 decoded->op = M68K_CMP; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
605 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
606 decoded->extra.size = (*istream >> 6) & 0x3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
607 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
608 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
609 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
610 switch (decoded->extra.size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
611 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
612 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
613 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
614 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
615 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
616 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
617 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
618 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
619 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
620 decoded->src.params.immed = (immed << 16) | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
621 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
622 } |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
623 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
823
b1b5a7e7d955
Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
624 if (!istream || !m68k_valid_immed_dst(&(decoded->dst))) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
625 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
626 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
627 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
628 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
629 case 7: |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
630 #ifdef M68010 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
631 decoded->op = M68K_MOVES; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
632 decoded->extra.size = *istream >> 6 & 0x3; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
633 immed = *(++istream); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
634 reg = immed >> 12 & 0x7; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
635 opmode = immed & 0x8000 ? MODE_AREG : MODE_REG; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
636 if (immed & 0x800) { |
642
08d0e3e7d0d8
Fix interpretation of moves direction field
Michael Pavone <pavone@retrodev.com>
parents:
641
diff
changeset
|
637 decoded->src.addr_mode = opmode; |
08d0e3e7d0d8
Fix interpretation of moves direction field
Michael Pavone <pavone@retrodev.com>
parents:
641
diff
changeset
|
638 decoded->src.params.regs.pri = reg; |
08d0e3e7d0d8
Fix interpretation of moves direction field
Michael Pavone <pavone@retrodev.com>
parents:
641
diff
changeset
|
639 m68k_decode_op_ex(istream, *start >> 3 & 0x7, *start & 0x7, decoded->extra.size, &(decoded->dst)); |
08d0e3e7d0d8
Fix interpretation of moves direction field
Michael Pavone <pavone@retrodev.com>
parents:
641
diff
changeset
|
640 } else { |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
641 m68k_decode_op_ex(istream, *start >> 3 & 0x7, *start & 0x7, decoded->extra.size, &(decoded->src)); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
642 decoded->dst.addr_mode = opmode; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
643 decoded->dst.params.regs.pri = reg; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
644 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
645 #endif |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
646 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
647 } |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
648 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
649 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
650 case MOVE_BYTE: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
651 case MOVE_LONG: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
652 case MOVE_WORD: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
653 decoded->op = M68K_MOVE; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
654 decoded->extra.size = optype == MOVE_BYTE ? OPSIZE_BYTE : (optype == MOVE_WORD ? OPSIZE_WORD : OPSIZE_LONG); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
655 opmode = (*istream >> 6) & 0x7; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
656 reg = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
657 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
658 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
659 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
660 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
661 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
662 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
663 if (!istream || decoded->dst.addr_mode > MODE_ABSOLUTE || (decoded->dst.addr_mode == MODE_AREG && optype == MOVE_BYTE)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
664 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
665 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
666 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
667 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
668 case MISC: |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
669 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
670 if ((*istream & 0x1C0) == 0x1C0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
671 decoded->op = M68K_LEA; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
672 decoded->extra.size = OPSIZE_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
673 decoded->dst.addr_mode = MODE_AREG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
674 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
675 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
1277
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
676 if ( |
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
677 !istream || decoded->src.addr_mode == MODE_REG || decoded->src.addr_mode == MODE_AREG |
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
678 || decoded->src.addr_mode == MODE_AREG_POSTINC || decoded->src.addr_mode == MODE_AREG_PREDEC |
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
679 || decoded->src.addr_mode == MODE_IMMEDIATE |
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
680 ) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
681 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
682 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
683 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
684 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
685 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
686 decoded->op = M68K_CHK; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
687 if ((*istream & 0x180) == 0x180) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
688 decoded->extra.size = OPSIZE_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
689 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
690 //only on M68020+ |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
691 #ifdef M68020 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
692 decoded->extra.size = OPSIZE_LONG; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
693 #else |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
694 decoded->op = M68K_INVALID; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
695 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
696 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
697 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
698 decoded->dst.addr_mode = MODE_REG; |
325
8db584faac4b
Fixed decoding of CHK destination
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
699 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
700 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
701 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
702 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
703 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
704 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
705 } else { |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
706 opmode = (*istream >> 3) & 0x7; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
707 if ((*istream & 0xB80) == 0x880 && opmode != MODE_REG && opmode != MODE_AREG) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
708 //TODO: Check for invalid modes that are dependent on direction |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
709 decoded->op = M68K_MOVEM; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
710 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
711 reg = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
712 if(*istream & 0x400) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
713 decoded->dst.addr_mode = MODE_REG; |
68
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
714 decoded->dst.params.immed = *(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
715 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->src)); |
1253
2a6049dddab0
immediate and predecrement are illegal source address modes for movem. Fixes ticket:8 and ticket:9
Michael Pavone <pavone@retrodev.com>
parents:
1226
diff
changeset
|
716 if (!istream || decoded->src.addr_mode == MODE_AREG_PREDEC || decoded->src.addr_mode == MODE_IMMEDIATE) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
717 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
718 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
719 } |
412
00d5a2b532f4
Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents:
325
diff
changeset
|
720 if (decoded->src.addr_mode == MODE_PC_DISPLACE || decoded->src.addr_mode == MODE_PC_INDEX_DISP8) { |
00d5a2b532f4
Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents:
325
diff
changeset
|
721 //adjust displacement to account for extra instruction word |
00d5a2b532f4
Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents:
325
diff
changeset
|
722 decoded->src.params.regs.displacement += 2; |
00d5a2b532f4
Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents:
325
diff
changeset
|
723 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
724 } else { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
725 decoded->src.addr_mode = MODE_REG; |
68
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
726 decoded->src.params.immed = *(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
727 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
728 if (!istream || !m68k_valid_movem_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
729 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
730 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
731 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
732 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
733 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
734 optype = (*istream >> 9) & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
735 size = (*istream >> 6) & 0x3; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
736 switch(optype) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
737 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
738 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
739 //Move from SR or NEGX |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
740 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
741 decoded->op = M68K_MOVE_FROM_SR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
742 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
743 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
744 decoded->op = M68K_NEGX; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
745 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
746 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
747 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
748 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
749 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
750 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
751 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
752 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
753 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
754 //MOVE from CCR or CLR |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
755 if (size == OPSIZE_INVALID) { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
756 #ifdef M68010 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
757 decoded->op = M68K_MOVE_FROM_CCR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
758 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
759 #else |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
760 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
761 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
762 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
763 decoded->op = M68K_CLR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
764 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
765 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
766 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
767 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
768 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
769 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
770 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
771 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
772 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
773 //MOVE to CCR or NEG |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
774 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
775 decoded->op = M68K_MOVE_CCR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
776 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
777 istream= m68k_decode_op(istream, size, &(decoded->src)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
778 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
779 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
780 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
781 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
782 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
783 decoded->op = M68K_NEG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
784 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
785 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
786 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
787 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
788 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
789 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
790 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
791 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
792 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
793 //MOVE to SR or NOT |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
794 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
795 decoded->op = M68K_MOVE_SR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
796 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
797 istream= m68k_decode_op(istream, size, &(decoded->src)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
798 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
799 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
800 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
801 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
802 } else { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
803 decoded->op = M68K_NOT; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
804 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
805 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
806 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
807 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
808 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
809 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
810 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
811 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
812 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
813 //EXT, EXTB, LINK.l, NBCD, SWAP, BKPT, PEA |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
814 switch((*istream >> 3) & 0x3F) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
815 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
816 case 1: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
817 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
818 decoded->op = M68K_LINK; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
819 decoded->extra.size = OPSIZE_LONG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
820 reg = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
821 immed = *(++istream) << 16; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
822 immed |= *(++istream); |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
823 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
824 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
825 case 8: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
826 decoded->op = M68K_SWAP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
827 decoded->src.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
828 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
829 decoded->extra.size = OPSIZE_WORD; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
830 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
831 case 9: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
832 #ifdef M68010 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
833 decoded->op = M68K_BKPT; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
834 decoded->src.addr_mode = MODE_IMMEDIATE; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
835 decoded->extra.size = OPSIZE_UNSIZED; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
836 decoded->src.params.immed = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
837 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
838 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
839 case 0x10: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
840 decoded->op = M68K_EXT; |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
841 decoded->dst.addr_mode = MODE_REG; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
842 decoded->dst.params.regs.pri = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
843 decoded->extra.size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
844 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
845 case 0x18: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
846 decoded->op = M68K_EXT; |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
847 decoded->dst.addr_mode = MODE_REG; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
848 decoded->dst.params.regs.pri = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
849 decoded->extra.size = OPSIZE_LONG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
850 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
851 case 0x38: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
852 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
853 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
854 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
855 default: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
856 if (!(*istream & 0x1C0)) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
857 decoded->op = M68K_NBCD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
858 decoded->extra.size = OPSIZE_BYTE; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
859 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
860 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
861 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
862 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
863 } |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
864 } else if((*istream & 0x1C0) == 0x40) { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
865 decoded->op = M68K_PEA; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
866 decoded->extra.size = OPSIZE_LONG; |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
111
diff
changeset
|
867 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src)); |
1277
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
868 if ( |
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
869 !istream || decoded->src.addr_mode == MODE_REG || decoded->src.addr_mode == MODE_AREG |
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
870 || decoded->src.addr_mode == MODE_AREG_POSTINC || decoded->src.addr_mode == MODE_AREG_PREDEC |
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
871 || decoded->src.addr_mode == MODE_IMMEDIATE |
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
872 ) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
873 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
874 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
875 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
876 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
877 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
878 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
879 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
880 //BGND, ILLEGAL, TAS, TST |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
881 optype = *istream & 0xFF; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
882 if (optype == 0xFA) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
883 //BGND - CPU32 only |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
884 } else if (optype == 0xFC) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
885 decoded->op = M68K_ILLEGAL; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
886 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
887 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
888 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
889 decoded->op = M68K_TAS; |
835
b4cf6573a3f8
Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents:
823
diff
changeset
|
890 decoded->extra.size = OPSIZE_BYTE; |
b4cf6573a3f8
Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents:
823
diff
changeset
|
891 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst)); |
b4cf6573a3f8
Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents:
823
diff
changeset
|
892 if (!istream) { |
b4cf6573a3f8
Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents:
823
diff
changeset
|
893 decoded->op = M68K_INVALID; |
b4cf6573a3f8
Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents:
823
diff
changeset
|
894 break; |
b4cf6573a3f8
Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents:
823
diff
changeset
|
895 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
896 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
897 decoded->op = M68K_TST; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
898 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
899 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
900 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
901 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
902 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
903 } |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
904 #ifndef M68020 |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
905 if (!m68k_valid_immed_limited_dst(&decoded->src)) { |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
906 decoded->op = M68K_INVALID; |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
907 break; |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
908 } |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
909 #endif |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
910 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
911 } |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
912 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
913 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
914 //MULU, MULS, DIVU, DIVUL, DIVS, DIVSL |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
915 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
916 //TODO: Implement these for 68020+ support |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
917 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
918 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
919 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
920 //TRAP, LINK.w, UNLNK, MOVE USP, RESET, NOP, STOP, RTE, RTD, RTS, TRAPV, RTR, MOVEC, JSR, JMP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
921 if (*istream & 0x80) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
922 //JSR, JMP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
923 if (*istream & 0x40) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
924 decoded->op = M68K_JMP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
925 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
926 decoded->op = M68K_JSR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
927 } |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
928 decoded->extra.size = OPSIZE_UNSIZED; |
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
929 istream = m68k_decode_op(istream, OPSIZE_UNSIZED, &(decoded->src)); |
1345
696a029d09e9
Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents:
1330
diff
changeset
|
930 if ( |
696a029d09e9
Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents:
1330
diff
changeset
|
931 !istream |
696a029d09e9
Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents:
1330
diff
changeset
|
932 || (decoded->src.addr_mode < MODE_AREG_DISPLACE && decoded->src.addr_mode != MODE_AREG_INDIRECT) |
696a029d09e9
Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents:
1330
diff
changeset
|
933 || decoded->src.addr_mode == MODE_IMMEDIATE |
696a029d09e9
Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents:
1330
diff
changeset
|
934 ) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
935 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
936 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
937 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
938 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
939 //it would appear bit 6 needs to be set for it to be a valid instruction here |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
940 switch((*istream >> 3) & 0x7) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
941 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
942 case 0: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
943 case 1: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
944 //TRAP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
945 decoded->op = M68K_TRAP; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
946 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
947 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
948 decoded->src.params.immed = *istream & 0xF; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
949 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
950 case 2: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
951 //LINK.w |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
952 decoded->op = M68K_LINK; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
953 decoded->extra.size = OPSIZE_WORD; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
954 decoded->src.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
955 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
956 decoded->dst.addr_mode = MODE_IMMEDIATE; |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
957 decoded->dst.params.immed = sign_extend16(*(++istream)); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
958 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
959 case 3: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
960 //UNLK |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
961 decoded->op = M68K_UNLK; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
962 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
963 decoded->dst.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
964 decoded->dst.params.regs.pri = *istream & 0x7; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
965 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
966 case 4: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
967 case 5: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
968 //MOVE USP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
969 decoded->op = M68K_MOVE_USP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
970 if (*istream & 0x8) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
971 decoded->dst.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
972 decoded->dst.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
973 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
974 decoded->src.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
975 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
976 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
977 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
978 case 6: |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
979 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
980 switch(*istream & 0x7) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
981 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
982 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
983 decoded->op = M68K_RESET; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
984 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
985 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
986 decoded->op = M68K_NOP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
987 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
988 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
989 decoded->op = M68K_STOP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
990 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
991 decoded->src.params.immed =*(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
992 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
993 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
994 decoded->op = M68K_RTE; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
995 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
996 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
997 #ifdef M68010 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
998 decoded->op = M68K_RTD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
999 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1000 decoded->src.params.immed =*(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1001 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1002 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1003 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1004 decoded->op = M68K_RTS; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1005 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1006 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1007 decoded->op = M68K_TRAPV; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1008 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1009 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1010 decoded->op = M68K_RTR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1011 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1012 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1013 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1014 case 7: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1015 //MOVEC |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1016 #ifdef M68010 |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1017 decoded->op = M68K_MOVEC; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1018 immed = *(++istream); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1019 reg = immed >> 12 & 0x7; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1020 opmode = immed & 0x8000 ? MODE_AREG : MODE_REG; |
641 | 1021 immed &= 0xFFF; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1022 if (immed & 0x800) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1023 if (immed > MAX_HIGH_CR) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1024 decoded->op = M68K_INVALID; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1025 break; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1026 } else { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1027 immed = immed - 0x800 + CR_USP; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1028 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1029 } else { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1030 if (immed > MAX_LOW_CR) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1031 decoded->op = M68K_INVALID; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1032 break; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1033 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1034 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1035 if (*start & 1) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1036 decoded->src.addr_mode = opmode; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1037 decoded->src.params.regs.pri = reg; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1038 decoded->dst.params.immed = immed; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1039 } else { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1040 decoded->dst.addr_mode = opmode; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1041 decoded->dst.params.regs.pri = reg; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1042 decoded->src.params.immed = immed; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1043 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1044 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1045 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1046 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1047 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1048 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1049 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1050 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1051 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1052 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1053 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1054 case QUICK_ARITH_LOOP: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1055 size = (*istream >> 6) & 3; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1056 if (size == 0x3) { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1057 //DBcc, TRAPcc or Scc |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1058 m68k_decode_cond(*istream, decoded); |
111 | 1059 if (((*istream >> 3) & 0x7) == 1) { |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1060 decoded->op = M68K_DBCC; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1061 decoded->src.addr_mode = MODE_IMMEDIATE; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1062 decoded->dst.addr_mode = MODE_REG; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1063 decoded->dst.params.regs.pri = *istream & 0x7; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
1064 decoded->src.params.immed = sign_extend16(*(++istream)); |
111 | 1065 } else if(((*istream >> 3) & 0x7) == 1 && (*istream & 0x7) > 1 && (*istream & 0x7) < 5) { |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1066 #ifdef M68020 |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1067 decoded->op = M68K_TRAPCC; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1068 decoded->src.addr_mode = MODE_IMMEDIATE; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1069 //TODO: Figure out what to do with OPMODE and optional extention words |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1070 #endif |
111 | 1071 } else { |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1072 decoded->op = M68K_SCC; |
111 | 1073 decoded->extra.cond = (*istream >> 8) & 0xF; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1074 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1075 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1076 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1077 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1078 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1079 } |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1080 } else { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1081 //ADDQ, SUBQ |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1082 decoded->variant = VAR_QUICK; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1083 decoded->extra.size = size; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1084 decoded->src.addr_mode = MODE_IMMEDIATE; |
91
8c446fc19cc0
Fix decoding bug in addq/subq
Mike Pavone <pavone@retrodev.com>
parents:
90
diff
changeset
|
1085 immed = m68k_reg_quick_field(*istream); |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1086 if (!immed) { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1087 immed = 8; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1088 } |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1089 decoded->src.params.immed = immed; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1090 if (*istream & 0x100) { |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1091 decoded->op = M68K_SUB; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1092 } else { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1093 decoded->op = M68K_ADD; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1094 } |
94
a668a35a3463
Fix decoding bug for addq/subq
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
1095 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1096 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1097 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1098 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1099 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1100 } |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1101 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1102 case BRANCH: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1103 m68k_decode_cond(*istream, decoded); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1104 decoded->op = decoded->extra.cond == COND_FALSE ? M68K_BSR : M68K_BCC; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1105 decoded->src.addr_mode = MODE_IMMEDIATE; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1106 immed = *istream & 0xFF; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1107 if (immed == 0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1108 decoded->variant = VAR_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1109 immed = *(++istream); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1110 immed = sign_extend16(immed); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
140
diff
changeset
|
1111 #ifdef M68020 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1112 } else if (immed == 0xFF) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1113 decoded->variant = VAR_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1114 immed = *(++istream) << 16; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1115 immed |= *(++istream); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
140
diff
changeset
|
1116 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1117 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1118 decoded->variant = VAR_BYTE; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1119 immed = sign_extend8(immed); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1120 } |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1121 decoded->src.params.immed = immed; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1122 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1123 case MOVEQ: |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
197
diff
changeset
|
1124 if (*istream & 0x100) { |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
197
diff
changeset
|
1125 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1126 break; |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
197
diff
changeset
|
1127 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1128 decoded->op = M68K_MOVE; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1129 decoded->variant = VAR_QUICK; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1130 decoded->extra.size = OPSIZE_LONG; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1131 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1132 decoded->src.params.immed = sign_extend8(*istream & 0xFF); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1133 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1134 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1135 immed = *istream & 0xFF; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1136 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1137 case OR_DIV_SBCD: |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1138 //for OR, if opmode bit 2 is 1, then src = Dn, dst = <ea> |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1139 opmode = (*istream >> 6) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1140 size = opmode & 0x3; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1141 if (size == OPSIZE_INVALID || (opmode & 0x4 && !(*istream & 0x30))) { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1142 switch(opmode) |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1143 { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1144 case 3: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1145 decoded->op = M68K_DIVU; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1146 decoded->extra.size = OPSIZE_WORD; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1147 decoded->dst.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1148 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1149 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
183
2f08d9e90a4c
Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
1150 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1151 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1152 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1153 } |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1154 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1155 case 4: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1156 decoded->op = M68K_SBCD; |
613
09d5adf8d1ca
Fix opsize for sbcd in 68K instruction decoder. This fixes the timer bug in Strider 2
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1157 decoded->extra.size = OPSIZE_BYTE; |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1158 decoded->dst.addr_mode = decoded->src.addr_mode = *istream & 0x8 ? MODE_AREG_PREDEC : MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1159 decoded->src.params.regs.pri = *istream & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1160 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1161 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1162 case 5: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1163 #ifdef M68020 |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1164 #endif |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1165 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1166 case 6: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1167 #ifdef M68020 |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1168 #endif |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1169 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1170 case 7: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1171 decoded->op = M68K_DIVS; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1172 decoded->extra.size = OPSIZE_WORD; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1173 decoded->dst.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1174 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1175 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
183
2f08d9e90a4c
Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
1176 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1177 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1178 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1179 } |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1180 break; |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1181 } |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1182 } else { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1183 decoded->op = M68K_OR; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1184 decoded->extra.size = size; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1185 if (opmode & 0x4) { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1186 decoded->src.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1187 decoded->src.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1188 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
1218
054472ea077a
Properly treat bad addressing modes in OR/AND as illegal instructions
Michael Pavone <pavone@retrodev.com>
parents:
992
diff
changeset
|
1189 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1190 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1191 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1192 } |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1193 } else { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1194 decoded->dst.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1195 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1196 istream = m68k_decode_op(istream, size, &(decoded->src)); |
1218
054472ea077a
Properly treat bad addressing modes in OR/AND as illegal instructions
Michael Pavone <pavone@retrodev.com>
parents:
992
diff
changeset
|
1197 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1198 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1199 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1200 } |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1201 } |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1202 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1203 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1204 case SUB_SUBX: |
101
d7789186ba5e
Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
1205 size = (*istream >> 6) & 0x3; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1206 decoded->op = M68K_SUB; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1207 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1208 //<ea> destination, SUBA.l or SUBX |
101
d7789186ba5e
Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
1209 if (*istream & 0x30 || size == OPSIZE_INVALID) { |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1210 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1211 //SUBA.l |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1212 decoded->extra.size = OPSIZE_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1213 decoded->dst.addr_mode = MODE_AREG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1214 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1215 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1216 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1217 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1218 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1219 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1220 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1221 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1222 decoded->src.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1223 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1224 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1225 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1226 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1227 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1228 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1229 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1230 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1231 //SUBX |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1232 decoded->op = M68K_SUBX; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1233 decoded->extra.size = size; |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1234 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1235 decoded->src.params.regs.pri = *istream & 0x7; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1236 if (*istream & 0x8) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1237 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_AREG_PREDEC; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1238 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1239 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_REG; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1240 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1241 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1242 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1243 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1244 //SUBA.w |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1245 decoded->extra.size = OPSIZE_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1246 decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1247 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1248 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1249 decoded->dst.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1250 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1251 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1252 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1253 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1254 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1255 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1256 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1257 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1258 break; |
992
261995d06897
Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1259 case A_LINE: |
261995d06897
Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1260 decoded->op = M68K_A_LINE_TRAP; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1261 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1262 case CMP_XOR: |
120 | 1263 size = (*istream >> 6) & 0x3; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1264 decoded->op = M68K_CMP; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1265 if (*istream & 0x100) { |
120 | 1266 //CMPM or CMPA.l or EOR |
1267 if (size == OPSIZE_INVALID) { | |
1268 decoded->extra.size = OPSIZE_LONG; | |
1269 decoded->dst.addr_mode = MODE_AREG; | |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1270 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
136
e64554246d11
Fix some bugs in decoding cmp
Mike Pavone <pavone@retrodev.com>
parents:
134
diff
changeset
|
1271 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1272 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1273 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1274 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1275 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1276 } else { |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1277 reg = m68k_reg_quick_field(*istream); |
120 | 1278 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1279 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1280 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1281 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1282 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
1283 decoded->extra.size = size; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
1284 if (decoded->dst.addr_mode == MODE_AREG) { |
120 | 1285 //CMPM |
1286 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG_POSTINC; | |
1287 decoded->src.params.regs.pri = decoded->dst.params.regs.pri; | |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1288 decoded->dst.params.regs.pri = reg; |
120 | 1289 } else { |
1290 //EOR | |
1291 decoded->op = M68K_EOR; | |
1292 decoded->src.addr_mode = MODE_REG; | |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1293 decoded->src.params.regs.pri = reg; |
120 | 1294 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1295 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1296 } else { |
120 | 1297 //CMP or CMPA.w |
1298 if (size == OPSIZE_INVALID) { | |
1299 decoded->extra.size = OPSIZE_WORD; | |
1300 decoded->dst.addr_mode = MODE_AREG; | |
1301 } else { | |
1302 decoded->extra.size = size; | |
1303 decoded->dst.addr_mode = MODE_REG; | |
1304 } | |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1305 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
136
e64554246d11
Fix some bugs in decoding cmp
Mike Pavone <pavone@retrodev.com>
parents:
134
diff
changeset
|
1306 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1307 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1308 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1309 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1310 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1311 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1312 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1313 case AND_MUL_ABCD_EXG: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1314 //page 575 for summary |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1315 //EXG opmodes: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1316 //01000 -data regs |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1317 //01001 -addr regs |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1318 //10001 -one of each |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1319 //AND opmodes: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1320 //operand order bit + 2 size bits (00 - 10) |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1321 //no address register direct addressing |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1322 //data register direct not allowed when <ea> is the source (operand order bit of 1) |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1323 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1324 if ((*istream & 0xC0) == 0xC0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1325 decoded->op = M68K_MULS; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1326 decoded->extra.size = OPSIZE_WORD; |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1327 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1328 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1329 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1330 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1331 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1332 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1333 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1334 } else if(!(*istream & 0xF0)) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1335 decoded->op = M68K_ABCD; |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1336 decoded->extra.size = OPSIZE_BYTE; |
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1337 decoded->src.params.regs.pri = *istream & 0x7; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1338 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1339 decoded->dst.addr_mode = decoded->src.addr_mode = (*istream & 8) ? MODE_AREG_PREDEC : MODE_REG; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1340 } else if(!(*istream & 0x30)) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1341 decoded->op = M68K_EXG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1342 decoded->extra.size = OPSIZE_LONG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1343 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1344 decoded->dst.params.regs.pri = *istream & 0x7; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1345 if (*istream & 0x8) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1346 if (*istream & 0x80) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1347 decoded->src.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1348 decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1349 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1350 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1351 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1352 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1353 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1354 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1355 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1356 decoded->op = M68K_AND; |
90 | 1357 decoded->extra.size = (*istream >> 6) & 0x3; |
60
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1358 decoded->src.addr_mode = MODE_REG; |
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1359 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1360 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst)); |
1218
054472ea077a
Properly treat bad addressing modes in OR/AND as illegal instructions
Michael Pavone <pavone@retrodev.com>
parents:
992
diff
changeset
|
1361 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1362 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1363 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1364 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1365 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1366 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1367 if ((*istream & 0xC0) == 0xC0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1368 decoded->op = M68K_MULU; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1369 decoded->extra.size = OPSIZE_WORD; |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1370 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1371 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1372 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1373 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1374 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1375 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1376 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1377 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1378 decoded->op = M68K_AND; |
90 | 1379 decoded->extra.size = (*istream >> 6) & 0x3; |
60
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1380 decoded->dst.addr_mode = MODE_REG; |
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1381 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1382 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
1218
054472ea077a
Properly treat bad addressing modes in OR/AND as illegal instructions
Michael Pavone <pavone@retrodev.com>
parents:
992
diff
changeset
|
1383 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1384 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1385 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1386 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1387 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1388 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1389 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1390 case ADD_ADDX: |
101
d7789186ba5e
Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
1391 size = (*istream >> 6) & 0x3; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1392 decoded->op = M68K_ADD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1393 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1394 //<ea> destination, ADDA.l or ADDX |
101
d7789186ba5e
Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
1395 if (*istream & 0x30 || size == OPSIZE_INVALID) { |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1396 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1397 //ADDA.l |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1398 decoded->extra.size = OPSIZE_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1399 decoded->dst.addr_mode = MODE_AREG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1400 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1401 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1402 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1403 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1404 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1405 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1406 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1407 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1408 decoded->src.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1409 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1410 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1411 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1412 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1413 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1414 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1415 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1416 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1417 //ADDX |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1418 decoded->op = M68K_ADDX; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1419 decoded->extra.size = size; |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1420 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1421 decoded->src.params.regs.pri = *istream & 0x7; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1422 if (*istream & 0x8) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1423 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_AREG_PREDEC; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1424 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1425 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_REG; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1426 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1427 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1428 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1429 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1430 //ADDA.w |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1431 decoded->extra.size = OPSIZE_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1432 decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1433 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1434 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1435 decoded->dst.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1436 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1437 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1438 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1439 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1440 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1441 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1442 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1443 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1444 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1445 case SHIFT_ROTATE: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1446 if ((*istream & 0x8C0) == 0xC0) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1447 switch((*istream >> 8) & 0x7) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1448 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1449 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1450 decoded->op = M68K_ASR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1451 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1452 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1453 decoded->op = M68K_ASL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1454 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1455 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1456 decoded->op = M68K_LSR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1457 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1458 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1459 decoded->op = M68K_LSL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1460 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1461 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1462 decoded->op = M68K_ROXR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1463 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1464 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1465 decoded->op = M68K_ROXL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1466 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1467 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1468 decoded->op = M68K_ROR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1469 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1470 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1471 decoded->op = M68K_ROL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1472 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1473 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1474 decoded->extra.size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1475 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1476 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1477 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1478 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1479 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1480 } else if((*istream & 0xC0) != 0xC0) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1481 switch(((*istream >> 2) & 0x6) | ((*istream >> 8) & 1)) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1482 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1483 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1484 decoded->op = M68K_ASR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1485 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1486 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1487 decoded->op = M68K_ASL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1488 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1489 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1490 decoded->op = M68K_LSR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1491 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1492 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1493 decoded->op = M68K_LSL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1494 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1495 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1496 decoded->op = M68K_ROXR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1497 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1498 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1499 decoded->op = M68K_ROXL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1500 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1501 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1502 decoded->op = M68K_ROR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1503 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1504 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1505 decoded->op = M68K_ROL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1506 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1507 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1508 decoded->extra.size = (*istream >> 6) & 0x3; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1509 immed = (*istream >> 9) & 0x7; |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
50
diff
changeset
|
1510 if (*istream & 0x20) { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1511 decoded->src.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1512 decoded->src.params.regs.pri = immed; |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1513 } else { |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1514 decoded->src.addr_mode = MODE_IMMEDIATE; |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1515 if (!immed) { |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1516 immed = 8; |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1517 } |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1518 decoded->src.params.immed = immed; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1519 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1520 decoded->dst.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1521 decoded->dst.params.regs.pri = *istream & 0x7; |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1522 |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1523 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1524 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1525 //TODO: Implement bitfield instructions for M68020+ support |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1526 switch (*istream >> 8 & 7) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1527 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1528 case 0: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1529 decoded->op = M68K_BFTST; //<ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1530 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1531 case 1: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1532 decoded->op = M68K_BFEXTU; //<ea>, Dn |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1533 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1534 case 2: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1535 decoded->op = M68K_BFCHG; //<ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1536 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1537 case 3: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1538 decoded->op = M68K_BFEXTS; //<ea>, Dn |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1539 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1540 case 4: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1541 decoded->op = M68K_BFCLR; //<ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1542 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1543 case 5: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1544 decoded->op = M68K_BFFFO; //<ea>, Dn |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1545 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1546 case 6: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1547 decoded->op = M68K_BFSET; //<ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1548 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1549 case 7: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1550 decoded->op = M68K_BFINS; //Dn, <ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1551 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1552 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1553 opmode = *istream >> 3 & 0x7; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1554 reg = *istream & 0x7; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1555 m68k_op_info *ea, *other; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1556 if (decoded->op == M68K_BFEXTU || decoded->op == M68K_BFEXTS || decoded->op == M68K_BFFFO) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1557 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1558 ea = &(decoded->src); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1559 other = &(decoded->dst); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1560 } else { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1561 ea = &(decoded->dst); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1562 other = &(decoded->dst); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1563 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1564 if (*istream & 0x100) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1565 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1566 immed = *(istream++); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1567 other->addr_mode = MODE_REG; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1568 other->params.regs.pri = immed >> 12 & 0x7; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1569 } else { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1570 immed = *(istream++); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1571 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1572 decoded->extra.size = OPSIZE_UNSIZED; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1573 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, ea); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1574 ea->addr_mode |= M68K_FLAG_BITFIELD; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1575 ea->bitfield = immed & 0xFFF; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1576 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1577 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1578 break; |
992
261995d06897
Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1579 case F_LINE: |
261995d06897
Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1580 //TODO: Decode FPU instructions for members of the 68K family with an FPU |
261995d06897
Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1581 decoded->op = M68K_F_LINE_TRAP; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1582 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1583 } |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1584 if (decoded->op == M68K_INVALID) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1585 decoded->src.params.immed = *start; |
981
902c53d9c16f
Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
835
diff
changeset
|
1586 decoded->bytes = 2; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1587 return start + 1; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1588 } |
981
902c53d9c16f
Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
835
diff
changeset
|
1589 decoded->bytes = 2 * (istream + 1 - start); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1590 return istream+1; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1591 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1592 |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1593 uint32_t m68k_branch_target(m68kinst * inst, uint32_t *dregs, uint32_t *aregs) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1594 { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1595 if(inst->op == M68K_BCC || inst->op == M68K_BSR || inst->op == M68K_DBCC) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1596 return inst->address + 2 + inst->src.params.immed; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1597 } else if(inst->op == M68K_JMP || inst->op == M68K_JSR) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1598 uint32_t ret = 0; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1599 switch(inst->src.addr_mode) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1600 { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1601 case MODE_AREG_INDIRECT: |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1602 ret = aregs[inst->src.params.regs.pri]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1603 break; |
1330
af26a1ce92f7
Handle address register displacement when calculating branch targets in debugger
Michael Pavone <pavone@retrodev.com>
parents:
1277
diff
changeset
|
1604 case MODE_AREG_DISPLACE: |
af26a1ce92f7
Handle address register displacement when calculating branch targets in debugger
Michael Pavone <pavone@retrodev.com>
parents:
1277
diff
changeset
|
1605 ret = aregs[inst->src.params.regs.pri] + inst->src.params.regs.displacement; |
af26a1ce92f7
Handle address register displacement when calculating branch targets in debugger
Michael Pavone <pavone@retrodev.com>
parents:
1277
diff
changeset
|
1606 break; |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1607 case MODE_AREG_INDEX_DISP8: { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1608 uint8_t sec_reg = inst->src.params.regs.sec >> 1 & 0x7; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1609 ret = aregs[inst->src.params.regs.pri]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1610 uint32_t * regfile = inst->src.params.regs.sec & 0x10 ? aregs : dregs; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1611 if (inst->src.params.regs.sec & 1) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1612 //32-bit index register |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1613 ret += regfile[sec_reg]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1614 } else { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1615 //16-bit index register |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1616 if (regfile[sec_reg] & 0x8000) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1617 ret += (0xFFFF0000 | regfile[sec_reg]); |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1618 } else { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1619 ret += regfile[sec_reg]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1620 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1621 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1622 ret += inst->src.params.regs.displacement; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1623 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1624 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1625 case MODE_PC_DISPLACE: |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1626 ret = inst->src.params.regs.displacement + inst->address + 2; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1627 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1628 case MODE_PC_INDEX_DISP8: { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1629 uint8_t sec_reg = inst->src.params.regs.sec >> 1 & 0x7; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1630 ret = inst->address + 2; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1631 uint32_t * regfile = inst->src.params.regs.sec & 0x10 ? aregs : dregs; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1632 if (inst->src.params.regs.sec & 1) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1633 //32-bit index register |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1634 ret += regfile[sec_reg]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1635 } else { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1636 //16-bit index register |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1637 if (regfile[sec_reg] & 0x8000) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1638 ret += (0xFFFF0000 | regfile[sec_reg]); |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1639 } else { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1640 ret += regfile[sec_reg]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1641 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1642 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1643 ret += inst->src.params.regs.displacement; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1644 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1645 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1646 case MODE_ABSOLUTE: |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1647 case MODE_ABSOLUTE_SHORT: |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1648 ret = inst->src.params.immed; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1649 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1650 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1651 return ret; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1652 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1653 return 0; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1654 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1655 |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1656 uint8_t m68k_is_branch(m68kinst * inst) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1657 { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1658 return (inst->op == M68K_BCC && inst->extra.cond != COND_FALSE) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1659 || (inst->op == M68K_DBCC && inst->extra.cond != COND_TRUE) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1660 || inst->op == M68K_BSR || inst->op == M68K_JMP || inst->op == M68K_JSR; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1661 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1662 |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1663 uint8_t m68k_is_noncall_branch(m68kinst * inst) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1664 { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1665 return m68k_is_branch(inst) && inst->op != M68K_BSR && inst->op != M68K_JSR; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1666 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1667 |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1668 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1669 char * mnemonics[] = { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1670 "abcd", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1671 "add", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1672 "addx", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1673 "and", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1674 "andi",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1675 "andi",//sr |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1676 "asl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1677 "asr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1678 "bcc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1679 "bchg", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1680 "bclr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1681 "bset", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1682 "bsr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1683 "btst", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1684 "chk", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1685 "clr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1686 "cmp", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1687 "dbcc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1688 "divs", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1689 "divu", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1690 "eor", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1691 "eori",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1692 "eori",//sr |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1693 "exg", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1694 "ext", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1695 "illegal", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1696 "jmp", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1697 "jsr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1698 "lea", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1699 "link", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1700 "lsl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1701 "lsr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1702 "move", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1703 "move",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1704 "move",//from_sr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1705 "move",//sr |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1706 "move",//usp |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1707 "movem", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1708 "movep", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1709 "muls", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1710 "mulu", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1711 "nbcd", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1712 "neg", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1713 "negx", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1714 "nop", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1715 "not", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1716 "or", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1717 "ori",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1718 "ori",//sr |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1719 "pea", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1720 "reset", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1721 "rol", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1722 "ror", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1723 "roxl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1724 "roxr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1725 "rte", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1726 "rtr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1727 "rts", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1728 "sbcd", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1729 "scc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1730 "stop", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1731 "sub", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1732 "subx", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1733 "swap", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1734 "tas", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1735 "trap", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1736 "trapv", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1737 "tst", |
12
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
1738 "unlk", |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1739 "invalid", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1740 #ifdef M68010 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1741 "bkpt", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1742 "move", //from ccr |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1743 "movec", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1744 "moves", |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1745 "rtd", |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1746 #endif |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1747 #ifdef M68020 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1748 "bfchg", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1749 "bfclr", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1750 "bfexts", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1751 "bfextu", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1752 "bfffo", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1753 "bfins", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1754 "bfset", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1755 "bftst", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1756 "callm", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1757 "cas", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1758 "cas2", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1759 "chk2", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1760 "cmp2", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1761 "cpbcc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1762 "cpdbcc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1763 "cpgen", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1764 "cprestore", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1765 "cpsave", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1766 "cpscc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1767 "cptrapcc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1768 "divsl", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1769 "divul", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1770 "extb", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1771 "pack", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1772 "rtm", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1773 "trapcc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1774 "unpk" |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1775 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1776 }; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1777 |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1778 char * cond_mnem[] = { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1779 "ra", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1780 "f", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1781 "hi", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1782 "ls", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1783 "cc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1784 "cs", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1785 "ne", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1786 "eq", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1787 "vc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1788 "vs", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1789 "pl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1790 "mi", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1791 "ge", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1792 "lt", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1793 "gt", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1794 "le" |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1795 }; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1796 #ifdef M68010 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1797 char * cr_mnem[] = { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1798 "SFC", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1799 "DFC", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1800 #ifdef M68020 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1801 "CACR", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1802 #endif |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1803 "USP", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1804 "VBR", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1805 #ifdef M68020 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1806 "CAAR", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1807 "MSP", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1808 "ISP" |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1809 #endif |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1810 }; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1811 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1812 |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1813 int m68k_disasm_op(m68k_op_info *decoded, char *dst, int need_comma, uint8_t labels, uint32_t address, format_label_fun label_fun, void * data) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1814 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1815 char * c = need_comma ? "," : ""; |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1816 int ret = 0; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1817 #ifdef M68020 |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1818 uint8_t addr_mode = decoded->addr_mode & (~M68K_FLAG_BITFIELD); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1819 #else |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1820 uint8_t addr_mode = decoded->addr_mode; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1821 #endif |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1822 switch(addr_mode) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1823 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1824 case MODE_REG: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1825 ret = sprintf(dst, "%s d%d", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1826 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1827 case MODE_AREG: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1828 ret = sprintf(dst, "%s a%d", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1829 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1830 case MODE_AREG_INDIRECT: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1831 ret = sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1832 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1833 case MODE_AREG_POSTINC: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1834 ret = sprintf(dst, "%s (a%d)+", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1835 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1836 case MODE_AREG_PREDEC: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1837 ret = sprintf(dst, "%s -(a%d)", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1838 break; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1839 case MODE_AREG_DISPLACE: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1840 ret = sprintf(dst, "%s (%d, a%d)", c, decoded->params.regs.displacement, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1841 break; |
79
d212e0cd0b7e
Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents:
69
diff
changeset
|
1842 case MODE_AREG_INDEX_DISP8: |
638
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1843 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1844 if (decoded->params.regs.scale) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1845 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1846 ret = sprintf(dst, "%s (%d, a%d, %c%d.%c*%d)", c, decoded->params.regs.displacement, decoded->params.regs.pri, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1847 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1848 #endif |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1849 ret = sprintf(dst, "%s (%d, a%d, %c%d.%c)", c, decoded->params.regs.displacement, decoded->params.regs.pri, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1850 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1851 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1852 #endif |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1853 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1854 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1855 case MODE_AREG_INDEX_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1856 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1857 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1858 ret = sprintf(dst, "%s (%d.%c, a%d, %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1859 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1860 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1861 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1862 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1863 ret = sprintf(dst, "%s (a%d, %c%d.%c*%d)", c, decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1864 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1865 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1866 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1867 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1868 case MODE_AREG_PREINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1869 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1870 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1871 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1872 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1873 ret = sprintf(dst, "%s ([a%d, %c%d.%c*%d])", c, decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1874 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1875 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1876 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1877 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1878 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1879 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1880 ret = sprintf(dst, "%s ([%d.%c, a%d, %c%d.%c*%d])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1881 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1882 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1883 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1884 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1885 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1886 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1887 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1888 ret = sprintf(dst, "%s ([a%d, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1889 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1890 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1891 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1892 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1893 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1894 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1895 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1896 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1897 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1898 ret = sprintf(dst, "%s ([%d.%c, a%d, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1899 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1900 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1901 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1902 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1903 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1904 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1905 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1906 case MODE_AREG_POSTINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1907 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1908 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1909 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1910 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1911 ret = sprintf(dst, "%s ([a%d], %c%d.%c*%d)", c, decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1912 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1913 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1914 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1915 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1916 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1917 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1918 ret = sprintf(dst, "%s ([%d.%c, a%d], %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1919 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1920 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1921 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1922 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1923 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1924 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1925 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1926 ret = sprintf(dst, "%s ([a%d], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1927 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1928 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1929 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1930 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1931 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1932 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1933 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1934 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1935 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1936 ret = sprintf(dst, "%s ([%d.%c, a%d], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1937 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1938 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1939 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1940 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1941 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1942 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1943 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1944 case MODE_AREG_MEM_INDIRECT: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1945 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1946 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1947 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1948 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1949 ret = sprintf(dst, "%s ([a%d])", c, decoded->params.regs.pri); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1950 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1951 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1952 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1953 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1954 ret = sprintf(dst, "%s ([%d.%c, a%d])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1955 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1956 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1957 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1958 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1959 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1960 ret = sprintf(dst, "%s ([a%d], %d.%c)", c, decoded->params.regs.pri, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1961 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1962 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1963 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1964 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1965 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1966 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1967 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1968 ret = sprintf(dst, "%s ([%d.%c, a%d], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1969 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1970 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1971 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1972 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1973 break; |
638
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1974 case MODE_AREG_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1975 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1976 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1977 ret = sprintf(dst, "%s (%d.%c, a%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1978 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', decoded->params.regs.pri); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1979 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1980 //this is a lossy representation of the encoded instruction |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1981 //not sure if there's a better way to print it though |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1982 ret = sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1983 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1984 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1985 case MODE_INDEX_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1986 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1987 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1988 ret = sprintf(dst, "%s (%d.%c, %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1989 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1990 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1991 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1992 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1993 ret = sprintf(dst, "%s (%c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1994 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1995 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1996 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1997 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1998 case MODE_PREINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1999 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2000 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2001 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2002 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2003 ret = sprintf(dst, "%s ([%c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2004 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2005 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2006 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2007 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2008 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2009 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2010 ret = sprintf(dst, "%s ([%d.%c, %c%d.%c*%d])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2011 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2012 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2013 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2014 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2015 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2016 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2017 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2018 ret = sprintf(dst, "%s ([%c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2019 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2020 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2021 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2022 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2023 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2024 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2025 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2026 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2027 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2028 ret = sprintf(dst, "%s ([%d.%c, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2029 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2030 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2031 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2032 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2033 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2034 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2035 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2036 case MODE_POSTINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2037 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2038 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2039 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2040 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2041 ret = sprintf(dst, "%s ([], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2042 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2043 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2044 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2045 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2046 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2047 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2048 ret = sprintf(dst, "%s ([%d.%c], %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2049 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2050 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2051 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2052 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2053 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2054 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2055 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2056 ret = sprintf(dst, "%s ([], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2057 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2058 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2059 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2060 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2061 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2062 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2063 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2064 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2065 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2066 ret = sprintf(dst, "%s ([%d.%c], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2067 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2068 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2069 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2070 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2071 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2072 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2073 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2074 case MODE_MEM_INDIRECT: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2075 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2076 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2077 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2078 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2079 ret = sprintf(dst, "%s ([])", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2080 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2081 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2082 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2083 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2084 ret = sprintf(dst, "%s ([%d.%c])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2085 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2086 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2087 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2088 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2089 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2090 ret = sprintf(dst, "%s ([], %d.%c)", c, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2091 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2092 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2093 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2094 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2095 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2096 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2097 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2098 ret = sprintf(dst, "%s ([%d.%c], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2099 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2100 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2101 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2102 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2103 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2104 case MODE_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2105 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2106 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2107 ret = sprintf(dst, "%s (%d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2108 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2109 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2110 ret = sprintf(dst, "%s ()", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2111 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2112 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2113 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2114 case MODE_IMMEDIATE: |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
2115 case MODE_IMMEDIATE_WORD: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2116 ret = sprintf(dst, (decoded->params.immed <= 128 ? "%s #%d" : "%s #$%X"), c, decoded->params.immed); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2117 break; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2118 case MODE_ABSOLUTE_SHORT: |
638
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2119 if (labels) { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2120 ret = sprintf(dst, "%s ", c); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2121 ret += label_fun(dst+ret, decoded->params.immed, data); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2122 strcat(dst+ret, ".w"); |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2123 ret = ret + 2; |
134 | 2124 } else { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2125 ret = sprintf(dst, "%s $%X.w", c, decoded->params.immed); |
134 | 2126 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2127 break; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2128 case MODE_ABSOLUTE: |
134 | 2129 if (labels) { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2130 ret = sprintf(dst, "%s ", c); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2131 ret += label_fun(dst+ret, decoded->params.immed, data); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2132 strcat(dst+ret, ".l"); |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2133 ret = ret + 2; |
134 | 2134 } else { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2135 ret = sprintf(dst, "%s $%X", c, decoded->params.immed); |
134 | 2136 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2137 break; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2138 case MODE_PC_DISPLACE: |
134 | 2139 if (labels) { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2140 ret = sprintf(dst, "%s ", c); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2141 ret += label_fun(dst+ret, address + 2 + decoded->params.regs.displacement, data); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2142 strcat(dst+ret, "(pc)"); |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2143 ret = ret + 4; |
134 | 2144 } else { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2145 ret = sprintf(dst, "%s (%d, pc)", c, decoded->params.regs.displacement); |
134 | 2146 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2147 break; |
79
d212e0cd0b7e
Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents:
69
diff
changeset
|
2148 case MODE_PC_INDEX_DISP8: |
638
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2149 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2150 if (decoded->params.regs.scale) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2151 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2152 ret = sprintf(dst, "%s (%d, pc, %c%d.%c*%d)", c, decoded->params.regs.displacement, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2153 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2154 #endif |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2155 ret = sprintf(dst, "%s (%d, pc, %c%d.%c)", c, decoded->params.regs.displacement, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2156 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2157 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2158 #endif |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2159 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2160 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2161 case MODE_PC_INDEX_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2162 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2163 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2164 ret = sprintf(dst, "%s (%d.%c, pc, %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2165 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2166 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2167 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2168 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2169 ret = sprintf(dst, "%s (pc, %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2170 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2171 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2172 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2173 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2174 case MODE_PC_PREINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2175 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2176 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2177 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2178 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2179 ret = sprintf(dst, "%s ([pc, %c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2180 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2181 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2182 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2183 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2184 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2185 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2186 ret = sprintf(dst, "%s ([%d.%c, pc, %c%d.%c*%d])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2187 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2188 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2189 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2190 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2191 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2192 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2193 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2194 ret = sprintf(dst, "%s ([pc, %c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2195 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2196 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2197 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2198 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2199 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2200 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2201 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2202 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2203 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2204 ret = sprintf(dst, "%s ([%d.%c, pc, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2205 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2206 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2207 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2208 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2209 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2210 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2211 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2212 case MODE_PC_POSTINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2213 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2214 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2215 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2216 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2217 ret = sprintf(dst, "%s ([pc], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2218 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2219 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2220 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2221 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2222 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2223 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2224 ret = sprintf(dst, "%s ([%d.%c, pc], %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2225 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2226 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2227 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2228 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2229 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2230 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2231 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2232 ret = sprintf(dst, "%s ([pc], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2233 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2234 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2235 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2236 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2237 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2238 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2239 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2240 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2241 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2242 ret = sprintf(dst, "%s ([%d.%c, pc], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2243 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2244 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2245 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2246 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2247 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2248 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2249 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2250 case MODE_PC_MEM_INDIRECT: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2251 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2252 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2253 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2254 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2255 ret = sprintf(dst, "%s ([pc])", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2256 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2257 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2258 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2259 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2260 ret = sprintf(dst, "%s ([%d.%c, pc])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2261 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2262 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2263 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2264 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2265 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2266 ret = sprintf(dst, "%s ([pc], %d.%c)", c, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2267 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2268 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2269 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2270 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2271 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2272 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2273 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2274 ret = sprintf(dst, "%s ([%d.%c, pc], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2275 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2276 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2277 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2278 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2279 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2280 case MODE_PC_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2281 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2282 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2283 ret = sprintf(dst, "%s (%d.%c, pc)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2284 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2285 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2286 ret = sprintf(dst, "%s (pc)", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2287 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2288 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2289 case MODE_ZPC_INDEX_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2290 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2291 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2292 ret = sprintf(dst, "%s (%d.%c, zpc, %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2293 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2294 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2295 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2296 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2297 ret = sprintf(dst, "%s (zpc, %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2298 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2299 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2300 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2301 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2302 case MODE_ZPC_PREINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2303 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2304 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2305 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2306 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2307 ret = sprintf(dst, "%s ([zpc, %c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2308 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2309 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2310 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2311 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2312 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2313 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2314 ret = sprintf(dst, "%s ([%d.%c, zpc, %c%d.%c*%d])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2315 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2316 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2317 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2318 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2319 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2320 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2321 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2322 ret = sprintf(dst, "%s ([zpc, %c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2323 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2324 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2325 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2326 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2327 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2328 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2329 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2330 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2331 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2332 ret = sprintf(dst, "%s ([%d.%c, zpc, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2333 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2334 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2335 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2336 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2337 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2338 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2339 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2340 case MODE_ZPC_POSTINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2341 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2342 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2343 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2344 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2345 ret = sprintf(dst, "%s ([zpc], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2346 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2347 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2348 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2349 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2350 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2351 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2352 ret = sprintf(dst, "%s ([%d.%c, zpc], %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2353 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2354 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2355 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2356 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2357 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2358 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2359 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2360 ret = sprintf(dst, "%s ([zpc], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2361 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2362 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2363 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2364 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2365 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2366 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2367 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2368 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2369 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2370 ret = sprintf(dst, "%s ([%d.%c, zpc], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2371 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2372 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2373 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2374 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2375 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2376 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2377 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2378 case MODE_ZPC_MEM_INDIRECT: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2379 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2380 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2381 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2382 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2383 ret = sprintf(dst, "%s ([zpc])", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2384 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2385 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2386 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2387 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2388 ret = sprintf(dst, "%s ([%d.%c, zpc])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2389 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2390 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2391 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2392 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2393 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2394 ret = sprintf(dst, "%s ([zpc], %d.%c)", c, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2395 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2396 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2397 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2398 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2399 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2400 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2401 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2402 ret = sprintf(dst, "%s ([%d.%c, zpc], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2403 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2404 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2405 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2406 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2407 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2408 case MODE_ZPC_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2409 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2410 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2411 ret = sprintf(dst, "%s (%d.%c, zpc)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2412 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2413 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2414 ret = sprintf(dst, "%s (zpc)", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2415 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2416 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2417 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2418 default: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2419 ret = 0; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2420 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2421 #ifdef M68020 |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2422 if (decoded->addr_mode & M68K_FLAG_BITFIELD) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2423 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2424 switch (decoded->bitfield & 0x820) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2425 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2426 case 0: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2427 return ret + sprintf(dst+ret, " {$%X:%d}", decoded->bitfield >> 6 & 0x1F, decoded->bitfield & 0x1F ? decoded->bitfield & 0x1F : 32); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2428 case 0x20: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2429 return ret + sprintf(dst+ret, " {$%X:d%d}", decoded->bitfield >> 6 & 0x1F, decoded->bitfield & 0x7); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2430 case 0x800: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2431 return ret + sprintf(dst+ret, " {d%d:%d}", decoded->bitfield >> 6 & 0x7, decoded->bitfield & 0x1F ? decoded->bitfield & 0x1F : 32); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2432 case 0x820: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2433 return ret + sprintf(dst+ret, " {d%d:d%d}", decoded->bitfield >> 6 & 0x7, decoded->bitfield & 0x7); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2434 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2435 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2436 #endif |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2437 return ret; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2438 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2439 |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2440 int m68k_disasm_movem_op(m68k_op_info *decoded, m68k_op_info *other, char *dst, int need_comma, uint8_t labels, uint32_t address, format_label_fun label_fun, void * data) |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2441 { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2442 int8_t dir, reg, bit, regnum, last=-1, lastreg, first=-1; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2443 char *rtype, *last_rtype; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2444 int oplen; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2445 if (decoded->addr_mode == MODE_REG) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2446 if (other->addr_mode == MODE_AREG_PREDEC) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2447 bit = 15; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2448 dir = -1; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2449 } else { |
69
36f1133837d0
Fix disassembly of reg list in MOVEM when the reg list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
68
diff
changeset
|
2450 dir = 1; |
36f1133837d0
Fix disassembly of reg list in MOVEM when the reg list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
68
diff
changeset
|
2451 bit = 0; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2452 } |
68
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2453 if (need_comma) { |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2454 strcat(dst, ", "); |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2455 oplen = 2; |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2456 } else { |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2457 strcat(dst, " "); |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2458 oplen = 1; |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2459 } |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2460 for (reg=0; bit < 16 && bit > -1; bit += dir, reg++) { |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
2461 if (decoded->params.immed & (1 << bit)) { |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2462 if (reg > 7) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2463 rtype = "a"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2464 regnum = reg - 8; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2465 } else { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2466 rtype = "d"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2467 regnum = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2468 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2469 if (last >= 0 && last == regnum - 1 && lastreg == reg - 1) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2470 last = regnum; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2471 lastreg = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2472 } else if(last >= 0) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2473 if (first != last) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2474 oplen += sprintf(dst + oplen, "-%s%d/%s%d",last_rtype, last, rtype, regnum); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2475 } else { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2476 oplen += sprintf(dst + oplen, "/%s%d", rtype, regnum); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2477 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2478 first = last = regnum; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2479 last_rtype = rtype; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2480 lastreg = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2481 } else { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2482 oplen += sprintf(dst + oplen, "%s%d", rtype, regnum); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2483 first = last = regnum; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2484 last_rtype = rtype; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2485 lastreg = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2486 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2487 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2488 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2489 if (last >= 0 && last != first) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2490 oplen += sprintf(dst + oplen, "-%s%d", last_rtype, last); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2491 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2492 return oplen; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2493 } else { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2494 return m68k_disasm_op(decoded, dst, need_comma, labels, address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2495 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2496 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2497 |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2498 int m68k_default_label_fun(char * dst, uint32_t address, void * data) |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2499 { |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2500 return sprintf(dst, "ADR_%X", address); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2501 } |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2502 |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2503 int m68k_disasm_ex(m68kinst * decoded, char * dst, uint8_t labels, format_label_fun label_fun, void * data) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2504 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2505 int ret,op1len; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2506 uint8_t size; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2507 char * special_op = "CCR"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2508 switch (decoded->op) |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2509 { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2510 case M68K_BCC: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2511 case M68K_DBCC: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2512 case M68K_SCC: |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2513 ret = strlen(mnemonics[decoded->op]) - 2; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2514 memcpy(dst, mnemonics[decoded->op], ret); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2515 dst[ret] = 0; |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2516 strcpy(dst+ret, cond_mnem[decoded->extra.cond]); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2517 ret = strlen(dst); |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2518 if (decoded->op != M68K_SCC) { |
134 | 2519 if (labels) { |
2520 if (decoded->op == M68K_DBCC) { | |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2521 ret += sprintf(dst+ret, " d%d, ", decoded->dst.params.regs.pri); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2522 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data); |
134 | 2523 } else { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2524 dst[ret++] = ' '; |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2525 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data); |
134 | 2526 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2527 } else { |
134 | 2528 if (decoded->op == M68K_DBCC) { |
2529 ret += sprintf(dst+ret, " d%d, #%d <%X>", decoded->dst.params.regs.pri, decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed); | |
2530 } else { | |
2531 ret += sprintf(dst+ret, " #%d <%X>", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed); | |
2532 } | |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2533 } |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2534 return ret; |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2535 } |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2536 break; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2537 case M68K_BSR: |
134 | 2538 if (labels) { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2539 ret = sprintf(dst, "bsr%s ", decoded->variant == VAR_BYTE ? ".s" : ""); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2540 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data); |
134 | 2541 } else { |
2542 ret = sprintf(dst, "bsr%s #%d <%X>", decoded->variant == VAR_BYTE ? ".s" : "", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed); | |
2543 } | |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2544 return ret; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2545 case M68K_MOVE_FROM_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2546 ret = sprintf(dst, "%s", mnemonics[decoded->op]); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2547 ret += sprintf(dst + ret, " SR"); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2548 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 1, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2549 return ret; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2550 case M68K_ANDI_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2551 case M68K_EORI_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2552 case M68K_MOVE_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2553 case M68K_ORI_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2554 special_op = "SR"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2555 case M68K_ANDI_CCR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2556 case M68K_EORI_CCR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2557 case M68K_MOVE_CCR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2558 case M68K_ORI_CCR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2559 ret = sprintf(dst, "%s", mnemonics[decoded->op]); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2560 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2561 ret += sprintf(dst + ret, ", %s", special_op); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2562 return ret; |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2563 case M68K_MOVE_USP: |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2564 ret = sprintf(dst, "%s", mnemonics[decoded->op]); |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2565 if (decoded->src.addr_mode != MODE_UNUSED) { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2566 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data); |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2567 ret += sprintf(dst + ret, ", USP"); |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2568 } else { |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2569 ret += sprintf(dst + ret, "USP, "); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2570 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data); |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2571 } |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2572 return ret; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2573 case M68K_INVALID: |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2574 ret = sprintf(dst, "dc.w $%X", decoded->src.params.immed); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2575 return ret; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2576 #ifdef M68010 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2577 case M68K_MOVEC: |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2578 ret = sprintf(dst, "%s ", mnemonics[decoded->op]); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2579 if (decoded->src.addr_mode == MODE_UNUSED) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2580 ret += sprintf(dst + ret, "%s, ", cr_mnem[decoded->src.params.immed]); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2581 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data); |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2582 } else { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2583 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data); |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2584 ret += sprintf(dst + ret, ", %s", cr_mnem[decoded->dst.params.immed]); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2585 } |
47123183c336
Improve support for disassembling 68010+ binaries
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518
diff
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|
2586 return ret; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2587 #endif |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2588 default: |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2589 size = decoded->extra.size; |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
2590 ret = sprintf(dst, "%s%s%s", |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
2591 mnemonics[decoded->op], |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
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|
2592 decoded->variant == VAR_QUICK ? "q" : (decoded->variant == VAR_IMMEDIATE ? "i" : ""), |
13
168b1a873895
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Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2593 size == OPSIZE_BYTE ? ".b" : (size == OPSIZE_WORD ? ".w" : (size == OPSIZE_LONG ? ".l" : ""))); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2594 } |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2595 if (decoded->op == M68K_MOVEM) { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2596 op1len = m68k_disasm_movem_op(&(decoded->src), &(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data); |
13
168b1a873895
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Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2597 ret += op1len; |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2598 ret += m68k_disasm_movem_op(&(decoded->dst), &(decoded->src), dst + ret, op1len, labels, decoded->address, label_fun, data); |
13
168b1a873895
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Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2599 } else { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2600 op1len = m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2601 ret += op1len; |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2602 ret += m68k_disasm_op(&(decoded->dst), dst + ret, op1len, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2603 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2604 return ret; |
5df303bf72e6
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Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2605 } |
5df303bf72e6
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Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2606 |
134 | 2607 int m68k_disasm(m68kinst * decoded, char * dst) |
2608 { | |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2609 return m68k_disasm_ex(decoded, dst, 0, NULL, NULL); |
134 | 2610 } |
2611 | |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2612 int m68k_disasm_labels(m68kinst * decoded, char * dst, format_label_fun label_fun, void * data) |
134 | 2613 { |
634
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Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2614 if (!label_fun) |
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Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2615 { |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2616 label_fun = m68k_default_label_fun; |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2617 } |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2618 return m68k_disasm_ex(decoded, dst, 1, label_fun, data); |
134 | 2619 } |