repos/blastem: backend_x86.c annotate

annotate backend_x86.c @ 2688:b42f00a3a937 default tip

Fix default target. Ensure m68k.h and z80.h are built before anything else when no dep info is available

author	Michael Pavone <pavone@retrodev.com>
date	Mon, 31 Mar 2025 21:06:18 -0700
parents	c97609fe8315
children

rev	line source
567 8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	1 #include "backend.h"
8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	2 #include "gen_x86.h"
1465 5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	3 #include <string.h>
567 8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	4
8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	5 void cycles(cpu_options *opts, uint32_t num)
8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	6 {
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 987 diff changeset	7 if (opts->limit < 0) {
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 987 diff changeset	8 sub_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 987 diff changeset	9 } else {
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 987 diff changeset	10 add_ir(&opts->code, num*opts->clock_divider, opts->cycles, SZ_D);
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 987 diff changeset	11 }
567 8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	12 }
8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	13
8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	14 void check_cycles_int(cpu_options *opts, uint32_t address)
8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	15 {
8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	16 code_info *code = &opts->code;
1109 4bc27caa6e20 Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2 Michael Pavone <pavone@retrodev.com> parents: 1107 diff changeset	17 uint8_t cc;
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 987 diff changeset	18 if (opts->limit < 0) {
1109 4bc27caa6e20 Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2 Michael Pavone <pavone@retrodev.com> parents: 1107 diff changeset	19 cmp_ir(code, 1, opts->cycles, SZ_D);
4bc27caa6e20 Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2 Michael Pavone <pavone@retrodev.com> parents: 1107 diff changeset	20 cc = CC_NS;
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 987 diff changeset	21 } else {
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 987 diff changeset	22 cmp_rr(code, opts->cycles, opts->limit, SZ_D);
1109 4bc27caa6e20 Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2 Michael Pavone <pavone@retrodev.com> parents: 1107 diff changeset	23 cc = CC_A;
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 987 diff changeset	24 }
567 8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	25 code_ptr jmp_off = code->cur+1;
1109 4bc27caa6e20 Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2 Michael Pavone <pavone@retrodev.com> parents: 1107 diff changeset	26 jcc(code, cc, jmp_off+1);
567 8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	27 mov_ir(code, address, opts->scratch1, SZ_D);
8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	28 call(code, opts->handle_cycle_limit_int);
8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	29 *jmp_off = code->cur - (jmp_off+1);
8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	30 }
8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	31
1465 5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	32 void retranslate_calc(cpu_options *opts)
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	33 {
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	34 code_info *code = &opts->code;
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	35 code_info tmp = *code;
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	36 uint8_t cc;
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	37 if (opts->limit < 0) {
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	38 cmp_ir(code, 1, opts->cycles, SZ_D);
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	39 cc = CC_NS;
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	40 } else {
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	41 cmp_rr(code, opts->cycles, opts->limit, SZ_D);
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	42 cc = CC_A;
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	43 }
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	44 jcc(code, cc, code->cur+2);
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	45 opts->move_pc_off = code->cur - tmp.cur;
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	46 mov_ir(code, 0x1234, opts->scratch1, SZ_D);
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	47 opts->move_pc_size = code->cur - tmp.cur - opts->move_pc_off;
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	48 *code = tmp;
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	49 }
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	50
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	51 void patch_for_retranslate(cpu_options *opts, code_ptr native_address, code_ptr handler)
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	52 {
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	53 if (!is_mov_ir(native_address)) {
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	54 //instruction is not already patched for either retranslation or a breakpoint
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	55 //copy original mov_ir instruction containing PC to beginning of native code area
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	56 memmove(native_address, native_address + opts->move_pc_off, opts->move_pc_size);
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	57 }
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	58 //jump to the retranslation handler
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	59 code_info tmp = {
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	60 .cur = native_address + opts->move_pc_size,
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	61 .last = native_address + 256,
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	62 .stack_off = 0
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	63 };
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	64 jmp(&tmp, handler);
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	65 }
5d41d0574863 Preserve original address when retranslating instructions instead of switching to the lowest alias Michael Pavone <pavone@retrodev.com> parents: 1145 diff changeset	66
2133 8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving Michael Pavone <pavone@retrodev.com> parents: 2113 diff changeset	67 void defer_translation(cpu_options *opts, uint32_t address, code_ptr handler)
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving Michael Pavone <pavone@retrodev.com> parents: 2113 diff changeset	68 {
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving Michael Pavone <pavone@retrodev.com> parents: 2113 diff changeset	69 mov_ir(&opts->code, address, opts->scratch1, SZ_D);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving Michael Pavone <pavone@retrodev.com> parents: 2113 diff changeset	70 jmp(&opts->code, handler);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving Michael Pavone <pavone@retrodev.com> parents: 2113 diff changeset	71 }
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving Michael Pavone <pavone@retrodev.com> parents: 2113 diff changeset	72
567 8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	73 void check_cycles(cpu_options * opts)
8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	74 {
8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	75 code_info *code = &opts->code;
1109 4bc27caa6e20 Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2 Michael Pavone <pavone@retrodev.com> parents: 1107 diff changeset	76 uint8_t cc;
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 987 diff changeset	77 if (opts->limit < 0) {
1109 4bc27caa6e20 Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2 Michael Pavone <pavone@retrodev.com> parents: 1107 diff changeset	78 cmp_ir(code, 1, opts->cycles, SZ_D);
4bc27caa6e20 Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2 Michael Pavone <pavone@retrodev.com> parents: 1107 diff changeset	79 cc = CC_NS;
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 987 diff changeset	80 } else {
6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 987 diff changeset	81 cmp_rr(code, opts->cycles, opts->limit, SZ_D);
1109 4bc27caa6e20 Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2 Michael Pavone <pavone@retrodev.com> parents: 1107 diff changeset	82 cc = CC_A;
1047 6b07af1515b5 Change cycle tracking code for Z80 core to only use a single register. Store low 7 bits of R in a reg and increment it appropriately. Michael Pavone <pavone@retrodev.com> parents: 987 diff changeset	83 }
2269 6677afe78a6f Hopefully make older versions of gcc happy Michael Pavone <pavone@retrodev.com> parents: 2268 diff changeset	84 code_ptr jmp_off;
2268 5b308c7b098c Avoid code mem allocation bomb when a div instruction gets rewritten Michael Pavone <pavone@retrodev.com> parents: 2237 diff changeset	85 ALLOC_CODE_RETRY_POINT
2269 6677afe78a6f Hopefully make older versions of gcc happy Michael Pavone <pavone@retrodev.com> parents: 2268 diff changeset	86 jmp_off = code->cur+1;
1109 4bc27caa6e20 Fix a subtle bug in interrupt handling introduced with the move to a single cycle register in the Z80 core. Fixes regression in Puyo Puyo 2 Michael Pavone <pavone@retrodev.com> parents: 1107 diff changeset	87 jcc(code, cc, jmp_off+1);
567 8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	88 call(code, opts->handle_cycle_limit);
2268 5b308c7b098c Avoid code mem allocation bomb when a div instruction gets rewritten Michael Pavone <pavone@retrodev.com> parents: 2237 diff changeset	89 CHECK_BRANCH_DEST(jmp_off);
567 8e395210f50f Refactor gen_x86 to use an interface more like gen_arm and to remove the need for the caller to decide whether an 8-bit or 32-bit displacement is needed in the rdisp functions. Update m68k_to_x86 to use the new version of the gen_x86 functions and do some minor refactoring there in the process Michael Pavone <pavone@retrodev.com> parents: diff changeset	90 }
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	91
697 7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 692 diff changeset	92 void log_address(cpu_options opts, uint32_t address, char format)
7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 692 diff changeset	93 {
7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 692 diff changeset	94 code_info *code = &opts->code;
7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 692 diff changeset	95 call(code, opts->save_context);
7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 692 diff changeset	96 push_r(code, opts->context_reg);
7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 692 diff changeset	97 mov_rr(code, opts->cycles, RDX, SZ_D);
7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 692 diff changeset	98 mov_ir(code, (int64_t)format, RDI, SZ_PTR);
7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 692 diff changeset	99 mov_ir(code, address, RSI, SZ_D);
7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 692 diff changeset	100 call_args_abi(code, (code_ptr)printf, 3, RDI, RSI, RDX);
7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 692 diff changeset	101 pop_r(code, opts->context_reg);
7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 692 diff changeset	102 call(code, opts->load_context);
7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 692 diff changeset	103 }
7f96bd1cb1be Sync fixes and logging to fix more sync issues Michael Pavone <pavone@retrodev.com> parents: 692 diff changeset	104
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 595 diff changeset	105 void check_code_prologue(code_info *code)
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 595 diff changeset	106 {
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 595 diff changeset	107 check_alloc_code(code, MAX_INST_LEN*4);
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 595 diff changeset	108 }
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 595 diff changeset	109
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	110 code_ptr gen_mem_fun(cpu_options * opts, memmap_chunk const * memmap, uint32_t num_chunks, ftype fun_type, code_ptr *after_inc)
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	111 {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	112 code_info *code = &opts->code;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	113 code_ptr start = code->cur;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	114 check_cycles(opts);
987 1f09994e92c5 Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing. Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	115 uint8_t is_write = fun_type == WRITE_16 \|\| fun_type == WRITE_8;
1f09994e92c5 Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing. Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	116 uint8_t adr_reg = is_write ? opts->scratch2 : opts->scratch1;
1f09994e92c5 Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing. Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	117 uint8_t size = (fun_type == READ_16 \|\| fun_type == WRITE_16) ? SZ_W : SZ_B;
1f09994e92c5 Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing. Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	118 if (size != SZ_B && opts->align_error_mask) {
1f09994e92c5 Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing. Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	119 test_ir(code, opts->align_error_mask, adr_reg, SZ_D);
1f09994e92c5 Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing. Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	120 jcc(code, CC_NZ, is_write ? opts->handle_align_error_write : opts->handle_align_error_read);
1f09994e92c5 Initial stab at implementing address error exceptions. Need to fill in the value of IR, undefined bits of last stack frame word and properly deal with address errors that occur during exception processing. Michael Pavone <pavone@retrodev.com> parents: 894 diff changeset	121 }
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	122 cycles(opts, opts->bus_cycles);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 589 diff changeset	123 if (after_inc) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 589 diff changeset	124 *after_inc = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 589 diff changeset	125 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	126
750 59b499f6b24f Fix handling of address mask in gen_mem_fun Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	127 if (opts->address_size == SZ_D && opts->address_mask != 0xFFFFFFFF) {
59b499f6b24f Fix handling of address mask in gen_mem_fun Michael Pavone <pavone@retrodev.com> parents: 697 diff changeset	128 and_ir(code, opts->address_mask, adr_reg, SZ_D);
1116 fe8c79f82c22 More cleanup in preparation for SMS/Mark III support Michael Pavone <pavone@retrodev.com> parents: 1109 diff changeset	129 } else if (opts->address_size == SZ_W && opts->address_mask != 0xFFFF) {
fe8c79f82c22 More cleanup in preparation for SMS/Mark III support Michael Pavone <pavone@retrodev.com> parents: 1109 diff changeset	130 and_ir(code, opts->address_mask, adr_reg, SZ_W);
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	131 }
2396 bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	132
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	133 code_ptr check_watchpoints = size == SZ_W ? (code_ptr)opts->check_watchpoints_16 : (code_ptr)opts->check_watchpoints_8;
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	134 if (is_write && check_watchpoints) {
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	135 //watchpoints are enabled, check if the address is within the watchpoint range
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	136 cmp_rdispr(code, opts->context_reg, opts->watchpoint_range_off, adr_reg, opts->address_size);
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	137 code_ptr watch_lb = code->cur + 1;
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	138 jcc(code, CC_C, code->cur + 2);
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	139 cmp_rdispr(code, opts->context_reg, opts->watchpoint_range_off + (opts->address_size == SZ_D ? 4 : 2), adr_reg, opts->address_size);
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	140 code_ptr watch_ub = code->cur + 1;
2400 c97609fe8315 Implement watchpoints in Z80 debugger Michael Pavone <pavone@retrodev.com> parents: 2396 diff changeset	141 jcc(code, CC_A, code->cur + 2);
2396 bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	142
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	143 push_r(code, opts->scratch1);
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	144 push_r(code, opts->scratch2);
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	145 call(code, opts->save_context);
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	146 call_args_abi(code, check_watchpoints, 3, opts->scratch2, opts->context_reg, opts->scratch1);
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	147 mov_rr(code, RAX, opts->context_reg, SZ_PTR);
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	148 call(code, opts->load_context);
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	149 pop_r(code, opts->scratch2);
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	150 pop_r(code, opts->scratch1);
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	151
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	152 *watch_lb = code->cur - (watch_lb + 1);
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	153 *watch_ub = code->cur - (watch_ub + 1);
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	154 }
bf4f1a8d1d48 Implement 68K watchpoints in internal debugger Michael Pavone <pavone@retrodev.com> parents: 2339 diff changeset	155
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	156 code_ptr lb_jcc = NULL, ub_jcc = NULL;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	157 uint16_t access_flag = is_write ? MMAP_WRITE : MMAP_READ;
690 fc04781f4d28 Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	158 uint32_t ram_flags_off = opts->ram_flags_off;
1086 f0a1e0a2263c Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement Michael Pavone <pavone@retrodev.com> parents: 1084 diff changeset	159 uint32_t min_address = 0;
f0a1e0a2263c Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement Michael Pavone <pavone@retrodev.com> parents: 1084 diff changeset	160 uint32_t max_address = opts->max_address;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	161 uint8_t need_wide_jcc = 0;
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	162 for (uint32_t chunk = 0; chunk < num_chunks; chunk++)
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	163 {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	164 code_info chunk_start = *code;
1086 f0a1e0a2263c Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement Michael Pavone <pavone@retrodev.com> parents: 1084 diff changeset	165 if (memmap[chunk].start > min_address) {
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	166 cmp_ir(code, memmap[chunk].start, adr_reg, opts->address_size);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	167 lb_jcc = code->cur + 1;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	168 if (need_wide_jcc) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	169 jcc(code, CC_C, code->cur + 130);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	170 lb_jcc++;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	171 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	172 jcc(code, CC_C, code->cur + 2);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	173 }
1086 f0a1e0a2263c Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement Michael Pavone <pavone@retrodev.com> parents: 1084 diff changeset	174 } else {
f0a1e0a2263c Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement Michael Pavone <pavone@retrodev.com> parents: 1084 diff changeset	175 min_address = memmap[chunk].end;
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	176 }
1086 f0a1e0a2263c Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement Michael Pavone <pavone@retrodev.com> parents: 1084 diff changeset	177 if (memmap[chunk].end < max_address) {
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	178 cmp_ir(code, memmap[chunk].end, adr_reg, opts->address_size);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	179 ub_jcc = code->cur + 1;
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	180 if (need_wide_jcc) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	181 jcc(code, CC_NC, code->cur + 130);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	182 ub_jcc++;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	183 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	184 jcc(code, CC_NC, code->cur + 2);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	185 }
1086 f0a1e0a2263c Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement Michael Pavone <pavone@retrodev.com> parents: 1084 diff changeset	186 } else {
f0a1e0a2263c Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement Michael Pavone <pavone@retrodev.com> parents: 1084 diff changeset	187 max_address = memmap[chunk].start;
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	188 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	189
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	190 if (memmap[chunk].mask != opts->address_mask) {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	191 and_ir(code, memmap[chunk].mask, adr_reg, opts->address_size);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	192 }
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	193 code_ptr after_normal = NULL;
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	194 uint8_t need_addr_pop = 0;
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	195 if (size == SZ_B && memmap[chunk].shift != 0) {
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	196 if (is_write && (memmap[chunk].flags & MMAP_CODE)) {
b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	197 push_r(code, adr_reg);
b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	198 need_addr_pop = 1;
b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	199 }
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	200 btr_ir(code, 0, adr_reg, opts->address_size);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	201 code_ptr normal = code->cur+1;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	202 jcc(code, CC_NC, normal);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	203 if (memmap[chunk].shift > 0) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	204 shl_ir(code, memmap[chunk].shift, adr_reg, opts->address_size);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	205 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	206 shr_ir(code, -memmap[chunk].shift, adr_reg, opts->address_size);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	207 }
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	208 or_ir(code, 1, adr_reg, opts->address_size);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	209 after_normal = code->cur + 1;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	210 jmp(code, after_normal);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	211 *normal = code->cur - (normal + 1);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	212 }
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	213 if (memmap[chunk].shift > 0) {
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	214 if (!need_addr_pop && is_write && (memmap[chunk].flags & MMAP_CODE)) {
b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	215 push_r(code, adr_reg);
b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	216 need_addr_pop = 1;
b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	217 }
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	218 shl_ir(code, memmap[chunk].shift, adr_reg, opts->address_size);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	219 } else if (memmap[chunk].shift < 0) {
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	220 if (!need_addr_pop && is_write && (memmap[chunk].flags & MMAP_CODE)) {
b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	221 push_r(code, adr_reg);
b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	222 need_addr_pop = 1;
b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	223 }
2134 9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	224 shr_ir(code, -memmap[chunk].shift, adr_reg, opts->address_size);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	225 }
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	226 if (after_normal) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	227 *after_normal = code->cur - (after_normal + 1);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests Michael Pavone <pavone@retrodev.com> parents: 2133 diff changeset	228 }
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	229 void * cfun;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	230 switch (fun_type)
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	231 {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	232 case READ_16:
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	233 cfun = memmap[chunk].read_16;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	234 break;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	235 case READ_8:
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	236 cfun = memmap[chunk].read_8;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	237 break;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	238 case WRITE_16:
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	239 cfun = memmap[chunk].write_16;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	240 break;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	241 case WRITE_8:
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	242 cfun = memmap[chunk].write_8;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	243 break;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	244 default:
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	245 cfun = NULL;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	246 }
604 39d7d463ed5b Get Z80 banked access sort of working again Michael Pavone <pavone@retrodev.com> parents: 601 diff changeset	247 if(memmap[chunk].flags & access_flag) {
2237 f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	248 uint8_t tmp_size = size;
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	249 if (memmap[chunk].flags & MMAP_PTR_IDX) {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	250 if (memmap[chunk].flags & MMAP_FUNC_NULL) {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	251 cmp_irdisp(code, 0, opts->context_reg, opts->mem_ptr_off + sizeof(void) memmap[chunk].ptr_index, SZ_PTR);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	252 code_ptr not_null = code->cur + 1;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	253 jcc(code, CC_NZ, code->cur + 2);
2339 8990c2f431b1 Fix crash when function pointer path is taken in MMAP_FUNC_NULL region that also has MMAP_CODE Michael Pavone <pavone@retrodev.com> parents: 2269 diff changeset	254 uint32_t stack_off;
8990c2f431b1 Fix crash when function pointer path is taken in MMAP_FUNC_NULL region that also has MMAP_CODE Michael Pavone <pavone@retrodev.com> parents: 2269 diff changeset	255 if (need_addr_pop) {
8990c2f431b1 Fix crash when function pointer path is taken in MMAP_FUNC_NULL region that also has MMAP_CODE Michael Pavone <pavone@retrodev.com> parents: 2269 diff changeset	256 stack_off = code->stack_off;
8990c2f431b1 Fix crash when function pointer path is taken in MMAP_FUNC_NULL region that also has MMAP_CODE Michael Pavone <pavone@retrodev.com> parents: 2269 diff changeset	257 pop_r(code, adr_reg);
8990c2f431b1 Fix crash when function pointer path is taken in MMAP_FUNC_NULL region that also has MMAP_CODE Michael Pavone <pavone@retrodev.com> parents: 2269 diff changeset	258 }
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	259 call(code, opts->save_context);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	260 if (is_write) {
658 6aa29ac33f1a Use call_args and call_args_abi inside gen_mem_fun Michael Pavone <pavone@retrodev.com> parents: 620 diff changeset	261 call_args_abi(code, cfun, 3, opts->scratch2, opts->context_reg, opts->scratch1);
6aa29ac33f1a Use call_args and call_args_abi inside gen_mem_fun Michael Pavone <pavone@retrodev.com> parents: 620 diff changeset	262 mov_rr(code, RAX, opts->context_reg, SZ_PTR);
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	263 } else {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	264 push_r(code, opts->context_reg);
658 6aa29ac33f1a Use call_args and call_args_abi inside gen_mem_fun Michael Pavone <pavone@retrodev.com> parents: 620 diff changeset	265 call_args_abi(code, cfun, 2, opts->scratch1, opts->context_reg);
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	266 pop_r(code, opts->context_reg);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	267 mov_rr(code, RAX, opts->scratch1, size);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	268 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	269 jmp(code, opts->load_context);
2339 8990c2f431b1 Fix crash when function pointer path is taken in MMAP_FUNC_NULL region that also has MMAP_CODE Michael Pavone <pavone@retrodev.com> parents: 2269 diff changeset	270 if (need_addr_pop) {
8990c2f431b1 Fix crash when function pointer path is taken in MMAP_FUNC_NULL region that also has MMAP_CODE Michael Pavone <pavone@retrodev.com> parents: 2269 diff changeset	271 code->stack_off = stack_off;
8990c2f431b1 Fix crash when function pointer path is taken in MMAP_FUNC_NULL region that also has MMAP_CODE Michael Pavone <pavone@retrodev.com> parents: 2269 diff changeset	272 }
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	273
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	274 *not_null = code->cur - (not_null + 1);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	275 }
2237 f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	276 if (size == SZ_B) {
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	277 if ((memmap[chunk].flags & MMAP_ONLY_ODD) \|\| (memmap[chunk].flags & MMAP_ONLY_EVEN)) {
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	278 bt_ir(code, 0, adr_reg, opts->address_size);
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	279 code_ptr good_addr = code->cur + 1;
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	280 jcc(code, (memmap[chunk].flags & MMAP_ONLY_ODD) ? CC_C : CC_NC, code->cur + 2);
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	281 if (!is_write) {
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	282 mov_ir(code, 0xFF, opts->scratch1, SZ_B);
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	283 }
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	284 retn(code);
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	285 *good_addr = code->cur - (good_addr + 1);
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	286 shr_ir(code, 1, adr_reg, opts->address_size);
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	287 } else if (opts->byte_swap \|\| memmap[chunk].flags & MMAP_BYTESWAP) {
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	288 xor_ir(code, 1, adr_reg, opts->address_size);
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	289 }
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	290 } else if ((memmap[chunk].flags & MMAP_ONLY_ODD) \|\| (memmap[chunk].flags & MMAP_ONLY_EVEN)) {
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	291 tmp_size = SZ_B;
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	292 shr_ir(code, 1, adr_reg, opts->address_size);
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	293 if ((memmap[chunk].flags & MMAP_ONLY_EVEN) && is_write) {
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	294 shr_ir(code, 8, opts->scratch1, SZ_W);
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	295 }
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	296 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	297 if (opts->address_size != SZ_D) {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	298 movzx_rr(code, adr_reg, adr_reg, opts->address_size, SZ_D);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	299 }
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	300 if (!need_addr_pop && is_write && (memmap[chunk].flags & MMAP_CODE)) {
1081 89cc20cf1ad3 Fix handling of MMAP_CODE chunks that also have MMAP_PTR_IDX set Michael Pavone <pavone@retrodev.com> parents: 1047 diff changeset	301 push_r(code, adr_reg);
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	302 need_addr_pop = 1;
1081 89cc20cf1ad3 Fix handling of MMAP_CODE chunks that also have MMAP_PTR_IDX set Michael Pavone <pavone@retrodev.com> parents: 1047 diff changeset	303 }
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	304 add_rdispr(code, opts->context_reg, opts->mem_ptr_off + sizeof(void) memmap[chunk].ptr_index, adr_reg, SZ_PTR);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	305 if (is_write) {
2237 f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	306 mov_rrind(code, opts->scratch1, opts->scratch2, tmp_size);
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	307 } else {
2237 f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	308 mov_rindr(code, opts->scratch1, opts->scratch1, tmp_size);
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	309 }
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	310 if (size != tmp_size && !is_write) {
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	311 if (memmap[chunk].flags & MMAP_ONLY_EVEN) {
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	312 shl_ir(code, 8, opts->scratch1, SZ_W);
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	313 mov_ir(code, 0xFF, opts->scratch1, SZ_B);
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	314 } else {
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	315 or_ir(code, 0xFF00, opts->scratch1, SZ_W);
f82c090c1e89 Implement MMAP_ONLY_ODD/EVEN in combination with MMAP_PTR_IDX. Fixes games that have SRAM when a system with TMSS is selected Michael Pavone <pavone@retrodev.com> parents: 2138 diff changeset	316 }
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	317 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	318 } else {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	319 if (size == SZ_B) {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	320 if ((memmap[chunk].flags & MMAP_ONLY_ODD) \|\| (memmap[chunk].flags & MMAP_ONLY_EVEN)) {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	321 bt_ir(code, 0, adr_reg, opts->address_size);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	322 code_ptr good_addr = code->cur + 1;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	323 jcc(code, (memmap[chunk].flags & MMAP_ONLY_ODD) ? CC_C : CC_NC, code->cur + 2);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	324 if (!is_write) {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	325 mov_ir(code, 0xFF, opts->scratch1, SZ_B);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	326 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	327 retn(code);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	328 *good_addr = code->cur - (good_addr + 1);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	329 shr_ir(code, 1, adr_reg, opts->address_size);
604 39d7d463ed5b Get Z80 banked access sort of working again Michael Pavone <pavone@retrodev.com> parents: 601 diff changeset	330 } else if (opts->byte_swap \|\| memmap[chunk].flags & MMAP_BYTESWAP) {
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	331 xor_ir(code, 1, adr_reg, opts->address_size);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	332 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	333 } else if ((memmap[chunk].flags & MMAP_ONLY_ODD) \|\| (memmap[chunk].flags & MMAP_ONLY_EVEN)) {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	334 tmp_size = SZ_B;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	335 shr_ir(code, 1, adr_reg, opts->address_size);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	336 if ((memmap[chunk].flags & MMAP_ONLY_EVEN) && is_write) {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	337 shr_ir(code, 8, opts->scratch1, SZ_W);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	338 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	339 }
595 68f86ca4bb32 Add a couple of missing checks for the byte_swap and address_size parameters in gen_mem_fun Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	340 if (opts->address_size != SZ_D) {
68f86ca4bb32 Add a couple of missing checks for the byte_swap and address_size parameters in gen_mem_fun Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	341 movzx_rr(code, adr_reg, adr_reg, opts->address_size, SZ_D);
68f86ca4bb32 Add a couple of missing checks for the byte_swap and address_size parameters in gen_mem_fun Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	342 }
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	343 if ((intptr_t)memmap[chunk].buffer <= 0x7FFFFFFF && (intptr_t)memmap[chunk].buffer >= -2147483648) {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	344 if (is_write) {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	345 mov_rrdisp(code, opts->scratch1, opts->scratch2, (intptr_t)memmap[chunk].buffer, tmp_size);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	346 } else {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	347 mov_rdispr(code, opts->scratch1, (intptr_t)memmap[chunk].buffer, opts->scratch1, tmp_size);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	348 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	349 } else {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	350 if (is_write) {
760 656b1fded67f Fix self modifying code checks on platforms like OS X on which guest RAM ends up at an address unreachable with a 32-bit displacement Michael Pavone <pavone@retrodev.com> parents: 756 diff changeset	351 push_r(code, opts->scratch2);
656b1fded67f Fix self modifying code checks on platforms like OS X on which guest RAM ends up at an address unreachable with a 32-bit displacement Michael Pavone <pavone@retrodev.com> parents: 756 diff changeset	352 mov_ir(code, (intptr_t)memmap[chunk].buffer, opts->scratch2, SZ_PTR);
656b1fded67f Fix self modifying code checks on platforms like OS X on which guest RAM ends up at an address unreachable with a 32-bit displacement Michael Pavone <pavone@retrodev.com> parents: 756 diff changeset	353 add_rdispr(code, RSP, 0, opts->scratch2, SZ_PTR);
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	354 mov_rrind(code, opts->scratch1, opts->scratch2, tmp_size);
760 656b1fded67f Fix self modifying code checks on platforms like OS X on which guest RAM ends up at an address unreachable with a 32-bit displacement Michael Pavone <pavone@retrodev.com> parents: 756 diff changeset	355 if (is_write && (memmap[chunk].flags & MMAP_CODE)) {
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	356 need_addr_pop = 1;
760 656b1fded67f Fix self modifying code checks on platforms like OS X on which guest RAM ends up at an address unreachable with a 32-bit displacement Michael Pavone <pavone@retrodev.com> parents: 756 diff changeset	357 } else {
1511 2a5649a767e7 Fix accidental add to RSP with SZ_D and SZ_PTR. Using SZ_D breakse when the stack is located outside of the 32-bit addressable range Michael Pavone <pavone@retrodev.com> parents: 1465 diff changeset	358 add_ir(code, sizeof(void*), RSP, SZ_PTR);
894 a7774fc2de4b Partially working change to do proper stack alignment rather than doing a lame alignment check when calling a C compile dfunction. 68K core seems okay, but Z80 is busted. Michael Pavone <pavone@retrodev.com> parents: 892 diff changeset	359 code->stack_off -= sizeof(void *);
760 656b1fded67f Fix self modifying code checks on platforms like OS X on which guest RAM ends up at an address unreachable with a 32-bit displacement Michael Pavone <pavone@retrodev.com> parents: 756 diff changeset	360 }
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	361 } else {
756 e1dc98f7ed9f Preserve scratch2 when using it as a temporary in memory read functions. This fixes a bunch of issues with the Z80 core and possibly some issues with the 68K core as well Michael Pavone <pavone@retrodev.com> parents: 750 diff changeset	362 push_r(code, opts->scratch2);
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	363 mov_ir(code, (intptr_t)memmap[chunk].buffer, opts->scratch2, SZ_PTR);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	364 mov_rindexr(code, opts->scratch2, opts->scratch1, 1, opts->scratch1, tmp_size);
756 e1dc98f7ed9f Preserve scratch2 when using it as a temporary in memory read functions. This fixes a bunch of issues with the Z80 core and possibly some issues with the 68K core as well Michael Pavone <pavone@retrodev.com> parents: 750 diff changeset	365 pop_r(code, opts->scratch2);
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	366 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	367 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	368 if (size != tmp_size && !is_write) {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	369 if (memmap[chunk].flags & MMAP_ONLY_EVEN) {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	370 shl_ir(code, 8, opts->scratch1, SZ_W);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	371 mov_ir(code, 0xFF, opts->scratch1, SZ_B);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	372 } else {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	373 or_ir(code, 0xFF00, opts->scratch1, SZ_W);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	374 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	375 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	376 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	377 if (is_write && (memmap[chunk].flags & MMAP_CODE)) {
2138 b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	378 if (need_addr_pop) {
b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	379 pop_r(code, adr_reg);
b6338e18787e Fix some dynarec code invalidation issues Michael Pavone <pavone@retrodev.com> parents: 2134 diff changeset	380 }
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	381 mov_rr(code, opts->scratch2, opts->scratch1, opts->address_size);
620 9d6fed6501ba Fix handling of code writes for Z80 core. This seems to get things close to being back to where they were before the big refactor that broke the Z80 core. Some problems remain. Notably the sound driver in Sonic 2 is still quite broken. Michael Pavone <pavone@retrodev.com> parents: 604 diff changeset	382 shr_ir(code, opts->ram_flags_shift, opts->scratch1, opts->address_size);
690 fc04781f4d28 Removed hardcoded assumptions in M68K core about which parts of the memory map are RAM Michael Pavone <pavone@retrodev.com> parents: 667 diff changeset	383 bt_rrdisp(code, opts->scratch1, opts->context_reg, ram_flags_off, opts->address_size);
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	384 code_ptr not_code = code->cur + 1;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	385 jcc(code, CC_NC, code->cur + 2);
1084 193db42e702b Remove hacky assumption about Genesis memory map in M68K core Michael Pavone <pavone@retrodev.com> parents: 1081 diff changeset	386 if (memmap[chunk].mask != opts->address_mask) {
1107 fc125af5e4f1 Fix to the fix of handling of self modifying code. Was ORing the base address with the wrong register before calling the modified code handler Michael Pavone <pavone@retrodev.com> parents: 1086 diff changeset	387 or_ir(code, memmap[chunk].start, opts->scratch2, opts->address_size);
1084 193db42e702b Remove hacky assumption about Genesis memory map in M68K core Michael Pavone <pavone@retrodev.com> parents: 1081 diff changeset	388 }
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	389 call(code, opts->save_context);
658 6aa29ac33f1a Use call_args and call_args_abi inside gen_mem_fun Michael Pavone <pavone@retrodev.com> parents: 620 diff changeset	390 call_args(code, opts->handle_code_write, 2, opts->scratch2, opts->context_reg);
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	391 mov_rr(code, RAX, opts->context_reg, SZ_PTR);
1086 f0a1e0a2263c Made some optimizations to gen_mem_fun to keep the size of chunk handler sections within range of a single byte displacement Michael Pavone <pavone@retrodev.com> parents: 1084 diff changeset	392 jmp(code, opts->load_context);
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	393 *not_code = code->cur - (not_code+1);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	394 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	395 retn(code);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	396 } else if (cfun) {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	397 call(code, opts->save_context);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	398 if (is_write) {
658 6aa29ac33f1a Use call_args and call_args_abi inside gen_mem_fun Michael Pavone <pavone@retrodev.com> parents: 620 diff changeset	399 call_args_abi(code, cfun, 3, opts->scratch2, opts->context_reg, opts->scratch1);
6aa29ac33f1a Use call_args and call_args_abi inside gen_mem_fun Michael Pavone <pavone@retrodev.com> parents: 620 diff changeset	400 mov_rr(code, RAX, opts->context_reg, SZ_PTR);
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	401 } else {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	402 push_r(code, opts->context_reg);
658 6aa29ac33f1a Use call_args and call_args_abi inside gen_mem_fun Michael Pavone <pavone@retrodev.com> parents: 620 diff changeset	403 call_args_abi(code, cfun, 2, opts->scratch1, opts->context_reg);
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	404 pop_r(code, opts->context_reg);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	405 mov_rr(code, RAX, opts->scratch1, size);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	406 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	407 jmp(code, opts->load_context);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	408 } else {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	409 //Not sure the best course of action here
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	410 if (!is_write) {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	411 mov_ir(code, size == SZ_B ? 0xFF : 0xFFFF, opts->scratch1, size);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	412 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	413 retn(code);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	414 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	415 if (lb_jcc) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	416 if (need_wide_jcc) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	417 ((int32_t)lb_jcc) = code->cur - (lb_jcc+4);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	418 } else if (code->cur - (lb_jcc+1) > 0x7f) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	419 need_wide_jcc = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	420 chunk--;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	421 *code = chunk_start;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	422 continue;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	423 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	424 *lb_jcc = code->cur - (lb_jcc+1);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	425 }
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	426 lb_jcc = NULL;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	427 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	428 if (ub_jcc) {
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	429 if (need_wide_jcc) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	430 ((int32_t)ub_jcc) = code->cur - (ub_jcc+4);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	431 } else if (code->cur - (ub_jcc+1) > 0x7f) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	432 need_wide_jcc = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	433 chunk--;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	434 *code = chunk_start;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	435 continue;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	436 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	437 *ub_jcc = code->cur - (ub_jcc+1);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	438 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	439
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	440 ub_jcc = NULL;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	441 }
2070 afc54649ebed Fix error in code write detection introduced from "wide" jcc change Michael Pavone <pavone@retrodev.com> parents: 2054 diff changeset	442 if (memmap[chunk].flags & MMAP_CODE) {
2113 0013362c320c Fix handling of ram code flag offset calculation for ranges that are not an even multiple of the code flag page size Michael Pavone <pavone@retrodev.com> parents: 2070 diff changeset	443 uint32_t size = chunk_size(opts, memmap + chunk);
0013362c320c Fix handling of ram code flag offset calculation for ranges that are not an even multiple of the code flag page size Michael Pavone <pavone@retrodev.com> parents: 2070 diff changeset	444 uint32_t size_round_mask = (1 << (opts->ram_flags_shift + 3)) - 1;
0013362c320c Fix handling of ram code flag offset calculation for ranges that are not an even multiple of the code flag page size Michael Pavone <pavone@retrodev.com> parents: 2070 diff changeset	445 if (size & size_round_mask) {
0013362c320c Fix handling of ram code flag offset calculation for ranges that are not an even multiple of the code flag page size Michael Pavone <pavone@retrodev.com> parents: 2070 diff changeset	446 size &= ~size_round_mask;
0013362c320c Fix handling of ram code flag offset calculation for ranges that are not an even multiple of the code flag page size Michael Pavone <pavone@retrodev.com> parents: 2070 diff changeset	447 size += size_round_mask + 1;
2070 afc54649ebed Fix error in code write detection introduced from "wide" jcc change Michael Pavone <pavone@retrodev.com> parents: 2054 diff changeset	448 }
2113 0013362c320c Fix handling of ram code flag offset calculation for ranges that are not an even multiple of the code flag page size Michael Pavone <pavone@retrodev.com> parents: 2070 diff changeset	449 ram_flags_off += size >> (opts->ram_flags_shift + 3);
2070 afc54649ebed Fix error in code write detection introduced from "wide" jcc change Michael Pavone <pavone@retrodev.com> parents: 2054 diff changeset	450 }
2054 8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	451 if (need_wide_jcc) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	452 need_wide_jcc = 0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM Michael Pavone <pavone@retrodev.com> parents: 2036 diff changeset	453 }
589 2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	454 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	455 if (!is_write) {
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	456 mov_ir(code, size == SZ_B ? 0xFF : 0xFFFF, opts->scratch1, size);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	457 }
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	458 retn(code);
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	459 return start;
2dde38c1744f Split gen_mem_fun out of m68k_core_x86 and make it more generic so it can be used by the Z80 core Michael Pavone <pavone@retrodev.com> parents: 567 diff changeset	460 }

Mercurial > repos > blastem

annotate backend_x86.c @ 2688:b42f00a3a937 default tip