repos/tabletprog: modules/il.tp annotate

annotate modules/il.tp @ 353:95bc24c729e6

Move right hand parameter to cmp in _compileBinary to a temp reg if it is a constant since those are only supported in the left hand param currently

author	Michael Pavone <pavone@retrodev.com>
date	Tue, 14 Apr 2015 19:54:03 -0700
parents	f74ce841fd1e
children	a6cdcc1b1c02

rev	line source
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	1 {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	2 //commutative ops
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	3 _add <- 0
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	4 _and <- 1
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	5 _or <- 2
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 _xor <- 3
315 f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	7 _muls <- 4
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	8 _mulu <- 5
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	9 //non-commutative ops
315 f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	10 _divs <- 6
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	11 _divu <- 7
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	12 _sub <- 8
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	13 _cmp <- 9
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	14 _not <- 10
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	15 _sl <- 11
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	16 _asr <- 12
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	17 _lsr <- 13
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	18 _rol <- 14
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	19 _ror <- 15
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	20 _mov <- 16
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	21 _call <- 17
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	22 _ret <- 18
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	23 _skipif <- 19
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	24 _skipifelse <- 20
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	25 _save <- 21
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	26 _bool <- 22
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	27
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	28 _names <- #[
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	29 "add"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	30 "and"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	31 "or"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	32 "xor"
315 f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	33 "muls"
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	34 "mulu"
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	35 "divs"
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	36 "divu"
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	37 "sub"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	38 "cmp"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	39 "not"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	40 "sl"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	41 "asr"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	42 "lsr"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	43 "rol"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	44 "ror"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	45 "mov"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	46 "call"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	47 "ret"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	48 "skipIf"
315 f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	49 "skipIf:else"
195 7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	50 "save"
310 2308336790d4 WIP compiler module for low-level dialect Michael Pavone <pavone@retrodev.com> parents: 203 diff changeset	51 "bool"
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	52 ]
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	53
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	54 op3:a:b:out:size <- :_opcode :_ina :_inb :_out :_size {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	55 #{
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	56 opcode <- { _opcode }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	57 ina <- { _ina }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	58 inb <- { _inb }
315 f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	59 commutative? <- { _opcode < _divs }
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	60 out <- { _out }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	61 size <- { _size }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	62 numops <- { 3 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	63 name <- { _names get: _opcode }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	64 string <- { name . " " . (string: _ina) . " " . (string: _inb) . " " . (string: _out) . " " . (string: _size) }
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	65 recordUsage:at <- :tracker :address {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	66 if: (not: (_ina isInteger?)) {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	67 _ina recordUsage: tracker at: 0 \| address withSize: _size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	68 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	69 _inb recordUsage: tracker at: 0 \| address withSize: _size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	70 _out recordUsage: tracker at: 1 \| address withSize: _size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	71 }
200 49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	72 assignRegs:at:withSource:andUsage <- :assignments :at :regSrc :usage {
194 30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	73 newa <- if: (not: (_ina isInteger?)) {
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	74 _ina assign: assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	75 } else: { _ina }
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	76 newb <- _inb assign: assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	77 newout <- _out assign: assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	78 op3: _opcode a: newa b: newb out: newout size: _size
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	79 }
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	80 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	81 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	82 op2:in:out:size <- :_opcode :_in :_out :_size {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	83 #{
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	84 opcode <- { _opcode }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	85 in <- { _in }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	86 out <- { _out }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	87 size <- { _size }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	88 numops <- { 2 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	89 name <- { _names get: _opcode }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	90 string <- { name . " " . (string: _in) . " " . (string: _out) . " " . (string: _size) }
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	91 recordUsage:at <- :tracker :address {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	92 if: (not: (_in isInteger?)) {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	93 _in recordUsage: tracker at: 0 \| address withSize: _size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	94 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	95 _out recordUsage: tracker at: 1 \| address withSize: _size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	96 }
200 49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	97 assignRegs:at:withSource:andUsage <- :assignments :at :regSrc :usage {
194 30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	98 newin <- if: (not: (_in isInteger?)) {
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	99 _in assign: assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	100 } else: { _in }
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	101 newout <- _out assign: assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	102 op2: _opcode in: newin out: newout size: _size
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	103 }
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	104 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	105 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	106 op1:arg:size <- :_opcode :_arg :_size {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	107 #{
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	108 opcode <- { _opcode }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	109 arg <- { _arg }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	110 size <- { _size }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	111 numops <- { 1 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	112 name <- { _names get: _opcode }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	113 string <- { name . " " . (string: _arg) . " " . (string: _size) }
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	114 recordUsage:at <- :tracker :address {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	115 if: (not: (_arg isInteger?)) {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	116 _arg recordUsage: tracker at: address withSize: _size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	117 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	118 }
200 49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	119 assignRegs:at:withSource:andUsage <- :assignments :at :regSrc :usage {
194 30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	120 newarg <- if: (not: (_arg isInteger?)) {
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	121 _arg assign: assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	122 } else: { _arg }
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	123 op1: _opcode arg: newarg size: _size
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	124 }
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	125 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	126 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	127
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	128 _sizenames <- #["b" "w" "l" "q"]
193 4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	129 _size <- :_bytes {
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	130 #{
193 4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	131 bytes <- { _bytes }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	132 string <- {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	133 idx <- if: _bytes = 8 { 3 } else: { _bytes / 2}
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	134 _sizenames get: idx
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	135 }
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	136 = <- :other {
193 4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	137 _bytes = (other bytes)
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	138 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	139 <= <- :other {
193 4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	140 _bytes <= (other bytes)
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	141 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	142 >= <- :other {
193 4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	143 _bytes >= (other bytes)
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	144 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	145 > <- :other {
193 4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	146 _bytes > (other bytes)
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	147 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	148 < <- :other {
193 4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	149 _bytes < (other bytes)
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	150 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	151 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	152 }
193 4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	153 byte <- _size: 1
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	154 word <- _size: 2
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	155 long <- _size: 4
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	156 quad <- _size: 8
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	157
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	158 _retr <- #{
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	159 isInteger? <- { false }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	160 register? <- { true }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	161 argument? <- { false }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	162 return? <- { true }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	163 string <- { "retr" }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	164 = <- :other {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	165 (not: (other isInteger?)) && (other register?) && (other return?)
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	166 }
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	167 != <- :other {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	168 not: self = other
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	169 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	170 recordUsage:at:withSize <- :tracker :address :size {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	171 //TODO: Figure out what tracking is necessary here
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	172 }
194 30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	173 assign:withSource <- :assignments :regSrc {
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	174 regSrc allocRet
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	175 }
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	176 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	177
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	178 _condnames <- #[
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	179 "eq"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	180 "neq"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	181 "ge"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	182 "le"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	183 "gr"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	184 "ls"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	185 "uge"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	186 "ule"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	187 "ugr"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	188 "uls"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	189 ]
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	190 condition <- :num {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	191 #{
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	192 cc <- { num }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	193 string <- { _condnames get: num }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	194 = <- :other { num = (other cc) }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	196 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	197 _eq <- condition: 0
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	198 _neq <- condition: 1
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	199 _ge <- condition: 2
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	200 _le <- condition: 3
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	201 _gr <- condition: 4
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	202 _ls <- condition: 5
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	203 _uge <- condition: 6
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	204 _ule <- condition: 7
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	205 _ugr <- condition: 8
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	206 _uls <- condition: 9
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	207
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	208 #{
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	209 b <- { byte }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	210 w <- { word }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	211 l <- { long }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	212 q <- { quad }
352 f74ce841fd1e Produce something resembling correct il from low level dialect Michael Pavone <pavone@retrodev.com> parents: 350 diff changeset	213
f74ce841fd1e Produce something resembling correct il from low level dialect Michael Pavone <pavone@retrodev.com> parents: 350 diff changeset	214 sizeFromBytes <- :bytes {
f74ce841fd1e Produce something resembling correct il from low level dialect Michael Pavone <pavone@retrodev.com> parents: 350 diff changeset	215 if: bytes < 4 {
f74ce841fd1e Produce something resembling correct il from low level dialect Michael Pavone <pavone@retrodev.com> parents: 350 diff changeset	216 if: bytes = 1 { b } else: { w }
f74ce841fd1e Produce something resembling correct il from low level dialect Michael Pavone <pavone@retrodev.com> parents: 350 diff changeset	217 } else: {
f74ce841fd1e Produce something resembling correct il from low level dialect Michael Pavone <pavone@retrodev.com> parents: 350 diff changeset	218 if: bytes = 4 { l } else: { q }
f74ce841fd1e Produce something resembling correct il from low level dialect Michael Pavone <pavone@retrodev.com> parents: 350 diff changeset	219 }
f74ce841fd1e Produce something resembling correct il from low level dialect Michael Pavone <pavone@retrodev.com> parents: 350 diff changeset	220 }
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	221
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	222 eq <- { _eq }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	223 neq <- { _neq }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	224
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	225 //signed conditions
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	226 ge <- { _ge }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	227 le <- { _le }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	228 gr <- { _gr }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	229 ls <- { _ls }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	230
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	231 //unsigned conditions
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	232 uge <- { _uge }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	233 ule <- { _ule }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	234 ugr <- { _ugr }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	235 uls <- { _uls }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	236
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	237
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	238 reg <- :num {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	239 #{
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	240 isInteger? <- { false }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	241 register? <- { true }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	242 argument? <- { false }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	243 return? <- { false }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	244 regnum <- { num }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	245 string <- { "r" . (string: num) }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	246 = <- :other {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	247 (not: (other isInteger?)) && (other register?) && (not: (other argument?)) && (not: (other return?)) && num = (other regnum)
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	248 }
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	249 != <- :other {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	250 not: self = other
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	251 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	252 recordUsage:at:withSize <- :tracker :address :size {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	253 tracker reg: self usedAt: address withSize: size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	254 }
194 30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	255 assign:withSource <- :assignments :regSrc {
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	256 assignments get: self
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	257 }
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	258 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	259 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	260 arg <- :num {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	261 #{
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	262 isInteger? <- { false }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	263 register? <- { true }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	264 argument? <- { true }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	265 return? <- { false }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	266 argnum <- { num }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	267 string <- { "a" . (string: num) }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	268 = <- :other {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	269 (not: (other isInteger?)) && (other register?) && (other argument?) && num = (other regnum)
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	270 }
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	271 != <- :other {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	272 not: self = other
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	273 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	274 recordUsage:at:withSize <- :tracker :address :size {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	275 tracker arg: self usedAt: address withSize: size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	276 }
194 30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	277 assign:withSource <- :assignments :regSrc {
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	278 regSrc allocArg: num
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	279 }
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	280 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	281 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	282 retr <- { _retr }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	283
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	284 base:offset <- :_base :_offset {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	285 #{
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	286 base <- { _base }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	287 offset <- { _offset }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	288 string <- {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	289 start <- if: _offset = 0 { "" } else: { (string: _offset) }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	290 start . "[" . (string: _base) . "]"
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	291 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	292 recordUsage:at:withSize <- :tracker :address :size {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	293 _base recordUsage: tracker at: address withSize: size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	294 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	295 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	296 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	297
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	298 add <- :ina inb out size {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	299 op3: _add a: ina b: inb out: out size: size
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	300 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	301
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	302 sub <- :ina inb out size {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	303 op3: _sub a: ina b: inb out: out size: size
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	304 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	305
315 f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	306 cmp <- :ina inb size {
352 f74ce841fd1e Produce something resembling correct il from low level dialect Michael Pavone <pavone@retrodev.com> parents: 350 diff changeset	307 op2: _cmp in: ina out: inb size: size
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	308 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	309
315 f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	310 band <- :ina inb out size {
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	311 op3: _and a: ina b: inb out: out size: size
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	312 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	313
315 f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	314 bor <- :ina inb out size {
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	315 op3: _or a: ina b: inb out: out size: size
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	316 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	317
315 f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	318 bxor <- :ina inb out size {
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	319 op3: _xor a: ina b: inb out: out size: size
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	320 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	321
315 f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	322 muls <- :ina inb out size {
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	323 op3: _muls a: ina b: inb out: out size: size
310 2308336790d4 WIP compiler module for low-level dialect Michael Pavone <pavone@retrodev.com> parents: 203 diff changeset	324 }
2308336790d4 WIP compiler module for low-level dialect Michael Pavone <pavone@retrodev.com> parents: 203 diff changeset	325
315 f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	326 mulu <- :ina inb out size {
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	327 op3: _mulu a: ina b: inb out: out size: size
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	328 }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	329
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	330 divs <- :ina inb out size {
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	331 op3: _divs a: ina b: inb out: out size: size
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	332 }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	333
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	334 divu <- :ina inb out size {
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	335 op3: _divu a: ina b: inb out: out size: size
310 2308336790d4 WIP compiler module for low-level dialect Michael Pavone <pavone@retrodev.com> parents: 203 diff changeset	336 }
2308336790d4 WIP compiler module for low-level dialect Michael Pavone <pavone@retrodev.com> parents: 203 diff changeset	337
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	338 bnot <- :in out size {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	339 op2: _not in: in out: out size: size
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	340 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	341
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	342 sl <- :shift in out size {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	343 op3: _sl a: shift b: in out: out size: size
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	344 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	345
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	346 asr <- :shift in out size {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	347 op3: _asr a: shift b: in out: out size: size
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	348 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	349
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	350 lsr <- :shift in out size {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	351 op3: _lsr a: shift b: in out: out size: size
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	352 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	353
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	354 rol <- :rot in out size {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	355 op3: _rol a: rot b: in out: out size: size
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	356 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	357
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	358 ror <- :rot in out size {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	359 op3: _ror a: rot b: in out: out size: size
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	360 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	361
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	362 mov <- :in out size {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	363 op2: _mov in: in out: out size: size
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	364 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	365
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	366 call:withArgs <- :_target :_args {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	367 #{
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	368 opcode <- { _call }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	369 target <- { _target }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	370 args <- { _args }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	371 numops <- { 0 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	372 name <- { _names get: _call }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	373 string <- {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	374 argstr <- _args map: :el {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	375 string: el
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	376 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	377 name . " " . (string: _target) . " " . (argstr join: " ")
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	378 }
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	379 recordUsage:at <- :tracker :address {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	380 if: (not: (_target isString?)) {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	381 //TODO: use size l for 32-bit targets or an abstract pointer size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	382 _target recordUsage: tracker at: address withSize: q
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	383 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	384 foreach: _args :_ arg {
348 a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	385 if: (not: (arg isInteger?)) {
a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	386 //TODO: have some mechanism for properly expressing sizes of arguments
a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	387 arg recordUsage: tracker at: address withSize: q
a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	388 }
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	389 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	390 }
200 49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	391 assignRegs:at:withSource:andUsage <- :assignments :address :regSrc :usage {
194 30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	392 newtarget <- if: (_target isString?) { _target } else: {
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	393 _target assign: assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	394 }
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	395 newargs <- _args map: :arg {
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	396 if: (arg isInteger?) { arg } else: {
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	397 arg assign: assignments withSource: regSrc
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	398 }
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	399 }
200 49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	400 newcall <- call: newtarget withArgs: newargs
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	401 regSrc returnAll
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	402 raddress <- address reverse
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	403 foreach: (usage liveArgsAt: raddress) :_ arg {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	404 regSrc allocArg: (arg num)
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	405 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	406 foreach: (usage liveRegsAt: raddress) :_ reg {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	407 regSrc allocSpecific: (assignments get: reg)
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	408 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	409 tosave <- regSrc needSaveForCall
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	410 if: (tosave length) > 0 {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	411 save: tosave #[newcall]
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	412 } else: {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	413 newcall
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	414 }
194 30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	415 }
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	416 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	417 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	418
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	419 return <- :val size {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	420 op1: _ret arg: val size: size
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	421 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	422 skipIf <- :_cond _toskip {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	423 #{
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	424 opcode <- { _skipif }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	425 toskip <- { _toskip }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	426 cond <- { _cond }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	427 numops <- { 0 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	428 name <- { _names get: _skipif }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	429 string <- {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	430 block <- (_toskip map: :el { string: el }) join: "\n\t"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	431 if: (_toskip length) > 0 {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	432 block <- "\n\t" . block . "\n"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	433 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	434 name . " " . (string: _cond) . " {" . block . "}"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	435 }
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	436 recordUsage:at <- :tracker :address {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	437 foreach: _toskip :idx inst {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	438 inst recordUsage: tracker at: idx \| address
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	439 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	440 }
200 49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	441 assignRegs:at:withSource:andUsage <- :assignments :address :regSrc :usage {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	442 newskip <- #[]
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	443 foreach: _toskip :idx inst {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	444 newskip append: (inst assignRegs: assignments at: idx \| address withSource: regSrc andUsage: usage)
194 30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	445 }
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	446 skipIf: _cond newskip
30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	447 }
200 49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	448 to2OpInst <- {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	449 skipIf: _cond (to2Op: _toskip)
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	450 }
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	451 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	452 }
315 f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	453 skipIf:else <- :_cond _toskip :_else {
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	454 #{
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	455 opcode <- { _skipif }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	456 toskip <- { _toskip }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	457 else <- { _else }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	458 cond <- { _cond }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	459 numops <- { 0 }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	460 name <- { _names get: _skipifelse }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	461 string <- {
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	462 block <- (_toskip map: :el { string: el }) join: "\n\t"
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	463 if: (_toskip length) > 0 {
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	464 block <- "\n\t" . block . "\n"
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	465 }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	466 elseblock <- (_else map: :el { string: el }) join: "\n\t"
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	467 if: (_else length) > 0 {
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	468 elseblock <- "\n\t" . elseblock . "\n"
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	469 }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	470 name . " " . (string: _cond) . " {" . block . "} {" . elseblock . "}"
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	471 }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	472 recordUsage:at <- :tracker :address {
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	473 foreach: _toskip :idx inst {
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	474 inst recordUsage: tracker at: idx \| address
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	475 }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	476 foreach: _else :idx inst {
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	477 inst recordUsage: tracker at: idx \| address
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	478 }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	479 }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	480 assignRegs:at:withSource:andUsage <- :assignments :address :regSrc :usage {
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	481 newskip <- #[]
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	482 foreach: _toskip :idx inst {
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	483 newskip append: (inst assignRegs: assignments at: idx \| address withSource: regSrc andUsage: usage)
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	484 }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	485 newelse <- #[]
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	486 foreach: _else :idx inst {
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	487 newelse append: (inst assignRegs: assignments at: idx \| address withSource: regSrc andUsage: usage)
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	488 }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	489 skipIf: _cond newskip else: newelse
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	490 }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	491 to2OpInst <- {
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	492 skipIf: _cond (to2Op: _toskip) (to2Op: _else)
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	493 }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	494 }
f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	495 }
203 56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	496 save <- :regs :_scope{
195 7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	497 #{
7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	498 opcode <- { _save }
7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	499 numops <- { 0 }
7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	500 name <- { _names get: _save }
203 56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	501 tosave <- { regs }
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	502 scope <- { _scope }
195 7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	503 string <- {
203 56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	504 block <- _scope join: "\n\t"
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	505 if: (_scope length) > 0 {
195 7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	506 block <- "\n\t" . block . "\n"
7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	507 }
7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	508 name . " " . (regs join: " ") . " {" . block . "}"
7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	509 }
200 49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	510 to2OpInst <- {
203 56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	511 save: regs (to2Op: _scope)
200 49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	512 }
195 7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	513 }
7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	514 }
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	515
310 2308336790d4 WIP compiler module for low-level dialect Michael Pavone <pavone@retrodev.com> parents: 203 diff changeset	516 //produces a non-zero value or zero based on condition code flags
2308336790d4 WIP compiler module for low-level dialect Michael Pavone <pavone@retrodev.com> parents: 203 diff changeset	517 bool <- :_cond _out {
2308336790d4 WIP compiler module for low-level dialect Michael Pavone <pavone@retrodev.com> parents: 203 diff changeset	518 #{
2308336790d4 WIP compiler module for low-level dialect Michael Pavone <pavone@retrodev.com> parents: 203 diff changeset	519 opcode <- { _bool }
2308336790d4 WIP compiler module for low-level dialect Michael Pavone <pavone@retrodev.com> parents: 203 diff changeset	520 cond <- { _cond }
315 f987bb2a1911 WIP native compiler work Michael Pavone <pavone@retrodev.com> parents: 310 diff changeset	521 out <- { _out }
352 f74ce841fd1e Produce something resembling correct il from low level dialect Michael Pavone <pavone@retrodev.com> parents: 350 diff changeset	522 name <- { _names get: _bool }
310 2308336790d4 WIP compiler module for low-level dialect Michael Pavone <pavone@retrodev.com> parents: 203 diff changeset	523 numops <- { 0 }
352 f74ce841fd1e Produce something resembling correct il from low level dialect Michael Pavone <pavone@retrodev.com> parents: 350 diff changeset	524 string <- {
f74ce841fd1e Produce something resembling correct il from low level dialect Michael Pavone <pavone@retrodev.com> parents: 350 diff changeset	525 name . " " . cond . " " . out
f74ce841fd1e Produce something resembling correct il from low level dialect Michael Pavone <pavone@retrodev.com> parents: 350 diff changeset	526 }
310 2308336790d4 WIP compiler module for low-level dialect Michael Pavone <pavone@retrodev.com> parents: 203 diff changeset	527 }
2308336790d4 WIP compiler module for low-level dialect Michael Pavone <pavone@retrodev.com> parents: 203 diff changeset	528 }
2308336790d4 WIP compiler module for low-level dialect Michael Pavone <pavone@retrodev.com> parents: 203 diff changeset	529
348 a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	530 allocRegs:withSource <- :instarr :regSrc {
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	531 _regMap <- dict linear
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	532 _argMap <- dict linear
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	533
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	534 _usageTracker <- :_firstUsage {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	535 #{
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	536 firstUsage <- _firstUsage
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	537 lastUsage <- _firstUsage
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	538 useCount <- 0
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	539 maxSize <- byte
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	540 usedAt:withSize <- :address :size {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	541 useCount <- useCount + 1
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	542 lastUsage <- address
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	543 if: size > maxSize {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	544 maxSize <- size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	545 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	546 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	547 string <- {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	548 "Uses: " . useCount . ", FirstUse: " . (firstUsage join: ":") . ", Last Use: " . (lastUsage join: ":") . ", Max Size: " . maxSize
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	549 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	550 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	551 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	552
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	553 _maxUses <- 0
200 49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	554 liveFrom:to <- :regs :from :to {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	555 live <- #[]
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	556 foreach: regs :reg usage {
348 a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	557 if: (addrGreatEq: (usage lastUsage) from) && (addrLessEq: (usage firstUsage) to) {
200 49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	558 live append: reg
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	559 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	560 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	561 live
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	562 }
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	563 regUsage <- #{
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	564 reg:usedAt:withSize <- :reg :address :size {
193 4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	565 raddress <- address reverse
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	566 usage <- _regMap get: reg elseSet: {
193 4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	567 _usageTracker: raddress
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	568 }
193 4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	569 usage usedAt: raddress withSize: size
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	570 if: (usage useCount) > _maxUses {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	571 _maxUses <- usage useCount
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	572 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	573 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	574 arg:usedAt:withSize <- :arg :address :size {
193 4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	575 raddress <- address reverse
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	576 usage <- _argMap get: arg elseSet: {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	577 _usageTracker: [0 0]
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	578 }
193 4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	579 usage usedAt: raddress withSize: size
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	580 }
200 49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	581
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	582 liveRegsAt <- :address {
348 a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	583 liveFrom: _regMap address to: address
200 49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	584 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	585 liveArgsAt <- :address {
348 a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	586 liveFrom: _argMap address to: address
200 49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	587 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	588
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	589 print <- {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	590 foreach: _regMap :reg usage {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	591 print: (string: reg) . " \| " . (string: usage) . "\n"
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	592 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	593 foreach: _argMap :arg usage {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	594 print: (string: arg) . " \| " . (string: usage) . "\n"
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	595 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	596 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	597 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	598 foreach: instarr :idx inst {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	599 inst recordUsage: regUsage at: [idx]
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	600 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	601 print: regUsage
193 4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	602
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	603 addrLessEq <- :left :right {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	604 lesseq <- true
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	605 while: { lesseq && (not: (left empty?)) && (not: (right empty?)) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	606 if: (left value) > (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	607 lesseq <- false
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	608 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	609 if: (left value) < (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	610 left <- []
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	611 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	612 left <- left tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	613 right <- right tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	614 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	615 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	616 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	617 lesseq
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	618 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	619
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	620 addrGreatEq <- :left :right {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	621 greateq <- true
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	622 while: { greateq && (not: (left empty?)) && (not: (right empty?)) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	623 if: (left value) < (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	624 greateq <- false
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	625 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	626 if: (left value) > (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	627 left <- []
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	628 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	629 left <- left tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	630 right <- right tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	631 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	632 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	633 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	634 greateq
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	635 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	636
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	637 _assignments <- dict linear
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	638 curuses <- _maxUses
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	639 while: { curuses > 0 && (_assignments length) < (_regMap length) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	640 foreach: _regMap :reg usage {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	641 if: (usage useCount) = curuses {
348 a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	642 liveArgs <- liveFrom: _argMap (usage firstUsage) to: (usage lastUsage)
193 4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	643 foreach: liveArgs :_ arg {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	644 regSrc allocArg: (arg num)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	645 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	646
348 a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	647 liveRegs <- liveFrom: _regMap (usage firstUsage) to: (usage lastUsage)
193 4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	648 print: (string: reg) . " \| Live: " . (liveRegs join: ", ") . ", Live Args: " . (liveArgs join: ", ") . "\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	649 foreach: liveRegs :_ reg {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	650 if: (_assignments contains?: reg) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	651 regSrc allocSpecific: (_assignments get: reg)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	652 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	653 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	654 _assignments set: reg (regSrc alloc: (usage maxSize))
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	655
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	656 regSrc returnAll
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	657 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	658 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	659 curuses <- curuses - 1
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	660 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	661 print: "\n\nAssignments:\n\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	662 foreach: _assignments :reg assign {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	663 print: (string: reg) . " = " . assign . "\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module Mike Pavone <pavone@retrodev.com> parents: 189 diff changeset	664 }
194 30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	665
200 49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	666 withassign <- #[]
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	667 foreach: instarr :idx inst {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	668 withassign append: (inst assignRegs: _assignments at: [idx] withSource: regSrc andUsage: regUsage)
194 30bed95cbb18 Apply register assignments in il module Mike Pavone <pavone@retrodev.com> parents: 193 diff changeset	669 }
195 7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	670 psave <- regSrc needSaveProlog
7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	671 if: (psave length) > 0 {
7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	672 withassign <- #[save: psave withassign]
7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	673 }
7856f0916549 Add save il instruction to save callee saved registers in function prolog Mike Pavone <pavone@retrodev.com> parents: 194 diff changeset	674 withassign
189 a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	675 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator Mike Pavone <pavone@retrodev.com> parents: 185 diff changeset	676
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	677 //used to convert IL to a format suitable for a 2-operand architecture
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	678 //should be run after register allocation (I think....)
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	679 to2Op <- :instarr {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	680 instarr fold: #[] with: :newarr inst {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	681 if: (inst numops) = 3 {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	682 if: (inst inb) = (inst out) {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	683 newarr append: (op2: (inst opcode) in: (inst ina) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	684 } else: {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	685 if: (inst commutative?) && (inst ina) = (inst out) {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	686 newarr append: (op2: (inst opcode) in: (inst inb) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	687 } else: {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	688 newarr append: (mov: (inst inb) (inst out) (inst size))
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	689 newarr append: (op2: (inst opcode) in: (inst ina) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	690 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	691 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	692 } else: {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	693 if: (inst numops) = 2 && (inst opcode) != _mov {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	694 if: (inst in) != (inst out) {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	695 newarr append: (mov: (inst in) (inst out) (inst size))
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	696 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	697 newarr append: (op1: (inst opcode) val: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	698 } else: {
200 49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	699 if: (inst opcode) = _skipif \|\| (inst opcode) = _save {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	700 newarr append: (inst to2OpInst)
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	701 } else: {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	702 newarr append: inst
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions. Mike Pavone <pavone@retrodev.com> parents: 195 diff changeset	703 }
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	704 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	705 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	706 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	707 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	708
203 56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	709 toBackend <- :program :backend {
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	710 prepped <- program map: :fun {
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	711 backend adjustIL: fun
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	712 }
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	713 labels <- prepped map: :_ {
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	714 backend label
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	715 }
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	716 outprog <- #[]
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	717 foreach: prepped :name instarr {
350 a3b06d53bcb9 Make il and x86 modules cope with dict hash instead of dict linear for the program definition Michael Pavone <pavone@retrodev.com> parents: 348 diff changeset	718 outprog append: (labels get: name else: { false })
203 56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	719 foreach: instarr :_ inst {
348 a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	720 print: "Translating: " . inst . "\n"
203 56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	721 backend convertIL: inst to: outprog withLabels: labels
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	722 }
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	723 }
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	724 outprog
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	725 }
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	726
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	727 main <- {
203 56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	728 prog <- dict linear
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	729
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	730 fib <- #[
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	731 sub: 2 (arg: 0) (reg: 0) q
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	732 skipIf: ge #[
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	733 return: 1 q
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	734 ]
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	735 call: "fib" withArgs: #[reg: 0]
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	736 mov: retr (reg: 1) q
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	737 add: 1 (reg: 0) (reg: 2) q
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	738 call: "fib" withArgs: #[reg: 2]
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	739 add: retr (reg: 1) (reg: 3) q
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	740 return: (reg: 3) q
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	741 ]
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	742 print: "Original:\n\n"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	743 foreach: fib :idx inst {
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	744 print: (string: inst) . "\n"
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	745 }
203 56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	746 prog set: "fib" fib
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	747
348 a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	748 mprog <- toBackend: prog x86
a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	749 foreach: mprog :_ inst {
a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	750 print: (string: inst) . "\n"
a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	751 }
203 56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	752 ba <- bytearray executableFromBytes: mprog
348 a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	753 res <- if: (ba length) = 0 {
a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	754 print: "Failed to translate code\n"
a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	755 -1
a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	756 } else: {
a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	757 ba runWithArg: 30u64
a840e9a068a2 Get sample builtin to il module working again Michael Pavone <pavone@retrodev.com> parents: 315 diff changeset	758 }
203 56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	759 print: (string: res) . "\n"
56b2100d9fff Add code for converting IL into x86 machine code Mike Pavone <pavone@retrodev.com> parents: 200 diff changeset	760 0
185 181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	761 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	762 }
181d8754a2ae Initial work on IL module Mike Pavone <pavone@retrodev.com> parents: diff changeset	763 }

Mercurial > repos > tabletprog

annotate modules/il.tp @ 353:95bc24c729e6