annotate modules/il.tp @ 350:a3b06d53bcb9

Make il and x86 modules cope with dict hash instead of dict linear for the program definition
author Michael Pavone <pavone@retrodev.com>
date Fri, 10 Apr 2015 01:19:46 -0700
parents a840e9a068a2
children f74ce841fd1e
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1 {
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2 //commutative ops
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3 _add <- 0
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4 _and <- 1
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5 _or <- 2
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6 _xor <- 3
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7 _muls <- 4
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8 _mulu <- 5
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9 //non-commutative ops
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10 _divs <- 6
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11 _divu <- 7
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12 _sub <- 8
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13 _cmp <- 9
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14 _not <- 10
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15 _sl <- 11
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16 _asr <- 12
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17 _lsr <- 13
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18 _rol <- 14
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19 _ror <- 15
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20 _mov <- 16
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21 _call <- 17
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22 _ret <- 18
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23 _skipif <- 19
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24 _skipifelse <- 20
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25 _save <- 21
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26 _bool <- 22
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27
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28 _names <- #[
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29 "add"
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30 "and"
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31 "or"
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32 "xor"
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33 "muls"
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34 "mulu"
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35 "divs"
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36 "divu"
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37 "sub"
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38 "cmp"
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39 "not"
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40 "sl"
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41 "asr"
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42 "lsr"
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43 "rol"
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44 "ror"
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45 "mov"
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46 "call"
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47 "ret"
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48 "skipIf"
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49 "skipIf:else"
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50 "save"
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51 "bool"
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52 ]
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53
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54 op3:a:b:out:size <- :_opcode :_ina :_inb :_out :_size {
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55 #{
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56 opcode <- { _opcode }
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57 ina <- { _ina }
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58 inb <- { _inb }
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59 commutative? <- { _opcode < _divs }
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60 out <- { _out }
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61 size <- { _size }
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62 numops <- { 3 }
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63 name <- { _names get: _opcode }
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64 string <- { name . " " . (string: _ina) . " " . (string: _inb) . " " . (string: _out) . " " . (string: _size) }
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65 recordUsage:at <- :tracker :address {
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66 if: (not: (_ina isInteger?)) {
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67 _ina recordUsage: tracker at: 0 | address withSize: _size
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68 }
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69 _inb recordUsage: tracker at: 0 | address withSize: _size
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70 _out recordUsage: tracker at: 1 | address withSize: _size
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71 }
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72 assignRegs:at:withSource:andUsage <- :assignments :at :regSrc :usage {
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73 newa <- if: (not: (_ina isInteger?)) {
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74 _ina assign: assignments withSource: regSrc
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75 } else: { _ina }
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76 newb <- _inb assign: assignments withSource: regSrc
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77 newout <- _out assign: assignments withSource: regSrc
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78 op3: _opcode a: newa b: newb out: newout size: _size
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79 }
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80 }
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81 }
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82 op2:in:out:size <- :_opcode :_in :_out :_size {
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83 #{
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84 opcode <- { _opcode }
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85 in <- { _in }
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86 out <- { _out }
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87 size <- { _size }
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88 numops <- { 2 }
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89 name <- { _names get: _opcode }
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90 string <- { name . " " . (string: _in) . " " . (string: _out) . " " . (string: _size) }
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91 recordUsage:at <- :tracker :address {
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92 if: (not: (_in isInteger?)) {
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93 _in recordUsage: tracker at: 0 | address withSize: _size
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94 }
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95 _out recordUsage: tracker at: 1 | address withSize: _size
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96 }
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97 assignRegs:at:withSource:andUsage <- :assignments :at :regSrc :usage {
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98 newin <- if: (not: (_in isInteger?)) {
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99 _in assign: assignments withSource: regSrc
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100 } else: { _in }
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101 newout <- _out assign: assignments withSource: regSrc
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102 op2: _opcode in: newin out: newout size: _size
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103 }
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104 }
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105 }
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106 op1:arg:size <- :_opcode :_arg :_size {
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107 #{
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108 opcode <- { _opcode }
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109 arg <- { _arg }
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110 size <- { _size }
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111 numops <- { 1 }
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112 name <- { _names get: _opcode }
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113 string <- { name . " " . (string: _arg) . " " . (string: _size) }
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114 recordUsage:at <- :tracker :address {
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115 if: (not: (_arg isInteger?)) {
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116 _arg recordUsage: tracker at: address withSize: _size
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117 }
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118 }
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119 assignRegs:at:withSource:andUsage <- :assignments :at :regSrc :usage {
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120 newarg <- if: (not: (_arg isInteger?)) {
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121 _arg assign: assignments withSource: regSrc
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122 } else: { _arg }
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123 op1: _opcode arg: newarg size: _size
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124 }
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125 }
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126 }
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127
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128 _sizenames <- #["b" "w" "l" "q"]
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129 _size <- :_bytes {
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130 #{
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131 bytes <- { _bytes }
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132 string <- {
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133 idx <- if: _bytes = 8 { 3 } else: { _bytes / 2}
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134 _sizenames get: idx
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135 }
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136 = <- :other {
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137 _bytes = (other bytes)
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138 }
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139 <= <- :other {
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140 _bytes <= (other bytes)
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141 }
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142 >= <- :other {
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143 _bytes >= (other bytes)
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144 }
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145 > <- :other {
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146 _bytes > (other bytes)
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147 }
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148 < <- :other {
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149 _bytes < (other bytes)
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150 }
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151 }
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152 }
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153 byte <- _size: 1
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154 word <- _size: 2
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155 long <- _size: 4
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156 quad <- _size: 8
185
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157
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158 _retr <- #{
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159 isInteger? <- { false }
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160 register? <- { true }
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161 argument? <- { false }
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162 return? <- { true }
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163 string <- { "retr" }
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164 = <- :other {
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165 (not: (other isInteger?)) && (other register?) && (other return?)
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166 }
189
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167 != <- :other {
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168 not: self = other
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169 }
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170 recordUsage:at:withSize <- :tracker :address :size {
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171 //TODO: Figure out what tracking is necessary here
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172 }
194
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173 assign:withSource <- :assignments :regSrc {
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174 regSrc allocRet
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175 }
185
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176 }
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177
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178 _condnames <- #[
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179 "eq"
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180 "neq"
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181 "ge"
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182 "le"
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183 "gr"
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184 "ls"
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185 "uge"
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186 "ule"
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187 "ugr"
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188 "uls"
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189 ]
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190 condition <- :num {
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191 #{
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192 cc <- { num }
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193 string <- { _condnames get: num }
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194 = <- :other { num = (other cc) }
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195 }
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196 }
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197 _eq <- condition: 0
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198 _neq <- condition: 1
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199 _ge <- condition: 2
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200 _le <- condition: 3
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201 _gr <- condition: 4
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202 _ls <- condition: 5
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203 _uge <- condition: 6
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204 _ule <- condition: 7
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205 _ugr <- condition: 8
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206 _uls <- condition: 9
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207
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208 #{
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209 b <- { byte }
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210 w <- { word }
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211 l <- { long }
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212 q <- { quad }
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213
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214 eq <- { _eq }
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215 neq <- { _neq }
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216
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217 //signed conditions
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218 ge <- { _ge }
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219 le <- { _le }
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220 gr <- { _gr }
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221 ls <- { _ls }
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222
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223 //unsigned conditions
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224 uge <- { _uge }
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225 ule <- { _ule }
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226 ugr <- { _ugr }
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227 uls <- { _uls }
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228
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229
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230 reg <- :num {
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231 #{
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232 isInteger? <- { false }
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233 register? <- { true }
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234 argument? <- { false }
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235 return? <- { false }
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236 regnum <- { num }
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237 string <- { "r" . (string: num) }
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238 = <- :other {
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239 (not: (other isInteger?)) && (other register?) && (not: (other argument?)) && (not: (other return?)) && num = (other regnum)
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240 }
189
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241 != <- :other {
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242 not: self = other
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243 }
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244 recordUsage:at:withSize <- :tracker :address :size {
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245 tracker reg: self usedAt: address withSize: size
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246 }
194
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247 assign:withSource <- :assignments :regSrc {
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248 assignments get: self
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249 }
185
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250 }
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251 }
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252 arg <- :num {
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253 #{
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254 isInteger? <- { false }
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255 register? <- { true }
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256 argument? <- { true }
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257 return? <- { false }
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258 argnum <- { num }
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259 string <- { "a" . (string: num) }
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260 = <- :other {
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261 (not: (other isInteger?)) && (other register?) && (other argument?) && num = (other regnum)
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262 }
189
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263 != <- :other {
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264 not: self = other
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265 }
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266 recordUsage:at:withSize <- :tracker :address :size {
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267 tracker arg: self usedAt: address withSize: size
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268 }
194
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269 assign:withSource <- :assignments :regSrc {
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270 regSrc allocArg: num
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271 }
185
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272 }
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273 }
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274 retr <- { _retr }
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275
189
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276 base:offset <- :_base :_offset {
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277 #{
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278 base <- { _base }
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279 offset <- { _offset }
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280 string <- {
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281 start <- if: _offset = 0 { "" } else: { (string: _offset) }
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282 start . "[" . (string: _base) . "]"
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283 }
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284 recordUsage:at:withSize <- :tracker :address :size {
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285 _base recordUsage: tracker at: address withSize: size
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286 }
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287 }
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288 }
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289
185
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290 add <- :ina inb out size {
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291 op3: _add a: ina b: inb out: out size: size
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292 }
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293
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294 sub <- :ina inb out size {
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295 op3: _sub a: ina b: inb out: out size: size
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296 }
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297
315
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298 cmp <- :ina inb size {
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299 op2: _cmp a: ina out: inb size: size
185
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300 }
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301
315
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302 band <- :ina inb out size {
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303 op3: _and a: ina b: inb out: out size: size
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304 }
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305
315
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306 bor <- :ina inb out size {
185
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307 op3: _or a: ina b: inb out: out size: size
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308 }
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309
315
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310 bxor <- :ina inb out size {
185
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311 op3: _xor a: ina b: inb out: out size: size
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312 }
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313
315
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314 muls <- :ina inb out size {
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315 op3: _muls a: ina b: inb out: out size: size
310
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316 }
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317
315
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318 mulu <- :ina inb out size {
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319 op3: _mulu a: ina b: inb out: out size: size
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320 }
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321
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322 divs <- :ina inb out size {
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323 op3: _divs a: ina b: inb out: out size: size
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324 }
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325
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326 divu <- :ina inb out size {
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327 op3: _divu a: ina b: inb out: out size: size
310
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328 }
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329
185
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330 bnot <- :in out size {
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331 op2: _not in: in out: out size: size
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332 }
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333
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334 sl <- :shift in out size {
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335 op3: _sl a: shift b: in out: out size: size
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336 }
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337
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338 asr <- :shift in out size {
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339 op3: _asr a: shift b: in out: out size: size
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340 }
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341
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342 lsr <- :shift in out size {
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343 op3: _lsr a: shift b: in out: out size: size
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344 }
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345
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346 rol <- :rot in out size {
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347 op3: _rol a: rot b: in out: out size: size
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348 }
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349
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350 ror <- :rot in out size {
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351 op3: _ror a: rot b: in out: out size: size
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352 }
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353
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354 mov <- :in out size {
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355 op2: _mov in: in out: out size: size
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356 }
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357
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358 call:withArgs <- :_target :_args {
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359 #{
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360 opcode <- { _call }
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361 target <- { _target }
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362 args <- { _args }
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363 numops <- { 0 }
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364 name <- { _names get: _call }
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365 string <- {
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366 argstr <- _args map: :el {
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367 string: el
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368 }
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369 name . " " . (string: _target) . " " . (argstr join: " ")
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370 }
189
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371 recordUsage:at <- :tracker :address {
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372 if: (not: (_target isString?)) {
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373 //TODO: use size l for 32-bit targets or an abstract pointer size
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374 _target recordUsage: tracker at: address withSize: q
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375 }
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376 foreach: _args :_ arg {
348
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377 if: (not: (arg isInteger?)) {
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378 //TODO: have some mechanism for properly expressing sizes of arguments
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379 arg recordUsage: tracker at: address withSize: q
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380 }
189
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381 }
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382 }
200
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383 assignRegs:at:withSource:andUsage <- :assignments :address :regSrc :usage {
194
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384 newtarget <- if: (_target isString?) { _target } else: {
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385 _target assign: assignments withSource: regSrc
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386 }
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387 newargs <- _args map: :arg {
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388 if: (arg isInteger?) { arg } else: {
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389 arg assign: assignments withSource: regSrc
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390 }
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391 }
200
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392 newcall <- call: newtarget withArgs: newargs
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393 regSrc returnAll
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394 raddress <- address reverse
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395 foreach: (usage liveArgsAt: raddress) :_ arg {
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396 regSrc allocArg: (arg num)
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397 }
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398 foreach: (usage liveRegsAt: raddress) :_ reg {
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399 regSrc allocSpecific: (assignments get: reg)
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400 }
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401 tosave <- regSrc needSaveForCall
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402 if: (tosave length) > 0 {
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403 save: tosave #[newcall]
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404 } else: {
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diff changeset
405 newcall
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406 }
194
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407 }
185
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408 }
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409 }
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410
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411 return <- :val size {
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412 op1: _ret arg: val size: size
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413 }
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414 skipIf <- :_cond _toskip {
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415 #{
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416 opcode <- { _skipif }
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417 toskip <- { _toskip }
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418 cond <- { _cond }
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419 numops <- { 0 }
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420 name <- { _names get: _skipif }
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421 string <- {
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422 block <- (_toskip map: :el { string: el }) join: "\n\t"
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diff changeset
423 if: (_toskip length) > 0 {
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424 block <- "\n\t" . block . "\n"
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425 }
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426 name . " " . (string: _cond) . " {" . block . "}"
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diff changeset
427 }
189
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diff changeset
428 recordUsage:at <- :tracker :address {
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diff changeset
429 foreach: _toskip :idx inst {
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diff changeset
430 inst recordUsage: tracker at: idx | address
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diff changeset
431 }
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432 }
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
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433 assignRegs:at:withSource:andUsage <- :assignments :address :regSrc :usage {
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diff changeset
434 newskip <- #[]
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diff changeset
435 foreach: _toskip :idx inst {
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diff changeset
436 newskip append: (inst assignRegs: assignments at: idx | address withSource: regSrc andUsage: usage)
194
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diff changeset
437 }
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diff changeset
438 skipIf: _cond newskip
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439 }
200
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diff changeset
440 to2OpInst <- {
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diff changeset
441 skipIf: _cond (to2Op: _toskip)
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diff changeset
442 }
185
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443 }
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diff changeset
444 }
315
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diff changeset
445 skipIf:else <- :_cond _toskip :_else {
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diff changeset
446 #{
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diff changeset
447 opcode <- { _skipif }
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diff changeset
448 toskip <- { _toskip }
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diff changeset
449 else <- { _else }
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450 cond <- { _cond }
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diff changeset
451 numops <- { 0 }
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diff changeset
452 name <- { _names get: _skipifelse }
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diff changeset
453 string <- {
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diff changeset
454 block <- (_toskip map: :el { string: el }) join: "\n\t"
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diff changeset
455 if: (_toskip length) > 0 {
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diff changeset
456 block <- "\n\t" . block . "\n"
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diff changeset
457 }
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diff changeset
458 elseblock <- (_else map: :el { string: el }) join: "\n\t"
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diff changeset
459 if: (_else length) > 0 {
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diff changeset
460 elseblock <- "\n\t" . elseblock . "\n"
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diff changeset
461 }
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diff changeset
462 name . " " . (string: _cond) . " {" . block . "} {" . elseblock . "}"
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parents: 310
diff changeset
463 }
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diff changeset
464 recordUsage:at <- :tracker :address {
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diff changeset
465 foreach: _toskip :idx inst {
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diff changeset
466 inst recordUsage: tracker at: idx | address
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diff changeset
467 }
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diff changeset
468 foreach: _else :idx inst {
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diff changeset
469 inst recordUsage: tracker at: idx | address
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diff changeset
470 }
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diff changeset
471 }
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diff changeset
472 assignRegs:at:withSource:andUsage <- :assignments :address :regSrc :usage {
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diff changeset
473 newskip <- #[]
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diff changeset
474 foreach: _toskip :idx inst {
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diff changeset
475 newskip append: (inst assignRegs: assignments at: idx | address withSource: regSrc andUsage: usage)
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diff changeset
476 }
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diff changeset
477 newelse <- #[]
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diff changeset
478 foreach: _else :idx inst {
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diff changeset
479 newelse append: (inst assignRegs: assignments at: idx | address withSource: regSrc andUsage: usage)
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diff changeset
480 }
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diff changeset
481 skipIf: _cond newskip else: newelse
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482 }
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diff changeset
483 to2OpInst <- {
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diff changeset
484 skipIf: _cond (to2Op: _toskip) (to2Op: _else)
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diff changeset
485 }
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diff changeset
486 }
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487 }
203
56b2100d9fff Add code for converting IL into x86 machine code
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488 save <- :regs :_scope{
195
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489 #{
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diff changeset
490 opcode <- { _save }
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diff changeset
491 numops <- { 0 }
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diff changeset
492 name <- { _names get: _save }
203
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diff changeset
493 tosave <- { regs }
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diff changeset
494 scope <- { _scope }
195
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diff changeset
495 string <- {
203
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diff changeset
496 block <- _scope join: "\n\t"
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diff changeset
497 if: (_scope length) > 0 {
195
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diff changeset
498 block <- "\n\t" . block . "\n"
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diff changeset
499 }
7856f0916549 Add save il instruction to save callee saved registers in function prolog
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diff changeset
500 name . " " . (regs join: " ") . " {" . block . "}"
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diff changeset
501 }
200
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diff changeset
502 to2OpInst <- {
203
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diff changeset
503 save: regs (to2Op: _scope)
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
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diff changeset
504 }
195
7856f0916549 Add save il instruction to save callee saved registers in function prolog
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diff changeset
505 }
7856f0916549 Add save il instruction to save callee saved registers in function prolog
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diff changeset
506 }
185
181d8754a2ae Initial work on IL module
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diff changeset
507
310
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diff changeset
508 //produces a non-zero value or zero based on condition code flags
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diff changeset
509 bool <- :_cond _out {
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510 #{
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diff changeset
511 opcode <- { _bool }
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diff changeset
512 cond <- { _cond }
315
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diff changeset
513 out <- { _out }
310
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diff changeset
514 name <- { _names get: _save }
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diff changeset
515 numops <- { 0 }
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diff changeset
516
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diff changeset
517 }
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diff changeset
518 }
2308336790d4 WIP compiler module for low-level dialect
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diff changeset
519
348
a840e9a068a2 Get sample builtin to il module working again
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diff changeset
520 allocRegs:withSource <- :instarr :regSrc {
189
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diff changeset
521 _regMap <- dict linear
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diff changeset
522 _argMap <- dict linear
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diff changeset
523
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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diff changeset
524 _usageTracker <- :_firstUsage {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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diff changeset
525 #{
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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diff changeset
526 firstUsage <- _firstUsage
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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parents: 185
diff changeset
527 lastUsage <- _firstUsage
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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diff changeset
528 useCount <- 0
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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diff changeset
529 maxSize <- byte
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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diff changeset
530 usedAt:withSize <- :address :size {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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parents: 185
diff changeset
531 useCount <- useCount + 1
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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diff changeset
532 lastUsage <- address
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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parents: 185
diff changeset
533 if: size > maxSize {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
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diff changeset
534 maxSize <- size
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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diff changeset
535 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
536 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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diff changeset
537 string <- {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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parents: 185
diff changeset
538 "Uses: " . useCount . ", FirstUse: " . (firstUsage join: ":") . ", Last Use: " . (lastUsage join: ":") . ", Max Size: " . maxSize
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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diff changeset
539 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
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diff changeset
540 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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diff changeset
541 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
542
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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diff changeset
543 _maxUses <- 0
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
544 liveFrom:to <- :regs :from :to {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
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parents: 195
diff changeset
545 live <- #[]
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
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parents: 195
diff changeset
546 foreach: regs :reg usage {
348
a840e9a068a2 Get sample builtin to il module working again
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diff changeset
547 if: (addrGreatEq: (usage lastUsage) from) && (addrLessEq: (usage firstUsage) to) {
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
548 live append: reg
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
549 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
550 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
551 live
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
552 }
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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parents: 185
diff changeset
553 regUsage <- #{
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parents: 185
diff changeset
554 reg:usedAt:withSize <- :reg :address :size {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
555 raddress <- address reverse
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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parents: 185
diff changeset
556 usage <- _regMap get: reg elseSet: {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 189
diff changeset
557 _usageTracker: raddress
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
558 }
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
559 usage usedAt: raddress withSize: size
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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parents: 185
diff changeset
560 if: (usage useCount) > _maxUses {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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parents: 185
diff changeset
561 _maxUses <- usage useCount
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
562 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
563 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
564 arg:usedAt:withSize <- :arg :address :size {
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
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parents: 189
diff changeset
565 raddress <- address reverse
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
566 usage <- _argMap get: arg elseSet: {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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parents: 185
diff changeset
567 _usageTracker: [0 0]
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
568 }
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
569 usage usedAt: raddress withSize: size
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
570 }
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
571
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
572 liveRegsAt <- :address {
348
a840e9a068a2 Get sample builtin to il module working again
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parents: 315
diff changeset
573 liveFrom: _regMap address to: address
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
574 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
575 liveArgsAt <- :address {
348
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
576 liveFrom: _argMap address to: address
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
577 }
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
578
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
579 print <- {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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parents: 185
diff changeset
580 foreach: _regMap :reg usage {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
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parents: 185
diff changeset
581 print: (string: reg) . " | " . (string: usage) . "\n"
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
582 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
583 foreach: _argMap :arg usage {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
584 print: (string: arg) . " | " . (string: usage) . "\n"
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
585 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
586 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
587 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
588 foreach: instarr :idx inst {
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
589 inst recordUsage: regUsage at: [idx]
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
590 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
591 print: regUsage
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
592
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
593 addrLessEq <- :left :right {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
594 lesseq <- true
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
595 while: { lesseq && (not: (left empty?)) && (not: (right empty?)) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
596 if: (left value) > (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
597 lesseq <- false
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
598 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
599 if: (left value) < (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
600 left <- []
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
601 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
602 left <- left tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
603 right <- right tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
604 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
605 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
606 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
607 lesseq
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
608 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
609
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
610 addrGreatEq <- :left :right {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
611 greateq <- true
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
612 while: { greateq && (not: (left empty?)) && (not: (right empty?)) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
613 if: (left value) < (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
614 greateq <- false
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
615 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
616 if: (left value) > (right value) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
617 left <- []
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
618 } else: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
619 left <- left tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
620 right <- right tail
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
621 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
622 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
623 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
624 greateq
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
625 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
626
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
627 _assignments <- dict linear
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
628 curuses <- _maxUses
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
629 while: { curuses > 0 && (_assignments length) < (_regMap length) } do: {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
630 foreach: _regMap :reg usage {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
631 if: (usage useCount) = curuses {
348
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
632 liveArgs <- liveFrom: _argMap (usage firstUsage) to: (usage lastUsage)
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
633 foreach: liveArgs :_ arg {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
634 regSrc allocArg: (arg num)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
635 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
636
348
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
637 liveRegs <- liveFrom: _regMap (usage firstUsage) to: (usage lastUsage)
193
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
638 print: (string: reg) . " | Live: " . (liveRegs join: ", ") . ", Live Args: " . (liveArgs join: ", ") . "\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
639 foreach: liveRegs :_ reg {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
640 if: (_assignments contains?: reg) {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
641 regSrc allocSpecific: (_assignments get: reg)
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
642 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
643 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
644 _assignments set: reg (regSrc alloc: (usage maxSize))
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
645
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
646 regSrc returnAll
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
647 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
648 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
649 curuses <- curuses - 1
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
650 }
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
651 print: "\n\nAssignments:\n\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
652 foreach: _assignments :reg assign {
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
653 print: (string: reg) . " = " . assign . "\n"
4293c725394c Mostly complete register allocation in il module with a register source in the x86 module
Mike Pavone <pavone@retrodev.com>
parents: 189
diff changeset
654 }
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
655
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
656 withassign <- #[]
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
657 foreach: instarr :idx inst {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
658 withassign append: (inst assignRegs: _assignments at: [idx] withSource: regSrc andUsage: regUsage)
194
30bed95cbb18 Apply register assignments in il module
Mike Pavone <pavone@retrodev.com>
parents: 193
diff changeset
659 }
195
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
660 psave <- regSrc needSaveProlog
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
661 if: (psave length) > 0 {
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
662 withassign <- #[save: psave withassign]
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
663 }
7856f0916549 Add save il instruction to save callee saved registers in function prolog
Mike Pavone <pavone@retrodev.com>
parents: 194
diff changeset
664 withassign
189
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
665 }
a45e535f7742 Determine live ranges for logical registers as part of initial work on register allocator
Mike Pavone <pavone@retrodev.com>
parents: 185
diff changeset
666
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
667 //used to convert IL to a format suitable for a 2-operand architecture
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
668 //should be run after register allocation (I think....)
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
669 to2Op <- :instarr {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
670 instarr fold: #[] with: :newarr inst {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
671 if: (inst numops) = 3 {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
672 if: (inst inb) = (inst out) {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
673 newarr append: (op2: (inst opcode) in: (inst ina) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
674 } else: {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
675 if: (inst commutative?) && (inst ina) = (inst out) {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
676 newarr append: (op2: (inst opcode) in: (inst inb) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
677 } else: {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
678 newarr append: (mov: (inst inb) (inst out) (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
679 newarr append: (op2: (inst opcode) in: (inst ina) out: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
680 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
681 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
682 } else: {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
683 if: (inst numops) = 2 && (inst opcode) != _mov {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
684 if: (inst in) != (inst out) {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
685 newarr append: (mov: (inst in) (inst out) (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
686 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
687 newarr append: (op1: (inst opcode) val: (inst out) size: (inst size))
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
688 } else: {
200
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
689 if: (inst opcode) = _skipif || (inst opcode) = _save {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
690 newarr append: (inst to2OpInst)
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
691 } else: {
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
692 newarr append: inst
49bca6487178 Add a save instruction around calls if there are caller-saved registers live at call-time. Fix to2Op for skipIf and save instructions.
Mike Pavone <pavone@retrodev.com>
parents: 195
diff changeset
693 }
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
694 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
695 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
696 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
697 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
698
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
699 toBackend <- :program :backend {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
700 prepped <- program map: :fun {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
701 backend adjustIL: fun
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
702 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
703 labels <- prepped map: :_ {
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
704 backend label
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
705 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
706 outprog <- #[]
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
707 foreach: prepped :name instarr {
350
a3b06d53bcb9 Make il and x86 modules cope with dict hash instead of dict linear for the program definition
Michael Pavone <pavone@retrodev.com>
parents: 348
diff changeset
708 outprog append: (labels get: name else: { false })
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
709 foreach: instarr :_ inst {
348
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
710 print: "Translating: " . inst . "\n"
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
711 backend convertIL: inst to: outprog withLabels: labels
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
712 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
713 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
714 outprog
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
715 }
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
716
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
717 main <- {
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
718 prog <- dict linear
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
719
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
720 fib <- #[
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
721 sub: 2 (arg: 0) (reg: 0) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
722 skipIf: ge #[
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
723 return: 1 q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
724 ]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
725 call: "fib" withArgs: #[reg: 0]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
726 mov: retr (reg: 1) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
727 add: 1 (reg: 0) (reg: 2) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
728 call: "fib" withArgs: #[reg: 2]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
729 add: retr (reg: 1) (reg: 3) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
730 return: (reg: 3) q
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
731 ]
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
732 print: "Original:\n\n"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
733 foreach: fib :idx inst {
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
734 print: (string: inst) . "\n"
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
735 }
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
736 prog set: "fib" fib
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
737
348
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
738 mprog <- toBackend: prog x86
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
739 foreach: mprog :_ inst {
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
740 print: (string: inst) . "\n"
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
741 }
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
742 ba <- bytearray executableFromBytes: mprog
348
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
743 res <- if: (ba length) = 0 {
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
744 print: "Failed to translate code\n"
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
745 -1
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
746 } else: {
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
747 ba runWithArg: 30u64
a840e9a068a2 Get sample builtin to il module working again
Michael Pavone <pavone@retrodev.com>
parents: 315
diff changeset
748 }
203
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
749 print: (string: res) . "\n"
56b2100d9fff Add code for converting IL into x86 machine code
Mike Pavone <pavone@retrodev.com>
parents: 200
diff changeset
750 0
185
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
751 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
752 }
181d8754a2ae Initial work on IL module
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
753 }