Mercurial > repos > blastem
annotate 68kinst.c @ 1925:039553703c20
Don't apply address and cd register changes to the 'live' registers until pending flag is cleared, but do preserve the upper address bits in the latch. Fixes regression in Overdrive 2 while preserving fix to Mona in 344 bytes
author | Michael Pavone <pavone@retrodev.com> |
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date | Mon, 13 Apr 2020 20:43:25 -0700 |
parents | dc1eab3ec092 |
children | 8554751f17b5 |
rev | line source |
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1 /* |
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2 Copyright 2013 Michael Pavone |
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3 This file is part of BlastEm. |
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text. |
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5 */ |
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6 #include "68kinst.h" |
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7 #include <string.h> |
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8 #include <stdio.h> |
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9 |
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10 uint32_t sign_extend16(uint32_t val) |
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11 { |
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12 return (val & 0x8000) ? val | 0xFFFF0000 : val; |
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13 } |
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14 |
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15 uint32_t sign_extend8(uint32_t val) |
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16 { |
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17 return (val & 0x80) ? val | 0xFFFFFF00 : val; |
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18 } |
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19 |
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20 uint16_t *m68k_decode_op_ex(uint16_t *cur, uint8_t mode, uint8_t reg, uint8_t size, m68k_op_info *dst) |
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21 { |
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22 uint16_t ext, tmp; |
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23 dst->addr_mode = mode; |
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24 switch(mode) |
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25 { |
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26 case MODE_REG: |
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27 case MODE_AREG: |
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28 case MODE_AREG_INDIRECT: |
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29 case MODE_AREG_POSTINC: |
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30 case MODE_AREG_PREDEC: |
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31 dst->params.regs.pri = reg; |
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32 break; |
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33 case MODE_AREG_DISPLACE: |
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34 ext = *(++cur); |
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35 dst->params.regs.pri = reg; |
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36 dst->params.regs.displacement = sign_extend16(ext); |
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37 break; |
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38 case MODE_AREG_INDEX_MEM: |
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39 dst->params.regs.pri = reg; |
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40 ext = *(++cur); |
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41 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit |
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42 #ifdef M68020 |
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43 dst->params.regs.scale = ext >> 9 & 3; |
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44 if (ext & 0x100) |
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45 { |
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46 dst->params.regs.disp_sizes = ext >> 4 & 3; |
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47 switch (dst->params.regs.disp_sizes) |
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48 { |
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49 case 0: |
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50 //reserved |
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51 return NULL; |
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52 case 1: |
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53 dst->params.regs.displacement = 0; |
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54 break; |
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55 case 2: |
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56 dst->params.regs.displacement = sign_extend16(*(cur++)); |
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57 break; |
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58 case 3: |
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59 tmp = *(cur++); |
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60 dst->params.regs.displacement = tmp << 16 | *(cur++); |
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61 break; |
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62 } |
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63 if (ext & 0x3) |
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64 { |
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65 //memory indirect |
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66 switch (ext & 0xC4) |
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67 { |
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68 case 0x00: |
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69 dst->addr_mode = MODE_AREG_PREINDEX; |
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70 break; |
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71 case 0x04: |
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72 dst->addr_mode = MODE_AREG_POSTINDEX; |
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73 break; |
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74 case 0x40: |
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75 dst->addr_mode = MODE_AREG_MEM_INDIRECT; |
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76 break; |
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77 case 0x80: |
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78 dst->addr_mode = MODE_PREINDEX; |
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79 break; |
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80 case 0x84: |
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81 dst->addr_mode = MODE_POSTINDEX; |
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82 break; |
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83 case 0xC0: |
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84 dst->addr_mode = MODE_MEM_INDIRECT; |
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85 break; |
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86 } |
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87 dst->params.regs.disp_sizes |= ext << 4 & 0x30; |
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88 switch (ext & 0x3) |
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89 { |
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90 case 0: |
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91 //reserved |
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92 return NULL; |
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93 case 1: |
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94 dst->params.regs.outer_disp = 0; |
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95 break; |
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96 case 2: |
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97 dst->params.regs.outer_disp = sign_extend16(*(cur++)); |
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98 break; |
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99 case 3: |
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100 tmp = *(cur++); |
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101 dst->params.regs.outer_disp = tmp << 16 | *(cur++); |
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102 break; |
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103 } |
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104 } else { |
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105 switch (ext >> 6 & 3) |
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106 { |
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107 case 0: |
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108 dst->addr_mode = MODE_AREG_INDEX_BASE_DISP; |
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109 break; |
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110 case 1: |
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111 dst->addr_mode = MODE_AREG_BASE_DISP; |
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112 break; |
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113 case 2: |
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114 dst->addr_mode = MODE_INDEX_BASE_DISP; |
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115 break; |
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116 case 3: |
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117 dst->addr_mode = MODE_BASE_DISP; |
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118 break; |
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119 } |
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120 } |
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121 } else { |
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122 #endif |
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123 dst->addr_mode = MODE_AREG_INDEX_DISP8; |
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124 dst->params.regs.displacement = sign_extend8(ext&0xFF); |
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125 #ifdef M68020 |
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126 } |
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127 #endif |
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128 break; |
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129 case MODE_PC_INDIRECT_ABS_IMMED: |
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130 switch(reg) |
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131 { |
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132 case 0: |
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133 dst->addr_mode = MODE_ABSOLUTE_SHORT; |
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134 ext = *(++cur); |
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135 dst->params.immed = sign_extend16(ext); |
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136 break; |
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137 case 1: |
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138 dst->addr_mode = MODE_ABSOLUTE; |
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139 ext = *(++cur); |
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140 dst->params.immed = ext << 16 | *(++cur); |
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141 break; |
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142 case 3: |
638
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143 ext = *(++cur); |
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144 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit |
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145 #ifdef M68020 |
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146 dst->params.regs.scale = ext >> 9 & 3; |
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147 if (ext & 0x100) |
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148 { |
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149 dst->params.regs.disp_sizes = ext >> 4 & 3; |
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150 switch (dst->params.regs.disp_sizes) |
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151 { |
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152 case 0: |
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153 //reserved |
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154 return NULL; |
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155 case 1: |
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156 dst->params.regs.displacement = 0; |
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157 break; |
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158 case 2: |
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159 dst->params.regs.displacement = sign_extend16(*(cur++)); |
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160 break; |
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161 case 3: |
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162 tmp = *(cur++); |
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163 dst->params.regs.displacement = tmp << 16 | *(cur++); |
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164 break; |
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165 } |
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166 if (ext & 0x3) |
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167 { |
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168 //memory indirect |
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169 switch (ext & 0xC4) |
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170 { |
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171 case 0x00: |
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172 dst->addr_mode = MODE_PC_PREINDEX; |
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173 break; |
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174 case 0x04: |
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175 dst->addr_mode = MODE_PC_POSTINDEX; |
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176 break; |
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177 case 0x40: |
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178 dst->addr_mode = MODE_PC_MEM_INDIRECT; |
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179 break; |
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180 case 0x80: |
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181 dst->addr_mode = MODE_ZPC_PREINDEX; |
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182 break; |
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183 case 0x84: |
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184 dst->addr_mode = MODE_ZPC_POSTINDEX; |
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185 break; |
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186 case 0xC0: |
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187 dst->addr_mode = MODE_ZPC_MEM_INDIRECT; |
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188 break; |
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189 } |
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190 dst->params.regs.disp_sizes |= ext << 4 & 0x30; |
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191 switch (ext & 0x3) |
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192 { |
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193 case 0: |
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194 //reserved |
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195 return NULL; |
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196 case 1: |
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197 dst->params.regs.outer_disp = 0; |
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198 break; |
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199 case 2: |
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200 dst->params.regs.outer_disp = sign_extend16(*(cur++)); |
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201 break; |
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202 case 3: |
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203 tmp = *(cur++); |
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204 dst->params.regs.outer_disp = tmp << 16 | *(cur++); |
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205 break; |
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206 } |
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207 } else { |
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208 switch (ext >> 6 & 3) |
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209 { |
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210 case 0: |
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211 dst->addr_mode = MODE_PC_INDEX_BASE_DISP; |
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212 break; |
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213 case 1: |
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214 dst->addr_mode = MODE_PC_BASE_DISP; |
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215 break; |
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216 case 2: |
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217 dst->addr_mode = MODE_ZPC_INDEX_BASE_DISP; |
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218 break; |
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219 case 3: |
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220 dst->addr_mode = MODE_ZPC_BASE_DISP; |
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221 break; |
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222 } |
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223 } |
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224 } else { |
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225 #endif |
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226 dst->addr_mode = MODE_PC_INDEX_DISP8; |
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227 dst->params.regs.displacement = sign_extend8(ext&0xFF); |
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228 #ifdef M68020 |
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229 } |
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230 #endif |
95
dd3c680c618c
Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
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231 break; |
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232 case 2: |
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233 dst->addr_mode = MODE_PC_DISPLACE; |
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234 ext = *(++cur); |
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235 dst->params.regs.displacement = sign_extend16(ext); |
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236 break; |
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237 case 4: |
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238 dst->addr_mode = MODE_IMMEDIATE; |
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239 ext = *(++cur); |
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240 switch (size) |
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241 { |
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242 case OPSIZE_BYTE: |
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243 dst->params.immed = ext & 0xFF; |
2
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244 break; |
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245 case OPSIZE_WORD: |
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246 dst->params.immed = ext; |
2
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247 break; |
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248 case OPSIZE_LONG: |
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249 dst->params.immed = ext << 16 | *(++cur); |
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250 break; |
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251 } |
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252 break; |
176
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253 default: |
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254 return NULL; |
2
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255 } |
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256 break; |
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257 } |
2
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258 return cur; |
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259 } |
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260 |
823
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261 uint8_t m68k_valid_immed_dst(m68k_op_info *dst) |
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262 { |
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263 if (dst->addr_mode == MODE_AREG || dst->addr_mode == MODE_IMMEDIATE) { |
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264 return 0; |
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265 } |
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266 return 1; |
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267 } |
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268 |
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269 uint8_t m68k_valid_immed_limited_dst(m68k_op_info *dst) |
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270 { |
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271 if (dst->addr_mode == MODE_AREG || dst->addr_mode > MODE_ABSOLUTE) { |
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272 return 0; |
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273 } |
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274 return 1; |
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275 } |
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276 |
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277 uint8_t m68k_valid_full_arith_dst(m68k_op_info *dst) |
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278 { |
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279 if (dst->addr_mode < MODE_AREG_INDIRECT || dst->addr_mode > MODE_ABSOLUTE) { |
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280 return 0; |
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281 } |
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282 return 1; |
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283 } |
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284 |
1458
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285 uint8_t m68k_valid_movem_dst(m68k_op_info *dst) |
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286 { |
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287 if (dst->addr_mode == MODE_REG || dst->addr_mode == MODE_AREG_POSTINC) { |
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288 return 0; |
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289 } |
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290 return m68k_valid_immed_limited_dst(dst); |
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291 } |
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292 |
2
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293 uint16_t *m68k_decode_op(uint16_t *cur, uint8_t size, m68k_op_info *dst) |
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294 { |
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295 uint8_t mode = (*cur >> 3) & 0x7; |
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296 uint8_t reg = *cur & 0x7; |
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297 return m68k_decode_op_ex(cur, mode, reg, size, dst); |
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298 } |
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299 |
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300 void m68k_decode_cond(uint16_t op, m68kinst * decoded) |
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301 { |
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302 decoded->extra.cond = (op >> 0x8) & 0xF; |
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303 } |
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|
304 |
18
3e7bfde7606e
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|
305 uint8_t m68k_reg_quick_field(uint16_t op) |
2
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|
306 { |
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|
307 return (op >> 9) & 0x7; |
0
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|
308 } |
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|
309 |
18
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310 uint16_t * m68k_decode(uint16_t * istream, m68kinst * decoded, uint32_t address) |
0
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311 { |
176
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312 uint16_t *start = istream; |
0
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313 uint8_t optype = *istream >> 12; |
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314 uint8_t size; |
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|
315 uint8_t reg; |
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316 uint8_t opmode; |
2
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|
317 uint32_t immed; |
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318 decoded->op = M68K_INVALID; |
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319 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_UNUSED; |
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320 decoded->variant = VAR_NORMAL; |
18
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|
321 decoded->address = address; |
0
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|
322 switch(optype) |
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|
323 { |
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|
324 case BIT_MOVEP_IMMED: |
163 | 325 if ((*istream & 0x138) == 0x108) { |
326 //MOVEP | |
327 decoded->op = M68K_MOVEP; | |
328 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD; | |
329 if (*istream & 0x80) { | |
330 //memory dest | |
331 decoded->src.addr_mode = MODE_REG; | |
332 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); | |
333 decoded->dst.addr_mode = MODE_AREG_DISPLACE; | |
334 decoded->dst.params.regs.pri = *istream & 0x7; | |
335 decoded->dst.params.regs.displacement = *(++istream); | |
336 } else { | |
337 //memory source | |
338 decoded->dst.addr_mode = MODE_REG; | |
339 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); | |
340 decoded->src.addr_mode = MODE_AREG_DISPLACE; | |
341 decoded->src.params.regs.pri = *istream & 0x7; | |
342 decoded->src.params.regs.displacement = *(++istream); | |
343 } | |
344 } else if (*istream & 0x100) { | |
4
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345 //BTST, BCHG, BCLR, BSET |
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346 switch ((*istream >> 6) & 0x3) |
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347 { |
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348 case 0: |
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349 decoded->op = M68K_BTST; |
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350 break; |
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351 case 1: |
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352 decoded->op = M68K_BCHG; |
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353 break; |
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354 case 2: |
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355 decoded->op = M68K_BCLR; |
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356 break; |
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357 case 3: |
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358 decoded->op = M68K_BSET; |
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359 break; |
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360 } |
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|
361 decoded->src.addr_mode = MODE_REG; |
18
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diff
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|
362 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
363 decoded->extra.size = OPSIZE_BYTE; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
364 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
365 if ( |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
366 !istream || decoded->dst.addr_mode == MODE_AREG |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
367 || (decoded->op != M68K_BTST && !m68k_valid_immed_limited_dst(&decoded->dst)) |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
368 ) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
369 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
370 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
371 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
372 if (decoded->dst.addr_mode == MODE_REG) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
373 decoded->extra.size = OPSIZE_LONG; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
374 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
375 } else if ((*istream & 0xF00) == 0x800) { |
12
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
376 //BTST, BCHG, BCLR, BSET |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
377 switch ((*istream >> 6) & 0x3) |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
378 { |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
379 case 0: |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
380 decoded->op = M68K_BTST; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
381 break; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
382 case 1: |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
383 decoded->op = M68K_BCHG; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
384 break; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
385 case 2: |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
386 decoded->op = M68K_BCLR; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
387 break; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
388 case 3: |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
389 decoded->op = M68K_BSET; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
390 break; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
391 } |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
392 opmode = (*istream >> 3) & 0x7; |
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
393 reg = *istream & 0x7; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
394 decoded->src.addr_mode = MODE_IMMEDIATE_WORD; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
395 decoded->src.params.immed = *(++istream) & 0xFF; |
12
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
396 decoded->extra.size = OPSIZE_BYTE; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
397 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
1463
63f309cfbef9
Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1462
diff
changeset
|
398 if ( |
63f309cfbef9
Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1462
diff
changeset
|
399 !istream || !m68k_valid_immed_dst(&decoded->dst) |
63f309cfbef9
Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1462
diff
changeset
|
400 || (decoded->op != M68K_BTST && !m68k_valid_immed_limited_dst(&decoded->dst)) |
63f309cfbef9
Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1462
diff
changeset
|
401 ) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
402 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
403 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
404 } |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
405 if (decoded->dst.addr_mode == MODE_REG) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
406 decoded->extra.size = OPSIZE_LONG; |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
407 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
408 } else if ((*istream & 0xC0) == 0xC0) { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
409 #ifdef M68020 |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
410 //CMP2, CHK2, CAS, CAS2, RTM, CALLM |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
411 #endif |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
412 } else { |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
413 switch ((*istream >> 9) & 0x7) |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
414 { |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
415 case 0: |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
416 if ((*istream & 0xFF) == 0x3C) { |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
417 decoded->op = M68K_ORI_CCR; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
418 decoded->extra.size = OPSIZE_BYTE; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
419 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
420 decoded->src.params.immed = *(++istream) & 0xFF; |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
421 } else if((*istream & 0xFF) == 0x7C) { |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
422 decoded->op = M68K_ORI_SR; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
423 decoded->extra.size = OPSIZE_WORD; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
424 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
425 decoded->src.params.immed = *(++istream); |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
426 } else { |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
427 decoded->op = M68K_OR; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
428 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
429 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
430 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
431 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
432 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
433 switch (size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
434 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
435 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
436 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
437 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
438 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
439 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
440 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
441 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
442 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
443 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
444 break; |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
445 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
446 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
823
b1b5a7e7d955
Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
447 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
448 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
449 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
450 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
451 } |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
452 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
453 case 1: |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
454 //ANDI, ANDI to CCR, ANDI to SR |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
455 if ((*istream & 0xFF) == 0x3C) { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
456 decoded->op = M68K_ANDI_CCR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
457 decoded->extra.size = OPSIZE_BYTE; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
458 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
459 decoded->src.params.immed = *(++istream) & 0xFF; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
460 } else if((*istream & 0xFF) == 0x7C) { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
461 decoded->op = M68K_ANDI_SR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
462 decoded->extra.size = OPSIZE_WORD; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
463 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
464 decoded->src.params.immed = *(++istream); |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
465 } else { |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
466 decoded->op = M68K_AND; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
467 decoded->variant = VAR_IMMEDIATE; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
468 decoded->src.addr_mode = MODE_IMMEDIATE; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
469 decoded->extra.size = size = (*istream >> 6) & 3; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
470 reg = *istream & 0x7; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
471 opmode = (*istream >> 3) & 0x7; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
472 switch (size) |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
473 { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
474 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
475 decoded->src.params.immed = *(++istream) & 0xFF; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
476 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
477 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
478 decoded->src.params.immed = *(++istream); |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
479 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
480 case OPSIZE_LONG: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
481 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
482 decoded->src.params.immed = immed << 16 | *(++istream); |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
483 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
484 } |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
485 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
823
b1b5a7e7d955
Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
486 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
487 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
488 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
489 } |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
490 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
491 break; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
492 case 2: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
493 decoded->op = M68K_SUB; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
494 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
495 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
496 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
497 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
498 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
499 switch (size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
500 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
501 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
502 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
503 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
504 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
505 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
506 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
507 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
508 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
509 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
510 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
511 } |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
512 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
823
b1b5a7e7d955
Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
513 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
514 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
515 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
516 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
517 break; |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
518 case 3: |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
519 decoded->op = M68K_ADD; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
520 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
521 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
522 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
523 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
524 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
525 switch (size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
526 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
527 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
528 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
529 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
530 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
531 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
532 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
533 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
534 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
535 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
536 break; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
537 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
538 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
823
b1b5a7e7d955
Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
539 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
540 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
541 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
542 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
543 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
544 case 4: |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
545 //BTST, BCHG, BCLR, BSET |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
546 //Seems like this should be unnecessary since bit instructions are explicitly handled above |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
547 //Possible this is redundant or the case above is overly restrictive |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
548 //TODO: Investigate whether this can be removed |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
549 switch ((*istream >> 6) & 0x3) |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
550 { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
551 case 0: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
552 decoded->op = M68K_BTST; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
553 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
554 case 1: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
555 decoded->op = M68K_BCHG; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
556 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
557 case 2: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
558 decoded->op = M68K_BCLR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
559 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
560 case 3: |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
561 decoded->op = M68K_BSET; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
562 break; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
563 } |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
564 decoded->src.addr_mode = MODE_IMMEDIATE_WORD; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
565 decoded->src.params.immed = *(++istream) & 0xFF; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
566 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
567 if ( |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
568 !istream || !m68k_valid_immed_dst(&decoded->dst) |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
569 || (decoded->op != M68K_BTST && !m68k_valid_immed_limited_dst(&decoded->dst)) |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
570 ) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
571 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
572 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
573 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
574 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
575 case 5: |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
576 //EORI, EORI to CCR, EORI to SR |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
577 if ((*istream & 0xFF) == 0x3C) { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
578 decoded->op = M68K_EORI_CCR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
579 decoded->extra.size = OPSIZE_BYTE; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
580 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
581 decoded->src.params.immed = *(++istream) & 0xFF; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
582 } else if((*istream & 0xFF) == 0x7C) { |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
583 decoded->op = M68K_EORI_SR; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
584 decoded->extra.size = OPSIZE_WORD; |
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
585 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
586 decoded->src.params.immed = *(++istream); |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
587 } else { |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
588 decoded->op = M68K_EOR; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
589 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
590 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
591 decoded->extra.size = size = (*istream >> 6) & 3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
592 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
593 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
594 switch (size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
595 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
596 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
597 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
598 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
599 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
600 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
601 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
602 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
603 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
604 decoded->src.params.immed = immed << 16 | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
605 break; |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
606 } |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
607 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst)); |
823
b1b5a7e7d955
Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents:
652
diff
changeset
|
608 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
609 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
610 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
611 } |
5
85699517043f
More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents:
4
diff
changeset
|
612 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
613 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
614 case 6: |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
615 decoded->op = M68K_CMP; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
616 decoded->variant = VAR_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
617 decoded->extra.size = (*istream >> 6) & 0x3; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
618 decoded->src.addr_mode = MODE_IMMEDIATE; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
619 reg = *istream & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
620 opmode = (*istream >> 3) & 0x7; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
621 switch (decoded->extra.size) |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
622 { |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
623 case OPSIZE_BYTE: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
624 decoded->src.params.immed = *(++istream) & 0xFF; |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
625 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
626 case OPSIZE_WORD: |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
627 decoded->src.params.immed = *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
628 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
629 case OPSIZE_LONG: |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
630 immed = *(++istream); |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
631 decoded->src.params.immed = (immed << 16) | *(++istream); |
8
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
632 break; |
23b83d94c633
Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents:
5
diff
changeset
|
633 } |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
634 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
1463
63f309cfbef9
Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1462
diff
changeset
|
635 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
636 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
637 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
638 } |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
639 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
640 case 7: |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
641 #ifdef M68010 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
642 decoded->op = M68K_MOVES; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
643 decoded->extra.size = *istream >> 6 & 0x3; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
644 immed = *(++istream); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
645 reg = immed >> 12 & 0x7; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
646 opmode = immed & 0x8000 ? MODE_AREG : MODE_REG; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
647 if (immed & 0x800) { |
642
08d0e3e7d0d8
Fix interpretation of moves direction field
Michael Pavone <pavone@retrodev.com>
parents:
641
diff
changeset
|
648 decoded->src.addr_mode = opmode; |
08d0e3e7d0d8
Fix interpretation of moves direction field
Michael Pavone <pavone@retrodev.com>
parents:
641
diff
changeset
|
649 decoded->src.params.regs.pri = reg; |
08d0e3e7d0d8
Fix interpretation of moves direction field
Michael Pavone <pavone@retrodev.com>
parents:
641
diff
changeset
|
650 m68k_decode_op_ex(istream, *start >> 3 & 0x7, *start & 0x7, decoded->extra.size, &(decoded->dst)); |
08d0e3e7d0d8
Fix interpretation of moves direction field
Michael Pavone <pavone@retrodev.com>
parents:
641
diff
changeset
|
651 } else { |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
652 m68k_decode_op_ex(istream, *start >> 3 & 0x7, *start & 0x7, decoded->extra.size, &(decoded->src)); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
653 decoded->dst.addr_mode = opmode; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
654 decoded->dst.params.regs.pri = reg; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
655 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
656 #endif |
4
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
657 break; |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
658 } |
6f6a2d7cc889
Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents:
3
diff
changeset
|
659 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
660 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
661 case MOVE_BYTE: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
662 case MOVE_LONG: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
663 case MOVE_WORD: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
664 decoded->op = M68K_MOVE; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
665 decoded->extra.size = optype == MOVE_BYTE ? OPSIZE_BYTE : (optype == MOVE_WORD ? OPSIZE_WORD : OPSIZE_LONG); |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
666 opmode = (*istream >> 6) & 0x7; |
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
667 reg = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
668 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
1462
d276ec2fff11
More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents:
1458
diff
changeset
|
669 if (!istream || (decoded->src.addr_mode == MODE_AREG && optype == MOVE_BYTE)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
670 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
671 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
672 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
673 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
674 if (!istream || decoded->dst.addr_mode > MODE_ABSOLUTE || (decoded->dst.addr_mode == MODE_AREG && optype == MOVE_BYTE)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
675 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
676 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
677 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
678 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
679 case MISC: |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
680 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
681 if ((*istream & 0x1C0) == 0x1C0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
682 decoded->op = M68K_LEA; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
683 decoded->extra.size = OPSIZE_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
684 decoded->dst.addr_mode = MODE_AREG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
685 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
686 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
1277
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
687 if ( |
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
688 !istream || decoded->src.addr_mode == MODE_REG || decoded->src.addr_mode == MODE_AREG |
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
689 || decoded->src.addr_mode == MODE_AREG_POSTINC || decoded->src.addr_mode == MODE_AREG_PREDEC |
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
690 || decoded->src.addr_mode == MODE_IMMEDIATE |
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
691 ) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
692 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
693 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
694 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
695 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
696 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
697 decoded->op = M68K_CHK; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
698 if ((*istream & 0x180) == 0x180) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
699 decoded->extra.size = OPSIZE_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
700 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
701 //only on M68020+ |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
702 #ifdef M68020 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
703 decoded->extra.size = OPSIZE_LONG; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
704 #else |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
705 decoded->op = M68K_INVALID; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
706 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
707 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
708 } |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
709 decoded->dst.addr_mode = MODE_REG; |
325
8db584faac4b
Fixed decoding of CHK destination
Mike Pavone <pavone@retrodev.com>
parents:
208
diff
changeset
|
710 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
711 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
712 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
713 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
714 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
715 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
716 } else { |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
717 opmode = (*istream >> 3) & 0x7; |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
718 if ((*istream & 0xB80) == 0x880 && opmode != MODE_REG && opmode != MODE_AREG) { |
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
719 //TODO: Check for invalid modes that are dependent on direction |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
720 decoded->op = M68K_MOVEM; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
721 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
722 reg = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
723 if(*istream & 0x400) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
724 decoded->dst.addr_mode = MODE_REG; |
68
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
725 decoded->dst.params.immed = *(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
726 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->src)); |
1253
2a6049dddab0
immediate and predecrement are illegal source address modes for movem. Fixes ticket:8 and ticket:9
Michael Pavone <pavone@retrodev.com>
parents:
1226
diff
changeset
|
727 if (!istream || decoded->src.addr_mode == MODE_AREG_PREDEC || decoded->src.addr_mode == MODE_IMMEDIATE) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
728 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
729 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
730 } |
412
00d5a2b532f4
Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents:
325
diff
changeset
|
731 if (decoded->src.addr_mode == MODE_PC_DISPLACE || decoded->src.addr_mode == MODE_PC_INDEX_DISP8) { |
00d5a2b532f4
Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents:
325
diff
changeset
|
732 //adjust displacement to account for extra instruction word |
00d5a2b532f4
Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents:
325
diff
changeset
|
733 decoded->src.params.regs.displacement += 2; |
00d5a2b532f4
Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents:
325
diff
changeset
|
734 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
735 } else { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
736 decoded->src.addr_mode = MODE_REG; |
68
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
737 decoded->src.params.immed = *(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
738 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
739 if (!istream || !m68k_valid_movem_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
740 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
741 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
742 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
743 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
744 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
745 optype = (*istream >> 9) & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
746 size = (*istream >> 6) & 0x3; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
747 switch(optype) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
748 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
749 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
750 //Move from SR or NEGX |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
751 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
752 decoded->op = M68K_MOVE_FROM_SR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
753 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
754 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
755 decoded->op = M68K_NEGX; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
756 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
757 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
758 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
759 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
760 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
761 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
762 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
763 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
764 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
765 //MOVE from CCR or CLR |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
766 if (size == OPSIZE_INVALID) { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
767 #ifdef M68010 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
768 decoded->op = M68K_MOVE_FROM_CCR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
769 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
770 #else |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
771 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
772 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
773 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
774 decoded->op = M68K_CLR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
775 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
776 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
777 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
778 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
779 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
780 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
781 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
782 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
783 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
784 //MOVE to CCR or NEG |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
785 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
786 decoded->op = M68K_MOVE_CCR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
787 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
788 istream= m68k_decode_op(istream, size, &(decoded->src)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
789 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
790 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
791 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
792 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
793 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
794 decoded->op = M68K_NEG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
795 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
796 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
797 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
798 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
799 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
800 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
801 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
802 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
803 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
804 //MOVE to SR or NOT |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
805 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
806 decoded->op = M68K_MOVE_SR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
807 size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
808 istream= m68k_decode_op(istream, size, &(decoded->src)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
809 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
810 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
811 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
812 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
813 } else { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
814 decoded->op = M68K_NOT; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
815 istream= m68k_decode_op(istream, size, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
816 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
817 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
818 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
819 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
820 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
821 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
822 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
823 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
824 //EXT, EXTB, LINK.l, NBCD, SWAP, BKPT, PEA |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
825 switch((*istream >> 3) & 0x3F) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
826 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
827 case 1: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
828 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
829 decoded->op = M68K_LINK; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
830 decoded->extra.size = OPSIZE_LONG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
831 reg = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
832 immed = *(++istream) << 16; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
833 immed |= *(++istream); |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
834 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
835 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
836 case 8: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
837 decoded->op = M68K_SWAP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
838 decoded->src.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
839 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
840 decoded->extra.size = OPSIZE_WORD; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
841 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
842 case 9: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
843 #ifdef M68010 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
844 decoded->op = M68K_BKPT; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
845 decoded->src.addr_mode = MODE_IMMEDIATE; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
846 decoded->extra.size = OPSIZE_UNSIZED; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
847 decoded->src.params.immed = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
848 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
849 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
850 case 0x10: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
851 decoded->op = M68K_EXT; |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
852 decoded->dst.addr_mode = MODE_REG; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
853 decoded->dst.params.regs.pri = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
854 decoded->extra.size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
855 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
856 case 0x18: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
857 decoded->op = M68K_EXT; |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
858 decoded->dst.addr_mode = MODE_REG; |
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
859 decoded->dst.params.regs.pri = *istream & 0x7; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
860 decoded->extra.size = OPSIZE_LONG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
861 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
862 case 0x38: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
863 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
864 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
865 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
866 default: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
867 if (!(*istream & 0x1C0)) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
868 decoded->op = M68K_NBCD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
869 decoded->extra.size = OPSIZE_BYTE; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
870 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst)); |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
871 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
872 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
873 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
874 } |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
875 } else if((*istream & 0x1C0) == 0x40) { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
876 decoded->op = M68K_PEA; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
877 decoded->extra.size = OPSIZE_LONG; |
116
9eaba47c429d
Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents:
111
diff
changeset
|
878 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src)); |
1277
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
879 if ( |
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
880 !istream || decoded->src.addr_mode == MODE_REG || decoded->src.addr_mode == MODE_AREG |
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
881 || decoded->src.addr_mode == MODE_AREG_POSTINC || decoded->src.addr_mode == MODE_AREG_PREDEC |
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
882 || decoded->src.addr_mode == MODE_IMMEDIATE |
78416556ae02
Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents:
1253
diff
changeset
|
883 ) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
884 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
885 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
886 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
887 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
888 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
889 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
890 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
891 //BGND, ILLEGAL, TAS, TST |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
892 optype = *istream & 0xFF; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
893 if (optype == 0xFA) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
894 //BGND - CPU32 only |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
895 } else if (optype == 0xFC) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
896 decoded->op = M68K_ILLEGAL; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
897 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
898 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
899 if (size == OPSIZE_INVALID) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
900 decoded->op = M68K_TAS; |
835
b4cf6573a3f8
Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents:
823
diff
changeset
|
901 decoded->extra.size = OPSIZE_BYTE; |
b4cf6573a3f8
Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents:
823
diff
changeset
|
902 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst)); |
1463
63f309cfbef9
Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1462
diff
changeset
|
903 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) { |
835
b4cf6573a3f8
Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents:
823
diff
changeset
|
904 decoded->op = M68K_INVALID; |
b4cf6573a3f8
Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents:
823
diff
changeset
|
905 break; |
b4cf6573a3f8
Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents:
823
diff
changeset
|
906 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
907 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
908 decoded->op = M68K_TST; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
909 decoded->extra.size = size; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
910 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
911 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
912 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
913 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
914 } |
1458
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
915 #ifndef M68020 |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
916 if (!m68k_valid_immed_limited_dst(&decoded->src)) { |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
917 decoded->op = M68K_INVALID; |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
918 break; |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
919 } |
b81428ef0396
Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1345
diff
changeset
|
920 #endif |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
921 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
922 } |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
923 break; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
924 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
925 //MULU, MULS, DIVU, DIVUL, DIVS, DIVSL |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
926 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
927 //TODO: Implement these for 68020+ support |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
928 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
929 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
930 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
931 //TRAP, LINK.w, UNLNK, MOVE USP, RESET, NOP, STOP, RTE, RTD, RTS, TRAPV, RTR, MOVEC, JSR, JMP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
932 if (*istream & 0x80) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
933 //JSR, JMP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
934 if (*istream & 0x40) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
935 decoded->op = M68K_JMP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
936 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
937 decoded->op = M68K_JSR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
938 } |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
939 decoded->extra.size = OPSIZE_UNSIZED; |
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
940 istream = m68k_decode_op(istream, OPSIZE_UNSIZED, &(decoded->src)); |
1345
696a029d09e9
Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents:
1330
diff
changeset
|
941 if ( |
696a029d09e9
Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents:
1330
diff
changeset
|
942 !istream |
696a029d09e9
Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents:
1330
diff
changeset
|
943 || (decoded->src.addr_mode < MODE_AREG_DISPLACE && decoded->src.addr_mode != MODE_AREG_INDIRECT) |
696a029d09e9
Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents:
1330
diff
changeset
|
944 || decoded->src.addr_mode == MODE_IMMEDIATE |
696a029d09e9
Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents:
1330
diff
changeset
|
945 ) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
946 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
947 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
948 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
949 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
950 //it would appear bit 6 needs to be set for it to be a valid instruction here |
1462
d276ec2fff11
More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents:
1458
diff
changeset
|
951 if (!(*istream & 0x40)) { |
d276ec2fff11
More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents:
1458
diff
changeset
|
952 decoded->op = M68K_INVALID; |
d276ec2fff11
More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents:
1458
diff
changeset
|
953 break; |
d276ec2fff11
More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents:
1458
diff
changeset
|
954 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
955 switch((*istream >> 3) & 0x7) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
956 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
957 case 0: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
958 case 1: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
959 //TRAP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
960 decoded->op = M68K_TRAP; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
961 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
962 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
963 decoded->src.params.immed = *istream & 0xF; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
964 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
965 case 2: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
966 //LINK.w |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
967 decoded->op = M68K_LINK; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
968 decoded->extra.size = OPSIZE_WORD; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
969 decoded->src.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
970 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
971 decoded->dst.addr_mode = MODE_IMMEDIATE; |
93
f63b0e58e2d5
Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents:
91
diff
changeset
|
972 decoded->dst.params.immed = sign_extend16(*(++istream)); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
973 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
974 case 3: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
975 //UNLK |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
976 decoded->op = M68K_UNLK; |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
977 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
978 decoded->dst.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
979 decoded->dst.params.regs.pri = *istream & 0x7; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
980 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
981 case 4: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
982 case 5: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
983 //MOVE USP |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
984 decoded->op = M68K_MOVE_USP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
985 if (*istream & 0x8) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
986 decoded->dst.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
987 decoded->dst.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
988 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
989 decoded->src.addr_mode = MODE_AREG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
990 decoded->src.params.regs.pri = *istream & 0x7; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
991 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
992 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
993 case 6: |
10
4553fc97b15e
Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents:
9
diff
changeset
|
994 decoded->extra.size = OPSIZE_UNSIZED; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
995 switch(*istream & 0x7) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
996 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
997 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
998 decoded->op = M68K_RESET; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
999 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1000 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1001 decoded->op = M68K_NOP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1002 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1003 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1004 decoded->op = M68K_STOP; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1005 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1006 decoded->src.params.immed =*(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1007 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1008 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1009 decoded->op = M68K_RTE; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1010 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1011 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1012 #ifdef M68010 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1013 decoded->op = M68K_RTD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1014 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1015 decoded->src.params.immed =*(++istream); |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1016 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1017 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1018 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1019 decoded->op = M68K_RTS; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1020 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1021 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1022 decoded->op = M68K_TRAPV; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1023 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1024 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1025 decoded->op = M68K_RTR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1026 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1027 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1028 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1029 case 7: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1030 //MOVEC |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1031 #ifdef M68010 |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1032 decoded->op = M68K_MOVEC; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1033 immed = *(++istream); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1034 reg = immed >> 12 & 0x7; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1035 opmode = immed & 0x8000 ? MODE_AREG : MODE_REG; |
641 | 1036 immed &= 0xFFF; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1037 if (immed & 0x800) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1038 if (immed > MAX_HIGH_CR) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1039 decoded->op = M68K_INVALID; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1040 break; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1041 } else { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1042 immed = immed - 0x800 + CR_USP; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1043 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1044 } else { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1045 if (immed > MAX_LOW_CR) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1046 decoded->op = M68K_INVALID; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1047 break; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1048 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1049 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1050 if (*start & 1) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1051 decoded->src.addr_mode = opmode; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1052 decoded->src.params.regs.pri = reg; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1053 decoded->dst.params.immed = immed; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1054 } else { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1055 decoded->dst.addr_mode = opmode; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1056 decoded->dst.params.regs.pri = reg; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1057 decoded->src.params.immed = immed; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1058 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1059 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1060 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1061 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1062 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1063 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1064 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1065 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1066 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1067 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1068 break; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1069 case QUICK_ARITH_LOOP: |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1070 size = (*istream >> 6) & 3; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1071 if (size == 0x3) { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1072 //DBcc, TRAPcc or Scc |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1073 m68k_decode_cond(*istream, decoded); |
111 | 1074 if (((*istream >> 3) & 0x7) == 1) { |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1075 decoded->op = M68K_DBCC; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1076 decoded->src.addr_mode = MODE_IMMEDIATE; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1077 decoded->dst.addr_mode = MODE_REG; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1078 decoded->dst.params.regs.pri = *istream & 0x7; |
46
f2aaaf36c875
Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents:
18
diff
changeset
|
1079 decoded->src.params.immed = sign_extend16(*(++istream)); |
111 | 1080 } else if(((*istream >> 3) & 0x7) == 1 && (*istream & 0x7) > 1 && (*istream & 0x7) < 5) { |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1081 #ifdef M68020 |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1082 decoded->op = M68K_TRAPCC; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1083 decoded->src.addr_mode = MODE_IMMEDIATE; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1084 //TODO: Figure out what to do with OPMODE and optional extention words |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1085 #endif |
111 | 1086 } else { |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1087 decoded->op = M68K_SCC; |
111 | 1088 decoded->extra.cond = (*istream >> 8) & 0xF; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1089 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst)); |
1462
d276ec2fff11
More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents:
1458
diff
changeset
|
1090 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1091 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1092 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1093 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1094 } |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1095 } else { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1096 //ADDQ, SUBQ |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1097 decoded->variant = VAR_QUICK; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1098 decoded->extra.size = size; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1099 decoded->src.addr_mode = MODE_IMMEDIATE; |
91
8c446fc19cc0
Fix decoding bug in addq/subq
Mike Pavone <pavone@retrodev.com>
parents:
90
diff
changeset
|
1100 immed = m68k_reg_quick_field(*istream); |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1101 if (!immed) { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1102 immed = 8; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1103 } |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1104 decoded->src.params.immed = immed; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1105 if (*istream & 0x100) { |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1106 decoded->op = M68K_SUB; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1107 } else { |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1108 decoded->op = M68K_ADD; |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1109 } |
94
a668a35a3463
Fix decoding bug for addq/subq
Mike Pavone <pavone@retrodev.com>
parents:
93
diff
changeset
|
1110 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
1462
d276ec2fff11
More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents:
1458
diff
changeset
|
1111 if (!istream || decoded->dst.addr_mode > MODE_ABSOLUTE || (size == OPSIZE_BYTE && decoded->dst.addr_mode == MODE_AREG)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1112 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1113 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1114 } |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1115 } |
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1116 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1117 case BRANCH: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1118 m68k_decode_cond(*istream, decoded); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1119 decoded->op = decoded->extra.cond == COND_FALSE ? M68K_BSR : M68K_BCC; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1120 decoded->src.addr_mode = MODE_IMMEDIATE; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1121 immed = *istream & 0xFF; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1122 if (immed == 0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1123 decoded->variant = VAR_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1124 immed = *(++istream); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1125 immed = sign_extend16(immed); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
140
diff
changeset
|
1126 #ifdef M68020 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1127 } else if (immed == 0xFF) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1128 decoded->variant = VAR_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1129 immed = *(++istream) << 16; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1130 immed |= *(++istream); |
154
4791c0204410
Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
140
diff
changeset
|
1131 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1132 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1133 decoded->variant = VAR_BYTE; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1134 immed = sign_extend8(immed); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1135 } |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1136 decoded->src.params.immed = immed; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1137 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1138 case MOVEQ: |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
197
diff
changeset
|
1139 if (*istream & 0x100) { |
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
197
diff
changeset
|
1140 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1141 break; |
208
3457dc6fd558
Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents:
197
diff
changeset
|
1142 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1143 decoded->op = M68K_MOVE; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1144 decoded->variant = VAR_QUICK; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1145 decoded->extra.size = OPSIZE_LONG; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1146 decoded->src.addr_mode = MODE_IMMEDIATE; |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
1147 decoded->src.params.immed = sign_extend8(*istream & 0xFF); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1148 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1149 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1150 immed = *istream & 0xFF; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1151 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1152 case OR_DIV_SBCD: |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1153 //for OR, if opmode bit 2 is 1, then src = Dn, dst = <ea> |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1154 opmode = (*istream >> 6) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1155 size = opmode & 0x3; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1156 if (size == OPSIZE_INVALID || (opmode & 0x4 && !(*istream & 0x30))) { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1157 switch(opmode) |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1158 { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1159 case 3: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1160 decoded->op = M68K_DIVU; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1161 decoded->extra.size = OPSIZE_WORD; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1162 decoded->dst.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1163 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1164 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
183
2f08d9e90a4c
Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
1165 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1166 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1167 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1168 } |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1169 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1170 case 4: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1171 decoded->op = M68K_SBCD; |
613
09d5adf8d1ca
Fix opsize for sbcd in 68K instruction decoder. This fixes the timer bug in Strider 2
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1172 decoded->extra.size = OPSIZE_BYTE; |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1173 decoded->dst.addr_mode = decoded->src.addr_mode = *istream & 0x8 ? MODE_AREG_PREDEC : MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1174 decoded->src.params.regs.pri = *istream & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1175 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1176 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1177 case 5: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1178 #ifdef M68020 |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1179 #endif |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1180 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1181 case 6: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1182 #ifdef M68020 |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1183 #endif |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1184 break; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1185 case 7: |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1186 decoded->op = M68K_DIVS; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1187 decoded->extra.size = OPSIZE_WORD; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1188 decoded->dst.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1189 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1190 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
183
2f08d9e90a4c
Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents:
181
diff
changeset
|
1191 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1192 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1193 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1194 } |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1195 break; |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1196 } |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1197 } else { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1198 decoded->op = M68K_OR; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1199 decoded->extra.size = size; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1200 if (opmode & 0x4) { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1201 decoded->src.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1202 decoded->src.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1203 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
1463
63f309cfbef9
Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1462
diff
changeset
|
1204 if (!istream || !m68k_valid_full_arith_dst(&(decoded->dst))) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1205 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1206 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1207 } |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1208 } else { |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1209 decoded->dst.addr_mode = MODE_REG; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1210 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7; |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1211 istream = m68k_decode_op(istream, size, &(decoded->src)); |
1218
054472ea077a
Properly treat bad addressing modes in OR/AND as illegal instructions
Michael Pavone <pavone@retrodev.com>
parents:
992
diff
changeset
|
1212 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1213 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1214 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1215 } |
11
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1216 } |
d5e9bac9ebdf
Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents:
10
diff
changeset
|
1217 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1218 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1219 case SUB_SUBX: |
101
d7789186ba5e
Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
1220 size = (*istream >> 6) & 0x3; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1221 decoded->op = M68K_SUB; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1222 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1223 //<ea> destination, SUBA.l or SUBX |
101
d7789186ba5e
Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
1224 if (*istream & 0x30 || size == OPSIZE_INVALID) { |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1225 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1226 //SUBA.l |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1227 decoded->extra.size = OPSIZE_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1228 decoded->dst.addr_mode = MODE_AREG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1229 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1230 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1231 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1232 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1233 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1234 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1235 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1236 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1237 decoded->src.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1238 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1239 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
1462
d276ec2fff11
More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents:
1458
diff
changeset
|
1240 if (!istream || !m68k_valid_full_arith_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1241 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1242 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1243 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1244 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1245 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1246 //SUBX |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1247 decoded->op = M68K_SUBX; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1248 decoded->extra.size = size; |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1249 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1250 decoded->src.params.regs.pri = *istream & 0x7; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1251 if (*istream & 0x8) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1252 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_AREG_PREDEC; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1253 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1254 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_REG; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1255 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1256 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1257 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1258 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1259 //SUBA.w |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1260 decoded->extra.size = OPSIZE_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1261 decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1262 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1263 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1264 decoded->dst.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1265 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1266 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1267 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
1462
d276ec2fff11
More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents:
1458
diff
changeset
|
1268 if (!istream || (decoded->src.addr_mode == MODE_AREG && decoded->extra.size == OPSIZE_BYTE)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1269 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1270 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1271 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1272 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1273 break; |
992
261995d06897
Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1274 case A_LINE: |
261995d06897
Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1275 decoded->op = M68K_A_LINE_TRAP; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1276 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1277 case CMP_XOR: |
120 | 1278 size = (*istream >> 6) & 0x3; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1279 decoded->op = M68K_CMP; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1280 if (*istream & 0x100) { |
120 | 1281 //CMPM or CMPA.l or EOR |
1282 if (size == OPSIZE_INVALID) { | |
1283 decoded->extra.size = OPSIZE_LONG; | |
1284 decoded->dst.addr_mode = MODE_AREG; | |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1285 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
136
e64554246d11
Fix some bugs in decoding cmp
Mike Pavone <pavone@retrodev.com>
parents:
134
diff
changeset
|
1286 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1287 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1288 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1289 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1290 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1291 } else { |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1292 reg = m68k_reg_quick_field(*istream); |
120 | 1293 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1294 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1295 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1296 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1297 } |
181
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
1298 decoded->extra.size = size; |
3b4ef459aa8d
Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents:
176
diff
changeset
|
1299 if (decoded->dst.addr_mode == MODE_AREG) { |
120 | 1300 //CMPM |
1301 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG_POSTINC; | |
1302 decoded->src.params.regs.pri = decoded->dst.params.regs.pri; | |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1303 decoded->dst.params.regs.pri = reg; |
1462
d276ec2fff11
More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents:
1458
diff
changeset
|
1304 } else if (!m68k_valid_immed_limited_dst(&decoded->dst)){ |
d276ec2fff11
More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents:
1458
diff
changeset
|
1305 decoded->op = M68K_INVALID; |
d276ec2fff11
More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents:
1458
diff
changeset
|
1306 break; |
120 | 1307 } else { |
1308 //EOR | |
1309 decoded->op = M68K_EOR; | |
1310 decoded->src.addr_mode = MODE_REG; | |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1311 decoded->src.params.regs.pri = reg; |
120 | 1312 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1313 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1314 } else { |
120 | 1315 //CMP or CMPA.w |
1316 if (size == OPSIZE_INVALID) { | |
1317 decoded->extra.size = OPSIZE_WORD; | |
1318 decoded->dst.addr_mode = MODE_AREG; | |
1319 } else { | |
1320 decoded->extra.size = size; | |
1321 decoded->dst.addr_mode = MODE_REG; | |
1322 } | |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1323 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
136
e64554246d11
Fix some bugs in decoding cmp
Mike Pavone <pavone@retrodev.com>
parents:
134
diff
changeset
|
1324 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
1463
63f309cfbef9
Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1462
diff
changeset
|
1325 if (!istream || (decoded->src.addr_mode == MODE_AREG && decoded->extra.size == OPSIZE_BYTE)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1326 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1327 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1328 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1329 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1330 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1331 case AND_MUL_ABCD_EXG: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1332 //page 575 for summary |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1333 //EXG opmodes: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1334 //01000 -data regs |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1335 //01001 -addr regs |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1336 //10001 -one of each |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1337 //AND opmodes: |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1338 //operand order bit + 2 size bits (00 - 10) |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1339 //no address register direct addressing |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1340 //data register direct not allowed when <ea> is the source (operand order bit of 1) |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1341 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1342 if ((*istream & 0xC0) == 0xC0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1343 decoded->op = M68K_MULS; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1344 decoded->extra.size = OPSIZE_WORD; |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1345 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1346 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1347 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
1463
63f309cfbef9
Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1462
diff
changeset
|
1348 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1349 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1350 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1351 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1352 } else if(!(*istream & 0xF0)) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1353 decoded->op = M68K_ABCD; |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1354 decoded->extra.size = OPSIZE_BYTE; |
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1355 decoded->src.params.regs.pri = *istream & 0x7; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1356 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1357 decoded->dst.addr_mode = decoded->src.addr_mode = (*istream & 8) ? MODE_AREG_PREDEC : MODE_REG; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1358 } else if(!(*istream & 0x30)) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1359 decoded->op = M68K_EXG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1360 decoded->extra.size = OPSIZE_LONG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1361 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1362 decoded->dst.params.regs.pri = *istream & 0x7; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1363 if (*istream & 0x8) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1364 if (*istream & 0x80) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1365 decoded->src.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1366 decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1367 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1368 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1369 } |
1463
63f309cfbef9
Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1462
diff
changeset
|
1370 } else if (*istream & 0x40) { |
63f309cfbef9
Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1462
diff
changeset
|
1371 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_REG; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1372 } else { |
1463
63f309cfbef9
Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1462
diff
changeset
|
1373 decoded->op = M68K_INVALID; |
63f309cfbef9
Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1462
diff
changeset
|
1374 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1375 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1376 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1377 decoded->op = M68K_AND; |
90 | 1378 decoded->extra.size = (*istream >> 6) & 0x3; |
60
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1379 decoded->src.addr_mode = MODE_REG; |
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1380 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1381 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst)); |
1463
63f309cfbef9
Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1462
diff
changeset
|
1382 if (!istream || !m68k_valid_full_arith_dst(&(decoded->dst))) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1383 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1384 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1385 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1386 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1387 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1388 if ((*istream & 0xC0) == 0xC0) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1389 decoded->op = M68K_MULU; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1390 decoded->extra.size = OPSIZE_WORD; |
3
a4ad0e3e3e0e
Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents:
2
diff
changeset
|
1391 decoded->dst.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1392 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1393 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src)); |
1463
63f309cfbef9
Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents:
1462
diff
changeset
|
1394 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1395 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1396 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1397 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1398 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1399 decoded->op = M68K_AND; |
90 | 1400 decoded->extra.size = (*istream >> 6) & 0x3; |
60
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1401 decoded->dst.addr_mode = MODE_REG; |
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1402 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
6ffea8607730
Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1403 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
1218
054472ea077a
Properly treat bad addressing modes in OR/AND as illegal instructions
Michael Pavone <pavone@retrodev.com>
parents:
992
diff
changeset
|
1404 if (!istream || decoded->src.addr_mode == MODE_AREG) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1405 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1406 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1407 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1408 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1409 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1410 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1411 case ADD_ADDX: |
101
d7789186ba5e
Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
1412 size = (*istream >> 6) & 0x3; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1413 decoded->op = M68K_ADD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1414 if (*istream & 0x100) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1415 //<ea> destination, ADDA.l or ADDX |
101
d7789186ba5e
Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents:
95
diff
changeset
|
1416 if (*istream & 0x30 || size == OPSIZE_INVALID) { |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1417 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1418 //ADDA.l |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1419 decoded->extra.size = OPSIZE_LONG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1420 decoded->dst.addr_mode = MODE_AREG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1421 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1422 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src)); |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1423 if (!istream) { |
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1424 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1425 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1426 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1427 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1428 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1429 decoded->src.addr_mode = MODE_REG; |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1430 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1431 istream = m68k_decode_op(istream, size, &(decoded->dst)); |
1462
d276ec2fff11
More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents:
1458
diff
changeset
|
1432 if (!istream || !m68k_valid_full_arith_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1433 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1434 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1435 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1436 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1437 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1438 //ADDX |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1439 decoded->op = M68K_ADDX; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1440 decoded->extra.size = size; |
184
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1441 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1442 decoded->src.params.regs.pri = *istream & 0x7; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1443 if (*istream & 0x8) { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1444 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_AREG_PREDEC; |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1445 } else { |
ebcbdd1c4cc8
Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents:
183
diff
changeset
|
1446 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_REG; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1447 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1448 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1449 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1450 if (size == OPSIZE_INVALID) { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1451 //ADDA.w |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1452 decoded->extra.size = OPSIZE_WORD; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1453 decoded->dst.addr_mode = MODE_AREG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1454 } else { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1455 decoded->extra.size = size; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1456 decoded->dst.addr_mode = MODE_REG; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1457 } |
18
3e7bfde7606e
M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents:
15
diff
changeset
|
1458 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1459 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src)); |
1462
d276ec2fff11
More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents:
1458
diff
changeset
|
1460 if (!istream || (decoded->src.addr_mode == MODE_AREG && decoded->extra.size == OPSIZE_BYTE)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1461 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1462 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1463 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1464 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1465 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1466 case SHIFT_ROTATE: |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1467 if ((*istream & 0x8C0) == 0xC0) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1468 switch((*istream >> 8) & 0x7) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1469 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1470 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1471 decoded->op = M68K_ASR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1472 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1473 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1474 decoded->op = M68K_ASL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1475 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1476 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1477 decoded->op = M68K_LSR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1478 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1479 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1480 decoded->op = M68K_LSL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1481 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1482 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1483 decoded->op = M68K_ROXR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1484 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1485 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1486 decoded->op = M68K_ROXL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1487 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1488 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1489 decoded->op = M68K_ROR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1490 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1491 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1492 decoded->op = M68K_ROL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1493 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1494 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1495 decoded->extra.size = OPSIZE_WORD; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1496 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->dst)); |
1462
d276ec2fff11
More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents:
1458
diff
changeset
|
1497 if (!istream || !m68k_valid_full_arith_dst(&decoded->dst)) { |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1498 decoded->op = M68K_INVALID; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1499 break; |
176
e2918b5208eb
Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents:
163
diff
changeset
|
1500 } |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1501 } else if((*istream & 0xC0) != 0xC0) { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1502 switch(((*istream >> 2) & 0x6) | ((*istream >> 8) & 1)) |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1503 { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1504 case 0: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1505 decoded->op = M68K_ASR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1506 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1507 case 1: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1508 decoded->op = M68K_ASL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1509 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1510 case 2: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1511 decoded->op = M68K_LSR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1512 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1513 case 3: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1514 decoded->op = M68K_LSL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1515 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1516 case 4: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1517 decoded->op = M68K_ROXR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1518 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1519 case 5: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1520 decoded->op = M68K_ROXL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1521 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1522 case 6: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1523 decoded->op = M68K_ROR; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1524 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1525 case 7: |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1526 decoded->op = M68K_ROL; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1527 break; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1528 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1529 decoded->extra.size = (*istream >> 6) & 0x3; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1530 immed = (*istream >> 9) & 0x7; |
51
937b47c9b79b
Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents:
50
diff
changeset
|
1531 if (*istream & 0x20) { |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1532 decoded->src.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1533 decoded->src.params.regs.pri = immed; |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1534 } else { |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1535 decoded->src.addr_mode = MODE_IMMEDIATE; |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1536 if (!immed) { |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1537 immed = 8; |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1538 } |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1539 decoded->src.params.immed = immed; |
1627
dc1eab3ec092
Fix cycle count for shift/rotate instructions with a static shift ammount
Michael Pavone <pavone@retrodev.com>
parents:
1463
diff
changeset
|
1540 decoded->variant = VAR_QUICK; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1541 } |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1542 decoded->dst.addr_mode = MODE_REG; |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1543 decoded->dst.params.regs.pri = *istream & 0x7; |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1544 |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1545 } else { |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1546 #ifdef M68020 |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1547 //TODO: Implement bitfield instructions for M68020+ support |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1548 switch (*istream >> 8 & 7) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1549 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1550 case 0: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1551 decoded->op = M68K_BFTST; //<ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1552 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1553 case 1: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1554 decoded->op = M68K_BFEXTU; //<ea>, Dn |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1555 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1556 case 2: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1557 decoded->op = M68K_BFCHG; //<ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1558 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1559 case 3: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1560 decoded->op = M68K_BFEXTS; //<ea>, Dn |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1561 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1562 case 4: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1563 decoded->op = M68K_BFCLR; //<ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1564 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1565 case 5: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1566 decoded->op = M68K_BFFFO; //<ea>, Dn |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1567 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1568 case 6: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1569 decoded->op = M68K_BFSET; //<ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1570 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1571 case 7: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1572 decoded->op = M68K_BFINS; //Dn, <ea> |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1573 break; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1574 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1575 opmode = *istream >> 3 & 0x7; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1576 reg = *istream & 0x7; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1577 m68k_op_info *ea, *other; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1578 if (decoded->op == M68K_BFEXTU || decoded->op == M68K_BFEXTS || decoded->op == M68K_BFFFO) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1579 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1580 ea = &(decoded->src); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1581 other = &(decoded->dst); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1582 } else { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1583 ea = &(decoded->dst); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1584 other = &(decoded->dst); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1585 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1586 if (*istream & 0x100) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1587 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1588 immed = *(istream++); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1589 other->addr_mode = MODE_REG; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1590 other->params.regs.pri = immed >> 12 & 0x7; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1591 } else { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1592 immed = *(istream++); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1593 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1594 decoded->extra.size = OPSIZE_UNSIZED; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1595 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, ea); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1596 ea->addr_mode |= M68K_FLAG_BITFIELD; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1597 ea->bitfield = immed & 0xFFF; |
9
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1598 #endif |
0a0cd3705c19
Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents:
8
diff
changeset
|
1599 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1600 break; |
992
261995d06897
Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1601 case F_LINE: |
261995d06897
Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1602 //TODO: Decode FPU instructions for members of the 68K family with an FPU |
261995d06897
Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents:
981
diff
changeset
|
1603 decoded->op = M68K_F_LINE_TRAP; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1604 break; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1605 } |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1606 if (decoded->op == M68K_INVALID) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1607 decoded->src.params.immed = *start; |
981
902c53d9c16f
Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
835
diff
changeset
|
1608 decoded->bytes = 2; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1609 return start + 1; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1610 } |
981
902c53d9c16f
Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents:
835
diff
changeset
|
1611 decoded->bytes = 2 * (istream + 1 - start); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1612 return istream+1; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1613 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1614 |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1615 uint32_t m68k_branch_target(m68kinst * inst, uint32_t *dregs, uint32_t *aregs) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1616 { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1617 if(inst->op == M68K_BCC || inst->op == M68K_BSR || inst->op == M68K_DBCC) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1618 return inst->address + 2 + inst->src.params.immed; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1619 } else if(inst->op == M68K_JMP || inst->op == M68K_JSR) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1620 uint32_t ret = 0; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1621 switch(inst->src.addr_mode) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1622 { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1623 case MODE_AREG_INDIRECT: |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1624 ret = aregs[inst->src.params.regs.pri]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1625 break; |
1330
af26a1ce92f7
Handle address register displacement when calculating branch targets in debugger
Michael Pavone <pavone@retrodev.com>
parents:
1277
diff
changeset
|
1626 case MODE_AREG_DISPLACE: |
af26a1ce92f7
Handle address register displacement when calculating branch targets in debugger
Michael Pavone <pavone@retrodev.com>
parents:
1277
diff
changeset
|
1627 ret = aregs[inst->src.params.regs.pri] + inst->src.params.regs.displacement; |
af26a1ce92f7
Handle address register displacement when calculating branch targets in debugger
Michael Pavone <pavone@retrodev.com>
parents:
1277
diff
changeset
|
1628 break; |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1629 case MODE_AREG_INDEX_DISP8: { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1630 uint8_t sec_reg = inst->src.params.regs.sec >> 1 & 0x7; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1631 ret = aregs[inst->src.params.regs.pri]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1632 uint32_t * regfile = inst->src.params.regs.sec & 0x10 ? aregs : dregs; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1633 if (inst->src.params.regs.sec & 1) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1634 //32-bit index register |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1635 ret += regfile[sec_reg]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1636 } else { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1637 //16-bit index register |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1638 if (regfile[sec_reg] & 0x8000) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1639 ret += (0xFFFF0000 | regfile[sec_reg]); |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1640 } else { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1641 ret += regfile[sec_reg]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1642 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1643 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1644 ret += inst->src.params.regs.displacement; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1645 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1646 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1647 case MODE_PC_DISPLACE: |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1648 ret = inst->src.params.regs.displacement + inst->address + 2; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1649 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1650 case MODE_PC_INDEX_DISP8: { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1651 uint8_t sec_reg = inst->src.params.regs.sec >> 1 & 0x7; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1652 ret = inst->address + 2; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1653 uint32_t * regfile = inst->src.params.regs.sec & 0x10 ? aregs : dregs; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1654 if (inst->src.params.regs.sec & 1) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1655 //32-bit index register |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1656 ret += regfile[sec_reg]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1657 } else { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1658 //16-bit index register |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1659 if (regfile[sec_reg] & 0x8000) { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1660 ret += (0xFFFF0000 | regfile[sec_reg]); |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1661 } else { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1662 ret += regfile[sec_reg]; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1663 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1664 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1665 ret += inst->src.params.regs.displacement; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1666 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1667 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1668 case MODE_ABSOLUTE: |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1669 case MODE_ABSOLUTE_SHORT: |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1670 ret = inst->src.params.immed; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1671 break; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1672 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1673 return ret; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1674 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1675 return 0; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1676 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1677 |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1678 uint8_t m68k_is_branch(m68kinst * inst) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1679 { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1680 return (inst->op == M68K_BCC && inst->extra.cond != COND_FALSE) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1681 || (inst->op == M68K_DBCC && inst->extra.cond != COND_TRUE) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1682 || inst->op == M68K_BSR || inst->op == M68K_JMP || inst->op == M68K_JSR; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1683 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1684 |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1685 uint8_t m68k_is_noncall_branch(m68kinst * inst) |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1686 { |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1687 return m68k_is_branch(inst) && inst->op != M68K_BSR && inst->op != M68K_JSR; |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1688 } |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1689 |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
1690 |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1691 char * mnemonics[] = { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1692 "abcd", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1693 "add", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1694 "addx", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1695 "and", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1696 "andi",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1697 "andi",//sr |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1698 "asl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1699 "asr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1700 "bcc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1701 "bchg", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1702 "bclr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1703 "bset", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1704 "bsr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1705 "btst", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1706 "chk", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1707 "clr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1708 "cmp", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1709 "dbcc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1710 "divs", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1711 "divu", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1712 "eor", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1713 "eori",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1714 "eori",//sr |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1715 "exg", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1716 "ext", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1717 "illegal", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1718 "jmp", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1719 "jsr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1720 "lea", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1721 "link", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1722 "lsl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1723 "lsr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1724 "move", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1725 "move",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1726 "move",//from_sr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1727 "move",//sr |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
1728 "move",//usp |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1729 "movem", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1730 "movep", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1731 "muls", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1732 "mulu", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1733 "nbcd", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1734 "neg", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1735 "negx", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1736 "nop", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1737 "not", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1738 "or", |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1739 "ori",//ccr |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1740 "ori",//sr |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1741 "pea", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1742 "reset", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1743 "rol", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1744 "ror", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1745 "roxl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1746 "roxr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1747 "rte", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1748 "rtr", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1749 "rts", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1750 "sbcd", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1751 "scc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1752 "stop", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1753 "sub", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1754 "subx", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1755 "swap", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1756 "tas", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1757 "trap", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1758 "trapv", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1759 "tst", |
12
db60ed283d8d
Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents:
11
diff
changeset
|
1760 "unlk", |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1761 "invalid", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1762 #ifdef M68010 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1763 "bkpt", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1764 "move", //from ccr |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1765 "movec", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1766 "moves", |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1767 "rtd", |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1768 #endif |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1769 #ifdef M68020 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1770 "bfchg", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1771 "bfclr", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1772 "bfexts", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1773 "bfextu", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1774 "bfffo", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1775 "bfins", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1776 "bfset", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1777 "bftst", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1778 "callm", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1779 "cas", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1780 "cas2", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1781 "chk2", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1782 "cmp2", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1783 "cpbcc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1784 "cpdbcc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1785 "cpgen", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1786 "cprestore", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1787 "cpsave", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1788 "cpscc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1789 "cptrapcc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1790 "divsl", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1791 "divul", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1792 "extb", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1793 "pack", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1794 "rtm", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1795 "trapcc", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1796 "unpk" |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1797 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1798 }; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1799 |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1800 char * cond_mnem[] = { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1801 "ra", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1802 "f", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1803 "hi", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1804 "ls", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1805 "cc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1806 "cs", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1807 "ne", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1808 "eq", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1809 "vc", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1810 "vs", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1811 "pl", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1812 "mi", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1813 "ge", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1814 "lt", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1815 "gt", |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1816 "le" |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1817 }; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1818 #ifdef M68010 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1819 char * cr_mnem[] = { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1820 "SFC", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1821 "DFC", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1822 #ifdef M68020 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1823 "CACR", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1824 #endif |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1825 "USP", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1826 "VBR", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1827 #ifdef M68020 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1828 "CAAR", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1829 "MSP", |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1830 "ISP" |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1831 #endif |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1832 }; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
1833 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1834 |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
1835 int m68k_disasm_op(m68k_op_info *decoded, char *dst, int need_comma, uint8_t labels, uint32_t address, format_label_fun label_fun, void * data) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1836 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1837 char * c = need_comma ? "," : ""; |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1838 int ret = 0; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1839 #ifdef M68020 |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1840 uint8_t addr_mode = decoded->addr_mode & (~M68K_FLAG_BITFIELD); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1841 #else |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1842 uint8_t addr_mode = decoded->addr_mode; |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1843 #endif |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1844 switch(addr_mode) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1845 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1846 case MODE_REG: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1847 ret = sprintf(dst, "%s d%d", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1848 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1849 case MODE_AREG: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1850 ret = sprintf(dst, "%s a%d", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1851 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1852 case MODE_AREG_INDIRECT: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1853 ret = sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1854 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1855 case MODE_AREG_POSTINC: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1856 ret = sprintf(dst, "%s (a%d)+", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1857 break; |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
1858 case MODE_AREG_PREDEC: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1859 ret = sprintf(dst, "%s -(a%d)", c, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1860 break; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
1861 case MODE_AREG_DISPLACE: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1862 ret = sprintf(dst, "%s (%d, a%d)", c, decoded->params.regs.displacement, decoded->params.regs.pri); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1863 break; |
79
d212e0cd0b7e
Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents:
69
diff
changeset
|
1864 case MODE_AREG_INDEX_DISP8: |
638
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1865 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1866 if (decoded->params.regs.scale) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1867 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1868 ret = sprintf(dst, "%s (%d, a%d, %c%d.%c*%d)", c, decoded->params.regs.displacement, decoded->params.regs.pri, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1869 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1870 #endif |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1871 ret = sprintf(dst, "%s (%d, a%d, %c%d.%c)", c, decoded->params.regs.displacement, decoded->params.regs.pri, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1872 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1873 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1874 #endif |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1875 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1876 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1877 case MODE_AREG_INDEX_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1878 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1879 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1880 ret = sprintf(dst, "%s (%d.%c, a%d, %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1881 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1882 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1883 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1884 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1885 ret = sprintf(dst, "%s (a%d, %c%d.%c*%d)", c, decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1886 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1887 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1888 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1889 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1890 case MODE_AREG_PREINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1891 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1892 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1893 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1894 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1895 ret = sprintf(dst, "%s ([a%d, %c%d.%c*%d])", c, decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1896 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1897 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1898 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1899 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1900 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1901 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1902 ret = sprintf(dst, "%s ([%d.%c, a%d, %c%d.%c*%d])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1903 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1904 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1905 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1906 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1907 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1908 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1909 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1910 ret = sprintf(dst, "%s ([a%d, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1911 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1912 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1913 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1914 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1915 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1916 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1917 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1918 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1919 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1920 ret = sprintf(dst, "%s ([%d.%c, a%d, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1921 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1922 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1923 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1924 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1925 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1926 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1927 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1928 case MODE_AREG_POSTINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1929 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1930 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1931 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1932 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1933 ret = sprintf(dst, "%s ([a%d], %c%d.%c*%d)", c, decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1934 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1935 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1936 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1937 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1938 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1939 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1940 ret = sprintf(dst, "%s ([%d.%c, a%d], %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1941 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1942 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1943 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1944 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1945 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1946 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1947 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1948 ret = sprintf(dst, "%s ([a%d], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1949 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1950 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1951 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1952 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1953 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1954 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1955 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1956 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1957 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1958 ret = sprintf(dst, "%s ([%d.%c, a%d], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1959 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1960 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1961 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1962 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1963 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1964 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1965 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1966 case MODE_AREG_MEM_INDIRECT: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1967 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1968 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1969 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1970 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1971 ret = sprintf(dst, "%s ([a%d])", c, decoded->params.regs.pri); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1972 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1973 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1974 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1975 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1976 ret = sprintf(dst, "%s ([%d.%c, a%d])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1977 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1978 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1979 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1980 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1981 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1982 ret = sprintf(dst, "%s ([a%d], %d.%c)", c, decoded->params.regs.pri, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1983 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1984 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1985 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1986 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1987 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1988 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1989 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1990 ret = sprintf(dst, "%s ([%d.%c, a%d], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1991 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1992 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1993 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1994 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
1995 break; |
638
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1996 case MODE_AREG_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1997 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1998 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
1999 ret = sprintf(dst, "%s (%d.%c, a%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2000 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', decoded->params.regs.pri); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2001 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2002 //this is a lossy representation of the encoded instruction |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2003 //not sure if there's a better way to print it though |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2004 ret = sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2005 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2006 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2007 case MODE_INDEX_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2008 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2009 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2010 ret = sprintf(dst, "%s (%d.%c, %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2011 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2012 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2013 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2014 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2015 ret = sprintf(dst, "%s (%c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2016 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2017 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2018 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2019 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2020 case MODE_PREINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2021 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2022 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2023 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2024 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2025 ret = sprintf(dst, "%s ([%c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2026 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2027 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2028 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2029 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2030 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2031 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2032 ret = sprintf(dst, "%s ([%d.%c, %c%d.%c*%d])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2033 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2034 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2035 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2036 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2037 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2038 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2039 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2040 ret = sprintf(dst, "%s ([%c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2041 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2042 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2043 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2044 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2045 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2046 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2047 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2048 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2049 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2050 ret = sprintf(dst, "%s ([%d.%c, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2051 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2052 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2053 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2054 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2055 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2056 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2057 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2058 case MODE_POSTINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2059 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2060 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2061 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2062 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2063 ret = sprintf(dst, "%s ([], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2064 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2065 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2066 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2067 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2068 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2069 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2070 ret = sprintf(dst, "%s ([%d.%c], %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2071 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2072 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2073 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2074 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2075 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2076 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2077 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2078 ret = sprintf(dst, "%s ([], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2079 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2080 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2081 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2082 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2083 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2084 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2085 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2086 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2087 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2088 ret = sprintf(dst, "%s ([%d.%c], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2089 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2090 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2091 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2092 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2093 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2094 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2095 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2096 case MODE_MEM_INDIRECT: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2097 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2098 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2099 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2100 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2101 ret = sprintf(dst, "%s ([])", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2102 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2103 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2104 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2105 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2106 ret = sprintf(dst, "%s ([%d.%c])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2107 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2108 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2109 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2110 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2111 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2112 ret = sprintf(dst, "%s ([], %d.%c)", c, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2113 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2114 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2115 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2116 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2117 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2118 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2119 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2120 ret = sprintf(dst, "%s ([%d.%c], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2121 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2122 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2123 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2124 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2125 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2126 case MODE_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2127 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2128 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2129 ret = sprintf(dst, "%s (%d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2130 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2131 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2132 ret = sprintf(dst, "%s ()", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2133 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2134 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2135 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2136 case MODE_IMMEDIATE: |
61
918468c623e9
Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents:
60
diff
changeset
|
2137 case MODE_IMMEDIATE_WORD: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2138 ret = sprintf(dst, (decoded->params.immed <= 128 ? "%s #%d" : "%s #$%X"), c, decoded->params.immed); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2139 break; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2140 case MODE_ABSOLUTE_SHORT: |
638
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2141 if (labels) { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2142 ret = sprintf(dst, "%s ", c); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2143 ret += label_fun(dst+ret, decoded->params.immed, data); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2144 strcat(dst+ret, ".w"); |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2145 ret = ret + 2; |
134 | 2146 } else { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2147 ret = sprintf(dst, "%s $%X.w", c, decoded->params.immed); |
134 | 2148 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2149 break; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2150 case MODE_ABSOLUTE: |
134 | 2151 if (labels) { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2152 ret = sprintf(dst, "%s ", c); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2153 ret += label_fun(dst+ret, decoded->params.immed, data); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2154 strcat(dst+ret, ".l"); |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2155 ret = ret + 2; |
134 | 2156 } else { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2157 ret = sprintf(dst, "%s $%X", c, decoded->params.immed); |
134 | 2158 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2159 break; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2160 case MODE_PC_DISPLACE: |
134 | 2161 if (labels) { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2162 ret = sprintf(dst, "%s ", c); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2163 ret += label_fun(dst+ret, address + 2 + decoded->params.regs.displacement, data); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2164 strcat(dst+ret, "(pc)"); |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2165 ret = ret + 4; |
134 | 2166 } else { |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2167 ret = sprintf(dst, "%s (%d, pc)", c, decoded->params.regs.displacement); |
134 | 2168 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2169 break; |
79
d212e0cd0b7e
Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents:
69
diff
changeset
|
2170 case MODE_PC_INDEX_DISP8: |
638
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2171 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2172 if (decoded->params.regs.scale) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2173 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2174 ret = sprintf(dst, "%s (%d, pc, %c%d.%c*%d)", c, decoded->params.regs.displacement, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2175 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2176 #endif |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2177 ret = sprintf(dst, "%s (%d, pc, %c%d.%c)", c, decoded->params.regs.displacement, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2178 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2179 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2180 #endif |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2181 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2182 #ifdef M68020 |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2183 case MODE_PC_INDEX_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2184 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2185 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2186 ret = sprintf(dst, "%s (%d.%c, pc, %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2187 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2188 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2189 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2190 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2191 ret = sprintf(dst, "%s (pc, %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2192 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2193 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2194 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2195 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2196 case MODE_PC_PREINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2197 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2198 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2199 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2200 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2201 ret = sprintf(dst, "%s ([pc, %c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2202 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2203 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2204 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2205 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2206 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2207 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2208 ret = sprintf(dst, "%s ([%d.%c, pc, %c%d.%c*%d])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2209 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2210 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2211 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2212 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2213 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2214 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2215 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2216 ret = sprintf(dst, "%s ([pc, %c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2217 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2218 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2219 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2220 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2221 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2222 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2223 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2224 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2225 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2226 ret = sprintf(dst, "%s ([%d.%c, pc, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2227 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2228 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2229 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2230 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2231 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2232 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2233 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2234 case MODE_PC_POSTINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2235 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2236 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2237 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2238 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2239 ret = sprintf(dst, "%s ([pc], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2240 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2241 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2242 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2243 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2244 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2245 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2246 ret = sprintf(dst, "%s ([%d.%c, pc], %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2247 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2248 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2249 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2250 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2251 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2252 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2253 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2254 ret = sprintf(dst, "%s ([pc], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2255 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2256 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2257 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2258 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2259 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2260 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2261 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2262 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2263 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2264 ret = sprintf(dst, "%s ([%d.%c, pc], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2265 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2266 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2267 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2268 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2269 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2270 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2271 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2272 case MODE_PC_MEM_INDIRECT: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2273 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2274 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2275 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2276 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2277 ret = sprintf(dst, "%s ([pc])", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2278 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2279 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2280 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2281 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2282 ret = sprintf(dst, "%s ([%d.%c, pc])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2283 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2284 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2285 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2286 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2287 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2288 ret = sprintf(dst, "%s ([pc], %d.%c)", c, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2289 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2290 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2291 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2292 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2293 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2294 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2295 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2296 ret = sprintf(dst, "%s ([%d.%c, pc], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2297 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2298 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2299 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2300 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2301 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2302 case MODE_PC_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2303 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2304 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2305 ret = sprintf(dst, "%s (%d.%c, pc)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2306 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2307 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2308 ret = sprintf(dst, "%s (pc)", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2309 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2310 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2311 case MODE_ZPC_INDEX_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2312 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2313 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2314 ret = sprintf(dst, "%s (%d.%c, zpc, %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2315 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2316 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2317 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2318 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2319 ret = sprintf(dst, "%s (zpc, %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2320 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2321 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2322 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2323 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2324 case MODE_ZPC_PREINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2325 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2326 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2327 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2328 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2329 ret = sprintf(dst, "%s ([zpc, %c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2330 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2331 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2332 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2333 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2334 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2335 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2336 ret = sprintf(dst, "%s ([%d.%c, zpc, %c%d.%c*%d])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2337 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2338 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2339 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2340 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2341 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2342 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2343 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2344 ret = sprintf(dst, "%s ([zpc, %c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2345 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2346 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2347 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2348 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2349 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2350 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2351 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2352 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2353 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2354 ret = sprintf(dst, "%s ([%d.%c, zpc, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2355 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2356 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2357 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2358 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2359 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2360 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2361 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2362 case MODE_ZPC_POSTINDEX: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2363 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2364 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2365 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2366 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2367 ret = sprintf(dst, "%s ([zpc], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2368 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2369 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2370 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2371 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2372 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2373 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2374 ret = sprintf(dst, "%s ([%d.%c, zpc], %c%d.%c*%d)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2375 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2376 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2377 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2378 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2379 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2380 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2381 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2382 ret = sprintf(dst, "%s ([zpc], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2383 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2384 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2385 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2386 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2387 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2388 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2389 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2390 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2391 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2392 ret = sprintf(dst, "%s ([%d.%c, zpc], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2393 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2394 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2395 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2396 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2397 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2398 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2399 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2400 case MODE_ZPC_MEM_INDIRECT: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2401 switch (decoded->params.regs.disp_sizes) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2402 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2403 case 0x11: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2404 //no base displacement or outer displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2405 ret = sprintf(dst, "%s ([zpc])", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2406 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2407 case 0x12: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2408 case 0x13: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2409 //base displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2410 ret = sprintf(dst, "%s ([%d.%c, zpc])", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2411 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2412 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2413 case 0x21: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2414 case 0x31: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2415 //outer displacement only |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2416 ret = sprintf(dst, "%s ([zpc], %d.%c)", c, decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2417 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2418 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2419 case 0x22: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2420 case 0x23: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2421 case 0x32: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2422 case 0x33: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2423 //both outer and inner displacement |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2424 ret = sprintf(dst, "%s ([%d.%c, zpc], %d.%c)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2425 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2426 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2427 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2428 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2429 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2430 case MODE_ZPC_BASE_DISP: |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2431 if (decoded->params.regs.disp_sizes > 1) |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2432 { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2433 ret = sprintf(dst, "%s (%d.%c, zpc)", c, decoded->params.regs.displacement, |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2434 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l'); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2435 } else { |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2436 ret = sprintf(dst, "%s (zpc)", c); |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2437 } |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2438 break; |
8a3198c17207
Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents:
636
diff
changeset
|
2439 #endif |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2440 default: |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2441 ret = 0; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2442 } |
636
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2443 #ifdef M68020 |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2444 if (decoded->addr_mode & M68K_FLAG_BITFIELD) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2445 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2446 switch (decoded->bitfield & 0x820) |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2447 { |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2448 case 0: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2449 return ret + sprintf(dst+ret, " {$%X:%d}", decoded->bitfield >> 6 & 0x1F, decoded->bitfield & 0x1F ? decoded->bitfield & 0x1F : 32); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2450 case 0x20: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2451 return ret + sprintf(dst+ret, " {$%X:d%d}", decoded->bitfield >> 6 & 0x1F, decoded->bitfield & 0x7); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2452 case 0x800: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2453 return ret + sprintf(dst+ret, " {d%d:%d}", decoded->bitfield >> 6 & 0x7, decoded->bitfield & 0x1F ? decoded->bitfield & 0x1F : 32); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2454 case 0x820: |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2455 return ret + sprintf(dst+ret, " {d%d:d%d}", decoded->bitfield >> 6 & 0x7, decoded->bitfield & 0x7); |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2456 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2457 } |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2458 #endif |
22e357678fad
Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents:
634
diff
changeset
|
2459 return ret; |
0
2432d177e1ac
Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
2460 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2461 |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2462 int m68k_disasm_movem_op(m68k_op_info *decoded, m68k_op_info *other, char *dst, int need_comma, uint8_t labels, uint32_t address, format_label_fun label_fun, void * data) |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2463 { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2464 int8_t dir, reg, bit, regnum, last=-1, lastreg, first=-1; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2465 char *rtype, *last_rtype; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2466 int oplen; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2467 if (decoded->addr_mode == MODE_REG) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2468 if (other->addr_mode == MODE_AREG_PREDEC) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2469 bit = 15; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2470 dir = -1; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2471 } else { |
69
36f1133837d0
Fix disassembly of reg list in MOVEM when the reg list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
68
diff
changeset
|
2472 dir = 1; |
36f1133837d0
Fix disassembly of reg list in MOVEM when the reg list is the destination
Mike Pavone <pavone@retrodev.com>
parents:
68
diff
changeset
|
2473 bit = 0; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2474 } |
68
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2475 if (need_comma) { |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2476 strcat(dst, ", "); |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2477 oplen = 2; |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2478 } else { |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2479 strcat(dst, " "); |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2480 oplen = 1; |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2481 } |
1c9a4052a2c0
Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents:
62
diff
changeset
|
2482 for (reg=0; bit < 16 && bit > -1; bit += dir, reg++) { |
15
c0f339564819
Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents:
13
diff
changeset
|
2483 if (decoded->params.immed & (1 << bit)) { |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2484 if (reg > 7) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2485 rtype = "a"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2486 regnum = reg - 8; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2487 } else { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2488 rtype = "d"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2489 regnum = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2490 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2491 if (last >= 0 && last == regnum - 1 && lastreg == reg - 1) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2492 last = regnum; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2493 lastreg = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2494 } else if(last >= 0) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2495 if (first != last) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2496 oplen += sprintf(dst + oplen, "-%s%d/%s%d",last_rtype, last, rtype, regnum); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2497 } else { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2498 oplen += sprintf(dst + oplen, "/%s%d", rtype, regnum); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2499 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2500 first = last = regnum; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2501 last_rtype = rtype; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2502 lastreg = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2503 } else { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2504 oplen += sprintf(dst + oplen, "%s%d", rtype, regnum); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2505 first = last = regnum; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2506 last_rtype = rtype; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2507 lastreg = reg; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2508 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2509 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2510 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2511 if (last >= 0 && last != first) { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2512 oplen += sprintf(dst + oplen, "-%s%d", last_rtype, last); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2513 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2514 return oplen; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2515 } else { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2516 return m68k_disasm_op(decoded, dst, need_comma, labels, address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2517 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2518 } |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2519 |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2520 int m68k_default_label_fun(char * dst, uint32_t address, void * data) |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2521 { |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2522 return sprintf(dst, "ADR_%X", address); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2523 } |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2524 |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2525 int m68k_disasm_ex(m68kinst * decoded, char * dst, uint8_t labels, format_label_fun label_fun, void * data) |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2526 { |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2527 int ret,op1len; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2528 uint8_t size; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2529 char * special_op = "CCR"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2530 switch (decoded->op) |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2531 { |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2532 case M68K_BCC: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2533 case M68K_DBCC: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2534 case M68K_SCC: |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2535 ret = strlen(mnemonics[decoded->op]) - 2; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2536 memcpy(dst, mnemonics[decoded->op], ret); |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2537 dst[ret] = 0; |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2538 strcpy(dst+ret, cond_mnem[decoded->extra.cond]); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2539 ret = strlen(dst); |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2540 if (decoded->op != M68K_SCC) { |
134 | 2541 if (labels) { |
2542 if (decoded->op == M68K_DBCC) { | |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2543 ret += sprintf(dst+ret, " d%d, ", decoded->dst.params.regs.pri); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2544 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data); |
134 | 2545 } else { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2546 dst[ret++] = ' '; |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2547 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data); |
134 | 2548 } |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2549 } else { |
134 | 2550 if (decoded->op == M68K_DBCC) { |
2551 ret += sprintf(dst+ret, " d%d, #%d <%X>", decoded->dst.params.regs.pri, decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed); | |
2552 } else { | |
2553 ret += sprintf(dst+ret, " #%d <%X>", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed); | |
2554 } | |
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
51
diff
changeset
|
2555 } |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2556 return ret; |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2557 } |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2558 break; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2559 case M68K_BSR: |
134 | 2560 if (labels) { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2561 ret = sprintf(dst, "bsr%s ", decoded->variant == VAR_BYTE ? ".s" : ""); |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2562 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data); |
134 | 2563 } else { |
2564 ret = sprintf(dst, "bsr%s #%d <%X>", decoded->variant == VAR_BYTE ? ".s" : "", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed); | |
2565 } | |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2566 return ret; |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2567 case M68K_MOVE_FROM_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2568 ret = sprintf(dst, "%s", mnemonics[decoded->op]); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2569 ret += sprintf(dst + ret, " SR"); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2570 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 1, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2571 return ret; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2572 case M68K_ANDI_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2573 case M68K_EORI_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2574 case M68K_MOVE_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2575 case M68K_ORI_SR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2576 special_op = "SR"; |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2577 case M68K_ANDI_CCR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2578 case M68K_EORI_CCR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2579 case M68K_MOVE_CCR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2580 case M68K_ORI_CCR: |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2581 ret = sprintf(dst, "%s", mnemonics[decoded->op]); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2582 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2583 ret += sprintf(dst + ret, ", %s", special_op); |
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2584 return ret; |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2585 case M68K_MOVE_USP: |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2586 ret = sprintf(dst, "%s", mnemonics[decoded->op]); |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2587 if (decoded->src.addr_mode != MODE_UNUSED) { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2588 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data); |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2589 ret += sprintf(dst + ret, ", USP"); |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2590 } else { |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2591 ret += sprintf(dst + ret, "USP, "); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2592 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data); |
50
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2593 } |
4836d1f3841a
Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents:
46
diff
changeset
|
2594 return ret; |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2595 case M68K_INVALID: |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2596 ret = sprintf(dst, "dc.w $%X", decoded->src.params.immed); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2597 return ret; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2598 #ifdef M68010 |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2599 case M68K_MOVEC: |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2600 ret = sprintf(dst, "%s ", mnemonics[decoded->op]); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2601 if (decoded->src.addr_mode == MODE_UNUSED) { |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2602 ret += sprintf(dst + ret, "%s, ", cr_mnem[decoded->src.params.immed]); |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2603 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data); |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2604 } else { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2605 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data); |
630
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2606 ret += sprintf(dst + ret, ", %s", cr_mnem[decoded->dst.params.immed]); |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2607 } |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2608 return ret; |
47123183c336
Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents:
518
diff
changeset
|
2609 #endif |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2610 default: |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2611 size = decoded->extra.size; |
1627
dc1eab3ec092
Fix cycle count for shift/rotate instructions with a static shift ammount
Michael Pavone <pavone@retrodev.com>
parents:
1463
diff
changeset
|
2612 uint8_t is_quick = decoded->variant == VAR_QUICK && decoded->op != M68K_ASL && decoded->op != M68K_ASR |
dc1eab3ec092
Fix cycle count for shift/rotate instructions with a static shift ammount
Michael Pavone <pavone@retrodev.com>
parents:
1463
diff
changeset
|
2613 && decoded->op != M68K_LSL && decoded->op != M68K_LSR && decoded->op != M68K_ROXR && decoded->op != M68K_ROXL |
dc1eab3ec092
Fix cycle count for shift/rotate instructions with a static shift ammount
Michael Pavone <pavone@retrodev.com>
parents:
1463
diff
changeset
|
2614 && decoded->op != M68K_ROR && decoded->op != M68K_ROL; |
518
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
2615 ret = sprintf(dst, "%s%s%s", |
775802dab98f
Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents:
467
diff
changeset
|
2616 mnemonics[decoded->op], |
1627
dc1eab3ec092
Fix cycle count for shift/rotate instructions with a static shift ammount
Michael Pavone <pavone@retrodev.com>
parents:
1463
diff
changeset
|
2617 is_quick ? "q" : (decoded->variant == VAR_IMMEDIATE ? "i" : ""), |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2618 size == OPSIZE_BYTE ? ".b" : (size == OPSIZE_WORD ? ".w" : (size == OPSIZE_LONG ? ".l" : ""))); |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2619 } |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2620 if (decoded->op == M68K_MOVEM) { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2621 op1len = m68k_disasm_movem_op(&(decoded->src), &(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2622 ret += op1len; |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2623 ret += m68k_disasm_movem_op(&(decoded->dst), &(decoded->src), dst + ret, op1len, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2624 } else { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2625 op1len = m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2626 ret += op1len; |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2627 ret += m68k_disasm_op(&(decoded->dst), dst + ret, op1len, labels, decoded->address, label_fun, data); |
13
168b1a873895
Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents:
12
diff
changeset
|
2628 } |
2
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2629 return ret; |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2630 } |
5df303bf72e6
Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents:
0
diff
changeset
|
2631 |
134 | 2632 int m68k_disasm(m68kinst * decoded, char * dst) |
2633 { | |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2634 return m68k_disasm_ex(decoded, dst, 0, NULL, NULL); |
134 | 2635 } |
2636 | |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2637 int m68k_disasm_labels(m68kinst * decoded, char * dst, format_label_fun label_fun, void * data) |
134 | 2638 { |
634
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2639 if (!label_fun) |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2640 { |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2641 label_fun = m68k_default_label_fun; |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2642 } |
4a6ec64acd79
Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents:
630
diff
changeset
|
2643 return m68k_disasm_ex(decoded, dst, 1, label_fun, data); |
134 | 2644 } |