Mercurial > repos > blastem

annotate 68kinst.c @ 1462:d276ec2fff11

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
More instruction decoder fixes
author Michael Pavone <pavone@retrodev.com>
date Thu, 07 Sep 2017 00:42:28 -0700
parents b81428ef0396
children 63f309cfbef9
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
467
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents: 412
diff changeset
1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents: 412
diff changeset
2 Copyright 2013 Michael Pavone
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3 This file is part of BlastEm.
467
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents: 412
diff changeset
4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents: 412
diff changeset
5 */
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
6 #include "68kinst.h"
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
7 #include <string.h>
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
8 #include <stdio.h>
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
9
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
10 uint32_t sign_extend16(uint32_t val)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
11 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
12 return (val & 0x8000) ? val | 0xFFFF0000 : val;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
13 }
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
14
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
15 uint32_t sign_extend8(uint32_t val)
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
16 {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
17 return (val & 0x80) ? val | 0xFFFFFF00 : val;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
18 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
19
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
20 uint16_t *m68k_decode_op_ex(uint16_t *cur, uint8_t mode, uint8_t reg, uint8_t size, m68k_op_info *dst)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
21 {
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
22 uint16_t ext, tmp;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
23 dst->addr_mode = mode;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
24 switch(mode)
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
25 {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
26 case MODE_REG:
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
27 case MODE_AREG:
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
28 case MODE_AREG_INDIRECT:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
29 case MODE_AREG_POSTINC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
30 case MODE_AREG_PREDEC:
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
31 dst->params.regs.pri = reg;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
32 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
33 case MODE_AREG_DISPLACE:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
34 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
35 dst->params.regs.pri = reg;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
36 dst->params.regs.displacement = sign_extend16(ext);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
37 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
38 case MODE_AREG_INDEX_MEM:
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
39 dst->params.regs.pri = reg;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
40 ext = *(++cur);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
41 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
42 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
43 dst->params.regs.scale = ext >> 9 & 3;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
44 if (ext & 0x100)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
45 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
46 dst->params.regs.disp_sizes = ext >> 4 & 3;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
47 switch (dst->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
48 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
49 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
50 //reserved
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
51 return NULL;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
52 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
53 dst->params.regs.displacement = 0;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
54 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
55 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
56 dst->params.regs.displacement = sign_extend16(*(cur++));
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
57 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
58 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
59 tmp = *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
60 dst->params.regs.displacement = tmp << 16 | *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
61 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
62 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
63 if (ext & 0x3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
64 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
65 //memory indirect
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
66 switch (ext & 0xC4)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
67 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
68 case 0x00:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
69 dst->addr_mode = MODE_AREG_PREINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
70 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
71 case 0x04:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
72 dst->addr_mode = MODE_AREG_POSTINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
73 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
74 case 0x40:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
75 dst->addr_mode = MODE_AREG_MEM_INDIRECT;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
76 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
77 case 0x80:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
78 dst->addr_mode = MODE_PREINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
79 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
80 case 0x84:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
81 dst->addr_mode = MODE_POSTINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
82 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
83 case 0xC0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
84 dst->addr_mode = MODE_MEM_INDIRECT;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
85 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
86 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
87 dst->params.regs.disp_sizes |= ext << 4 & 0x30;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
88 switch (ext & 0x3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
89 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
90 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
91 //reserved
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
92 return NULL;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
93 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
94 dst->params.regs.outer_disp = 0;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
95 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
96 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
97 dst->params.regs.outer_disp = sign_extend16(*(cur++));
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
98 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
99 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
100 tmp = *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
101 dst->params.regs.outer_disp = tmp << 16 | *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
102 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
103 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
104 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
105 switch (ext >> 6 & 3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
106 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
107 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
108 dst->addr_mode = MODE_AREG_INDEX_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
109 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
110 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
111 dst->addr_mode = MODE_AREG_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
112 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
113 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
114 dst->addr_mode = MODE_INDEX_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
115 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
116 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
117 dst->addr_mode = MODE_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
118 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
119 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
120 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
121 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
122 #endif
79
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 69
diff changeset
123 dst->addr_mode = MODE_AREG_INDEX_DISP8;
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 69
diff changeset
124 dst->params.regs.displacement = sign_extend8(ext&0xFF);
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
125 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
126 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
127 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
128 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
129 case MODE_PC_INDIRECT_ABS_IMMED:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
130 switch(reg)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
131 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
132 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
133 dst->addr_mode = MODE_ABSOLUTE_SHORT;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
134 ext = *(++cur);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
135 dst->params.immed = sign_extend16(ext);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
136 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
137 case 1:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
138 dst->addr_mode = MODE_ABSOLUTE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
139 ext = *(++cur);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
140 dst->params.immed = ext << 16 | *(++cur);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
141 break;
79
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 69
diff changeset
142 case 3:
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
143 ext = *(++cur);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
144 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
145 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
146 dst->params.regs.scale = ext >> 9 & 3;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
147 if (ext & 0x100)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
148 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
149 dst->params.regs.disp_sizes = ext >> 4 & 3;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
150 switch (dst->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
151 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
152 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
153 //reserved
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
154 return NULL;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
155 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
156 dst->params.regs.displacement = 0;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
157 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
158 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
159 dst->params.regs.displacement = sign_extend16(*(cur++));
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
160 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
161 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
162 tmp = *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
163 dst->params.regs.displacement = tmp << 16 | *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
164 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
165 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
166 if (ext & 0x3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
167 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
168 //memory indirect
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
169 switch (ext & 0xC4)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
170 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
171 case 0x00:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
172 dst->addr_mode = MODE_PC_PREINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
173 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
174 case 0x04:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
175 dst->addr_mode = MODE_PC_POSTINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
176 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
177 case 0x40:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
178 dst->addr_mode = MODE_PC_MEM_INDIRECT;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
179 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
180 case 0x80:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
181 dst->addr_mode = MODE_ZPC_PREINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
182 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
183 case 0x84:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
184 dst->addr_mode = MODE_ZPC_POSTINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
185 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
186 case 0xC0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
187 dst->addr_mode = MODE_ZPC_MEM_INDIRECT;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
188 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
189 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
190 dst->params.regs.disp_sizes |= ext << 4 & 0x30;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
191 switch (ext & 0x3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
192 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
193 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
194 //reserved
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
195 return NULL;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
196 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
197 dst->params.regs.outer_disp = 0;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
198 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
199 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
200 dst->params.regs.outer_disp = sign_extend16(*(cur++));
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
201 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
202 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
203 tmp = *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
204 dst->params.regs.outer_disp = tmp << 16 | *(cur++);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
205 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
206 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
207 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
208 switch (ext >> 6 & 3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
209 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
210 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
211 dst->addr_mode = MODE_PC_INDEX_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
212 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
213 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
214 dst->addr_mode = MODE_PC_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
215 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
216 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
217 dst->addr_mode = MODE_ZPC_INDEX_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
218 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
219 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
220 dst->addr_mode = MODE_ZPC_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
221 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
222 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
223 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
224 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
225 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
226 dst->addr_mode = MODE_PC_INDEX_DISP8;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
227 dst->params.regs.displacement = sign_extend8(ext&0xFF);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
228 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
229 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
230 #endif
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 94
diff changeset
231 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
232 case 2:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
233 dst->addr_mode = MODE_PC_DISPLACE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
234 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
235 dst->params.regs.displacement = sign_extend16(ext);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
236 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
237 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
238 dst->addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
239 ext = *(++cur);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
240 switch (size)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
241 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
242 case OPSIZE_BYTE:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
243 dst->params.immed = ext & 0xFF;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
244 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
245 case OPSIZE_WORD:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
246 dst->params.immed = ext;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
247 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
248 case OPSIZE_LONG:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
249 dst->params.immed = ext << 16 | *(++cur);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
250 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
251 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
252 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
253 default:
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
254 return NULL;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
255 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
256 break;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
257 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
258 return cur;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
259 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
260
823
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
261 uint8_t m68k_valid_immed_dst(m68k_op_info *dst)
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
262 {
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
263 if (dst->addr_mode == MODE_AREG || dst->addr_mode == MODE_IMMEDIATE) {
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
264 return 0;
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
265 }
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
266 return 1;
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
267 }
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
268
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
269 uint8_t m68k_valid_immed_limited_dst(m68k_op_info *dst)
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
270 {
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
271 if (dst->addr_mode == MODE_AREG || dst->addr_mode > MODE_ABSOLUTE) {
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
272 return 0;
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
273 }
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
274 return 1;
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
275 }
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
276
1462
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
277 uint8_t m68k_valid_full_arith_dst(m68k_op_info *dst)
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
278 {
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
279 if (dst->addr_mode < MODE_AREG_INDIRECT || dst->addr_mode > MODE_ABSOLUTE) {
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
280 return 0;
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
281 }
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
282 return 1;
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
283 }
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
284
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
285 uint8_t m68k_valid_movem_dst(m68k_op_info *dst)
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
286 {
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
287 if (dst->addr_mode == MODE_REG || dst->addr_mode == MODE_AREG_POSTINC) {
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
288 return 0;
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
289 }
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
290 return m68k_valid_immed_limited_dst(dst);
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
291 }
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
292
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
293 uint16_t *m68k_decode_op(uint16_t *cur, uint8_t size, m68k_op_info *dst)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
294 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
295 uint8_t mode = (*cur >> 3) & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
296 uint8_t reg = *cur & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
297 return m68k_decode_op_ex(cur, mode, reg, size, dst);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
298 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
299
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
300 void m68k_decode_cond(uint16_t op, m68kinst * decoded)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
301 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
302 decoded->extra.cond = (op >> 0x8) & 0xF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
303 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
304
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
305 uint8_t m68k_reg_quick_field(uint16_t op)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
306 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
307 return (op >> 9) & 0x7;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
308 }
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
309
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
310 uint16_t * m68k_decode(uint16_t * istream, m68kinst * decoded, uint32_t address)
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
311 {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
312 uint16_t *start = istream;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
313 uint8_t optype = *istream >> 12;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
314 uint8_t size;
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
315 uint8_t reg;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
316 uint8_t opmode;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
317 uint32_t immed;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
318 decoded->op = M68K_INVALID;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
319 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_UNUSED;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
320 decoded->variant = VAR_NORMAL;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
321 decoded->address = address;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
322 switch(optype)
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
323 {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
324 case BIT_MOVEP_IMMED:
163
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
325 if ((*istream & 0x138) == 0x108) {
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
326 //MOVEP
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
327 decoded->op = M68K_MOVEP;
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
328 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD;
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
329 if (*istream & 0x80) {
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
330 //memory dest
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
331 decoded->src.addr_mode = MODE_REG;
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
332 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
333 decoded->dst.addr_mode = MODE_AREG_DISPLACE;
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
334 decoded->dst.params.regs.pri = *istream & 0x7;
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
335 decoded->dst.params.regs.displacement = *(++istream);
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
336 } else {
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
337 //memory source
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
338 decoded->dst.addr_mode = MODE_REG;
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
339 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
340 decoded->src.addr_mode = MODE_AREG_DISPLACE;
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
341 decoded->src.params.regs.pri = *istream & 0x7;
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
342 decoded->src.params.regs.displacement = *(++istream);
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
343 }
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
344 } else if (*istream & 0x100) {
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
345 //BTST, BCHG, BCLR, BSET
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
346 switch ((*istream >> 6) & 0x3)
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
347 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
348 case 0:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
349 decoded->op = M68K_BTST;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
350 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
351 case 1:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
352 decoded->op = M68K_BCHG;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
353 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
354 case 2:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
355 decoded->op = M68K_BCLR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
356 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
357 case 3:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
358 decoded->op = M68K_BSET;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
359 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
360 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
361 decoded->src.addr_mode = MODE_REG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
362 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
363 decoded->extra.size = OPSIZE_BYTE;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
364 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst));
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
365 if (
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
366 !istream || decoded->dst.addr_mode == MODE_AREG
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
367 || (decoded->op != M68K_BTST && !m68k_valid_immed_limited_dst(&decoded->dst))
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
368 ) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
369 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
370 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
371 }
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
372 if (decoded->dst.addr_mode == MODE_REG) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
373 decoded->extra.size = OPSIZE_LONG;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
374 }
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
375 } else if ((*istream & 0xF00) == 0x800) {
12
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
376 //BTST, BCHG, BCLR, BSET
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
377 switch ((*istream >> 6) & 0x3)
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
378 {
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
379 case 0:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
380 decoded->op = M68K_BTST;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
381 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
382 case 1:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
383 decoded->op = M68K_BCHG;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
384 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
385 case 2:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
386 decoded->op = M68K_BCLR;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
387 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
388 case 3:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
389 decoded->op = M68K_BSET;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
390 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
391 }
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
392 opmode = (*istream >> 3) & 0x7;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
393 reg = *istream & 0x7;
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
394 decoded->src.addr_mode = MODE_IMMEDIATE_WORD;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
395 decoded->src.params.immed = *(++istream) & 0xFF;
12
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
396 decoded->extra.size = OPSIZE_BYTE;
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
397 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst));
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
398 if (!istream || !m68k_valid_immed_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
399 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
400 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
401 }
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
402 if (decoded->dst.addr_mode == MODE_REG) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
403 decoded->extra.size = OPSIZE_LONG;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
404 }
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
405 } else if ((*istream & 0xC0) == 0xC0) {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
406 #ifdef M68020
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
407 //CMP2, CHK2, CAS, CAS2, RTM, CALLM
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
408 #endif
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
409 } else {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
410 switch ((*istream >> 9) & 0x7)
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
411 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
412 case 0:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
413 if ((*istream & 0xFF) == 0x3C) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
414 decoded->op = M68K_ORI_CCR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
415 decoded->extra.size = OPSIZE_BYTE;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
416 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
417 decoded->src.params.immed = *(++istream) & 0xFF;
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
418 } else if((*istream & 0xFF) == 0x7C) {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
419 decoded->op = M68K_ORI_SR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
420 decoded->extra.size = OPSIZE_WORD;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
421 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
422 decoded->src.params.immed = *(++istream);
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
423 } else {
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
424 decoded->op = M68K_OR;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
425 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
426 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
427 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
428 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
429 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
430 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
431 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
432 case OPSIZE_BYTE:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
433 decoded->src.params.immed = *(++istream) & 0xFF;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
434 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
435 case OPSIZE_WORD:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
436 decoded->src.params.immed = *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
437 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
438 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
439 immed = *(++istream);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
440 decoded->src.params.immed = immed << 16 | *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
441 break;
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
442 }
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
443 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
823
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
444 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
445 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
446 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
447 }
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
448 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
449 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
450 case 1:
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
451 //ANDI, ANDI to CCR, ANDI to SR
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
452 if ((*istream & 0xFF) == 0x3C) {
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
453 decoded->op = M68K_ANDI_CCR;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
454 decoded->extra.size = OPSIZE_BYTE;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
455 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
456 decoded->src.params.immed = *(++istream) & 0xFF;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
457 } else if((*istream & 0xFF) == 0x7C) {
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
458 decoded->op = M68K_ANDI_SR;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
459 decoded->extra.size = OPSIZE_WORD;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
460 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
461 decoded->src.params.immed = *(++istream);
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
462 } else {
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
463 decoded->op = M68K_AND;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
464 decoded->variant = VAR_IMMEDIATE;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
465 decoded->src.addr_mode = MODE_IMMEDIATE;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
466 decoded->extra.size = size = (*istream >> 6) & 3;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
467 reg = *istream & 0x7;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
468 opmode = (*istream >> 3) & 0x7;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
469 switch (size)
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
470 {
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
471 case OPSIZE_BYTE:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
472 decoded->src.params.immed = *(++istream) & 0xFF;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
473 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
474 case OPSIZE_WORD:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
475 decoded->src.params.immed = *(++istream);
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
476 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
477 case OPSIZE_LONG:
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
478 immed = *(++istream);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
479 decoded->src.params.immed = immed << 16 | *(++istream);
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
480 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
481 }
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
482 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
823
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
483 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
484 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
485 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
486 }
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
487 }
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
488 break;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
489 case 2:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
490 decoded->op = M68K_SUB;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
491 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
492 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
493 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
494 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
495 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
496 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
497 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
498 case OPSIZE_BYTE:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
499 decoded->src.params.immed = *(++istream) & 0xFF;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
500 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
501 case OPSIZE_WORD:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
502 decoded->src.params.immed = *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
503 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
504 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
505 immed = *(++istream);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
506 decoded->src.params.immed = immed << 16 | *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
507 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
508 }
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
509 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
823
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
510 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
511 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
512 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
513 }
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
514 break;
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
515 case 3:
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
516 decoded->op = M68K_ADD;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
517 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
518 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
519 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
520 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
521 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
522 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
523 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
524 case OPSIZE_BYTE:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
525 decoded->src.params.immed = *(++istream) & 0xFF;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
526 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
527 case OPSIZE_WORD:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
528 decoded->src.params.immed = *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
529 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
530 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
531 immed = *(++istream);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
532 decoded->src.params.immed = immed << 16 | *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
533 break;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
534 }
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
535 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
823
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
536 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
537 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
538 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
539 }
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
540 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
541 case 4:
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
542 //BTST, BCHG, BCLR, BSET
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
543 //Seems like this should be unnecessary since bit instructions are explicitly handled above
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
544 //Possible this is redundant or the case above is overly restrictive
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
545 //TODO: Investigate whether this can be removed
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
546 switch ((*istream >> 6) & 0x3)
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
547 {
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
548 case 0:
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
549 decoded->op = M68K_BTST;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
550 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
551 case 1:
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
552 decoded->op = M68K_BCHG;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
553 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
554 case 2:
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
555 decoded->op = M68K_BCLR;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
556 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
557 case 3:
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
558 decoded->op = M68K_BSET;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
559 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
560 }
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
561 decoded->src.addr_mode = MODE_IMMEDIATE_WORD;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
562 decoded->src.params.immed = *(++istream) & 0xFF;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
563 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
564 if (
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
565 !istream || !m68k_valid_immed_dst(&decoded->dst)
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
566 || (decoded->op != M68K_BTST && !m68k_valid_immed_limited_dst(&decoded->dst))
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
567 ) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
568 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
569 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
570 }
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
571 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
572 case 5:
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
573 //EORI, EORI to CCR, EORI to SR
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
574 if ((*istream & 0xFF) == 0x3C) {
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
575 decoded->op = M68K_EORI_CCR;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
576 decoded->extra.size = OPSIZE_BYTE;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
577 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
578 decoded->src.params.immed = *(++istream) & 0xFF;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
579 } else if((*istream & 0xFF) == 0x7C) {
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
580 decoded->op = M68K_EORI_SR;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
581 decoded->extra.size = OPSIZE_WORD;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
582 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
583 decoded->src.params.immed = *(++istream);
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
584 } else {
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
585 decoded->op = M68K_EOR;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
586 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
587 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
588 decoded->extra.size = size = (*istream >> 6) & 3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
589 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
590 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
591 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
592 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
593 case OPSIZE_BYTE:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
594 decoded->src.params.immed = *(++istream) & 0xFF;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
595 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
596 case OPSIZE_WORD:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
597 decoded->src.params.immed = *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
598 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
599 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
600 immed = *(++istream);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
601 decoded->src.params.immed = immed << 16 | *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
602 break;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
603 }
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
604 istream = m68k_decode_op_ex(istream, opmode, reg, size, &(decoded->dst));
823
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
605 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
606 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
607 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
608 }
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
609 }
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
610 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
611 case 6:
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
612 decoded->op = M68K_CMP;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
613 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
614 decoded->extra.size = (*istream >> 6) & 0x3;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
615 decoded->src.addr_mode = MODE_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
616 reg = *istream & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
617 opmode = (*istream >> 3) & 0x7;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
618 switch (decoded->extra.size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
619 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
620 case OPSIZE_BYTE:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
621 decoded->src.params.immed = *(++istream) & 0xFF;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
622 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
623 case OPSIZE_WORD:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
624 decoded->src.params.immed = *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
625 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
626 case OPSIZE_LONG:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
627 immed = *(++istream);
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
628 decoded->src.params.immed = (immed << 16) | *(++istream);
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
629 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
630 }
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
631 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst));
823
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
632 if (!istream || !m68k_valid_immed_dst(&(decoded->dst))) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
633 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
634 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
635 }
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
636 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
637 case 7:
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
638 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
639 decoded->op = M68K_MOVES;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
640 decoded->extra.size = *istream >> 6 & 0x3;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
641 immed = *(++istream);
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
642 reg = immed >> 12 & 0x7;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
643 opmode = immed & 0x8000 ? MODE_AREG : MODE_REG;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
644 if (immed & 0x800) {
642
08d0e3e7d0d8 Fix interpretation of moves direction field
Michael Pavone <pavone@retrodev.com>
parents: 641
diff changeset
645 decoded->src.addr_mode = opmode;
08d0e3e7d0d8 Fix interpretation of moves direction field
Michael Pavone <pavone@retrodev.com>
parents: 641
diff changeset
646 decoded->src.params.regs.pri = reg;
08d0e3e7d0d8 Fix interpretation of moves direction field
Michael Pavone <pavone@retrodev.com>
parents: 641
diff changeset
647 m68k_decode_op_ex(istream, *start >> 3 & 0x7, *start & 0x7, decoded->extra.size, &(decoded->dst));
08d0e3e7d0d8 Fix interpretation of moves direction field
Michael Pavone <pavone@retrodev.com>
parents: 641
diff changeset
648 } else {
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
649 m68k_decode_op_ex(istream, *start >> 3 & 0x7, *start & 0x7, decoded->extra.size, &(decoded->src));
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
650 decoded->dst.addr_mode = opmode;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
651 decoded->dst.params.regs.pri = reg;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
652 }
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
653 #endif
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
654 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
655 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
656 }
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
657 break;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
658 case MOVE_BYTE:
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
659 case MOVE_LONG:
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
660 case MOVE_WORD:
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
661 decoded->op = M68K_MOVE;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
662 decoded->extra.size = optype == MOVE_BYTE ? OPSIZE_BYTE : (optype == MOVE_WORD ? OPSIZE_WORD : OPSIZE_LONG);
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
663 opmode = (*istream >> 6) & 0x7;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
664 reg = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
665 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
1462
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
666 if (!istream || (decoded->src.addr_mode == MODE_AREG && optype == MOVE_BYTE)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
667 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
668 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
669 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
670 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst));
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
671 if (!istream || decoded->dst.addr_mode > MODE_ABSOLUTE || (decoded->dst.addr_mode == MODE_AREG && optype == MOVE_BYTE)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
672 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
673 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
674 }
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
675 break;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
676 case MISC:
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
677
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
678 if ((*istream & 0x1C0) == 0x1C0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
679 decoded->op = M68K_LEA;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
680 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
681 decoded->dst.addr_mode = MODE_AREG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
682 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
683 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
1277
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
684 if (
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
685 !istream || decoded->src.addr_mode == MODE_REG || decoded->src.addr_mode == MODE_AREG
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
686 || decoded->src.addr_mode == MODE_AREG_POSTINC || decoded->src.addr_mode == MODE_AREG_PREDEC
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
687 || decoded->src.addr_mode == MODE_IMMEDIATE
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
688 ) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
689 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
690 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
691 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
692 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
693 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
694 decoded->op = M68K_CHK;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
695 if ((*istream & 0x180) == 0x180) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
696 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
697 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
698 //only on M68020+
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
699 #ifdef M68020
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
700 decoded->extra.size = OPSIZE_LONG;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
701 #else
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
702 decoded->op = M68K_INVALID;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
703 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
704 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
705 }
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
706 decoded->dst.addr_mode = MODE_REG;
325
8db584faac4b Fixed decoding of CHK destination
Mike Pavone <pavone@retrodev.com>
parents: 208
diff changeset
707 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
708 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
709 if (!istream || decoded->src.addr_mode == MODE_AREG) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
710 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
711 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
712 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
713 } else {
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
714 opmode = (*istream >> 3) & 0x7;
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
715 if ((*istream & 0xB80) == 0x880 && opmode != MODE_REG && opmode != MODE_AREG) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
716 //TODO: Check for invalid modes that are dependent on direction
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
717 decoded->op = M68K_MOVEM;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
718 decoded->extra.size = *istream & 0x40 ? OPSIZE_LONG : OPSIZE_WORD;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
719 reg = *istream & 0x7;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
720 if(*istream & 0x400) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
721 decoded->dst.addr_mode = MODE_REG;
68
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
722 decoded->dst.params.immed = *(++istream);
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
723 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->src));
1253
2a6049dddab0 immediate and predecrement are illegal source address modes for movem. Fixes ticket:8 and ticket:9
Michael Pavone <pavone@retrodev.com>
parents: 1226
diff changeset
724 if (!istream || decoded->src.addr_mode == MODE_AREG_PREDEC || decoded->src.addr_mode == MODE_IMMEDIATE) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
725 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
726 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
727 }
412
00d5a2b532f4 Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
728 if (decoded->src.addr_mode == MODE_PC_DISPLACE || decoded->src.addr_mode == MODE_PC_INDEX_DISP8) {
00d5a2b532f4 Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
729 //adjust displacement to account for extra instruction word
00d5a2b532f4 Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
730 decoded->src.params.regs.displacement += 2;
00d5a2b532f4 Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
731 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
732 } else {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
733 decoded->src.addr_mode = MODE_REG;
68
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
734 decoded->src.params.immed = *(++istream);
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
735 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, &(decoded->dst));
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
736 if (!istream || !m68k_valid_movem_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
737 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
738 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
739 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
740 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
741 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
742 optype = (*istream >> 9) & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
743 size = (*istream >> 6) & 0x3;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
744 switch(optype)
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
745 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
746 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
747 //Move from SR or NEGX
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
748 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
749 decoded->op = M68K_MOVE_FROM_SR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
750 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
751 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
752 decoded->op = M68K_NEGX;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
753 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
754 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
755 istream= m68k_decode_op(istream, size, &(decoded->dst));
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
756 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
757 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
758 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
759 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
760 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
761 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
762 //MOVE from CCR or CLR
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
763 if (size == OPSIZE_INVALID) {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
764 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
765 decoded->op = M68K_MOVE_FROM_CCR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
766 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
767 #else
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
768 break;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
769 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
770 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
771 decoded->op = M68K_CLR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
772 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
773 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
774 istream= m68k_decode_op(istream, size, &(decoded->dst));
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
775 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
776 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
777 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
778 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
779 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
780 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
781 //MOVE to CCR or NEG
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
782 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
783 decoded->op = M68K_MOVE_CCR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
784 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
785 istream= m68k_decode_op(istream, size, &(decoded->src));
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
786 if (!istream || decoded->src.addr_mode == MODE_AREG) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
787 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
788 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
789 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
790 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
791 decoded->op = M68K_NEG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
792 istream= m68k_decode_op(istream, size, &(decoded->dst));
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
793 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
794 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
795 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
796 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
797 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
798 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
799 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
800 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
801 //MOVE to SR or NOT
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
802 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
803 decoded->op = M68K_MOVE_SR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
804 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
805 istream= m68k_decode_op(istream, size, &(decoded->src));
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
806 if (!istream || decoded->src.addr_mode == MODE_AREG) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
807 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
808 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
809 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
810 } else {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
811 decoded->op = M68K_NOT;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
812 istream= m68k_decode_op(istream, size, &(decoded->dst));
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
813 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
814 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
815 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
816 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
817 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
818 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
819 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
820 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
821 //EXT, EXTB, LINK.l, NBCD, SWAP, BKPT, PEA
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
822 switch((*istream >> 3) & 0x3F)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
823 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
824 case 1:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
825 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
826 decoded->op = M68K_LINK;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
827 decoded->extra.size = OPSIZE_LONG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
828 reg = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
829 immed = *(++istream) << 16;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
830 immed |= *(++istream);
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
831 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
832 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
833 case 8:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
834 decoded->op = M68K_SWAP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
835 decoded->src.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
836 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
837 decoded->extra.size = OPSIZE_WORD;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
838 break;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
839 case 9:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
840 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
841 decoded->op = M68K_BKPT;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
842 decoded->src.addr_mode = MODE_IMMEDIATE;
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
843 decoded->extra.size = OPSIZE_UNSIZED;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
844 decoded->src.params.immed = *istream & 0x7;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
845 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
846 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
847 case 0x10:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
848 decoded->op = M68K_EXT;
93
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 91
diff changeset
849 decoded->dst.addr_mode = MODE_REG;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 91
diff changeset
850 decoded->dst.params.regs.pri = *istream & 0x7;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
851 decoded->extra.size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
852 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
853 case 0x18:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
854 decoded->op = M68K_EXT;
93
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 91
diff changeset
855 decoded->dst.addr_mode = MODE_REG;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 91
diff changeset
856 decoded->dst.params.regs.pri = *istream & 0x7;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
857 decoded->extra.size = OPSIZE_LONG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
858 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
859 case 0x38:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
860 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
861 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
862 break;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
863 default:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
864 if (!(*istream & 0x1C0)) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
865 decoded->op = M68K_NBCD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
866 decoded->extra.size = OPSIZE_BYTE;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
867 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
868 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
869 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
870 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
871 }
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
872 } else if((*istream & 0x1C0) == 0x40) {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
873 decoded->op = M68K_PEA;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
874 decoded->extra.size = OPSIZE_LONG;
116
9eaba47c429d Implement pea (untested).
Mike Pavone <pavone@retrodev.com>
parents: 111
diff changeset
875 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
1277
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
876 if (
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
877 !istream || decoded->src.addr_mode == MODE_REG || decoded->src.addr_mode == MODE_AREG
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
878 || decoded->src.addr_mode == MODE_AREG_POSTINC || decoded->src.addr_mode == MODE_AREG_PREDEC
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
879 || decoded->src.addr_mode == MODE_IMMEDIATE
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
880 ) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
881 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
882 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
883 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
884 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
885 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
886 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
887 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
888 //BGND, ILLEGAL, TAS, TST
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
889 optype = *istream & 0xFF;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
890 if (optype == 0xFA) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
891 //BGND - CPU32 only
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
892 } else if (optype == 0xFC) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
893 decoded->op = M68K_ILLEGAL;
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
894 decoded->extra.size = OPSIZE_UNSIZED;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
895 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
896 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
897 decoded->op = M68K_TAS;
835
b4cf6573a3f8 Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents: 823
diff changeset
898 decoded->extra.size = OPSIZE_BYTE;
b4cf6573a3f8 Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents: 823
diff changeset
899 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst));
b4cf6573a3f8 Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents: 823
diff changeset
900 if (!istream) {
b4cf6573a3f8 Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents: 823
diff changeset
901 decoded->op = M68K_INVALID;
b4cf6573a3f8 Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents: 823
diff changeset
902 break;
b4cf6573a3f8 Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents: 823
diff changeset
903 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
904 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
905 decoded->op = M68K_TST;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
906 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
907 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
908 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
909 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
910 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
911 }
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
912 #ifndef M68020
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
913 if (!m68k_valid_immed_limited_dst(&decoded->src)) {
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
914 decoded->op = M68K_INVALID;
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
915 break;
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
916 }
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
917 #endif
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
918 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
919 }
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
920 break;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
921 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
922 //MULU, MULS, DIVU, DIVUL, DIVS, DIVSL
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
923 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
924 //TODO: Implement these for 68020+ support
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
925 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
926 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
927 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
928 //TRAP, LINK.w, UNLNK, MOVE USP, RESET, NOP, STOP, RTE, RTD, RTS, TRAPV, RTR, MOVEC, JSR, JMP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
929 if (*istream & 0x80) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
930 //JSR, JMP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
931 if (*istream & 0x40) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
932 decoded->op = M68K_JMP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
933 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
934 decoded->op = M68K_JSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
935 }
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
936 decoded->extra.size = OPSIZE_UNSIZED;
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
937 istream = m68k_decode_op(istream, OPSIZE_UNSIZED, &(decoded->src));
1345
696a029d09e9 Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents: 1330
diff changeset
938 if (
696a029d09e9 Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents: 1330
diff changeset
939 !istream
696a029d09e9 Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents: 1330
diff changeset
940 || (decoded->src.addr_mode < MODE_AREG_DISPLACE && decoded->src.addr_mode != MODE_AREG_INDIRECT)
696a029d09e9 Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents: 1330
diff changeset
941 || decoded->src.addr_mode == MODE_IMMEDIATE
696a029d09e9 Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents: 1330
diff changeset
942 ) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
943 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
944 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
945 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
946 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
947 //it would appear bit 6 needs to be set for it to be a valid instruction here
1462
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
948 if (!(*istream & 0x40)) {
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
949 decoded->op = M68K_INVALID;
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
950 break;
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
951 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
952 switch((*istream >> 3) & 0x7)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
953 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
954 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
955 case 1:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
956 //TRAP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
957 decoded->op = M68K_TRAP;
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
958 decoded->extra.size = OPSIZE_UNSIZED;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
959 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
960 decoded->src.params.immed = *istream & 0xF;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
961 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
962 case 2:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
963 //LINK.w
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
964 decoded->op = M68K_LINK;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
965 decoded->extra.size = OPSIZE_WORD;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
966 decoded->src.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
967 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
968 decoded->dst.addr_mode = MODE_IMMEDIATE;
93
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 91
diff changeset
969 decoded->dst.params.immed = sign_extend16(*(++istream));
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
970 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
971 case 3:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
972 //UNLK
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
973 decoded->op = M68K_UNLK;
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
974 decoded->extra.size = OPSIZE_UNSIZED;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
975 decoded->dst.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
976 decoded->dst.params.regs.pri = *istream & 0x7;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
977 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
978 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
979 case 5:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
980 //MOVE USP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
981 decoded->op = M68K_MOVE_USP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
982 if (*istream & 0x8) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
983 decoded->dst.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
984 decoded->dst.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
985 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
986 decoded->src.addr_mode = MODE_AREG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
987 decoded->src.params.regs.pri = *istream & 0x7;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
988 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
989 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
990 case 6:
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
991 decoded->extra.size = OPSIZE_UNSIZED;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
992 switch(*istream & 0x7)
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
993 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
994 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
995 decoded->op = M68K_RESET;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
996 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
997 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
998 decoded->op = M68K_NOP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
999 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1000 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1001 decoded->op = M68K_STOP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1002 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
1003 decoded->src.params.immed =*(++istream);
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1004 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1005 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1006 decoded->op = M68K_RTE;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1007 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1008 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1009 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1010 decoded->op = M68K_RTD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1011 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
1012 decoded->src.params.immed =*(++istream);
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1013 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1014 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1015 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1016 decoded->op = M68K_RTS;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1017 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1018 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1019 decoded->op = M68K_TRAPV;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1020 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1021 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1022 decoded->op = M68K_RTR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1023 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1024 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1025 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1026 case 7:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1027 //MOVEC
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1028 #ifdef M68010
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1029 decoded->op = M68K_MOVEC;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1030 immed = *(++istream);
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1031 reg = immed >> 12 & 0x7;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1032 opmode = immed & 0x8000 ? MODE_AREG : MODE_REG;
641
66857bd2df0b Fix decoding of movec
Michael Pavone <pavone@retrodev.com>
parents: 638
diff changeset
1033 immed &= 0xFFF;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1034 if (immed & 0x800) {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1035 if (immed > MAX_HIGH_CR) {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1036 decoded->op = M68K_INVALID;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1037 break;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1038 } else {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1039 immed = immed - 0x800 + CR_USP;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1040 }
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1041 } else {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1042 if (immed > MAX_LOW_CR) {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1043 decoded->op = M68K_INVALID;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1044 break;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1045 }
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1046 }
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1047 if (*start & 1) {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1048 decoded->src.addr_mode = opmode;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1049 decoded->src.params.regs.pri = reg;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1050 decoded->dst.params.immed = immed;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1051 } else {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1052 decoded->dst.addr_mode = opmode;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1053 decoded->dst.params.regs.pri = reg;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1054 decoded->src.params.immed = immed;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1055 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1056 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1057 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1058 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1059 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1060 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1061 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1062 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1063 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1064 }
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1065 break;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1066 case QUICK_ARITH_LOOP:
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1067 size = (*istream >> 6) & 3;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1068 if (size == 0x3) {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1069 //DBcc, TRAPcc or Scc
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1070 m68k_decode_cond(*istream, decoded);
111
8b50d2c975b2 Fix decoding of Scc
Mike Pavone <pavone@retrodev.com>
parents: 101
diff changeset
1071 if (((*istream >> 3) & 0x7) == 1) {
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1072 decoded->op = M68K_DBCC;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1073 decoded->src.addr_mode = MODE_IMMEDIATE;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1074 decoded->dst.addr_mode = MODE_REG;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1075 decoded->dst.params.regs.pri = *istream & 0x7;
46
f2aaaf36c875 Add support for dbcc instruction
Mike Pavone <pavone@retrodev.com>
parents: 18
diff changeset
1076 decoded->src.params.immed = sign_extend16(*(++istream));
111
8b50d2c975b2 Fix decoding of Scc
Mike Pavone <pavone@retrodev.com>
parents: 101
diff changeset
1077 } else if(((*istream >> 3) & 0x7) == 1 && (*istream & 0x7) > 1 && (*istream & 0x7) < 5) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1078 #ifdef M68020
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1079 decoded->op = M68K_TRAPCC;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1080 decoded->src.addr_mode = MODE_IMMEDIATE;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1081 //TODO: Figure out what to do with OPMODE and optional extention words
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1082 #endif
111
8b50d2c975b2 Fix decoding of Scc
Mike Pavone <pavone@retrodev.com>
parents: 101
diff changeset
1083 } else {
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1084 decoded->op = M68K_SCC;
111
8b50d2c975b2 Fix decoding of Scc
Mike Pavone <pavone@retrodev.com>
parents: 101
diff changeset
1085 decoded->extra.cond = (*istream >> 8) & 0xF;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1086 istream = m68k_decode_op(istream, OPSIZE_BYTE, &(decoded->dst));
1462
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
1087 if (!istream || !m68k_valid_immed_limited_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1088 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1089 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1090 }
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1091 }
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1092 } else {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1093 //ADDQ, SUBQ
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1094 decoded->variant = VAR_QUICK;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1095 decoded->extra.size = size;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1096 decoded->src.addr_mode = MODE_IMMEDIATE;
91
8c446fc19cc0 Fix decoding bug in addq/subq
Mike Pavone <pavone@retrodev.com>
parents: 90
diff changeset
1097 immed = m68k_reg_quick_field(*istream);
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1098 if (!immed) {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1099 immed = 8;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1100 }
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
1101 decoded->src.params.immed = immed;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1102 if (*istream & 0x100) {
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1103 decoded->op = M68K_SUB;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1104 } else {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1105 decoded->op = M68K_ADD;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1106 }
94
a668a35a3463 Fix decoding bug for addq/subq
Mike Pavone <pavone@retrodev.com>
parents: 93
diff changeset
1107 istream = m68k_decode_op(istream, size, &(decoded->dst));
1462
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
1108 if (!istream || decoded->dst.addr_mode > MODE_ABSOLUTE || (size == OPSIZE_BYTE && decoded->dst.addr_mode == MODE_AREG)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1109 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1110 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1111 }
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1112 }
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1113 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1114 case BRANCH:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1115 m68k_decode_cond(*istream, decoded);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1116 decoded->op = decoded->extra.cond == COND_FALSE ? M68K_BSR : M68K_BCC;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1117 decoded->src.addr_mode = MODE_IMMEDIATE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1118 immed = *istream & 0xFF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1119 if (immed == 0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1120 decoded->variant = VAR_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1121 immed = *(++istream);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1122 immed = sign_extend16(immed);
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 140
diff changeset
1123 #ifdef M68020
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1124 } else if (immed == 0xFF) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1125 decoded->variant = VAR_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1126 immed = *(++istream) << 16;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1127 immed |= *(++istream);
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 140
diff changeset
1128 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1129 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1130 decoded->variant = VAR_BYTE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1131 immed = sign_extend8(immed);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1132 }
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
1133 decoded->src.params.immed = immed;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1134 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1135 case MOVEQ:
208
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 197
diff changeset
1136 if (*istream & 0x100) {
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 197
diff changeset
1137 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1138 break;
208
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 197
diff changeset
1139 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1140 decoded->op = M68K_MOVE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1141 decoded->variant = VAR_QUICK;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
1142 decoded->extra.size = OPSIZE_LONG;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1143 decoded->src.addr_mode = MODE_IMMEDIATE;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
1144 decoded->src.params.immed = sign_extend8(*istream & 0xFF);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1145 decoded->dst.addr_mode = MODE_REG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1146 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1147 immed = *istream & 0xFF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1148 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1149 case OR_DIV_SBCD:
11
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1150 //for OR, if opmode bit 2 is 1, then src = Dn, dst = <ea>
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1151 opmode = (*istream >> 6) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1152 size = opmode & 0x3;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1153 if (size == OPSIZE_INVALID || (opmode & 0x4 && !(*istream & 0x30))) {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1154 switch(opmode)
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1155 {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1156 case 3:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1157 decoded->op = M68K_DIVU;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1158 decoded->extra.size = OPSIZE_WORD;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1159 decoded->dst.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1160 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1161 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
183
2f08d9e90a4c Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
1162 if (!istream || decoded->src.addr_mode == MODE_AREG) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1163 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1164 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1165 }
11
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1166 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1167 case 4:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1168 decoded->op = M68K_SBCD;
613
09d5adf8d1ca Fix opsize for sbcd in 68K instruction decoder. This fixes the timer bug in Strider 2
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1169 decoded->extra.size = OPSIZE_BYTE;
11
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1170 decoded->dst.addr_mode = decoded->src.addr_mode = *istream & 0x8 ? MODE_AREG_PREDEC : MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1171 decoded->src.params.regs.pri = *istream & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1172 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1173 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1174 case 5:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1175 #ifdef M68020
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1176 #endif
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1177 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1178 case 6:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1179 #ifdef M68020
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1180 #endif
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1181 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1182 case 7:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1183 decoded->op = M68K_DIVS;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1184 decoded->extra.size = OPSIZE_WORD;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1185 decoded->dst.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1186 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1187 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
183
2f08d9e90a4c Fix (a7)+ src when size is byte, fix trap return address, make div with areg src decoded to invalid
Mike Pavone <pavone@retrodev.com>
parents: 181
diff changeset
1188 if (!istream || decoded->src.addr_mode == MODE_AREG) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1189 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1190 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1191 }
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1192 break;
11
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1193 }
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1194 } else {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1195 decoded->op = M68K_OR;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1196 decoded->extra.size = size;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1197 if (opmode & 0x4) {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1198 decoded->src.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1199 decoded->src.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1200 istream = m68k_decode_op(istream, size, &(decoded->dst));
1218
054472ea077a Properly treat bad addressing modes in OR/AND as illegal instructions
Michael Pavone <pavone@retrodev.com>
parents: 992
diff changeset
1201 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1202 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1203 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1204 }
11
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1205 } else {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1206 decoded->dst.addr_mode = MODE_REG;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1207 decoded->dst.params.regs.pri = (*istream >> 9) & 0x7;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1208 istream = m68k_decode_op(istream, size, &(decoded->src));
1218
054472ea077a Properly treat bad addressing modes in OR/AND as illegal instructions
Michael Pavone <pavone@retrodev.com>
parents: 992
diff changeset
1209 if (!istream || decoded->src.addr_mode == MODE_AREG) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1210 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1211 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1212 }
11
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1213 }
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1214 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1215 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1216 case SUB_SUBX:
101
d7789186ba5e Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
1217 size = (*istream >> 6) & 0x3;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1218 decoded->op = M68K_SUB;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1219 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1220 //<ea> destination, SUBA.l or SUBX
101
d7789186ba5e Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
1221 if (*istream & 0x30 || size == OPSIZE_INVALID) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1222 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1223 //SUBA.l
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1224 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1225 decoded->dst.addr_mode = MODE_AREG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1226 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1227 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1228 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1229 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1230 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1231 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1232 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1233 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1234 decoded->src.addr_mode = MODE_REG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1235 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1236 istream = m68k_decode_op(istream, size, &(decoded->dst));
1462
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
1237 if (!istream || !m68k_valid_full_arith_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1238 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1239 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1240 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1241 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1242 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1243 //SUBX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1244 decoded->op = M68K_SUBX;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1245 decoded->extra.size = size;
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1246 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1247 decoded->src.params.regs.pri = *istream & 0x7;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1248 if (*istream & 0x8) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1249 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_AREG_PREDEC;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1250 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1251 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_REG;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1252 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1253 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1254 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1255 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1256 //SUBA.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1257 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1258 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1259 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1260 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1261 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1262 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1263 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1264 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
1462
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
1265 if (!istream || (decoded->src.addr_mode == MODE_AREG && decoded->extra.size == OPSIZE_BYTE)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1266 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1267 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1268 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1269 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1270 break;
992
261995d06897 Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
1271 case A_LINE:
261995d06897 Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
1272 decoded->op = M68K_A_LINE_TRAP;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1273 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1274 case CMP_XOR:
120
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1275 size = (*istream >> 6) & 0x3;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1276 decoded->op = M68K_CMP;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1277 if (*istream & 0x100) {
120
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1278 //CMPM or CMPA.l or EOR
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1279 if (size == OPSIZE_INVALID) {
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1280 decoded->extra.size = OPSIZE_LONG;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1281 decoded->dst.addr_mode = MODE_AREG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1282 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
136
e64554246d11 Fix some bugs in decoding cmp
Mike Pavone <pavone@retrodev.com>
parents: 134
diff changeset
1283 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1284 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1285 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1286 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1287 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1288 } else {
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1289 reg = m68k_reg_quick_field(*istream);
120
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1290 istream = m68k_decode_op(istream, size, &(decoded->dst));
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1291 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1292 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1293 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1294 }
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
1295 decoded->extra.size = size;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
1296 if (decoded->dst.addr_mode == MODE_AREG) {
120
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1297 //CMPM
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1298 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG_POSTINC;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1299 decoded->src.params.regs.pri = decoded->dst.params.regs.pri;
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1300 decoded->dst.params.regs.pri = reg;
1462
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
1301 } else if (!m68k_valid_immed_limited_dst(&decoded->dst)){
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
1302 decoded->op = M68K_INVALID;
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
1303 break;
120
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1304 } else {
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1305 //EOR
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1306 decoded->op = M68K_EOR;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1307 decoded->src.addr_mode = MODE_REG;
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1308 decoded->src.params.regs.pri = reg;
120
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1309 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1310 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1311 } else {
120
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1312 //CMP or CMPA.w
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1313 if (size == OPSIZE_INVALID) {
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1314 decoded->extra.size = OPSIZE_WORD;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1315 decoded->dst.addr_mode = MODE_AREG;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1316 } else {
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1317 decoded->extra.size = size;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1318 decoded->dst.addr_mode = MODE_REG;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1319 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1320 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
136
e64554246d11 Fix some bugs in decoding cmp
Mike Pavone <pavone@retrodev.com>
parents: 134
diff changeset
1321 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1322 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1323 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1324 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1325 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1326 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1327 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1328 case AND_MUL_ABCD_EXG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1329 //page 575 for summary
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1330 //EXG opmodes:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1331 //01000 -data regs
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1332 //01001 -addr regs
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1333 //10001 -one of each
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1334 //AND opmodes:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1335 //operand order bit + 2 size bits (00 - 10)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1336 //no address register direct addressing
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1337 //data register direct not allowed when <ea> is the source (operand order bit of 1)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1338 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1339 if ((*istream & 0xC0) == 0xC0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1340 decoded->op = M68K_MULS;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1341 decoded->extra.size = OPSIZE_WORD;
3
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents: 2
diff changeset
1342 decoded->dst.addr_mode = MODE_REG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1343 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1344 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1345 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1346 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1347 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1348 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1349 } else if(!(*istream & 0xF0)) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1350 decoded->op = M68K_ABCD;
3
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents: 2
diff changeset
1351 decoded->extra.size = OPSIZE_BYTE;
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents: 2
diff changeset
1352 decoded->src.params.regs.pri = *istream & 0x7;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1353 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
3
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents: 2
diff changeset
1354 decoded->dst.addr_mode = decoded->src.addr_mode = (*istream & 8) ? MODE_AREG_PREDEC : MODE_REG;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1355 } else if(!(*istream & 0x30)) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1356 decoded->op = M68K_EXG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1357 decoded->extra.size = OPSIZE_LONG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1358 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1359 decoded->dst.params.regs.pri = *istream & 0x7;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1360 if (*istream & 0x8) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1361 if (*istream & 0x80) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1362 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1363 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1364 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1365 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1366 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1367 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1368 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1369 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1370 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1371 decoded->op = M68K_AND;
90
645fe435cb48 Fix decoding of and
Mike Pavone <pavone@retrodev.com>
parents: 79
diff changeset
1372 decoded->extra.size = (*istream >> 6) & 0x3;
60
6ffea8607730 Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1373 decoded->src.addr_mode = MODE_REG;
6ffea8607730 Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1374 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
6ffea8607730 Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1375 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->dst));
1218
054472ea077a Properly treat bad addressing modes in OR/AND as illegal instructions
Michael Pavone <pavone@retrodev.com>
parents: 992
diff changeset
1376 if (!istream || !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1377 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1378 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1379 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1380 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1381 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1382 if ((*istream & 0xC0) == 0xC0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1383 decoded->op = M68K_MULU;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1384 decoded->extra.size = OPSIZE_WORD;
3
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents: 2
diff changeset
1385 decoded->dst.addr_mode = MODE_REG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1386 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1387 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->src));
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1388 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1389 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1390 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1391 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1392 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1393 decoded->op = M68K_AND;
90
645fe435cb48 Fix decoding of and
Mike Pavone <pavone@retrodev.com>
parents: 79
diff changeset
1394 decoded->extra.size = (*istream >> 6) & 0x3;
60
6ffea8607730 Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1395 decoded->dst.addr_mode = MODE_REG;
6ffea8607730 Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1396 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
6ffea8607730 Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1397 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
1218
054472ea077a Properly treat bad addressing modes in OR/AND as illegal instructions
Michael Pavone <pavone@retrodev.com>
parents: 992
diff changeset
1398 if (!istream || decoded->src.addr_mode == MODE_AREG) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1399 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1400 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1401 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1402 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1403 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1404 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1405 case ADD_ADDX:
101
d7789186ba5e Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
1406 size = (*istream >> 6) & 0x3;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1407 decoded->op = M68K_ADD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1408 if (*istream & 0x100) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1409 //<ea> destination, ADDA.l or ADDX
101
d7789186ba5e Some fixes to add/addx sub/subx decoding
Mike Pavone <pavone@retrodev.com>
parents: 95
diff changeset
1410 if (*istream & 0x30 || size == OPSIZE_INVALID) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1411 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1412 //ADDA.l
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1413 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1414 decoded->dst.addr_mode = MODE_AREG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1415 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1416 istream = m68k_decode_op(istream, OPSIZE_LONG, &(decoded->src));
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1417 if (!istream) {
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1418 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1419 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1420 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1421 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1422 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1423 decoded->src.addr_mode = MODE_REG;
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1424 decoded->src.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1425 istream = m68k_decode_op(istream, size, &(decoded->dst));
1462
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
1426 if (!istream || !m68k_valid_full_arith_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1427 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1428 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1429 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1430 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1431 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1432 //ADDX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1433 decoded->op = M68K_ADDX;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1434 decoded->extra.size = size;
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1435 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1436 decoded->src.params.regs.pri = *istream & 0x7;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1437 if (*istream & 0x8) {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1438 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_AREG_PREDEC;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1439 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1440 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_REG;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1441 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1442 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1443 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1444 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1445 //ADDA.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1446 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1447 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1448 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1449 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1450 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1451 }
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
1452 decoded->dst.params.regs.pri = m68k_reg_quick_field(*istream);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1453 istream = m68k_decode_op(istream, decoded->extra.size, &(decoded->src));
1462
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
1454 if (!istream || (decoded->src.addr_mode == MODE_AREG && decoded->extra.size == OPSIZE_BYTE)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1455 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1456 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1457 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1458 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1459 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1460 case SHIFT_ROTATE:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1461 if ((*istream & 0x8C0) == 0xC0) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1462 switch((*istream >> 8) & 0x7)
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1463 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1464 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1465 decoded->op = M68K_ASR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1466 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1467 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1468 decoded->op = M68K_ASL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1469 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1470 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1471 decoded->op = M68K_LSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1472 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1473 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1474 decoded->op = M68K_LSL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1475 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1476 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1477 decoded->op = M68K_ROXR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1478 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1479 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1480 decoded->op = M68K_ROXL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1481 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1482 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1483 decoded->op = M68K_ROR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1484 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1485 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1486 decoded->op = M68K_ROL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1487 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1488 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1489 decoded->extra.size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1490 istream = m68k_decode_op(istream, OPSIZE_WORD, &(decoded->dst));
1462
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
1491 if (!istream || !m68k_valid_full_arith_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1492 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1493 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1494 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1495 } else if((*istream & 0xC0) != 0xC0) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1496 switch(((*istream >> 2) & 0x6) | ((*istream >> 8) & 1))
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1497 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1498 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1499 decoded->op = M68K_ASR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1500 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1501 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1502 decoded->op = M68K_ASL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1503 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1504 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1505 decoded->op = M68K_LSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1506 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1507 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1508 decoded->op = M68K_LSL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1509 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1510 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1511 decoded->op = M68K_ROXR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1512 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1513 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1514 decoded->op = M68K_ROXL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1515 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1516 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1517 decoded->op = M68K_ROR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1518 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1519 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1520 decoded->op = M68K_ROL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1521 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1522 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1523 decoded->extra.size = (*istream >> 6) & 0x3;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1524 immed = (*istream >> 9) & 0x7;
51
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding.
Mike Pavone <pavone@retrodev.com>
parents: 50
diff changeset
1525 if (*istream & 0x20) {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1526 decoded->src.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1527 decoded->src.params.regs.pri = immed;
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1528 } else {
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1529 decoded->src.addr_mode = MODE_IMMEDIATE;
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1530 if (!immed) {
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1531 immed = 8;
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1532 }
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1533 decoded->src.params.immed = immed;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1534 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1535 decoded->dst.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1536 decoded->dst.params.regs.pri = *istream & 0x7;
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1537
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1538 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1539 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1540 //TODO: Implement bitfield instructions for M68020+ support
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1541 switch (*istream >> 8 & 7)
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1542 {
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1543 case 0:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1544 decoded->op = M68K_BFTST; //<ea>
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1545 break;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1546 case 1:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1547 decoded->op = M68K_BFEXTU; //<ea>, Dn
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1548 break;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1549 case 2:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1550 decoded->op = M68K_BFCHG; //<ea>
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1551 break;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1552 case 3:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1553 decoded->op = M68K_BFEXTS; //<ea>, Dn
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1554 break;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1555 case 4:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1556 decoded->op = M68K_BFCLR; //<ea>
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1557 break;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1558 case 5:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1559 decoded->op = M68K_BFFFO; //<ea>, Dn
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1560 break;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1561 case 6:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1562 decoded->op = M68K_BFSET; //<ea>
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1563 break;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1564 case 7:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1565 decoded->op = M68K_BFINS; //Dn, <ea>
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1566 break;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1567 }
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1568 opmode = *istream >> 3 & 0x7;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1569 reg = *istream & 0x7;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1570 m68k_op_info *ea, *other;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1571 if (decoded->op == M68K_BFEXTU || decoded->op == M68K_BFEXTS || decoded->op == M68K_BFFFO)
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1572 {
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1573 ea = &(decoded->src);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1574 other = &(decoded->dst);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1575 } else {
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1576 ea = &(decoded->dst);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1577 other = &(decoded->dst);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1578 }
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1579 if (*istream & 0x100)
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1580 {
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1581 immed = *(istream++);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1582 other->addr_mode = MODE_REG;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1583 other->params.regs.pri = immed >> 12 & 0x7;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1584 } else {
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1585 immed = *(istream++);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1586 }
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1587 decoded->extra.size = OPSIZE_UNSIZED;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1588 istream = m68k_decode_op_ex(istream, opmode, reg, decoded->extra.size, ea);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1589 ea->addr_mode |= M68K_FLAG_BITFIELD;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1590 ea->bitfield = immed & 0xFFF;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1591 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1592 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1593 break;
992
261995d06897 Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
1594 case F_LINE:
261995d06897 Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
1595 //TODO: Decode FPU instructions for members of the 68K family with an FPU
261995d06897 Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
1596 decoded->op = M68K_F_LINE_TRAP;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1597 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1598 }
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1599 if (decoded->op == M68K_INVALID) {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1600 decoded->src.params.immed = *start;
981
902c53d9c16f Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 835
diff changeset
1601 decoded->bytes = 2;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1602 return start + 1;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1603 }
981
902c53d9c16f Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 835
diff changeset
1604 decoded->bytes = 2 * (istream + 1 - start);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1605 return istream+1;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1606 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1607
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1608 uint32_t m68k_branch_target(m68kinst * inst, uint32_t *dregs, uint32_t *aregs)
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1609 {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1610 if(inst->op == M68K_BCC || inst->op == M68K_BSR || inst->op == M68K_DBCC) {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1611 return inst->address + 2 + inst->src.params.immed;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1612 } else if(inst->op == M68K_JMP || inst->op == M68K_JSR) {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1613 uint32_t ret = 0;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1614 switch(inst->src.addr_mode)
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1615 {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1616 case MODE_AREG_INDIRECT:
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1617 ret = aregs[inst->src.params.regs.pri];
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1618 break;
1330
af26a1ce92f7 Handle address register displacement when calculating branch targets in debugger
Michael Pavone <pavone@retrodev.com>
parents: 1277
diff changeset
1619 case MODE_AREG_DISPLACE:
af26a1ce92f7 Handle address register displacement when calculating branch targets in debugger
Michael Pavone <pavone@retrodev.com>
parents: 1277
diff changeset
1620 ret = aregs[inst->src.params.regs.pri] + inst->src.params.regs.displacement;
af26a1ce92f7 Handle address register displacement when calculating branch targets in debugger
Michael Pavone <pavone@retrodev.com>
parents: 1277
diff changeset
1621 break;
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1622 case MODE_AREG_INDEX_DISP8: {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1623 uint8_t sec_reg = inst->src.params.regs.sec >> 1 & 0x7;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1624 ret = aregs[inst->src.params.regs.pri];
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1625 uint32_t * regfile = inst->src.params.regs.sec & 0x10 ? aregs : dregs;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1626 if (inst->src.params.regs.sec & 1) {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1627 //32-bit index register
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1628 ret += regfile[sec_reg];
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1629 } else {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1630 //16-bit index register
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1631 if (regfile[sec_reg] & 0x8000) {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1632 ret += (0xFFFF0000 | regfile[sec_reg]);
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1633 } else {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1634 ret += regfile[sec_reg];
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1635 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1636 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1637 ret += inst->src.params.regs.displacement;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1638 break;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1639 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1640 case MODE_PC_DISPLACE:
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1641 ret = inst->src.params.regs.displacement + inst->address + 2;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1642 break;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1643 case MODE_PC_INDEX_DISP8: {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1644 uint8_t sec_reg = inst->src.params.regs.sec >> 1 & 0x7;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1645 ret = inst->address + 2;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1646 uint32_t * regfile = inst->src.params.regs.sec & 0x10 ? aregs : dregs;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1647 if (inst->src.params.regs.sec & 1) {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1648 //32-bit index register
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1649 ret += regfile[sec_reg];
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1650 } else {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1651 //16-bit index register
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1652 if (regfile[sec_reg] & 0x8000) {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1653 ret += (0xFFFF0000 | regfile[sec_reg]);
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1654 } else {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1655 ret += regfile[sec_reg];
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1656 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1657 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1658 ret += inst->src.params.regs.displacement;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1659 break;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1660 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1661 case MODE_ABSOLUTE:
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1662 case MODE_ABSOLUTE_SHORT:
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1663 ret = inst->src.params.immed;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1664 break;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1665 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1666 return ret;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1667 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1668 return 0;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1669 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1670
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1671 uint8_t m68k_is_branch(m68kinst * inst)
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1672 {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1673 return (inst->op == M68K_BCC && inst->extra.cond != COND_FALSE)
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1674 || (inst->op == M68K_DBCC && inst->extra.cond != COND_TRUE)
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1675 || inst->op == M68K_BSR || inst->op == M68K_JMP || inst->op == M68K_JSR;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1676 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1677
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1678 uint8_t m68k_is_noncall_branch(m68kinst * inst)
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1679 {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1680 return m68k_is_branch(inst) && inst->op != M68K_BSR && inst->op != M68K_JSR;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1681 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1682
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1683
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1684 char * mnemonics[] = {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1685 "abcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1686 "add",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1687 "addx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1688 "and",
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1689 "andi",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1690 "andi",//sr
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1691 "asl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1692 "asr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1693 "bcc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1694 "bchg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1695 "bclr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1696 "bset",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1697 "bsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1698 "btst",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1699 "chk",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1700 "clr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1701 "cmp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1702 "dbcc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1703 "divs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1704 "divu",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1705 "eor",
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1706 "eori",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1707 "eori",//sr
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1708 "exg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1709 "ext",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1710 "illegal",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1711 "jmp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1712 "jsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1713 "lea",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1714 "link",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1715 "lsl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1716 "lsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1717 "move",
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1718 "move",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1719 "move",//from_sr
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1720 "move",//sr
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1721 "move",//usp
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1722 "movem",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1723 "movep",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1724 "muls",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1725 "mulu",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1726 "nbcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1727 "neg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1728 "negx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1729 "nop",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1730 "not",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1731 "or",
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1732 "ori",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1733 "ori",//sr
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1734 "pea",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1735 "reset",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1736 "rol",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1737 "ror",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1738 "roxl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1739 "roxr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1740 "rte",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1741 "rtr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1742 "rts",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1743 "sbcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1744 "scc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1745 "stop",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1746 "sub",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1747 "subx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1748 "swap",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1749 "tas",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1750 "trap",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1751 "trapv",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1752 "tst",
12
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
1753 "unlk",
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1754 "invalid",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1755 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1756 "bkpt",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1757 "move", //from ccr
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1758 "movec",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1759 "moves",
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1760 "rtd",
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1761 #endif
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1762 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1763 "bfchg",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1764 "bfclr",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1765 "bfexts",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1766 "bfextu",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1767 "bfffo",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1768 "bfins",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1769 "bfset",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1770 "bftst",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1771 "callm",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1772 "cas",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1773 "cas2",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1774 "chk2",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1775 "cmp2",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1776 "cpbcc",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1777 "cpdbcc",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1778 "cpgen",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1779 "cprestore",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1780 "cpsave",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1781 "cpscc",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1782 "cptrapcc",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1783 "divsl",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1784 "divul",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1785 "extb",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1786 "pack",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1787 "rtm",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1788 "trapcc",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1789 "unpk"
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1790 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1791 };
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1792
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1793 char * cond_mnem[] = {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1794 "ra",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1795 "f",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1796 "hi",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1797 "ls",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1798 "cc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1799 "cs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1800 "ne",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1801 "eq",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1802 "vc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1803 "vs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1804 "pl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1805 "mi",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1806 "ge",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1807 "lt",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1808 "gt",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1809 "le"
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1810 };
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1811 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1812 char * cr_mnem[] = {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1813 "SFC",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1814 "DFC",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1815 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1816 "CACR",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1817 #endif
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1818 "USP",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1819 "VBR",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1820 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1821 "CAAR",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1822 "MSP",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1823 "ISP"
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1824 #endif
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1825 };
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1826 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1827
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
1828 int m68k_disasm_op(m68k_op_info *decoded, char *dst, int need_comma, uint8_t labels, uint32_t address, format_label_fun label_fun, void * data)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1829 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1830 char * c = need_comma ? "," : "";
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1831 int ret = 0;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1832 #ifdef M68020
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1833 uint8_t addr_mode = decoded->addr_mode & (~M68K_FLAG_BITFIELD);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1834 #else
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1835 uint8_t addr_mode = decoded->addr_mode;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1836 #endif
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1837 switch(addr_mode)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1838 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1839 case MODE_REG:
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1840 ret = sprintf(dst, "%s d%d", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1841 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1842 case MODE_AREG:
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1843 ret = sprintf(dst, "%s a%d", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1844 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1845 case MODE_AREG_INDIRECT:
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1846 ret = sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1847 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1848 case MODE_AREG_POSTINC:
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1849 ret = sprintf(dst, "%s (a%d)+", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1850 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1851 case MODE_AREG_PREDEC:
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1852 ret = sprintf(dst, "%s -(a%d)", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1853 break;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1854 case MODE_AREG_DISPLACE:
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1855 ret = sprintf(dst, "%s (%d, a%d)", c, decoded->params.regs.displacement, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1856 break;
79
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 69
diff changeset
1857 case MODE_AREG_INDEX_DISP8:
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1858 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1859 if (decoded->params.regs.scale)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1860 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1861 ret = sprintf(dst, "%s (%d, a%d, %c%d.%c*%d)", c, decoded->params.regs.displacement, decoded->params.regs.pri, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1862 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1863 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1864 ret = sprintf(dst, "%s (%d, a%d, %c%d.%c)", c, decoded->params.regs.displacement, decoded->params.regs.pri, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1865 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1866 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1867 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1868 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1869 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1870 case MODE_AREG_INDEX_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1871 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1872 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1873 ret = sprintf(dst, "%s (%d.%c, a%d, %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1874 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1875 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1876 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1877 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1878 ret = sprintf(dst, "%s (a%d, %c%d.%c*%d)", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1879 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1880 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1881 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1882 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1883 case MODE_AREG_PREINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1884 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1885 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1886 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1887 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1888 ret = sprintf(dst, "%s ([a%d, %c%d.%c*%d])", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1889 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1890 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1891 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1892 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1893 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1894 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1895 ret = sprintf(dst, "%s ([%d.%c, a%d, %c%d.%c*%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1896 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1897 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1898 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1899 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1900 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1901 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1902 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1903 ret = sprintf(dst, "%s ([a%d, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1904 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1905 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1906 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1907 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1908 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1909 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1910 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1911 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1912 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1913 ret = sprintf(dst, "%s ([%d.%c, a%d, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1914 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1915 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1916 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1917 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1918 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1919 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1920 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1921 case MODE_AREG_POSTINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1922 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1923 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1924 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1925 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1926 ret = sprintf(dst, "%s ([a%d], %c%d.%c*%d)", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1927 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1928 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1929 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1930 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1931 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1932 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1933 ret = sprintf(dst, "%s ([%d.%c, a%d], %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1934 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1935 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1936 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1937 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1938 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1939 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1940 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1941 ret = sprintf(dst, "%s ([a%d], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1942 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1943 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1944 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1945 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1946 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1947 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1948 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1949 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1950 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1951 ret = sprintf(dst, "%s ([%d.%c, a%d], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1952 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1953 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1954 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1955 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1956 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1957 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1958 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1959 case MODE_AREG_MEM_INDIRECT:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1960 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1961 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1962 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1963 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1964 ret = sprintf(dst, "%s ([a%d])", c, decoded->params.regs.pri);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1965 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1966 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1967 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1968 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1969 ret = sprintf(dst, "%s ([%d.%c, a%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1970 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1971 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1972 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1973 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1974 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1975 ret = sprintf(dst, "%s ([a%d], %d.%c)", c, decoded->params.regs.pri, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1976 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1977 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1978 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1979 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1980 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1981 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1982 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1983 ret = sprintf(dst, "%s ([%d.%c, a%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1984 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1985 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1986 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1987 }
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1988 break;
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1989 case MODE_AREG_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1990 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1991 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1992 ret = sprintf(dst, "%s (%d.%c, a%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1993 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', decoded->params.regs.pri);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1994 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1995 //this is a lossy representation of the encoded instruction
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1996 //not sure if there's a better way to print it though
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1997 ret = sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1998 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1999 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2000 case MODE_INDEX_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2001 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2002 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2003 ret = sprintf(dst, "%s (%d.%c, %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2004 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2005 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2006 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2007 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2008 ret = sprintf(dst, "%s (%c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2009 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2010 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2011 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2012 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2013 case MODE_PREINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2014 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2015 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2016 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2017 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2018 ret = sprintf(dst, "%s ([%c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2019 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2020 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2021 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2022 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2023 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2024 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2025 ret = sprintf(dst, "%s ([%d.%c, %c%d.%c*%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2026 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2027 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2028 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2029 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2030 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2031 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2032 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2033 ret = sprintf(dst, "%s ([%c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2034 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2035 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2036 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2037 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2038 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2039 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2040 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2041 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2042 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2043 ret = sprintf(dst, "%s ([%d.%c, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2044 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2045 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2046 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2047 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2048 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2049 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2050 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2051 case MODE_POSTINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2052 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2053 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2054 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2055 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2056 ret = sprintf(dst, "%s ([], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2057 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2058 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2059 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2060 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2061 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2062 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2063 ret = sprintf(dst, "%s ([%d.%c], %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2064 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2065 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2066 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2067 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2068 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2069 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2070 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2071 ret = sprintf(dst, "%s ([], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2072 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2073 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2074 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2075 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2076 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2077 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2078 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2079 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2080 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2081 ret = sprintf(dst, "%s ([%d.%c], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2082 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2083 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2084 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2085 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2086 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2087 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2088 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2089 case MODE_MEM_INDIRECT:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2090 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2091 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2092 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2093 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2094 ret = sprintf(dst, "%s ([])", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2095 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2096 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2097 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2098 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2099 ret = sprintf(dst, "%s ([%d.%c])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2100 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2101 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2102 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2103 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2104 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2105 ret = sprintf(dst, "%s ([], %d.%c)", c, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2106 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2107 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2108 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2109 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2110 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2111 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2112 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2113 ret = sprintf(dst, "%s ([%d.%c], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2114 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2115 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2116 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2117 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2118 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2119 case MODE_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2120 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2121 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2122 ret = sprintf(dst, "%s (%d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2123 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2124 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2125 ret = sprintf(dst, "%s ()", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2126 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2127 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2128 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2129 case MODE_IMMEDIATE:
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
2130 case MODE_IMMEDIATE_WORD:
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2131 ret = sprintf(dst, (decoded->params.immed <= 128 ? "%s #%d" : "%s #$%X"), c, decoded->params.immed);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2132 break;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2133 case MODE_ABSOLUTE_SHORT:
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2134 if (labels) {
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2135 ret = sprintf(dst, "%s ", c);
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2136 ret += label_fun(dst+ret, decoded->params.immed, data);
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2137 strcat(dst+ret, ".w");
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2138 ret = ret + 2;
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2139 } else {
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2140 ret = sprintf(dst, "%s $%X.w", c, decoded->params.immed);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2141 }
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2142 break;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2143 case MODE_ABSOLUTE:
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2144 if (labels) {
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2145 ret = sprintf(dst, "%s ", c);
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2146 ret += label_fun(dst+ret, decoded->params.immed, data);
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2147 strcat(dst+ret, ".l");
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2148 ret = ret + 2;
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2149 } else {
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2150 ret = sprintf(dst, "%s $%X", c, decoded->params.immed);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2151 }
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2152 break;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2153 case MODE_PC_DISPLACE:
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2154 if (labels) {
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2155 ret = sprintf(dst, "%s ", c);
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2156 ret += label_fun(dst+ret, address + 2 + decoded->params.regs.displacement, data);
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2157 strcat(dst+ret, "(pc)");
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2158 ret = ret + 4;
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2159 } else {
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2160 ret = sprintf(dst, "%s (%d, pc)", c, decoded->params.regs.displacement);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2161 }
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2162 break;
79
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 69
diff changeset
2163 case MODE_PC_INDEX_DISP8:
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2164 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2165 if (decoded->params.regs.scale)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2166 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2167 ret = sprintf(dst, "%s (%d, pc, %c%d.%c*%d)", c, decoded->params.regs.displacement, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2168 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2169 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2170 ret = sprintf(dst, "%s (%d, pc, %c%d.%c)", c, decoded->params.regs.displacement, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2171 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2172 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2173 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2174 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2175 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2176 case MODE_PC_INDEX_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2177 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2178 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2179 ret = sprintf(dst, "%s (%d.%c, pc, %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2180 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2181 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2182 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2183 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2184 ret = sprintf(dst, "%s (pc, %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2185 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2186 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2187 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2188 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2189 case MODE_PC_PREINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2190 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2191 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2192 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2193 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2194 ret = sprintf(dst, "%s ([pc, %c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2195 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2196 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2197 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2198 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2199 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2200 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2201 ret = sprintf(dst, "%s ([%d.%c, pc, %c%d.%c*%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2202 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2203 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2204 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2205 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2206 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2207 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2208 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2209 ret = sprintf(dst, "%s ([pc, %c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2210 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2211 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2212 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2213 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2214 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2215 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2216 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2217 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2218 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2219 ret = sprintf(dst, "%s ([%d.%c, pc, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2220 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2221 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2222 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2223 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2224 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2225 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2226 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2227 case MODE_PC_POSTINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2228 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2229 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2230 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2231 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2232 ret = sprintf(dst, "%s ([pc], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2233 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2234 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2235 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2236 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2237 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2238 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2239 ret = sprintf(dst, "%s ([%d.%c, pc], %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2240 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2241 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2242 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2243 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2244 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2245 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2246 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2247 ret = sprintf(dst, "%s ([pc], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2248 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2249 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2250 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2251 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2252 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2253 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2254 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2255 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2256 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2257 ret = sprintf(dst, "%s ([%d.%c, pc], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2258 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2259 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2260 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2261 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2262 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2263 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2264 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2265 case MODE_PC_MEM_INDIRECT:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2266 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2267 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2268 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2269 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2270 ret = sprintf(dst, "%s ([pc])", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2271 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2272 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2273 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2274 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2275 ret = sprintf(dst, "%s ([%d.%c, pc])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2276 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2277 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2278 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2279 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2280 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2281 ret = sprintf(dst, "%s ([pc], %d.%c)", c, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2282 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2283 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2284 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2285 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2286 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2287 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2288 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2289 ret = sprintf(dst, "%s ([%d.%c, pc], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2290 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2291 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2292 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2293 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2294 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2295 case MODE_PC_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2296 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2297 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2298 ret = sprintf(dst, "%s (%d.%c, pc)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2299 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2300 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2301 ret = sprintf(dst, "%s (pc)", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2302 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2303 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2304 case MODE_ZPC_INDEX_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2305 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2306 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2307 ret = sprintf(dst, "%s (%d.%c, zpc, %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2308 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2309 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2310 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2311 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2312 ret = sprintf(dst, "%s (zpc, %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2313 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2314 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2315 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2316 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2317 case MODE_ZPC_PREINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2318 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2319 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2320 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2321 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2322 ret = sprintf(dst, "%s ([zpc, %c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2323 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2324 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2325 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2326 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2327 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2328 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2329 ret = sprintf(dst, "%s ([%d.%c, zpc, %c%d.%c*%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2330 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2331 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2332 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2333 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2334 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2335 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2336 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2337 ret = sprintf(dst, "%s ([zpc, %c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2338 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2339 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2340 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2341 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2342 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2343 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2344 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2345 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2346 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2347 ret = sprintf(dst, "%s ([%d.%c, zpc, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2348 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2349 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2350 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2351 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2352 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2353 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2354 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2355 case MODE_ZPC_POSTINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2356 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2357 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2358 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2359 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2360 ret = sprintf(dst, "%s ([zpc], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2361 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2362 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2363 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2364 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2365 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2366 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2367 ret = sprintf(dst, "%s ([%d.%c, zpc], %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2368 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2369 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2370 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2371 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2372 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2373 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2374 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2375 ret = sprintf(dst, "%s ([zpc], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2376 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2377 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2378 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2379 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2380 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2381 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2382 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2383 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2384 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2385 ret = sprintf(dst, "%s ([%d.%c, zpc], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2386 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2387 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2388 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2389 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2390 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2391 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2392 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2393 case MODE_ZPC_MEM_INDIRECT:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2394 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2395 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2396 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2397 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2398 ret = sprintf(dst, "%s ([zpc])", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2399 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2400 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2401 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2402 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2403 ret = sprintf(dst, "%s ([%d.%c, zpc])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2404 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2405 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2406 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2407 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2408 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2409 ret = sprintf(dst, "%s ([zpc], %d.%c)", c, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2410 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2411 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2412 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2413 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2414 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2415 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2416 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2417 ret = sprintf(dst, "%s ([%d.%c, zpc], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2418 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2419 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2420 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2421 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2422 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2423 case MODE_ZPC_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2424 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2425 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2426 ret = sprintf(dst, "%s (%d.%c, zpc)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2427 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2428 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2429 ret = sprintf(dst, "%s (zpc)", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2430 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2431 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2432 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2433 default:
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2434 ret = 0;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2435 }
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2436 #ifdef M68020
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2437 if (decoded->addr_mode & M68K_FLAG_BITFIELD)
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2438 {
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2439 switch (decoded->bitfield & 0x820)
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2440 {
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2441 case 0:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2442 return ret + sprintf(dst+ret, " {$%X:%d}", decoded->bitfield >> 6 & 0x1F, decoded->bitfield & 0x1F ? decoded->bitfield & 0x1F : 32);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2443 case 0x20:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2444 return ret + sprintf(dst+ret, " {$%X:d%d}", decoded->bitfield >> 6 & 0x1F, decoded->bitfield & 0x7);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2445 case 0x800:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2446 return ret + sprintf(dst+ret, " {d%d:%d}", decoded->bitfield >> 6 & 0x7, decoded->bitfield & 0x1F ? decoded->bitfield & 0x1F : 32);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2447 case 0x820:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2448 return ret + sprintf(dst+ret, " {d%d:d%d}", decoded->bitfield >> 6 & 0x7, decoded->bitfield & 0x7);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2449 }
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2450 }
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2451 #endif
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2452 return ret;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2453 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2454
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2455 int m68k_disasm_movem_op(m68k_op_info *decoded, m68k_op_info *other, char *dst, int need_comma, uint8_t labels, uint32_t address, format_label_fun label_fun, void * data)
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2456 {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2457 int8_t dir, reg, bit, regnum, last=-1, lastreg, first=-1;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2458 char *rtype, *last_rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2459 int oplen;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2460 if (decoded->addr_mode == MODE_REG) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2461 if (other->addr_mode == MODE_AREG_PREDEC) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2462 bit = 15;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2463 dir = -1;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2464 } else {
69
36f1133837d0 Fix disassembly of reg list in MOVEM when the reg list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 68
diff changeset
2465 dir = 1;
36f1133837d0 Fix disassembly of reg list in MOVEM when the reg list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 68
diff changeset
2466 bit = 0;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2467 }
68
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
2468 if (need_comma) {
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
2469 strcat(dst, ", ");
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
2470 oplen = 2;
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
2471 } else {
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
2472 strcat(dst, " ");
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
2473 oplen = 1;
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
2474 }
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
2475 for (reg=0; bit < 16 && bit > -1; bit += dir, reg++) {
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
2476 if (decoded->params.immed & (1 << bit)) {
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2477 if (reg > 7) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2478 rtype = "a";
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2479 regnum = reg - 8;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2480 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2481 rtype = "d";
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2482 regnum = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2483 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2484 if (last >= 0 && last == regnum - 1 && lastreg == reg - 1) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2485 last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2486 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2487 } else if(last >= 0) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2488 if (first != last) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2489 oplen += sprintf(dst + oplen, "-%s%d/%s%d",last_rtype, last, rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2490 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2491 oplen += sprintf(dst + oplen, "/%s%d", rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2492 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2493 first = last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2494 last_rtype = rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2495 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2496 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2497 oplen += sprintf(dst + oplen, "%s%d", rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2498 first = last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2499 last_rtype = rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2500 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2501 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2502 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2503 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2504 if (last >= 0 && last != first) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2505 oplen += sprintf(dst + oplen, "-%s%d", last_rtype, last);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2506 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2507 return oplen;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2508 } else {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2509 return m68k_disasm_op(decoded, dst, need_comma, labels, address, label_fun, data);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2510 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2511 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2512
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2513 int m68k_default_label_fun(char * dst, uint32_t address, void * data)
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2514 {
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2515 return sprintf(dst, "ADR_%X", address);
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2516 }
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2517
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2518 int m68k_disasm_ex(m68kinst * decoded, char * dst, uint8_t labels, format_label_fun label_fun, void * data)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2519 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2520 int ret,op1len;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2521 uint8_t size;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2522 char * special_op = "CCR";
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2523 switch (decoded->op)
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2524 {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2525 case M68K_BCC:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2526 case M68K_DBCC:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2527 case M68K_SCC:
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2528 ret = strlen(mnemonics[decoded->op]) - 2;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2529 memcpy(dst, mnemonics[decoded->op], ret);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2530 dst[ret] = 0;
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2531 strcpy(dst+ret, cond_mnem[decoded->extra.cond]);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2532 ret = strlen(dst);
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2533 if (decoded->op != M68K_SCC) {
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2534 if (labels) {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2535 if (decoded->op == M68K_DBCC) {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2536 ret += sprintf(dst+ret, " d%d, ", decoded->dst.params.regs.pri);
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2537 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2538 } else {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2539 dst[ret++] = ' ';
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2540 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2541 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
2542 } else {
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2543 if (decoded->op == M68K_DBCC) {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2544 ret += sprintf(dst+ret, " d%d, #%d <%X>", decoded->dst.params.regs.pri, decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2545 } else {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2546 ret += sprintf(dst+ret, " #%d <%X>", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2547 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
2548 }
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2549 return ret;
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2550 }
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2551 break;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2552 case M68K_BSR:
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2553 if (labels) {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2554 ret = sprintf(dst, "bsr%s ", decoded->variant == VAR_BYTE ? ".s" : "");
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2555 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2556 } else {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2557 ret = sprintf(dst, "bsr%s #%d <%X>", decoded->variant == VAR_BYTE ? ".s" : "", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2558 }
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2559 return ret;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2560 case M68K_MOVE_FROM_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2561 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2562 ret += sprintf(dst + ret, " SR");
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2563 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 1, labels, decoded->address, label_fun, data);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2564 return ret;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2565 case M68K_ANDI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2566 case M68K_EORI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2567 case M68K_MOVE_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2568 case M68K_ORI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2569 special_op = "SR";
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2570 case M68K_ANDI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2571 case M68K_EORI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2572 case M68K_MOVE_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2573 case M68K_ORI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2574 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2575 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2576 ret += sprintf(dst + ret, ", %s", special_op);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2577 return ret;
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2578 case M68K_MOVE_USP:
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2579 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2580 if (decoded->src.addr_mode != MODE_UNUSED) {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2581 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data);
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2582 ret += sprintf(dst + ret, ", USP");
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2583 } else {
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2584 ret += sprintf(dst + ret, "USP, ");
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2585 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data);
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2586 }
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2587 return ret;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2588 case M68K_INVALID:
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2589 ret = sprintf(dst, "dc.w $%X", decoded->src.params.immed);
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2590 return ret;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2591 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2592 case M68K_MOVEC:
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2593 ret = sprintf(dst, "%s ", mnemonics[decoded->op]);
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2594 if (decoded->src.addr_mode == MODE_UNUSED) {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2595 ret += sprintf(dst + ret, "%s, ", cr_mnem[decoded->src.params.immed]);
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2596 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data);
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2597 } else {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2598 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data);
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2599 ret += sprintf(dst + ret, ", %s", cr_mnem[decoded->dst.params.immed]);
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2600 }
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2601 return ret;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2602 #endif
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2603 default:
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2604 size = decoded->extra.size;
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
2605 ret = sprintf(dst, "%s%s%s",
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
2606 mnemonics[decoded->op],
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
2607 decoded->variant == VAR_QUICK ? "q" : (decoded->variant == VAR_IMMEDIATE ? "i" : ""),
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2608 size == OPSIZE_BYTE ? ".b" : (size == OPSIZE_WORD ? ".w" : (size == OPSIZE_LONG ? ".l" : "")));
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2609 }
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2610 if (decoded->op == M68K_MOVEM) {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2611 op1len = m68k_disasm_movem_op(&(decoded->src), &(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2612 ret += op1len;
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2613 ret += m68k_disasm_movem_op(&(decoded->dst), &(decoded->src), dst + ret, op1len, labels, decoded->address, label_fun, data);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2614 } else {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2615 op1len = m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2616 ret += op1len;
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2617 ret += m68k_disasm_op(&(decoded->dst), dst + ret, op1len, labels, decoded->address, label_fun, data);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2618 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2619 return ret;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2620 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2621
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2622 int m68k_disasm(m68kinst * decoded, char * dst)
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2623 {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2624 return m68k_disasm_ex(decoded, dst, 0, NULL, NULL);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2625 }
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2626
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2627 int m68k_disasm_labels(m68kinst * decoded, char * dst, format_label_fun label_fun, void * data)
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2628 {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2629 if (!label_fun)
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2630 {
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2631 label_fun = m68k_default_label_fun;
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2632 }
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2633 return m68k_disasm_ex(decoded, dst, 1, label_fun, data);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2634 }