Mercurial > repos > blastem

annotate m68k.cpu @ 2674:07cc0f7109f0

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Fix an issue in which CD timer interrupts could get missed, at least with the new interpreter
author Michael Pavone <pavone@retrodev.com>
date Sun, 09 Mar 2025 22:53:04 -0700
parents e0935d5878c3
children 7e86ec94c899
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1 info
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2 prefix m68k_
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
3 opcode_size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
4 body m68k_run_op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
5 header m68k.h
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
6 interrupt m68k_interrupt
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
7 include m68k_util.c
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
8 sync_cycle m68k_sync_cycle
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
9
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
10 declare
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
11 typedef m68k_context *(sync_fun)(m68k_context * context, uint32_t address);
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
12 typedef m68k_context *(*int_ack_fun)(m68k_context * context);
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
13 typedef m68k_context *(*m68k_reset_handler)(m68k_context *context);
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
14 void init_m68k_opts(m68k_options *opts, memmap_chunk * memmap, uint32_t num_chunks, uint32_t clock_divider, sync_fun *sync_components, int_ack_fun int_ack);
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
15 m68k_context *init_68k_context(m68k_options * opts, m68k_reset_handler *reset_handler);
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
16 void m68k_reset(m68k_context *context);
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
17 void m68k_print_regs(m68k_context *context);
2499
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
18 void m68k_serialize(m68k_context *context, uint32_t pc, serialize_buffer *buf);
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
19 void m68k_deserialize(deserialize_buffer *buf, void *vcontext);
2500
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
20 void start_68k_context(m68k_context *context, uint32_t pc);
2499
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
21 define NUM_MEM_AREAS 10
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
22 define M68K_OPT_BROKEN_READ_MODIFY 1
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
23 define INT_PENDING_SR_CHANGE 254
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
24 define INT_PENDING_NONE 255
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
25 define M68K_STATUS_TRACE 0x80
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
26 define m68k_invalidate_code_range(context, start, end)
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
27 define m68k_options_free free
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
28 define m68k_handle_code_write(address, context)
2500
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
29 define resume_68k(context) m68k_execute(context, context->target_cycle)
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
30 define insert_breakpoint(context, address, handler)
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
31 define remove_breakpoint(context, address)
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
32 define m68k_add_watchpoint(context, address, size)
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
33 define m68k_remove_watchpoint(context, address, size)
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
34
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
35 regs
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
36 dregs 32 d0 d1 d2 d3 d4 d5 d6 d7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
37 aregs 32 a0 a1 a2 a3 a4 a5 a6 a7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
38 pc 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
39 other_sp 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
40 scratch1 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
41 scratch2 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
42 int_cycle 32
2499
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
43 target_cycle 32
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
44 wp_hit_address 32
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
45 prefetch 16
2499
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
46 wp_hit_value 16
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
47 wp_old_value 16
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
48 int_priority 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
49 int_num 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
50 int_pending 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
51 int_pending_num 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
52 int_ack 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
53 status 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
54 ccr 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
55 xflag 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
56 nflag 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
57 zflag 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
58 vflag 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
59 cflag 8
2499
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
60 wp_hit 8
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
61 trace_pending 8
2500
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
62 should_return 8
2618
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
63 stopped 8
2499
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
64 system ptrvoid
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
65 reset_handler ptrvoid
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
66 int_ack_handler ptrvoid
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
67 sync_components ptrsync_fun
2500
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
68 mem_pointers ptr16 10
2666
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints
Michael Pavone <pavone@retrodev.com>
parents: 2653
diff changeset
69 read16 interp_read_16 256
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints
Michael Pavone <pavone@retrodev.com>
parents: 2653
diff changeset
70 read8 interp_read_8 256
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints
Michael Pavone <pavone@retrodev.com>
parents: 2653
diff changeset
71 write16 interp_write_16 256
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints
Michael Pavone <pavone@retrodev.com>
parents: 2653
diff changeset
72 write8 interp_write_8 256
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints
Michael Pavone <pavone@retrodev.com>
parents: 2653
diff changeset
73 read16_data ptrvoid 256
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints
Michael Pavone <pavone@retrodev.com>
parents: 2653
diff changeset
74 read8_data ptrvoid 256
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints
Michael Pavone <pavone@retrodev.com>
parents: 2653
diff changeset
75 write16_data ptrvoid 256
38c281ef57b0 Memory access optimizaiton in new 68K core that gives a modest speed bump on average and will allow low-cost watchpoints
Michael Pavone <pavone@retrodev.com>
parents: 2653
diff changeset
76 write8_data ptrvoid 256
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
77
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
78 flags
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
79 register ccr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
80 X 4 carry xflag
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
81 N 3 sign nflag
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
82 Z 2 zero zflag
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
83 V 1 overflow vflag
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
84 C 0 carry cflag
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
85
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
86 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
87 if dynarec
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
88
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
89 ccall m68k_read16_noinc context pc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
90 mov result prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
91
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
92 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
93
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
94 if interp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
95
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
96 mov pc scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
97 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
98 mov scratch1 prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
99
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
100 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
101
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
102 add 2 pc pc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
103
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
104 check_user_mode_swap_ssp_usp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
105 local tmp 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
106 and 0x20 status tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
107 if tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
108 else
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
109 xchg other_sp a7
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
110 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
111
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
112 m68k_get_sr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
113 lsl status 8 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
114 or ccr scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
115
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
116 m68k_write32_lowfirst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
117 arg value 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
118 add 2 scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
119 mov value scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
120 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
121
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
122 sub 2 scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
123 lsr value 16 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
124 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
125
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
126 m68k_write32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
127 arg value 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
128 local tmp 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
129 mov value tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
130 lsr value 16 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
131 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
132
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
133 add 2 scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
134 mov tmp scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
135 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
136
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
137 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
138 local tmp 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
139 add 2 scratch1 tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
140 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
141 xchg scratch1 tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
142 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
143 lsl tmp 16 tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
144 or tmp scratch1 scratch1
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
145
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
146 m68k_trap
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
147 arg vector 32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
148 check_user_mode_swap_ssp_usp
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
149 #save PC
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
150 a7 -= 4
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
151 scratch2 = a7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
152 m68k_write32_lowfirst pc
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
153 #save SR
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
154 a7 -= 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
155 scratch2 = a7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
156 m68k_get_sr
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
157 ocall write_16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
158 #set supervisor bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
159 status |= 0x20
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
160 #clear trace bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
161 status &= 0x7F
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
162 trace_pending = 0
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
163 scratch1 = vector << 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
164 m68k_read32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
165 pc = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
166 cycles 10
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
167 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
168
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
169
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
170
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
171 m68k_interrupt
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
172 if cycles >=U int_cycle
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
173
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
174 #INT_PENDING_NONE
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
175 if 255 = int_pending
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
176 int_pending = int_priority
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
177 int_pending_num = int_num
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
178 else
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
179 #INT_PENDING_SR_CHANGE
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
180 if 254 = int_pending
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
181 int_pending = int_priority
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
182 int_pending_num = int_num
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
183
2580
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
184 end
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
185
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
186 check_user_mode_swap_ssp_usp
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
187
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
188 cycles 6
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
189 #save status reg
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
190 a7 -= 6
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
191 m68k_get_sr
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
192 scratch2 = a7
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
193 ocall write_16
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
194
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
195 #update status register
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
196 status &= 0x78
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
197 status |= int_pending
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
198 status |= 0x20
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
199
2580
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
200 #Interrupt ack cycle
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
201 int_ack = int_pending
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
202 cycles 4
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
203 if int_ack_handler
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
204 pcall int_ack_handler int_ack_fun context
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
205 end
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
206 if int_pending_num
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
207 else
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
208 int_pending_num = int_pending + 24
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
209 end
2580
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
210
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
211 #save pc
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
212 scratch2 = a7 + 2
2618
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
213 if stopped
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
214 scratch1 = pc
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
215 stopped = 0
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
216 else
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
217 scratch1 = pc - 2
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
218 end
2580
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
219 m68k_write32_lowfirst scratch1
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
220
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
221 scratch1 = int_pending_num << 2
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
222 int_pending = 255 #INT_PENDING_NONE
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
223 int_pending_num = 0
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
224 m68k_read32
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
225 mov scratch1 pc
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
226 m68k_prefetch
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
227 update_sync
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
228 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
229 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
230
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
231 m68k_run_op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
232 dispatch prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
233
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
234 m68k_mem_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235 arg address 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
236 arg size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
237 arg isdst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238 mov address scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
239 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
240 mov address scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
241 meta ismem 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
242 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
243 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
244
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
245 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
246 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
247
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
248 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
249 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
250
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
251 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
252 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
253
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
254 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
255 meta op scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
256
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
257 m68k_write_size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
258 arg size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
259 arg lowfirst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
260 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
261 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
262 ocall write_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
263
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
264 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
265 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
266
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
267 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
268 if lowfirst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
269 m68k_write32_lowfirst scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
270 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
271 m68k_write32 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
272 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
273 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
274
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
275 m68k_index_word
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
276 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
277 local disp 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
278 and prefetch 255 disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
279 sext 16 disp disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
280 sext 32 disp disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
281 local index 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
282 lsr prefetch 12 index
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
283 local isareg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
284 and index 8 isareg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
285 and index 7 index
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
286 local islong 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
287 and prefetch 2048 islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
288
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
289 switch isareg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
290 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
291 switch islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
292 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
293 sext 32 dregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
294 case 2048
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
295 mov dregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
296 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
297 case 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
298 switch islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
299 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
300 sext 32 aregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
301 case 2048
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
302 mov aregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
303 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
304 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
305 add disp scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
306
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
307 m68k_fetch_op_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
308 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
309 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
310 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
311 arg isdst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
312 switch mode
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
313
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
314 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
315 #data reg direct
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
316 meta op dregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
317 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
318 meta ismem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
319 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
320
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
321 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
322 #address reg direct
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
323 meta op aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
324 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
325 meta ismem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
326 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
327
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
328 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
329 #address reg indirect
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
330 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
331
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
332 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
333 #postincrement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
334 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
335 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
336 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
337 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
338 addsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
339 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
340 addsize 1 aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
341 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
342 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
343 addsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
344 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
345
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
346 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
347 #predecrement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
348 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
349 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
350 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
351 decsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
352 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
353 decsize 1 aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
354 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
355 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
356 decsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
357 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
358 cycles 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
359 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
360
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
361 case 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
362 #displacement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
363 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
364 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
365 add scratch1 aregs.reg scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
366 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
367
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
368 case 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
369 #indexed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
370 m68k_index_word
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
371 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
372 add aregs.reg scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
373
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
374 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
375 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
376 #pc-relative and absolute modes
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
377
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
378 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
379 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
380 #absolute short
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
381 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
382 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
383 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
384
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
385 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
386 #absolute long
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
387 local address 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
388 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
389 lsl prefetch 16 address
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
390 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
391 or prefetch address scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
392 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
393
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
394 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
395 #pc displaceent
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
396 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
397 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
398 add scratch1 pc scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
399 sub 2 scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
400 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
401
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
402 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
403 #pc indexed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
404 m68k_index_word
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
405 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
406 add pc scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
407 sub 2 scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
408 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
409
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
410 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
411 #immediate
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
412 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
413 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
414 local tmp32 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
415 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
416 lsl prefetch 16 tmp32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
417 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
418 or prefetch tmp32 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
419
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
420 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
421 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
422 mov prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
423 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
424 meta op scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
425
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
426 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
427
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
428 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
429
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
430 m68k_fetch_src_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
431 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
432 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
433 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
434 m68k_fetch_op_ea mode reg Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
435 meta src op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
436 switch mode
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
437 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
438 meta src_is_mem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
439 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
440 meta src_is_mem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
441 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
442 meta src_is_mem 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
443 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
444
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
445 m68k_fetch_dst_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
446 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
447 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
448 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
449 m68k_fetch_op_ea mode reg Z 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
450 meta dst op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
451
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
452 m68k_save_dst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
453 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
454 if ismem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
455 m68k_write_size Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
456 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
457
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
458 1101DDD0ZZMMMRRR add_ea_dn
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
459 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
460 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
461 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
462 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
463 m68k_fetch_src_ea M R Z
2671
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
464 if Z = 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
465 switch M
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
466 case 0
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
467 #dreg src
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
468 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
469 case 1
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
470 #areg src
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
471 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
472 case 7
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
473 if R = 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
474 #immediate
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
475 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
476 else
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
477 cycles 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
478 end
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
479 default
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
480 cycles 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
481 end
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
482 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
483
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
484 add src dregs.D dregs.D Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
485 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
486 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
487
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
488 1101DDD1ZZMMMRRR add_dn_ea
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
489 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
490 invalid M 1
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
491 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
492 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
493 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
494 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
495 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
496 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
497 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
498 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
499
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
500 add dregs.D dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
501 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
502 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
503 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
505 1101AAAZ11MMMRRR adda
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
506 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
507 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
508 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
509 local size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
510 local ext_src 32
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
511 #TODO: ensure "penalty" cycles are in the right place
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
512 if Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
513 size = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
514 switch M
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
515 case 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
516 #dreg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
517 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
518 case 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
519 #areg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
520 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
521 case 7
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
522 if R = 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
523 #immediate
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
524 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
525 else
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
526 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
527 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
528 default
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
529 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
530 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
531 else
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
532 size = 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
533 cycles 4
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
534 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
535 m68k_fetch_src_ea M R size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
536 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
537 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
538 sext 32 src ext_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
539 meta src ext_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
540 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
541
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
542 add src aregs.A aregs.A
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
543 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
544
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
545 00000110ZZMMMRRR addi
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
546 local immed 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
547 invalid Z 3
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
548 invalid M 1
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
549 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
550 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
551 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
552 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
553 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
554 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
555 #fetch immediate operand
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
556 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
557 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
558 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
559 lsl prefetch 16 immed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
560 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
561 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
562 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
563 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
564 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
565 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
566 mov prefetch immed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
567 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
568 #fetch dst EA
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
569 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
570
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
571 add immed dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
572 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
573 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
574 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
575
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
576 0101III0ZZMMMRRR addq
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
577 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
578 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
579 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
580 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
581 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
582 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
583 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
584 local src 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
585 switch I
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
586 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
587 mov 8 src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
588 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
589 mov I src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
590 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
591
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
592 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
593 switch M
2671
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
594 case 0
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
595 if Z = 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
596 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
597 end
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
598 add src dst dst Z
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
599 update_flags XNZVC
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
600 case 1
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
601 cycles 4
2647
3c689000e571 Fix addq.w and subq.w with address register destination in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2646
diff changeset
602 add src dst dst 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
603 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
604 add src dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
605 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
606 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
607 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
608 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
609
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
610 1101DDD1ZZ000SSS addx_dy_dx
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
611 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
612 adc dregs.S dregs.D dregs.D Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
613 update_flags XNVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
614 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
615 case 0
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
616 local tmp8 8
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
617 mov dregs.D tmp8
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
618 if tmp8
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
619 update_flags Z0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
620 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
621 case 1
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
622 local tmp16 16
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
623 mov dregs.D tmp16
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
624 if tmp16
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
625 update_flags Z0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
626 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
627 case 2
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
628 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
629 if dregs.D
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
630 update_flags Z0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
631 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
632 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
633 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
634
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
635 1101DDD1ZZ001SSS addx_ay_ax
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
636 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
637 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
638 decsize Z aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
639 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
640 switch S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
641 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
642 sub 2 aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
643 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
644 decsize Z aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
645 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
646 end
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
647 #predec penalty on src only
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
648 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
649 mov aregs.S scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
650 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
651 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
652 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
653 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
654 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
655 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
656 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
657 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
658 mov scratch1 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
659 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
660 decsize Z aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
661 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
662 switch D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
663 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
664 sub 2 aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
665 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
666 decsize Z aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
667 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
668 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
669 mov aregs.D scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
670 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
671 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
672 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
673 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
674 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
675 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
676 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
677 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
678 adc scratch2 scratch1 scratch1 Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
679 update_flags XNVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
680 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
681 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
682 local tmp8 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
683 mov dregs.D tmp8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
684 if tmp8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
685 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
686 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
687 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
688 local tmp16 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
689 mov dregs.D tmp16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
690 if tmp16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
691 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
692 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
693 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
694 if dregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
695 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
696 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
697 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
698 mov aregs.D scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
699 m68k_write_size Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
700 m68k_prefetch
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
701
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
702 1100DDD0ZZMMMRRR and_ea_dn
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
703 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
704 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
705 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
706 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
707 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
708 m68k_fetch_src_ea M R Z
2671
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
709 if Z = 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
710 switch M
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
711 case 0
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
712 #dreg src
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
713 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
714 case 1
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
715 #areg src
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
716 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
717 case 7
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
718 if R = 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
719 #immediate
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
720 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
721 else
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
722 cycles 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
723 end
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
724 default
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
725 cycles 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
726 end
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
727 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
728
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
729 and src dregs.D dregs.D Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
730 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
731 m68k_prefetch
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
732
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
733 1100XXX100000YYY abcd_dy_dx
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
734 local lowx_corf 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
735 local lowy_cmp 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
736 local res 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
737 lowx_corf = dregs.X & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
738 lowy_cmp = dregs.Y & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
739 adc lowx_corf lowy_cmp lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
740 if lowy_cmp >=U 0xA
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
741 lowx_corf = 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
742 lowy_cmp = 0x9A
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
743 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
744 lowx_corf = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
745 lowy_cmp = 0xA0
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
746 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
747 adc dregs.Y dregs.X res 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
748 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
749 if cflag
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
750 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
751 res += lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
752 update_flags NV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
753 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
754 if res >=U lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
755 lowx_corf |= 0x60
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
756 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
757 res += lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
758 update_flags XCNV
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
759 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
760 if res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
761 update_flags Z0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
762 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
763 dregs.X:0 = res
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
764 cycles 2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
765 m68k_prefetch
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
766
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
767 1100XXX100001YYY abcd_ay_ax
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
768 local lowx_corf 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
769 local lowy_cmp 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
770 local res 8
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
771 if Y = 7
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
772 aregs.Y -= 2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
773 else
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
774 aregs.Y -= 1
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
775 end
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
776 #predec penalty on src only
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
777 cycles 2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
778 scratch1 = aregs.Y
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
779 ocall read_8
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
780 scratch2 = scratch1
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
781 if X = 7
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
782 aregs.X -= 2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
783 else
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
784 aregs.X -= 1
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
785 end
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
786 scratch1 = aregs.X
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
787 ocall read_8
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
788 lowx_corf = scratch1 & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
789 lowy_cmp = scratch2 & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
790 adc lowx_corf lowy_cmp lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
791 if lowy_cmp >=U 0xA
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
792 lowx_corf = 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
793 lowy_cmp = 0x9A
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
794 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
795 lowx_corf = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
796 lowy_cmp = 0xA0
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
797 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
798 adc scratch2 scratch1 res 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
799 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
800 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
801 if cflag
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
802 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
803 res += lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
804 update_flags NV
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
805 else
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
806 if res >=U lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
807 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
808 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
809 res += lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
810 update_flags XCNV
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
811 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
812 if res
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
813 update_flags Z0
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
814 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
815 scratch1 = res
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
816 scratch2 = aregs.X
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
817 ocall write_8
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
818 m68k_prefetch
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
819
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
820 1100XXX101000YYY exg_dn_dn
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
821 scratch1 = dregs.X
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
822 dregs.X = dregs.Y
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
823 dregs.Y = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
824 cycles 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
825 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
826
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
827 1100XXX101001YYY exg_an_an
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
828 scratch1 = aregs.X
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
829 aregs.X = aregs.Y
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
830 aregs.Y = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
831 cycles 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
832 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
833
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
834 1100XXX110001YYY exg_dn_an
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
835 scratch1 = dregs.X
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
836 dregs.X = aregs.Y
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
837 aregs.Y = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
838 cycles 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
839 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
840
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
841 1100DDD011MMMRRR mulu
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
842 local a 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
843 local b 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
844 invalid M 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
845 invalid M 7 R 5
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
846 invalid M 7 R 6
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
847 invalid M 7 R 7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
848
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
849 m68k_fetch_src_ea M R 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
850 #2-cycles per bit x 16, 2 for cleanup
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
851 cycles 34
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
852 #popcnt
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
853 a = src & 0b1010101010101010
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
854 a >>= 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
855 b = src & 0b0101010101010101
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
856 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
857 a = b & 0b1100110011001100
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
858 a >>= 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
859 b &= 0b0011001100110011
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
860 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
861 a = b & 0b1111000011110000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
862 a >>= 4
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
863 b &= 0b0000111100001111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
864 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
865 a = b & 0b1111111100000000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
866 a >>= 8
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
867 b &= 0b0000000011111111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
868 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
869 #2 cycles per set bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
870 b += b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
871 cycles b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
872 dregs.D = src * dregs.D
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
873 update_flags NZV0C0
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
874 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
875
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
876 1100DDD111MMMRRR muls
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
877 local a 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
878 local b 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
879 invalid M 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
880 invalid M 7 R 5
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
881 invalid M 7 R 6
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
882 invalid M 7 R 7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
883
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
884 m68k_fetch_src_ea M R 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
885 #2-cycles per bit x 16, 2 for cleanup
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
886 cycles 34
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
887 #muls timing is essentially the same as muls, but it's based on the number of 0/1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
888 #transitions rather than the number of 1 bits. xoring the value with itself shifted
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
889 #by one effectively sets one bit for every transition
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
890 b = src << 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
891 b ^= src
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
892 #popcnt
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
893 a = b & 0b1010101010101010
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
894 a >>= 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
895 b &= 0b0101010101010101
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
896 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
897 a = b & 0b1100110011001100
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
898 a >>= 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
899 b &= 0b0011001100110011
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
900 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
901 a = b & 0b1111000011110000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
902 a >>= 4
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
903 b &= 0b0000111100001111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
904 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
905 a = b & 0b1111111100000000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
906 a >>= 8
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
907 b &= 0b0000000011111111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
908 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
909 #2 cycles per set bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
910 b += b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
911 cycles b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
912 dregs.D = src *S dregs.D
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
913 update_flags NZV0C0
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
914 m68k_prefetch
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
915
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
916 1100DDD1ZZMMMRRR and_dn_ea
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
917 invalid M 0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
918 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
919 invalid M 7 R 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
920 invalid M 7 R 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
921 invalid M 7 R 4
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
922 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
923 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
924 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
925 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
926 m68k_fetch_dst_ea M R Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
927
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
928 and dregs.D dst dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
929 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
930 m68k_save_dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
931 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
932
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
933 00000010ZZMMMRRR andi
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
934 local immed 32
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
935 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
936 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
937 invalid M 7 R 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
938 invalid M 7 R 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
939 invalid M 7 R 4
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
940 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
941 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
942 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
943 #fetch immediate operand
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
944 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
945 switch Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
946 case 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
947 lsl prefetch 16 immed
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
948 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
949 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
950 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
951 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
952 end
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
953 default
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
954 mov prefetch immed
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
955 end
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
956 #fetch dst EA
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
957 m68k_fetch_dst_ea M R Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
958
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
959 and immed dst dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
960 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
961 m68k_save_dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
962 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
963
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
964 0000001000111100 andi_to_ccr
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
965 #fetch immediate operand
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
966 m68k_prefetch
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
967 ccr &= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
968 cycles 12 #TODO: where do these occur relative to fetches
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
969 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
970
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
971 0000001001111100 andi_to_sr
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
972 #TODO: privilege violation exception if in user mode
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
973 #fetch immediate operand
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
974 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
975 ccr &= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
976 scratch1 = prefetch >> 8
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
977 status &= scratch1
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
978 check_user_mode_swap_ssp_usp
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
979 update_sync
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
980 cycles 12 #TODO: where do these occur relative to fetches
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
981 m68k_prefetch
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
982
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
983 1011DDD1ZZMMMRRR eor_dn_ea
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
984 invalid M 1
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
985 invalid M 7 R 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
986 invalid M 7 R 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
987 invalid M 7 R 4
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
988 invalid M 7 R 5
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
989 invalid M 7 R 6
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
990 invalid M 7 R 7
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
991 invalid Z 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
992 m68k_fetch_dst_ea M R Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
993
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
994 if Z = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
995 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
996 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
997 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
998 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
999
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1000 xor dregs.D dst dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1001 update_flags NZV0C0
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1002 m68k_save_dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1003 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1004
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1005 00001010ZZMMMRRR eori
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1006 local immed 32
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1007 invalid Z 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1008 invalid M 1
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1009 invalid M 7 R 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1010 invalid M 7 R 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1011 invalid M 7 R 4
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1012 invalid M 7 R 5
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1013 invalid M 7 R 6
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1014 invalid M 7 R 7
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1015 #fetch immediate operand
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1016 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1017 switch Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1018 case 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1019 lsl prefetch 16 immed
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1020 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1021 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1022 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1023 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1024 end
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1025 default
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1026 mov prefetch immed
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1027 end
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1028 #fetch dst EA
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1029 m68k_fetch_dst_ea M R Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1030
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1031 xor immed dst dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1032 update_flags NZV0C0
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1033 m68k_save_dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1034 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1035
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1036 0000101000111100 eori_to_ccr
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1037 #fetch immediate operand
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1038 m68k_prefetch
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1039 ccr ^= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1040 cycles 12 #TODO: where do these occur relative to fetches
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1041 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1042
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1043 0000101001111100 eori_to_sr
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1044 #TODO: privilege violation exception if in user mode
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1045 #fetch immediate operand
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1046 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1047 ccr ^= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1048 scratch1 = prefetch >> 8
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1049 status ^= scratch1
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1050 check_user_mode_swap_ssp_usp
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1051 update_sync
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1052 cycles 12 #TODO: where do these occur relative to fetches
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1053 m68k_prefetch
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1054
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1055 1000DDD0ZZMMMRRR or_ea_dn
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1056 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1057 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1058 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1059 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1060 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1061 m68k_fetch_src_ea M R Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1062
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1063 if Z = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1064 switch M
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1065 case 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1066 #dreg
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1067 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1068 case 7
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1069 if R = 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1070 #immediate
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1071 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1072 else
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1073 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1074 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1075 default
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1076 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1077 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1078 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1079
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1080 or src dregs.D dregs.D Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1081 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1082 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1083
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1084 1000DDD1ZZMMMRRR or_dn_ea
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1085 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1086 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1087 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1088 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1089 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1090 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1091 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1092 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1093 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1094 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1095
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1096 or dregs.D dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1097 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1098 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1099 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1100
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1101 00000000ZZMMMRRR ori
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1102 local immed 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1103 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1104 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1105 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1106 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1107 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1108 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1109 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1110 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1111 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1112 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1113 switch Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1114 case 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1115 lsl prefetch 16 immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1116 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1117 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1118 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1119 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1120 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1121 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1122 mov prefetch immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1123 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1124 #fetch dst EA
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1125 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1126
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1127 or immed dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1128 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1129 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1130 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1131
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1132 0000000000111100 ori_to_ccr
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1133 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1134 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1135 or prefetch ccr ccr
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1136 cycles 12 #TODO: where do these occur relative to fetches
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1137 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1138
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1139 0000000001111100 ori_to_sr
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1140 #TODO: privilege violation exception if in user mode
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1141 #fetch immediate operand
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1142 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1143 ccr |= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1144 scratch1 = prefetch >> 8
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1145 status |= scratch1
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1146 update_sync
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1147 cycles 12 #TODO: where do these occur relative to fetches
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1148 m68k_prefetch
2587
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1149
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1150 1000YYY100000XXX sbcd_dx_dy
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1151 local lowx_corf 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1152 local lowy 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1153 local res 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1154 lowx_corf = dregs.X & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1155 lowy = dregs.Y & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1156 sbc lowx_corf lowy lowy
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1157 if lowy >=U 0x10
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1158 lowx_corf = 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1159 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1160 lowx_corf = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1161 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1162 sbc dregs.X dregs.Y res 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1163 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1164 if cflag
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1165 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1166 res -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1167 update_flags NV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1168 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1169 res -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1170 update_flags XCNV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1171 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1172 if res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1173 update_flags Z0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1174 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1175 dregs.Y:0 = res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1176 cycles 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1177 m68k_prefetch
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1178
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1179 1000YYY100001XXX sbcd_ax_ay
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1180 local lowx_corf 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1181 local lowy 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1182 if X = 7
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1183 aregs.X -= 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1184 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1185 aregs.X -= 1
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1186 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1187 #predec penalty on src only
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1188 cycles 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1189 scratch1 = aregs.X
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1190 ocall read_8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1191 scratch2 = scratch1
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1192 if Y = 7
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1193 aregs.Y -= 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1194 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1195 aregs.Y -= 1
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1196 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1197 scratch1 = aregs.Y
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1198 ocall read_8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1199 lowy = scratch1 & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1200 lowx_corf = scratch2 & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1201 sbc lowx_corf lowy lowy
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1202 if lowy >=U 0x10
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1203 lowx_corf = 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1204 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1205 lowx_corf = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1206 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1207 sbc scratch2 scratch1 scratch1 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1208 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1209 if cflag
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1210 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1211 scratch1:0 -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1212 update_flags NV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1213 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1214 scratch1:0 -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1215 update_flags XCNV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1216 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1217 scratch1 &= 0xFF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1218 if scratch1
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1219 update_flags Z0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1220 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1221 scratch2 = aregs.Y
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1222 ocall write_8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1223 m68k_prefetch
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1224
2587
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1225 1000DDD011MMMRRR divu
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1226 invalid M 1
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1227 invalid M 7 R 5
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1228 invalid M 7 R 6
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1229 invalid M 7 R 7
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1230 m68k_fetch_src_ea M R 1
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1231
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1232 if src = 0
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1233 cycles 4
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1234 update_flags N0Z0V0
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1235 m68k_trap 5
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1236 else
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1237 ccall divu context D src
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1238 m68k_prefetch
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1239 end
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1240
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1241
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1242 1000DDD111MMMRRR divs
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1243 invalid M 1
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1244 invalid M 7 R 5
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1245 invalid M 7 R 6
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1246 invalid M 7 R 7
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1247 local tmp 32
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1248 m68k_fetch_src_ea M R 1
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1249
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1250 if src = 0
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1251 cycles 4
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1252 update_flags N0Z0V0
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1253 m68k_trap 5
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1254 else
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1255 ccall divs context D src
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1256 m68k_prefetch
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1257 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1258
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1259 1001DDD0ZZMMMRRR sub_ea_dn
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1260 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1261 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1262 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1263 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1264 m68k_fetch_src_ea M R Z
2671
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1265 if Z = 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1266 switch M
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1267 case 0
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1268 #dreg src
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1269 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1270 case 1
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1271 #areg src
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1272 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1273 case 7
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1274 if R = 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1275 #immediate
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1276 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1277 else
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1278 cycles 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1279 end
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1280 default
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1281 cycles 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1282 end
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1283 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1284
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1285 sub src dregs.D dregs.D Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1286 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1287 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1288
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1289 1001DDD1ZZMMMRRR sub_dn_ea
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1290 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1291 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1292 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1293 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1294 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1295 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1296 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1297 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1298 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1299 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1300
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1301 sub dregs.D dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1302 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1303 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1304 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1305
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1306 1001AAAZ11MMMRRR suba
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1307 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1308 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1309 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1310 local size 16
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1311 local ext_src 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1312 if Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1313 size = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1314 switch M
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1315 case 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1316 #dreg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1317 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1318 case 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1319 #areg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1320 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1321 case 7
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1322 if R = 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1323 #immediate
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1324 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1325 else
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1326 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1327 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1328 default
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1329 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1330 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1331 else
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1332 size = 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1333 cycles 4
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1334 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1335 m68k_fetch_src_ea M R size
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1336 switch size
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1337 case 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1338 sext 32 src ext_src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1339 meta src ext_src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1340 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1341
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1342 sub src aregs.A aregs.A
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1343 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1344
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1345 00000100ZZMMMRRR subi
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1346 local immed 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1347 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1348 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1349 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1350 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1351 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1352 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1353 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1354 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1355 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1356 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1357 switch Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1358 case 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1359 lsl prefetch 16 immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1360 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1361 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1362 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1363 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1364 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1365 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1366 mov prefetch immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1367 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1368 #fetch dst EA
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1369 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1370
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1371 sub immed dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1372 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1373 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1374 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1375
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1376 0101III1ZZMMMRRR subq
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1377 invalid Z 3
2647
3c689000e571 Fix addq.w and subq.w with address register destination in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2646
diff changeset
1378 invalid M 1 Z 0
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1379 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1380 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1381 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1382 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1383 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1384 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1385 local src 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1386 switch I
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1387 case 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1388 mov 8 src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1389 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1390 mov I src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1391 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1392
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1393 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1394 switch M
2671
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1395 case 0
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1396 if Z = 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1397 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1398 end
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1399 sub src dst dst Z
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1400 update_flags XNZVC
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1401 case 1
2671
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1402 cycles 4
2647
3c689000e571 Fix addq.w and subq.w with address register destination in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2646
diff changeset
1403 sub src dst dst 2
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1404 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1405 sub src dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1406 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1407 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1408 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1409 m68k_prefetch
2586
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1410
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1411 1001DDD1ZZ000SSS subx_dy_dx
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1412 invalid Z 3
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1413 sbc dregs.S dregs.D dregs.D Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1414 update_flags XNVC
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1415 switch Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1416 case 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1417 local tmp8 8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1418 mov dregs.D tmp8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1419 if tmp8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1420 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1421 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1422 case 1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1423 local tmp16 16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1424 mov dregs.D tmp16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1425 if tmp16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1426 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1427 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1428 case 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1429 cycles 4
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1430 if dregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1431 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1432 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1433 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1434 m68k_prefetch
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1435
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1436 1001DDD1ZZ001SSS subx_ay_ax
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1437 invalid Z 3
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1438 if Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1439 decsize Z aregs.S aregs.S
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1440 else
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1441 switch S
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1442 case 7
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1443 sub 2 aregs.S aregs.S
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1444 default
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1445 decsize Z aregs.S aregs.S
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1446 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1447 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1448 #predec penalty on src only
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1449 cycles 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1450 mov aregs.S scratch1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1451 switch Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1452 case 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1453 ocall read_8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1454 case 1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1455 ocall read_16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1456 case 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1457 m68k_read32
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1458 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1459 mov scratch1 scratch2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1460 if Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1461 decsize Z aregs.D aregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1462 else
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1463 switch D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1464 case 7
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1465 sub 2 aregs.D aregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1466 default
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1467 decsize Z aregs.D aregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1468 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1469 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1470 mov aregs.D scratch1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1471 switch Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1472 case 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1473 ocall read_8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1474 case 1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1475 ocall read_16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1476 case 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1477 m68k_read32
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1478 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1479 sbc scratch2 scratch1 scratch1 Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1480 update_flags XNVC
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1481 switch Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1482 case 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1483 local tmp8 8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1484 mov dregs.D tmp8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1485 if tmp8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1486 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1487 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1488 case 1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1489 local tmp16 16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1490 mov dregs.D tmp16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1491 if tmp16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1492 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1493 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1494 case 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1495 if dregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1496 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1497 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1498 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1499 mov aregs.D scratch2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1500 m68k_write_size Z 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1501 m68k_prefetch
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1502
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1503 1110CCC0ZZ001RRR lsri
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1504 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1505 switch C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1506 case 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1507 meta shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1508 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1509 meta shift C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1510 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1511 lsr dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1512 update_flags XNZV0C
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1513 local cyc 32
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1514 cyc = shift + shift
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1515 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1516 case 2
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1517 cyc += 4
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1518 default
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1519 cyc += 2
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1520 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1521 cycles cyc
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1522 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1523 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1524
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1525 1110CCC0ZZ101RRR lsr_dn
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1526 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1527 local shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1528 and dregs.C 63 shift
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1529 switch Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1530 case 2
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1531 if shift >=U 32
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1532 if shift = 32
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1533 lsr dregs.R 31 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1534 lsr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1535 update_flags XN0Z1V0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1536 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1537 dregs.R:Z = 0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1538 update_flags X0N0Z1V0C0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1539 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1540 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1541 lsr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1542 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1543 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1544 xflag = cflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1545 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1546 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1547 case 1
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1548 if shift >=U 16
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1549 if shift = 16
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1550 lsr dregs.R 15 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1551 lsr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1552 update_flags XN0Z1V0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1553 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1554 dregs.R:Z = 0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1555 update_flags X0N0Z1V0C0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1556 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1557 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1558 lsr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1559 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1560 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1561 xflag = cflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1562 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1563 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1564 case 0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1565 if shift >=U 8
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1566 if shift = 8
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1567 lsr dregs.R 7 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1568 lsr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1569 update_flags XN0Z1V0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1570 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1571 dregs.R:Z = 0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1572 update_flags X0N0Z1V0C0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1573 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1574 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1575 lsr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1576 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1577 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1578 xflag = cflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1579 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1580 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1581 end
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1582 add shift shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1583 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1584 case 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1585 add 4 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1586 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1587 add 2 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1588 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1589 cycles shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1590 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1591 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1592
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1593 1110001011MMMRRR lsr_ea
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1594 invalid M 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1595 invalid M 1
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1596 invalid M 7 R 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1597 invalid M 7 R 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1598 invalid M 7 R 4
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1599 invalid M 7 R 5
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1600 invalid M 7 R 6
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1601 invalid M 7 R 7
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1602
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1603 m68k_fetch_dst_ea M R 1
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1604 lsr dst 1 dst 1
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1605 update_flags XNZV0C
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1606 m68k_save_dst 1
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1607 m68k_prefetch
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1608
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1609 1110CCC0ZZ000RRR asri
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1610 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1611 switch C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1612 case 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1613 meta shift 8
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1614 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1615 meta shift C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1616 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1617 asr dregs.R shift dregs.R Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1618 update_flags XNZV0C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1619 local cyc 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1620 cyc = shift + shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1621 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1622 case 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1623 cyc += 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1624 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1625 cyc += 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1626 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1627 cycles cyc
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1628 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1629 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1630
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1631 1110CCC0ZZ100RRR asr_dn
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1632 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1633 local shift 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1634 and dregs.C 63 shift
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1635 switch Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1636 case 2
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1637 if shift >=U 32
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1638 asr dregs.R 31 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1639 asr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1640 update_flags NZV0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1641 cflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1642 xflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1643 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1644 asr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1645 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1646 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1647 xflag = cflag
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1648 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1649 end
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1650 case 1
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1651 if shift >=U 16
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1652 asr dregs.R 15 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1653 asr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1654 update_flags NZV0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1655 cflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1656 xflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1657 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1658 asr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1659 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1660 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1661 xflag = cflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1662 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1663 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1664 case 0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1665 if shift >=U 8
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1666 asr dregs.R 7 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1667 asr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1668 update_flags NZV0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1669 cflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1670 xflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1671 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1672 asr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1673 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1674 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1675 xflag = cflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1676 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1677 end
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1678 end
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1679 shift += shift
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1680 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1681 case 2
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1682 shift += 4
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1683 default
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1684 shift += 2
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1685 end
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1686 cycles shift
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1687 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1688 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1689
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1690 1110000011MMMRRR asr_ea
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1691 invalid M 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1692 invalid M 1
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1693 invalid M 7 R 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1694 invalid M 7 R 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1695 invalid M 7 R 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1696 invalid M 7 R 5
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1697 invalid M 7 R 6
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1698 invalid M 7 R 7
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1699
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1700 m68k_fetch_dst_ea M R 1
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1701 asr dst 1 dst 1
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1702 update_flags XNZV0C
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1703 m68k_save_dst 1
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1704 m68k_prefetch
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1705
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1706 1110CCC1ZZ001RRR lsli
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1707 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1708 switch C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1709 case 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1710 meta shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1711 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1712 meta shift C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1713 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1714 lsl dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1715 update_flags XNZV0C
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1716 local cyc 32
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1717 cyc = shift + shift
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1718 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1719 case 2
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1720 cyc += 4
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1721 default
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1722 cyc += 2
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1723 end
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1724 cycles cyc
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1725 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1726 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1727
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1728 1110CCC1ZZ101RRR lsl_dn
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1729 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1730 local shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1731 and dregs.C 63 shift
2610
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1732 switch Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1733 case 2
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1734 if shift >=U 32
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1735 if shift = 32
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1736 lsl dregs.R 31 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1737 lsl dregs.R 1 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1738 update_flags XN0Z1V0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1739 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1740 dregs.R:Z = 0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1741 update_flags X0N0Z1V0C0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1742 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1743 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1744 lsl dregs.R shift dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1745 update_flags NZV0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1746 if shift
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1747 xflag = cflag
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1748 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1749 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1750 case 1
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1751 if shift >=U 16
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1752 if shift = 16
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1753 lsl dregs.R 15 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1754 lsl dregs.R 1 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1755 update_flags XN0Z1V0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1756 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1757 dregs.R:Z = 0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1758 update_flags X0N0Z1V0C0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1759 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1760 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1761 lsl dregs.R shift dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1762 update_flags NZV0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1763 if shift
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1764 xflag = cflag
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1765 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1766 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1767 case 0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1768 if shift >=U 8
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1769 if shift = 8
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1770 lsl dregs.R 7 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1771 lsl dregs.R 1 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1772 update_flags XN0Z1V0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1773 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1774 dregs.R:Z = 0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1775 update_flags X0N0Z1V0C0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1776 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1777 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1778 lsl dregs.R shift dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1779 update_flags NZV0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1780 if shift
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1781 xflag = cflag
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1782 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1783 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1784 end
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1785 add shift shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1786 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1787 case 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1788 add 4 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1789 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1790 add 2 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1791 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1792 cycles shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1793 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1794 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1795
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1796 1110001111MMMRRR lsl_ea
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1797 invalid M 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1798 invalid M 1
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1799 invalid M 7 R 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1800 invalid M 7 R 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1801 invalid M 7 R 4
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1802 invalid M 7 R 5
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1803 invalid M 7 R 6
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1804 invalid M 7 R 7
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1805
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1806 m68k_fetch_dst_ea M R 1
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1807 lsl dst 1 dst 1
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1808 update_flags XNZV0C
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1809 m68k_save_dst 1
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1810 m68k_prefetch
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1811
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1812 1110CCC1ZZ000RRR asli
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1813 invalid Z 3
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1814 local vtmp 8
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1815 local shift 8
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1816 vtmp = 0
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1817 switch C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1818 case 0
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1819 shift = 8
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1820 default
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1821 shift = C
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1822 end
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1823 shift -= 1
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1824 loop shift
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1825 lsl dregs.R 1 dregs.R Z
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1826 update_flags V
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1827 vtmp |= vflag
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1828 end
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1829 shift += 1
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1830 lsl dregs.R 1 dregs.R Z
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1831 update_flags XNZVC
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1832 vflag |= vtmp
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1833 local cyc 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1834 cyc = shift + shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1835 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1836 case 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1837 cyc += 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1838 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1839 cyc += 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1840 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1841 cycles cyc
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1842 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1843 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1844
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1845 1110CCC1ZZ100RRR asl_dn
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1846 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1847 local shift 8
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1848 local vtmp 8
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1849 and dregs.C 63 shift
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1850 vtmp = 0
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1851 if shift
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1852 shift -= 1
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1853 loop shift
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1854 lsl dregs.R 1 dregs.R Z
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1855 update_flags V
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1856 vtmp |= vflag
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1857 end
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1858 shift += 1
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1859 lsl dregs.R 1 dregs.R Z
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1860 update_flags XNZVC
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1861 vflag |= vtmp
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1862 else
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1863 cmp 0 dregs.R Z
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1864 update_flags NZV0C
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1865 end
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1866 shift += shift
2610
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1867 switch Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1868 case 2
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1869 shift += 4
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1870 default
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1871 shift += 2
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1872 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1873 cycles shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1874 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1875 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1876
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1877 1110000111MMMRRR asl_ea
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1878 invalid M 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1879 invalid M 1
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1880 invalid M 7 R 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1881 invalid M 7 R 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1882 invalid M 7 R 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1883 invalid M 7 R 5
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1884 invalid M 7 R 6
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1885 invalid M 7 R 7
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1886
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1887 m68k_fetch_dst_ea M R 1
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1888 lsl dst 1 dst 1
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1889 update_flags XNZV0C
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1890 m68k_save_dst 1
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1891 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1892
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1893 00ZZRRRMMMEEESSS move
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1894 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1895 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1896 invalid M 7 #not actually invalid, but will be handled separately due to DSL limitations
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1897 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1898 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1899 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1900 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1901 local memsrc 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1902 #move uses a different size format than most instructions
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1903 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1904 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1905 mov 0 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1906 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1907 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1908 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1909 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1910 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1911 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1912
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1913 if src_is_mem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1914 #avoid clobbering src if we need scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1915 mov src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1916 meta src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1917 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1918
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1919 cmp 0 src size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1920 update_flags NZV0C0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1921
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1922 switch M
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1923 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1924 mov src dregs.R size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1925
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1926 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1927 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1928 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1929 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1930
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1931 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1932 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1933 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1934 switch R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1935 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1936 if size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1937 addsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1938 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1939 addsize 1 aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1940 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1941 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1942 addsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1943 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1944 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1945
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1946 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1947 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1948 switch R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1949 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1950 if size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1951 decsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1952 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1953 decsize 1 aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1954 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1955 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1956 decsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1957 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1958 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1959 m68k_write_size size 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1960
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1961 case 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1962 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1963 sext 32 prefetch scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1964 add aregs.R scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1965 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1966 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1967
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1968 case 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1969 m68k_index_word
2670
9bcfdc1b56bd Fix cycle timing for move with indexed destination
Michael Pavone <pavone@retrodev.com>
parents: 2666
diff changeset
1970 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1971 add aregs.R scratch1 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1972 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1973 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1974 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1975 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1976
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1977
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1978 00ZZ00M111EEESSS move_abs
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1979 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1980 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1981 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1982 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1983 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1984 local memsrc 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1985 #move uses a different size format than most instructions
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1986 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1987 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1988 mov 0 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1989 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1990 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1991 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1992 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1993 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1994 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1995
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1996 if src_is_mem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1997 #avoid clobbering src if we need scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1998 mov src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1999 meta src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2000 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2001
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2002 cmp 0 src size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2003 update_flags NZV0C0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2004
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2005 switch M
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2006 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2007 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2008 sext 32 prefetch scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2009
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2010 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2011 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2012 lsl prefetch 16 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2013 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2014 or prefetch scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2015 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2016 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2017 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2018 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2019
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2020 00ZZRRR001EEESSS movea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2021 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2022 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2023 invalid Z 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2024 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2025 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2026 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2027 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2028 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2029 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2030 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2031 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2032 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2033 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2034 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2035 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2036 mov src aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2037 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2038 sext 32 src aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2039 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2040 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2041
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2042 0100010011MMMRRR move_to_ccr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2043 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2044 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2045 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2046 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2047 m68k_fetch_src_ea M R 1
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2048 mov src ccr
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2049 cycles 8
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2050 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2051
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2052 0100011011MMMRRR move_to_sr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2053 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2054 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2055 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2056 invalid M 7 R 7
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2057 #TODO: privilege violation exception if in user mode
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2058 m68k_fetch_src_ea M R 1
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2059 ccr = src
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2060 status = src >> 8
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
2061 check_user_mode_swap_ssp_usp
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2062 update_sync
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2063 cycles 8
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2064 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2065
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2066 0100000011MMMRRR move_from_sr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2067 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2068 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2069 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2070 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2071 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2072 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2073 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2074 m68k_fetch_dst_ea M R 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2075 lsl status 8 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2076 or ccr scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2077 mov scratch1 dst
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2078 if M
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2079 cycles 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2080 else
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2081 cycles 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2082 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2083 m68k_save_dst 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2084 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2085
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2086 01000000ZZMMMRRR negx
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2087 invalid M 1
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2088 invalid M 7 R 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2089 invalid M 7 R 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2090 invalid M 7 R 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2091 invalid M 7 R 5
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2092 invalid M 7 R 6
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2093 invalid M 7 R 7
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2094 m68k_fetch_dst_ea M R Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2095 sbc dst 0 dst Z
2633
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2096 update_flags XNVC
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2097 switch Z
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2098 case 0
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2099 local tmp8 8
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2100 tmp8 = dst
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2101 if tmp8
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2102 update_flags Z0
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2103 end
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2104 case 1
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2105 local tmp16 16
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2106 tmp16 = dst
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2107 if tmp16
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2108 update_flags Z0
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2109 end
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2110 case 2
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2111 local tmp32 32
2464
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2112 if M = 0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2113 cycles 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2114 end
2633
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2115 tmp32 = dst
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2116 if dst
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2117 update_flags Z0
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2118 end
2464
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2119 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2120 m68k_save_dst Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2121 m68k_prefetch
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2122
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2123 01000010ZZMMMRRR clr
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2124 invalid M 1
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2125 invalid M 7 R 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2126 invalid M 7 R 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2127 invalid M 7 R 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2128 invalid M 7 R 5
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2129 invalid M 7 R 6
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2130 invalid M 7 R 7
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2131 invalid Z 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2132 m68k_fetch_dst_ea M R Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2133 if Z = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2134 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2135 #register clears have 2 cycle penalty for longword size
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2136 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2137 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2138 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2139 dst:Z = 0
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2140 update_flags N0Z1V0C0
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2141 m68k_save_dst Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2142 m68k_prefetch
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2143
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2144 0100100000MMMRRR nbcd
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2145 local lowx_corf 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2146 local lowy_cmp 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2147 local res 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2148 invalid M 1
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2149 invalid M 7 R 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2150 invalid M 7 R 3
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2151 invalid M 7 R 4
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2152 invalid M 7 R 5
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2153 invalid M 7 R 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2154 invalid M 7 R 7
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2155 m68k_fetch_dst_ea M R 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2156 lowx_corf = dst & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2157 lowy_cmp = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2158 sbc lowx_corf lowy_cmp lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2159 if lowy_cmp >= 0xA
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2160 lowx_corf = 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2161 lowy_cmp = 0xA6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2162 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2163 lowx_corf = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2164 lowy_cmp = 0xA0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2165 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2166 res = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2167 sbc dst res res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2168 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2169 if cflag
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2170 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2171 res -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2172 update_flags NV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2173 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2174 if res >=U lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2175 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2176 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2177 res -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2178 update_flags XCNV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2179 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2180 if res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2181 update_flags Z0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2182 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2183 dst:0 = res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2184 if M = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2185 cycles 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2186 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2187 m68k_save_dst 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2188 m68k_prefetch
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2189
2453
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2190 00001100ZZMMMRRR cmpi
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2191 local immed 32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2192 invalid Z 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2193 invalid M 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2194 invalid M 7 R 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2195 invalid M 7 R 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2196 invalid M 7 R 4
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2197 invalid M 7 R 5
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2198 invalid M 7 R 6
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2199 invalid M 7 R 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2200 #fetch immediate operand
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2201 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2202 switch Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2203 case 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2204 immed = prefetch << 16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2205 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2206 immed |= prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2207 if M = 0
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2208 cycles 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2209 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2210 default
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2211 immed = prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2212 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2213 #fetch dst EA
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2214 m68k_fetch_dst_ea M R Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2215
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2216 cmp immed dst Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2217 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2218 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2219
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2220 1011DDD1ZZ001SSS cmpm
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2221 invalid Z 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2222 scratch1 = aregs.S
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2223 switch Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2224 case 0
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2225 ocall read_8
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2226 case 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2227 ocall read_16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2228 case 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2229 m68k_read32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2230 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2231 scratch2 = scratch1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2232 if Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2233 addsize Z aregs.S aregs.S
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2234 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2235 if S = 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2236 aregs.S += 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2237 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2238 aregs.S += 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2239 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2240 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2241 scratch1 = aregs.D
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2242 switch Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2243 case 0
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2244 ocall read_8
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2245 case 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2246 ocall read_16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2247 case 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2248 m68k_read32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2249 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2250 if Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2251 addsize Z aregs.D aregs.D
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2252 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2253 if D = 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2254 aregs.D += 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2255 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2256 aregs.D += 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2257 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2258 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2259 cmp scratch2 scratch1 Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2260 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2261 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2262
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2263 1011DDD0ZZMMMRRR cmp
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2264 invalid M 7 R 5
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2265 invalid M 7 R 6
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2266 invalid M 7 R 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2267 invalid Z 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2268 m68k_fetch_src_ea M R Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2269
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2270 if Z = 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2271 cycles 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2272 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2273
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2274 cmp src dregs.D Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2275 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2276 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2277
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2278 1011DDDZ11MMMRRR cmpa
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2279 invalid M 7 R 5
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2280 invalid M 7 R 6
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2281 invalid M 7 R 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2282 local size 16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2283 local ext_src 32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2284 if Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2285 size = 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2286 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2287 size = 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2288 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2289 m68k_fetch_src_ea M R size
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2290 cycles 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2291 if size = 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2292 sext 32 src ext_src
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2293 meta src ext_src
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2294 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2295 cmp src aregs.D
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2296 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2297 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2298
2454
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2299 0000100000MMMRRR btsti
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2300 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2301 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2302 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2303 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2304
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2305 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2306 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2307 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2308 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2309 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2310 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2311 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2312 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2313 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2314 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2315 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2316 m68k_fetch_src_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2317 tmp &= src
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2318 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2319 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2320
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2321 0000100001MMMRRR bchgi
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2322 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2323 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2324 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2325 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2326 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2327 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2328 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2329
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2330 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2331 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2332 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2333 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2334 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2335 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2336 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2337 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2338 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2339 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2340 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2341 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2342 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2343 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2344 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2345 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2346 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2347 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2348 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2349 dst ^= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2350 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2351 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2352
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2353 0000100010MMMRRR bclri
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2354 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2355 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2356 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2357 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2358 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2359 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2360 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2361
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2362 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2363 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2364 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2365 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2366 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2367 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2368 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2369 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2370 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2371 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2372 cycles 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2373 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2374 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2375 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2376 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2377 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2378 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2379 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2380 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2381 tmp = ~tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2382 dst &= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2383 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2384 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2385
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2386 0000100011MMMRRR bseti
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2387 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2388 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2389 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2390 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2391 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2392 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2393 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2394
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2395 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2396 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2397 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2398 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2399 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2400 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2401 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2402 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2403 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2404 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2405 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2406 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2407 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2408 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2409 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2410 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2411 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2412 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2413 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2414 dst |= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2415 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2416 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2417
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2418 0000SSS100MMMRRR btst_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2419 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2420 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2421 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2422 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2423
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2424 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2425 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2426 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2427 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2428 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2429 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2430 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2431 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2432 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2433 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2434 m68k_fetch_src_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2435 tmp &= src
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2436 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2437 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2438
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2439 0000SSS101MMMRRR bchg_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2440 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2441 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2442 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2443 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2444 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2445 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2446 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2447
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2448 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2449 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2450 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2451 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2452 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2453 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2454 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2455 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2456 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2457 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2458 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2459 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2460 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2461 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2462 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2463 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2464 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2465 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2466 dst ^= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2467 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2468 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2469
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2470 0000SSS110MMMRRR bclr_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2471 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2472 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2473 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2474 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2475 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2476 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2477 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2478
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2479 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2480 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2481 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2482 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2483 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2484 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2485 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2486 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2487 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2488 cycles 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2489 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2490 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2491 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2492 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2493 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2494 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2495 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2496 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2497 tmp = ~tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2498 dst &= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2499 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2500 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2501
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2502 0000SSS111MMMRRR bset_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2503 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2504 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2505 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2506 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2507 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2508 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2509 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2510
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2511 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2512 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2513 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2514 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2515 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2516 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2517 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2518 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2519 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2520 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2521 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2522 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2523 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2524 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2525 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2526 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2527 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2528 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2529 dst |= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2530 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2531 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2532
2456
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2533 0000DDD10Z001AAA movep_ay_dx
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2534 local address 32
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2535 m68k_prefetch
2639
0046305e3fa8 Fix movep with negative displacement
Michael Pavone <pavone@retrodev.com>
parents: 2636
diff changeset
2536 sext 32 scratch1 scratch1
2456
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2537 scratch1 += aregs.A
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2538 address = scratch1 + 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2539 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2540 dregs.D:1 = scratch1 << 8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2541 scratch1 = address
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2542 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2543 dregs.D:0 = scratch1
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2544 if Z
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2545 address += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2546 scratch1 = address
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2547 dregs.D <<= 16
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2548 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2549 dregs.D:1 = scratch1 << 8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2550 scratch1 = address + 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2551 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2552 dregs.D:0 = scratch1
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2553 end
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2554 m68k_prefetch
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2555
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2556 0000DDD11Z001AAA movep_dx_ay
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2557 m68k_prefetch
2639
0046305e3fa8 Fix movep with negative displacement
Michael Pavone <pavone@retrodev.com>
parents: 2636
diff changeset
2558 sext 32 scratch1 scratch1
2456
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2559 scratch2 = scratch1 + aregs.A
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2560 if Z
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2561 scratch1 = dregs.D >> 24
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2562 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2563 scratch2 += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2564 scratch1 = dregs.D >> 16
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2565 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2566 scratch2 += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2567 end
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2568 scratch1 = dregs.D >> 8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2569 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2570 scratch2 += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2571 scratch1 = dregs.D
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2572 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2573 m68k_prefetch
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2574
2464
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2575 01000100ZZMMMRRR neg
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2576 invalid Z 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2577 invalid M 1
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2578 invalid M 7 R 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2579 invalid M 7 R 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2580 invalid M 7 R 4
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2581 invalid M 7 R 5
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2582 invalid M 7 R 6
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2583 invalid M 7 R 7
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2584
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2585 m68k_fetch_dst_ea M R Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2586 dst:Z = -dst
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2587 update_flags XNZVC
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2588 if Z = 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2589 if M = 0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2590 cycles 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2591 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2592 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2593 m68k_save_dst Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2594 m68k_prefetch
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2595
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2596 01000110ZZMMMRRR not
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2597 invalid Z 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2598 invalid M 1
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2599 invalid M 7 R 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2600 invalid M 7 R 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2601 invalid M 7 R 4
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2602 invalid M 7 R 5
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2603 invalid M 7 R 6
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2604 invalid M 7 R 7
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2605
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2606 m68k_fetch_dst_ea M R Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2607 dst:Z = ~dst
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2608 update_flags NZV0C0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2609 if Z = 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2610 if M = 0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2611 cycles 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2612 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2613 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2614 m68k_save_dst Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2615 m68k_prefetch
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2616
2468
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2617 01001000ZZ000RRR ext
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2618 invalid Z 0
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2619 invalid Z 1
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2620 if Z = 3
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2621 meta bits 32
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2622 else
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2623 meta bits 16
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2624 end
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2625 sext bits dregs.R dregs.R
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2626 update_flags NZV0C0
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2627 m68k_prefetch
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2628
2651
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2629 0100101011MMMRRR tas
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2630 invalid M 1
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2631 invalid M 7 R 2
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2632 invalid M 7 R 3
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2633 invalid M 7 R 4
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2634 invalid M 7 R 5
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2635 invalid M 7 R 6
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2636 invalid M 7 R 7
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2637
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2638 m68k_fetch_dst_ea M R 0
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2639 cmp 0 dst 0
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2640 update_flags NZV0C0
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2641 dst |= 0x80
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2642 if M
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2643 cycles 2
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2644 ocall rmw_writeback
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2645 end
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2646 m68k_prefetch
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2647
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2648 010011100100VVVV trap
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2649 local vector 32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2650 scratch1 = pc
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2651 vector = V + 32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2652 m68k_trap vector
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2653
2470
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2654 0100111001010RRR link
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2655 a7 -= 4
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2656 scratch2 = a7
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2657 #TODO: confirm order of fetch and write
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2658 m68k_write32 aregs.R
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2659 m68k_prefetch
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2660 aregs.R = a7
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2661 sext 32 scratch1 scratch1
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2662 a7 += scratch1
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2663 m68k_prefetch
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2664
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2665 0100111001011RRR unlk
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2666 a7 = aregs.R
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2667 scratch1 = a7
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2668 m68k_read32
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2669 a7 += 4
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2670 aregs.R = scratch1
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2671 m68k_prefetch
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2672
2472
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2673 0100100001000RRR swap
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2674 ror dregs.R 16 dregs.R
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2675 update_flags NZV0C0
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2676 m68k_prefetch
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2677
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2678 m68k_calc_ea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2679 arg mode 16
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2680 arg reg 16
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2681 arg index_penalty 32
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2682
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2683 switch mode
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2684 case 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2685 #address reg indirect
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2686 meta ea aregs.reg
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2687 case 3
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2688 #postincrement
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2689 meta ea aregs.reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2690 case 4
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2691 #predecrement
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2692 #note: this case is only used when m68k_calc_ea
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2693 #is called from movem_reg_to_mem which does its own decrementing
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2694 meta ea aregs.reg
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2695 case 5
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2696 #displacement
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2697 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2698 sext 32 prefetch scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2699 scratch1 += aregs.reg
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2700 meta ea scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2701 case 6
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2702 #index
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2703 m68k_index_word
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2704 cycles index_penalty
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2705 scratch1 += aregs.reg
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2706 meta ea scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2707 case 7
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2708 switch reg
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2709 case 0
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2710 #absolute short
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2711 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2712 sext 32 prefetch scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2713 case 1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2714 #absoltue long
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2715 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2716 scratch2 = prefetch << 16
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2717 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2718 scratch1 = scratch2 | prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2719 case 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2720 #pc displacement
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2721 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2722 sext 32 prefetch scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2723 scratch1 += pc
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2724 scratch1 -= 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2725 case 3
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2726 #pc indexed
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2727 m68k_index_word
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2728 cycles index_penalty
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2729 scratch1 += pc
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2730 scratch1 -= 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2731 end
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2732 meta ea scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2733 end
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2734
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2735 0100100001MMMRRR pea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2736 invalid M 0
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2737 invalid M 1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2738 invalid M 3
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2739 invalid M 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2740 invalid M 7 R 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2741 invalid M 7 R 5
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2742 invalid M 7 R 6
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2743 invalid M 7 R 7
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2744
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2745 m68k_calc_ea M R 4
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2746 scratch2 = a7 - 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2747 m68k_write32_lowfirst ea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2748 a7 -= 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2749
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2750 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2751
2622
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2752 0100DDDZZ0MMMRRR chk
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2753 invalid M 1
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2754 invalid M 7 R 5
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2755 invalid M 7 R 6
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2756 invalid M 7 R 7
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2757 invalid Z 0
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2758 invalid Z 1
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2759 local tmp 8
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2760 local src_alt 32
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2761 switch Z
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2762 case 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2763 meta size 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2764 case 3
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2765 meta size 1
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2766 end
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2767 m68k_fetch_src_ea M R size
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2768 if src_is_mem
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2769 src_alt = src
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2770 meta src src_alt
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2771 end
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2772 m68k_prefetch
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2773 cmp dregs.D src size
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2774 update_flags NZVC
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2775 tmp = vflag
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2776 tmp |= nflag
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2777 cmp 0 dregs.D size
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2778 update_flags NZV0C0
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2779 if tmp
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2780 # D > src (signed)
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2781 pc -= 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2782 m68k_trap 6
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2783 else
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2784 cycles 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2785 if nflag
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2786 # D < 0
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2787 pc -= 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2788 m68k_trap 6
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2789 else
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2790 cycles 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2791 end
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2792 end
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2793
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2794 0100DDD111MMMRRR lea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2795 invalid M 0
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2796 invalid M 1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2797 invalid M 3
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2798 invalid M 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2799 invalid M 7 R 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2800 invalid M 7 R 5
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2801 invalid M 7 R 6
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2802 invalid M 7 R 7
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2803
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2804 m68k_calc_ea M R 4
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2805 aregs.D = ea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2806
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2807 m68k_prefetch
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2808
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2809 01001010ZZMMMRRR tst
2653
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
2810 invalid Z 3
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2811 invalid M 7 R 5
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2812 invalid M 7 R 6
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2813 invalid M 7 R 7
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2814
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2815 m68k_fetch_dst_ea M R Z
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2816
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2817 cmp 0 dst Z
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2818 update_flags NZV0C0
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2819 m68k_prefetch
2472
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2820
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2821 0100111001110000 reset
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2822 if reset_handler
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2823 pcall reset_handler m68k_reset_handler context
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2824 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2825 cycles 128
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2826 m68k_prefetch
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2827
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2828 0100111001110001 nop
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2829 m68k_prefetch
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2830
2618
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2831 0100111001110010 stop
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2832 if stopped
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2833 else
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2834 mov pc scratch1
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2835 ocall read_16
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2836 pc += 2
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2837 ccr = scratch1
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2838 status = scratch1 >> 8
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2839 check_user_mode_swap_ssp_usp
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2840 update_sync
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2841 stopped = 1
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2842 end
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2843 loop
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2844 cycles 4
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2845 if cycles >=U int_cycle
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2846 break
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2847 end
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2848 if cycles >=U target_cycle
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2849 break
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2850 end
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2851 end
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2852
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2853 0100111001110011 rte
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2854 #TODO: privilege violation exception if in user mode
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2855 #Read saved SR
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2856 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2857 ocall read_16
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2858 a7 += 2
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2859 ccr = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2860 status = scratch1 >> 8
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2861 #Read saved PC
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2862 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2863 m68k_read32
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2864 a7 += 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2865 pc = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2866
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2867 check_user_mode_swap_ssp_usp
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2868 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2869 update_sync
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2870 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2871
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2872 0100111001110101 m68k_rts
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2873 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2874 m68k_read32
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2875 a7 += 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2876 pc = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2877
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2878 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2879 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2880
2622
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2881 0100111001110110 trapv
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2882 if vflag
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2883 m68k_trap 7
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2884 else
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2885 m68k_prefetch
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2886 end
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2887
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2888 0100111001110111 rtr
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2889 #Read saved CCR
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2890 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2891 ocall read_16
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2892 a7 += 2
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2893 ccr = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2894 #Read saved PC
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2895 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2896 m68k_read32
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2897 a7 += 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2898 pc = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2899
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2900 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2901 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2902
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2903 0100111010MMMRRR jsr
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2904 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2905 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2906 invalid M 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2907 invalid M 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2908 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2909 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2910 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2911 invalid M 7 R 7
2585
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2912 local tmp 32
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2913
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2914 m68k_calc_ea M R 2
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2915 tmp = ea
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2916
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2917 a7 -= 4
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2918 scratch2 = a7
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2919 m68k_write32 pc
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2920
2585
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2921 pc = tmp
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2922
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2923 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2924 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2925
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2926 0100111011MMMRRR jmp
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2927 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2928 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2929 invalid M 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2930 invalid M 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2931 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2932 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2933 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2934 invalid M 7 R 7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2935
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2936 m68k_calc_ea M R 2
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2937 pc = ea
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2938
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2939 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2940 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2941
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2942 m68k_movem_reg_to_mem
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2943 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2944 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2945 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2946 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2947
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2948 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2949 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2950 scratch2 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2951 scratch1 = reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2952 m68k_write_size size 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2953 addsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2954 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2955
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2956 m68k_movem_reg_to_mem_dec
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2957 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2958 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2959 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2960 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2961
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2962 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2963 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2964 decsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2965 scratch2 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2966 scratch1 = reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2967 m68k_write_size size 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2968 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2969
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2970
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2971 010010001ZMMMRRR movem_reg_to_mem
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2972 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2973 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2974 invalid M 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2975 invalid M 7 R 2
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2976 invalid M 7 R 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2977 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2978 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2979 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2980 invalid M 7 R 7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2981 local reglist 16
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2982 local address 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2983 local sz 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2984 sz = Z + 1
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2985
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2986 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2987 reglist = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2988
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2989 m68k_calc_ea M R 2
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2990 address = ea
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2991 meta addr address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2992 if M = 4
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2993 m68k_movem_reg_to_mem_dec reglist 1 a7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2994 m68k_movem_reg_to_mem_dec reglist 2 a6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2995 m68k_movem_reg_to_mem_dec reglist 4 a5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2996 m68k_movem_reg_to_mem_dec reglist 8 a4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2997 m68k_movem_reg_to_mem_dec reglist 16 a3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2998 m68k_movem_reg_to_mem_dec reglist 32 a2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2999 m68k_movem_reg_to_mem_dec reglist 64 a1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3000 m68k_movem_reg_to_mem_dec reglist 128 a0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3001 m68k_movem_reg_to_mem_dec reglist 256 d7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3002 m68k_movem_reg_to_mem_dec reglist 512 d6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3003 m68k_movem_reg_to_mem_dec reglist 1024 d5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3004 m68k_movem_reg_to_mem_dec reglist 2048 d4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3005 m68k_movem_reg_to_mem_dec reglist 4096 d3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3006 m68k_movem_reg_to_mem_dec reglist 8192 d2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3007 m68k_movem_reg_to_mem_dec reglist 16384 d1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3008 m68k_movem_reg_to_mem_dec reglist 32768 d0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3009 ea = address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3010 else
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3011 m68k_movem_reg_to_mem reglist 1 d0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3012 m68k_movem_reg_to_mem reglist 2 d1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3013 m68k_movem_reg_to_mem reglist 4 d2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3014 m68k_movem_reg_to_mem reglist 8 d3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3015 m68k_movem_reg_to_mem reglist 16 d4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3016 m68k_movem_reg_to_mem reglist 32 d5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3017 m68k_movem_reg_to_mem reglist 64 d6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3018 m68k_movem_reg_to_mem reglist 128 d7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3019 m68k_movem_reg_to_mem reglist 256 a0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3020 m68k_movem_reg_to_mem reglist 512 a1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3021 m68k_movem_reg_to_mem reglist 1024 a2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3022 m68k_movem_reg_to_mem reglist 2048 a3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3023 m68k_movem_reg_to_mem reglist 4096 a4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3024 m68k_movem_reg_to_mem reglist 8192 a5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3025 m68k_movem_reg_to_mem reglist 16384 a6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3026 m68k_movem_reg_to_mem reglist 32768 a7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3027 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3028 m68k_prefetch
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3029
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3030 m68k_movem_mem_to_dreg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3031 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3032 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3033 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3034 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3035
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3036 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3037 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3038 scratch1 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3039 if sz = 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3040 ocall read_16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3041 sext 32 scratch1 dregs.reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3042 else
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3043 m68k_read32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3044 dregs.reg = scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3045 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3046 addsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3047 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3048
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3049 m68k_movem_mem_to_areg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3050 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3051 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3052 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3053 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3054
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3055 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3056 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3057 scratch1 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3058 if sz = 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3059 ocall read_16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3060 sext 32 scratch1 aregs.reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3061 else
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3062 m68k_read32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3063 aregs.reg = scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3064 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3065 addsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3066 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3067
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3068 010011001ZMMMRRR movem_mem_to_reg
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3069 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3070 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3071 invalid M 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3072 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3073 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3074 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3075 invalid M 7 R 7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3076 local reglist 16
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3077 local address 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3078 local sz 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3079 sz = Z + 1
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3080
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3081 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3082 reglist = scratch1
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3083
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3084 m68k_calc_ea M R 2
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3085 address = ea
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3086 meta addr address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3087
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3088 m68k_movem_mem_to_dreg reglist 1 0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3089 m68k_movem_mem_to_dreg reglist 2 1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3090 m68k_movem_mem_to_dreg reglist 4 2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3091 m68k_movem_mem_to_dreg reglist 8 3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3092 m68k_movem_mem_to_dreg reglist 16 4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3093 m68k_movem_mem_to_dreg reglist 32 5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3094 m68k_movem_mem_to_dreg reglist 64 6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3095 m68k_movem_mem_to_dreg reglist 128 7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3096 m68k_movem_mem_to_areg reglist 256 0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3097 m68k_movem_mem_to_areg reglist 512 1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3098 m68k_movem_mem_to_areg reglist 1024 2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3099 m68k_movem_mem_to_areg reglist 2048 3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3100 m68k_movem_mem_to_areg reglist 4096 4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3101 m68k_movem_mem_to_areg reglist 8192 5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3102 m68k_movem_mem_to_areg reglist 16384 6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3103 m68k_movem_mem_to_areg reglist 32768 7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3104 #dummy read
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3105 scratch1 = address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3106 ocall read_16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3107 if M = 3
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3108 ea = address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3109 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3110
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3111 m68k_prefetch
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3112
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3113 0100111001100RRR move_to_usp
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3114 #TODO: trap if not in supervisor mode
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3115 other_sp = aregs.R
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3116 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3117
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3118 0100111001101RRR move_from_usp
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3119 #TODO: trap if not in supervisor mode
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3120 aregs.R = other_sp
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3121 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3122
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3123 0111RRR0IIIIIIII moveq
2591
563d05355a12 Cut down on code bloat in 68K core a little
Michael Pavone <pavone@retrodev.com>
parents: 2590
diff changeset
3124 nospecialize I
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3125 local tmp 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3126 sext 16 I tmp
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3127 sext 32 tmp dregs.R
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3128 cmp 0 dregs.R
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3129 update_flags NZV0C0
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3130 m68k_prefetch
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3131
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3132 0110000100000000 bsr_w
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3133 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3134 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3135 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3136 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3137 sext 32 prefetch offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3138
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3139 a7 -= 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3140 scratch2 = a7
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3141 m68k_write32 pc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3142
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3143 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3144 pc -= 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3145
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3146 cycles 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3147 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3148
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3149
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3150 01100001DDDDDDDD bsr
2591
563d05355a12 Cut down on code bloat in 68K core a little
Michael Pavone <pavone@retrodev.com>
parents: 2590
diff changeset
3151 nospecialize D
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3152 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3153 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3154 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3155 sext 16 D offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3156 sext 32 offset offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3157
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3158 a7 -= 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3159 scratch2 = a7
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3160 m68k_write32 pc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3161
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3162 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3163
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3164 cycles 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3165 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3166
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3167 m68k_check_cond
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3168 arg cond 16
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3169 local invert 8
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3170 switch cond
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3171 case 0
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3172 #true
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3173 meta istrue 1
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3174 case 1
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3175 #false
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3176 meta istrue 0
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3177 case 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3178 #high
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3179 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3180 invert = zflag | cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3181 invert = !invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3182 case 3
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3183 #low or same
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3184 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3185 invert = zflag | cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3186 case 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3187 #carry clear
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3188 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3189 invert = !cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3190 case 5
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3191 #carry set
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3192 meta istrue cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3193 case 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3194 #not equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3195 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3196 invert = !zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3197 case 7
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3198 #equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3199 meta istrue zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3200 case 8
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3201 #overflow clear
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3202 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3203 invert = !vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3204 case 9
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3205 #overflow set
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3206 meta istrue vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3207 case 10
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3208 #plus
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3209 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3210 invert = !nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3211 case 11
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3212 #minus
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3213 meta istrue nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3214 case 12
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3215 #greater or equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3216 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3217 invert = nflag - vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3218 invert = !invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3219 case 13
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3220 #less
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3221 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3222 invert = nflag - vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3223 case 14
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3224 #greater
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3225 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3226 invert = vflag ^ nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3227 invert |= zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3228 invert = !invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3229 case 15
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3230 #less or equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3231 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3232 invert = vflag ^ nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3233 invert |= zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3234 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3235
2584
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3236 0101CCCC11MMMDDD scc
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3237 invalid M 1
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3238 invalid M 7 D 2
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3239 invalid M 7 D 3
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3240 invalid M 7 D 4
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3241 invalid M 7 D 5
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3242 invalid M 7 D 6
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3243 invalid M 7 D 7
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3244 m68k_fetch_dst_ea M D 0
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3245 m68k_check_cond C
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3246 if istrue
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3247 if M = 0
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3248 cycles 2
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3249 end
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3250 dst:0 = 0xFF
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3251 else
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3252 dst:0 = 0
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3253 end
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3254 m68k_save_dst 0
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3255 m68k_prefetch
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3256
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3257 0110CCCC00000000 bcc_w
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3258 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3259 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3260 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3261 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3262 m68k_check_cond C
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3263 if istrue
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3264
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3265 sext 32 prefetch offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3266 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3267 pc -= 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3268 cycles 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3269 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3270 cycles 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3271 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3272 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3273
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3274 0110CCCCDDDDDDDD bcc
2591
563d05355a12 Cut down on code bloat in 68K core a little
Michael Pavone <pavone@retrodev.com>
parents: 2590
diff changeset
3275 nospecialize D
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3276 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3277 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3278 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3279 m68k_check_cond C
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3280 if istrue
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3281 sext 16 D offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3282 sext 32 offset offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3283
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3284 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3285
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3286 cycles 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3287 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3288 cycles 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3289 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3290 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3291
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3292 0101CCCC11001RRR dbcc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3293 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3294 local tmp 16
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3295 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3296 m68k_check_cond C
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3297 if istrue
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3298 cycles 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3299 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3300 dregs.R:1 -= 1
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3301 tmp = dregs.R
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3302 if tmp = 65535
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3303 cycles 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3304 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3305 sext 32 prefetch offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3306 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3307 pc -= 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3308 cycles 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3309 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3310 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3311 m68k_prefetch
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3312
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3313 1110CCC0ZZ011RRR rori
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3314 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3315 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3316 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3317 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3318 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3319 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3320 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3321 ror dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3322 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3323 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3324 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3325 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3326 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3327 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3328 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3329 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3330 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3331 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3332 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3333 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3334
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3335 1110CCC0ZZ111RRR ror_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3336 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3337 local shift 8
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3338 shift = dregs.C & 63
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3339 ror dregs.R shift dregs.R Z
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3340 update_flags NZV0C
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3341 shift += shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3342 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3343 case 2
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3344 shift += 4
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3345 default
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3346 shift += 2
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3347 end
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3348 cycles shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3349 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3350 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3351
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3352 1110011011MMMRRR ror_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3353 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3354 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3355 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3356 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3357 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3358 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3359 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3360 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3361
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3362 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3363 ror dst 1 dst 1
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3364 update_flags NZV0C
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3365 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3366 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3367
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3368 1110CCC1ZZ011RRR roli
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3369 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3370 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3371 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3372 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3373 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3374 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3375 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3376 rol dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3377 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3378 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3379 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3380 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3381 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3382 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3383 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3384 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3385 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3386 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3387 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3388 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3389
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3390 1110CCC1ZZ111RRR rol_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3391 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3392 local shift 8
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3393 shift = dregs.C & 63
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3394 rol dregs.R shift dregs.R Z
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3395 update_flags NZV0C
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3396 shift += shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3397 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3398 case 2
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3399 shift += 4
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3400 default
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3401 shift += 2
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3402 end
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3403 cycles shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3404 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3405 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3406
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3407 1110011111MMMRRR rol_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3408 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3409 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3410 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3411 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3412 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3413 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3414 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3415 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3416
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3417 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3418 rol dst 1 dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3419 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3420 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3421 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3422
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3423 1110CCC0ZZ010RRR roxri
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3424 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3425 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3426 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3427 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3428 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3429 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3430 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3431 rrc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3432 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3433 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3434 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3435 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3436 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3437 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3438 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3439 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3440 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3441 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3442 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3443 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3444
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3445 1110CCC0ZZ110RRR roxr_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3446 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3447 local shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3448 local cycle_shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3449 cycle_shift = dregs.C & 63
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3450 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3451 case 2
2631
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3452 meta max_shift 31
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3453 case 1
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3454 meta max_shift 15
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3455 case 0
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3456 meta max_shift 7
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3457 end
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3458 shift = cycle_shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3459 if shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3460 loop
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3461 if max_shift >=U shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3462 rrc dregs.R shift dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3463 update_flags XNZV0C
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3464 break
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3465 else
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3466 rrc dregs.R max_shift dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3467 update_flags X
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3468 shift -= max_shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3469 end
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3470 end
2631
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3471 else
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3472 cflag = xflag
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3473 cmp 0 dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3474 update_flags NZV0
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3475 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3476 cycle_shift += cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3477 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3478 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3479 cycle_shift += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3480 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3481 cycle_shift += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3482 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3483 cycles cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3484 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3485 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3486
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3487 1110010011MMMRRR roxr_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3488 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3489 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3490 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3491 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3492 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3493 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3494 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3495 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3496
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3497 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3498 rrc dst 1 dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3499 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3500 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3501 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3502
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3503 1110CCC1ZZ010RRR roxli
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3504 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3505 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3506 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3507 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3508 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3509 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3510 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3511 rlc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3512 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3513 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3514 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3515 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3516 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3517 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3518 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3519 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3520 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3521 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3522 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3523 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3524
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3525 1110CCC1ZZ110RRR roxl_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3526 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3527 local shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3528 local cycle_shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3529 cycle_shift = dregs.C & 63
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3530 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3531 case 2
2631
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3532 meta max_shift 31
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3533 case 1
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3534 meta max_shift 15
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3535 case 0
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3536 meta max_shift 7
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3537 end
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3538 shift = cycle_shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3539 if shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3540 loop
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3541 if max_shift >=U shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3542 rlc dregs.R shift dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3543 update_flags XNZV0C
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3544 break
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3545 else
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3546 rlc dregs.R max_shift dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3547 update_flags X
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3548 shift -= max_shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3549 end
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3550 end
2631
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3551 else
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3552 cflag = xflag
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3553 cmp 0 dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3554 update_flags NZV0
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3555 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3556 cycle_shift += cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3557 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3558 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3559 cycle_shift += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3560 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3561 cycle_shift += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3562 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3563 cycles cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3564 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3565 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3566
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3567 1110010111MMMRRR roxl_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3568 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3569 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3570 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3571 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3572 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3573 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3574 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3575 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3576
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3577 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3578 rlc dst 1 dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3579 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3580 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3581 m68k_prefetch
2636
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3582
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3583 1010XXXXXXXXXXXX line_a
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3584 nospecialize X
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3585 #TODO cycle counts
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3586 pc -= 2
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3587 m68k_trap 10
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3588
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3589 1111XXXXXXXXXXXX line_f
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3590 nospecialize X
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3591 #TODO cycle counts
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3592 pc -= 2
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3593 m68k_trap 11
2646
bde8ec2d0f83 Implement illegal instruction trap in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2639
diff changeset
3594
2653
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
3595 XXXXXXXXXXXXXXXX illegal
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
3596 nospecialize X
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
3597 #TODO cycle counts
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
3598 pc -= 2
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
3599 m68k_trap 4