repos/blastem: z80_to_x86.c annotate

annotate z80_to_x86.c @ 467:140af5509ce7

Added copyright notice to source files and added GPL license text in COPYING

author	Mike Pavone <pavone@retrodev.com>
date	Tue, 10 Sep 2013 23:31:08 -0700
parents	7e8e179116af
children	b7b7a1cab44a

rev	line source
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	2 Copyright 2013 Michael Pavone
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	3 This file is part of BlastEm.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	5 */
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	6 #include "z80inst.h"
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	7 #include "z80_to_x86.h"
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 #include "gen_x86.h"
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	9 #include "mem.h"
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	10 #include <stdio.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	11 #include <stdlib.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	12 #include <stddef.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	13 #include <string.h>
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	14
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 #define MODE_UNUSED (MODE_IMMED-1)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	16
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 #define ZCYCLES RBP
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	18 #define ZLIMIT RDI
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 #define SCRATCH1 R13
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 #define SCRATCH2 R14
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	21 #define CONTEXT RSI
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	22
315 684e71e9f0d0 Fix return address for RST Mike Pavone <pavone@retrodev.com> parents: 314 diff changeset	23 //#define DO_DEBUG_PRINT
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	24
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	25 #ifdef DO_DEBUG_PRINT
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	26 #define dprintf printf
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	27 #else
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	28 #define dprintf
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	29 #endif
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	30
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	31 void z80_read_byte();
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	32 void z80_read_word();
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	33 void z80_write_byte();
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	34 void z80_write_word_highfirst();
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	35 void z80_write_word_lowfirst();
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	36 void z80_save_context();
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	37 void z80_native_addr();
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	38 void z80_do_sync();
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	39 void z80_handle_cycle_limit_int();
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	40 void z80_retrans_stub();
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	41 void z80_io_read();
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	42 void z80_io_write();
285 021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	43 void z80_halt();
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	44 void z80_save_context();
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	45 void z80_load_context();
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	46
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	47 uint8_t z80_size(z80inst * inst)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	48 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	49 uint8_t reg = (inst->reg & 0x1F);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	50 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 return reg < Z80_BC ? SZ_B : SZ_W;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	52 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	53 //TODO: Handle any necessary special cases
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	54 return SZ_B;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	55 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	56
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	57 uint8_t * zcycles(uint8_t * dst, uint32_t num_cycles)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	58 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	59 return add_ir(dst, num_cycles, ZCYCLES, SZ_D);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	60 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	61
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	62 uint8_t * z80_check_cycles_int(uint8_t * dst, uint16_t address)
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	63 {
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	64 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D);
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	65 uint8_t * jmp_off = dst+1;
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	66 dst = jcc(dst, CC_NC, dst + 7);
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	67 dst = mov_ir(dst, address, SCRATCH1, SZ_W);
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	68 dst = call(dst, (uint8_t *)z80_handle_cycle_limit_int);
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	69 *jmp_off = dst - (jmp_off+1);
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	70 return dst;
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	71 }
5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	72
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	73 uint8_t * translate_z80_reg(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	74 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	75 if (inst->reg == Z80_USE_IMMED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	76 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	77 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	78 } else if ((inst->reg & 0x1F) == Z80_UNUSED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	79 ea->mode = MODE_UNUSED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	80 } else {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	81 ea->mode = MODE_REG_DIRECT;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	82 if (inst->reg == Z80_IYH) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	83 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	84 dst = mov_rr(dst, opts->regs[Z80_IY], SCRATCH1, SZ_W);
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	85 dst = ror_ir(dst, 8, SCRATCH1, SZ_W);
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	86 ea->base = SCRATCH1;
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	87 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	88 ea->base = opts->regs[Z80_IYL];
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	89 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	90 }
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	91 } else if(opts->regs[inst->reg] >= 0) {
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	92 ea->base = opts->regs[inst->reg];
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	93 if (ea->base >= AH && ea->base <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	94 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	95 uint8_t other_reg = opts->regs[inst->ea_reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	96 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	97 //we can't mix an *H reg with a register that requires the REX prefix
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	98 ea->base = opts->regs[z80_low_reg(inst->reg)];
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	99 dst = ror_ir(dst, 8, ea->base, SZ_W);
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	100 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	101 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	102 //temp regs require REX prefix too
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	103 ea->base = opts->regs[z80_low_reg(inst->reg)];
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	104 dst = ror_ir(dst, 8, ea->base, SZ_W);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	105 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	106 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	107 } else {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	108 ea->mode = MODE_REG_DISPLACE8;
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	109 ea->base = CONTEXT;
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	110 ea->disp = offsetof(z80_context, regs) + inst->reg;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	111 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	112 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	113 return dst;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	114 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	115
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	116 uint8_t * z80_save_reg(uint8_t * dst, z80inst * inst, x86_z80_options * opts)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	117 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	118 if (inst->reg == Z80_IYH) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	119 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	120 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	121 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_IYL], SZ_B);
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	122 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	123 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	124 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	125 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	126 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	127 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	128 uint8_t other_reg = opts->regs[inst->ea_reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	129 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	130 //we can't mix an *H reg with a register that requires the REX prefix
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	131 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	132 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	133 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	134 //temp regs require REX prefix too
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	135 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	136 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	137 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	138 return dst;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	139 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	140
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	141 uint8_t * translate_z80_ea(z80inst * inst, x86_ea * ea, uint8_t * dst, x86_z80_options * opts, uint8_t read, uint8_t modify)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	142 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	143 uint8_t size, reg, areg;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	144 ea->mode = MODE_REG_DIRECT;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	145 areg = read ? SCRATCH1 : SCRATCH2;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	146 switch(inst->addr_mode & 0x1F)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	147 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	148 case Z80_REG:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	149 if (inst->ea_reg == Z80_IYH) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	150 if (inst->reg == Z80_IYL) {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	151 dst = mov_rr(dst, opts->regs[Z80_IY], SCRATCH1, SZ_W);
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	152 dst = ror_ir(dst, 8, SCRATCH1, SZ_W);
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	153 ea->base = SCRATCH1;
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	154 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	155 ea->base = opts->regs[Z80_IYL];
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	156 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	157 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	158 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	159 ea->base = opts->regs[inst->ea_reg];
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	160 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	161 uint8_t other_reg = opts->regs[inst->reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	162 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	163 //we can't mix an *H reg with a register that requires the REX prefix
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	164 ea->base = opts->regs[z80_low_reg(inst->ea_reg)];
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	165 dst = ror_ir(dst, 8, ea->base, SZ_W);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	166 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	167 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	168 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	169 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	170 case Z80_REG_INDIRECT:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	171 dst = mov_rr(dst, opts->regs[inst->ea_reg], areg, SZ_W);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	172 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	173 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	174 if (modify) {
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	175 //dst = push_r(dst, SCRATCH1);
765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	176 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(z80_context, scratch1), SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	177 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	178 if (size == SZ_B) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	179 dst = call(dst, (uint8_t *)z80_read_byte);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	180 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	181 dst = call(dst, (uint8_t *)z80_read_word);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	182 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	183 if (modify) {
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	184 //dst = pop_r(dst, SCRATCH2);
765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	185 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, scratch1), SCRATCH2, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	186 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	187 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	188 ea->base = SCRATCH1;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	189 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	190 case Z80_IMMED:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	191 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	192 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	193 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	194 case Z80_IMMED_INDIRECT:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 dst = mov_ir(dst, inst->immed, areg, SZ_W);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	196 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	197 if (read) {
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	198 /*if (modify) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	199 dst = push_r(dst, SCRATCH1);
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	200 }*/
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	201 if (size == SZ_B) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	202 dst = call(dst, (uint8_t *)z80_read_byte);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	203 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	204 dst = call(dst, (uint8_t *)z80_read_word);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	205 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	206 if (modify) {
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	207 //dst = pop_r(dst, SCRATCH2);
765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	208 dst = mov_ir(dst, inst->immed, SCRATCH2, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	209 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	210 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	211 ea->base = SCRATCH1;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	212 break;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	213 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	214 case Z80_IY_DISPLACE:
300 9adc1dce39bf Fix IX/IY register selection when the direction bit is set Mike Pavone <pavone@retrodev.com> parents: 299 diff changeset	215 reg = opts->regs[(inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY];
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	216 dst = mov_rr(dst, reg, areg, SZ_W);
306 3970006fae90 Properly handle negative displacements in Z80 core Mike Pavone <pavone@retrodev.com> parents: 305 diff changeset	217 dst = add_ir(dst, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	218 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	219 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	220 if (modify) {
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	221 //dst = push_r(dst, SCRATCH1);
765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	222 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(z80_context, scratch1), SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	223 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	224 if (size == SZ_B) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	225 dst = call(dst, (uint8_t *)z80_read_byte);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	226 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	227 dst = call(dst, (uint8_t *)z80_read_word);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	228 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	229 if (modify) {
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	230 //dst = pop_r(dst, SCRATCH2);
765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	231 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, scratch1), SCRATCH2, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	232 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	233 }
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	234 ea->base = SCRATCH1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	235 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	236 case Z80_UNUSED:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	237 ea->mode = MODE_UNUSED;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	238 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	239 default:
300 9adc1dce39bf Fix IX/IY register selection when the direction bit is set Mike Pavone <pavone@retrodev.com> parents: 299 diff changeset	240 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	241 exit(1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	242 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	243 return dst;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	244 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	245
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	246 uint8_t * z80_save_ea(uint8_t * dst, z80inst * inst, x86_z80_options * opts)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	247 {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	248 if ((inst->addr_mode & 0x1F) == Z80_REG) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	249 if (inst->ea_reg == Z80_IYH) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	250 if (inst->reg == Z80_IYL) {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	251 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	252 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_IYL], SZ_B);
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	253 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	254 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	255 dst = ror_ir(dst, 8, opts->regs[Z80_IY], SZ_W);
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	256 }
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	257 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	258 uint8_t other_reg = opts->regs[inst->reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	259 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	260 //we can't mix an *H reg with a register that requires the REX prefix
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	261 dst = ror_ir(dst, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W);
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	262 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	263 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	264 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	265 return dst;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	266 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	267
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	268 uint8_t * z80_save_result(uint8_t * dst, z80inst * inst)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	269 {
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	270 switch(inst->addr_mode & 0x1f)
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	271 {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	272 case Z80_REG_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	273 case Z80_IMMED_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	274 case Z80_IX_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	275 case Z80_IY_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	276 if (z80_size(inst) == SZ_B) {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	277 dst = call(dst, (uint8_t *)z80_write_byte);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	278 } else {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	279 dst = call(dst, (uint8_t *)z80_write_word_lowfirst);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	280 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	281 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	282 return dst;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	283 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	284
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	285 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	286 DONT_READ=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	287 READ
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	288 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	289
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	290 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	291 DONT_MODIFY=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	292 MODIFY
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	293 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	294
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	295 uint8_t zf_off(uint8_t flag)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	296 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	297 return offsetof(z80_context, flags) + flag;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	298 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	299
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	300 uint8_t zaf_off(uint8_t flag)
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	301 {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	302 return offsetof(z80_context, alt_flags) + flag;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	303 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	304
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	305 uint8_t zar_off(uint8_t reg)
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	306 {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	307 return offsetof(z80_context, alt_regs) + reg;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	308 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	309
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	310 void z80_print_regs_exit(z80_context * context)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	311 {
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	312 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n",
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	313 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C],
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	314 context->regs[Z80_D], context->regs[Z80_E],
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	315 (context->regs[Z80_H] << 8) \| context->regs[Z80_L],
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	316 (context->regs[Z80_IXH] << 8) \| context->regs[Z80_IXL],
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	317 (context->regs[Z80_IYH] << 8) \| context->regs[Z80_IYL],
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	318 context->sp, context->im, context->iff1, context->iff2);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	319 puts("--Alternate Regs--");
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	320 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n",
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	321 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C],
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	322 context->alt_regs[Z80_D], context->alt_regs[Z80_E],
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	323 (context->alt_regs[Z80_H] << 8) \| context->alt_regs[Z80_L],
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	324 (context->alt_regs[Z80_IXH] << 8) \| context->alt_regs[Z80_IXL],
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	325 (context->alt_regs[Z80_IYH] << 8) \| context->alt_regs[Z80_IYL]);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	326 exit(0);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	327 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	328
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	329 uint8_t * translate_z80inst(z80inst * inst, uint8_t * dst, z80_context * context, uint16_t address)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	330 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	331 uint32_t cycles;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	332 x86_ea src_op, dst_op;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	333 uint8_t size;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	334 x86_z80_options *opts = context->options;
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	335 uint8_t * start = dst;
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	336 dst = z80_check_cycles_int(dst, address);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	337 switch(inst->op)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	338 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	339 case Z80_LD:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	340 size = z80_size(inst);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	341 switch (inst->addr_mode & 0x1F)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	342 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	343 case Z80_REG:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	344 case Z80_REG_INDIRECT:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	345 cycles = size == SZ_B ? 4 : 6;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	346 if (inst->ea_reg == Z80_IX \|\| inst->ea_reg == Z80_IY) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	347 cycles += 4;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	348 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	349 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	350 case Z80_IMMED:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	351 cycles = size == SZ_B ? 7 : 10;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	352 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	353 case Z80_IMMED_INDIRECT:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	354 cycles = 10;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	355 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	356 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	357 case Z80_IY_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	358 cycles = 12;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	359 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	360 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	361 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) \|\| inst->reg == Z80_IX \|\| inst->reg == Z80_IY) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	362 cycles += 4;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	363 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	364 dst = zcycles(dst, cycles);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	365 if (inst->addr_mode & Z80_DIR) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	366 dst = translate_z80_reg(inst, &src_op, dst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	367 dst = translate_z80_ea(inst, &dst_op, dst, opts, DONT_READ, MODIFY);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	368 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	369 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	370 dst = translate_z80_reg(inst, &dst_op, dst, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	371 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	372 if (src_op.mode == MODE_REG_DIRECT) {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	373 if(dst_op.mode == MODE_REG_DISPLACE8) {
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	374 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, size);
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	375 } else {
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	376 dst = mov_rr(dst, src_op.base, dst_op.base, size);
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	377 }
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	378 } else if(src_op.mode == MODE_IMMED) {
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	379 dst = mov_ir(dst, src_op.disp, dst_op.base, size);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	380 } else {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	381 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, size);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	382 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	383 dst = z80_save_reg(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	384 dst = z80_save_ea(dst, inst, opts);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	385 if (inst->addr_mode & Z80_DIR) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	386 dst = z80_save_result(dst, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	387 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	388 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	389 case Z80_PUSH:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	390 dst = zcycles(dst, (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) ? 9 : 5);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	391 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	392 if (inst->reg == Z80_AF) {
363 c708dea45f8b Fix push AF Mike Pavone <pavone@retrodev.com> parents: 360 diff changeset	393 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B);
c708dea45f8b Fix push AF Mike Pavone <pavone@retrodev.com> parents: 360 diff changeset	394 dst = shl_ir(dst, 8, SCRATCH1, SZ_W);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	395 dst = mov_rdisp8r(dst, CONTEXT, zf_off(ZF_S), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	396 dst = shl_ir(dst, 1, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	397 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_Z), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	398 dst = shl_ir(dst, 2, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	399 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_H), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	400 dst = shl_ir(dst, 2, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	401 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_PV), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	402 dst = shl_ir(dst, 1, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	403 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_N), SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	404 dst = shl_ir(dst, 1, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	405 dst = or_rdisp8r(dst, CONTEXT, zf_off(ZF_C), SCRATCH1, SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	406 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	407 dst = translate_z80_reg(inst, &src_op, dst, opts);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	408 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	409 }
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	410 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	411 dst = call(dst, (uint8_t *)z80_write_word_highfirst);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	412 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	413 //the upper half of a register pair
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	414 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	415 case Z80_POP:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	416 dst = zcycles(dst, (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) ? 8 : 4);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	417 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	418 dst = call(dst, (uint8_t *)z80_read_word);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	419 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	420 if (inst->reg == Z80_AF) {
294 921f9d8819da Fix byte order of pop AF Mike Pavone <pavone@retrodev.com> parents: 292 diff changeset	421
921f9d8819da Fix byte order of pop AF Mike Pavone <pavone@retrodev.com> parents: 292 diff changeset	422 dst = bt_ir(dst, 0, SCRATCH1, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	423 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
294 921f9d8819da Fix byte order of pop AF Mike Pavone <pavone@retrodev.com> parents: 292 diff changeset	424 dst = bt_ir(dst, 1, SCRATCH1, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	425 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_N));
294 921f9d8819da Fix byte order of pop AF Mike Pavone <pavone@retrodev.com> parents: 292 diff changeset	426 dst = bt_ir(dst, 2, SCRATCH1, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	427 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_PV));
294 921f9d8819da Fix byte order of pop AF Mike Pavone <pavone@retrodev.com> parents: 292 diff changeset	428 dst = bt_ir(dst, 4, SCRATCH1, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	429 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_H));
294 921f9d8819da Fix byte order of pop AF Mike Pavone <pavone@retrodev.com> parents: 292 diff changeset	430 dst = bt_ir(dst, 6, SCRATCH1, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	431 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_Z));
294 921f9d8819da Fix byte order of pop AF Mike Pavone <pavone@retrodev.com> parents: 292 diff changeset	432 dst = bt_ir(dst, 7, SCRATCH1, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	433 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_S));
294 921f9d8819da Fix byte order of pop AF Mike Pavone <pavone@retrodev.com> parents: 292 diff changeset	434 dst = shr_ir(dst, 8, SCRATCH1, SZ_W);
921f9d8819da Fix byte order of pop AF Mike Pavone <pavone@retrodev.com> parents: 292 diff changeset	435 dst = mov_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	436 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	437 dst = translate_z80_reg(inst, &src_op, dst, opts);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	438 dst = mov_rr(dst, SCRATCH1, src_op.base, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	439 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	440 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	441 //the upper half of a register pair
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	442 break;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	443 case Z80_EX:
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	444 if (inst->addr_mode == Z80_REG \|\| inst->reg == Z80_HL) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	445 cycles = 4;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	446 } else {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	447 cycles = 8;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	448 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	449 dst = zcycles(dst, cycles);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	450 if (inst->addr_mode == Z80_REG) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	451 if(inst->reg == Z80_AF) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	452 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH1, SZ_B);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	453 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_A), opts->regs[Z80_A], SZ_B);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	454 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_A), SZ_B);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	455
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	456 //Flags are currently word aligned, so we can move
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	457 //them efficiently a word at a time
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	458 for (int f = ZF_C; f < ZF_NUM; f+=2) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	459 dst = mov_rdisp8r(dst, CONTEXT, zf_off(f), SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	460 dst = mov_rdisp8r(dst, CONTEXT, zaf_off(f), SCRATCH2, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	461 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zaf_off(f), SZ_W);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	462 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zf_off(f), SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	463 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	464 } else {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	465 dst = xchg_rr(dst, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	466 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	467 } else {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	468 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	469 dst = call(dst, (uint8_t *)z80_read_byte);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	470 dst = xchg_rr(dst, opts->regs[inst->reg], SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	471 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	472 dst = call(dst, (uint8_t *)z80_write_byte);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	473 dst = zcycles(dst, 1);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	474 uint8_t high_reg = z80_high_reg(inst->reg);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	475 uint8_t use_reg;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	476 //even though some of the upper halves can be used directly
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	477 //the limitations on mixing *H regs with the REX prefix
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	478 //prevent us from taking advantage of it
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	479 use_reg = opts->regs[inst->reg];
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	480 dst = ror_ir(dst, 8, use_reg, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	481 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	482 dst = add_ir(dst, 1, SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	483 dst = call(dst, (uint8_t *)z80_read_byte);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	484 dst = xchg_rr(dst, use_reg, SCRATCH1, SZ_B);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	485 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	486 dst = add_ir(dst, 1, SCRATCH2, SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	487 dst = call(dst, (uint8_t *)z80_write_byte);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	488 //restore reg to normal rotation
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	489 dst = ror_ir(dst, 8, use_reg, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	490 dst = zcycles(dst, 2);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	491 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	492 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	493 case Z80_EXX:
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	494 dst = zcycles(dst, 4);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	495 dst = mov_rr(dst, opts->regs[Z80_BC], SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	496 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	497 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	498 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	499 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_C), SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	500 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, zar_off(Z80_L), SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	501 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH1, SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	502 dst = mov_rdisp8r(dst, CONTEXT, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	503 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, zar_off(Z80_E), SZ_W);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	504 break;
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	505 case Z80_LDI: {
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	506 dst = zcycles(dst, 8);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	507 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	508 dst = call(dst, (uint8_t *)z80_read_byte);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	509 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W);
385 e45327305bb7 Fix LDI Mike Pavone <pavone@retrodev.com> parents: 384 diff changeset	510 dst = call(dst, (uint8_t *)z80_write_byte);
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	511 dst = zcycles(dst, 2);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	512 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	513 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	514 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	515 //TODO: Implement half-carry
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	516 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	517 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV));
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	518 break;
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	519 }
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	520 case Z80_LDIR: {
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	521 dst = zcycles(dst, 8);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	522 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	523 dst = call(dst, (uint8_t *)z80_read_byte);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	524 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W);
397 c20607e5b272 Fix LDIR Mike Pavone <pavone@retrodev.com> parents: 394 diff changeset	525 dst = call(dst, (uint8_t *)z80_write_byte);
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	526 dst = add_ir(dst, 1, opts->regs[Z80_DE], SZ_W);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	527 dst = add_ir(dst, 1, opts->regs[Z80_HL], SZ_W);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	528
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	529 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	530 uint8_t * cont = dst+1;
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	531 dst = jcc(dst, CC_Z, dst+2);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	532 dst = zcycles(dst, 7);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	533 //TODO: Figure out what the flag state should be here
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	534 //TODO: Figure out whether an interrupt can interrupt this
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	535 dst = jmp(dst, start);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	536 *cont = dst - (cont + 1);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	537 dst = zcycles(dst, 2);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	538 //TODO: Implement half-carry
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	539 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	540 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B);
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	541 break;
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	542 }
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	543 case Z80_LDD: {
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	544 dst = zcycles(dst, 8);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	545 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	546 dst = call(dst, (uint8_t *)z80_read_byte);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	547 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W);
388 228e4c696317 Fix LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 387 diff changeset	548 dst = call(dst, (uint8_t *)z80_write_byte);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	549 dst = zcycles(dst, 2);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	550 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	551 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	552 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	553 //TODO: Implement half-carry
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	554 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	555 dst = setcc_rdisp8(dst, CC_NZ, CONTEXT, zf_off(ZF_PV));
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	556 break;
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	557 }
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	558 case Z80_LDDR: {
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	559 dst = zcycles(dst, 8);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	560 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	561 dst = call(dst, (uint8_t *)z80_read_byte);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	562 dst = mov_rr(dst, opts->regs[Z80_DE], SCRATCH2, SZ_W);
388 228e4c696317 Fix LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 387 diff changeset	563 dst = call(dst, (uint8_t *)z80_write_byte);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	564 dst = sub_ir(dst, 1, opts->regs[Z80_DE], SZ_W);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	565 dst = sub_ir(dst, 1, opts->regs[Z80_HL], SZ_W);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	566
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	567 dst = sub_ir(dst, 1, opts->regs[Z80_BC], SZ_W);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	568 uint8_t * cont = dst+1;
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	569 dst = jcc(dst, CC_Z, dst+2);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	570 dst = zcycles(dst, 7);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	571 //TODO: Figure out what the flag state should be here
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	572 //TODO: Figure out whether an interrupt can interrupt this
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	573 dst = jmp(dst, start);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	574 *cont = dst - (cont + 1);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	575 dst = zcycles(dst, 2);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	576 //TODO: Implement half-carry
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	577 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	578 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B);
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	579 break;
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	580 }
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	581 /*case Z80_CPI:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	582 case Z80_CPIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	583 case Z80_CPD:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	584 case Z80_CPDR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	585 break;*/
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	586 case Z80_ADD:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	587 cycles = 4;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	588 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	589 cycles += 12;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	590 } else if(inst->addr_mode == Z80_IMMED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	591 cycles += 3;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	592 } else if(z80_size(inst) == SZ_W) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	593 cycles += 4;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	594 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	595 dst = zcycles(dst, cycles);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	596 dst = translate_z80_reg(inst, &dst_op, dst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	597 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	598 if (src_op.mode == MODE_REG_DIRECT) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	599 dst = add_rr(dst, src_op.base, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	600 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	601 dst = add_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	602 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	603 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	604 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	605 //TODO: Implement half-carry flag
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	606 if (z80_size(inst) == SZ_B) {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	607 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	608 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	609 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	610 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	611 dst = z80_save_reg(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	612 dst = z80_save_ea(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	613 break;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	614 case Z80_ADC:
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	615 cycles = 4;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	616 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	617 cycles += 12;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	618 } else if(inst->addr_mode == Z80_IMMED) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	619 cycles += 3;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	620 } else if(z80_size(inst) == SZ_W) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	621 cycles += 4;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	622 }
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	623 dst = zcycles(dst, cycles);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	624 dst = translate_z80_reg(inst, &dst_op, dst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	625 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
399 acaae7c3d34c Fix adc and sbc Mike Pavone <pavone@retrodev.com> parents: 397 diff changeset	626 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	627 if (src_op.mode == MODE_REG_DIRECT) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	628 dst = adc_rr(dst, src_op.base, dst_op.base, z80_size(inst));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	629 } else {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	630 dst = adc_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	631 }
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	632 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	633 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	634 //TODO: Implement half-carry flag
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	635 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	636 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	637 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	638 dst = z80_save_reg(dst, inst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	639 dst = z80_save_ea(dst, inst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	640 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	641 case Z80_SUB:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	642 cycles = 4;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	643 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	644 cycles += 12;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	645 } else if(inst->addr_mode == Z80_IMMED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	646 cycles += 3;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	647 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	648 dst = zcycles(dst, cycles);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	649 dst = translate_z80_reg(inst, &dst_op, dst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	650 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	651 if (src_op.mode == MODE_REG_DIRECT) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	652 dst = sub_rr(dst, src_op.base, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	653 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	654 dst = sub_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	655 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	656 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	657 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	658 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	659 //TODO: Implement half-carry flag
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	660 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	661 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	662 dst = z80_save_reg(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	663 dst = z80_save_ea(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	664 break;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	665 case Z80_SBC:
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	666 cycles = 4;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	667 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	668 cycles += 12;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	669 } else if(inst->addr_mode == Z80_IMMED) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	670 cycles += 3;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	671 } else if(z80_size(inst) == SZ_W) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	672 cycles += 4;
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	673 }
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	674 dst = zcycles(dst, cycles);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	675 dst = translate_z80_reg(inst, &dst_op, dst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	676 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
399 acaae7c3d34c Fix adc and sbc Mike Pavone <pavone@retrodev.com> parents: 397 diff changeset	677 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	678 if (src_op.mode == MODE_REG_DIRECT) {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	679 dst = sbb_rr(dst, src_op.base, dst_op.base, z80_size(inst));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	680 } else {
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	681 dst = sbb_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	682 }
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	683 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
309 cb6a37861e42 Correctly set the N flag for SBC Mike Pavone <pavone@retrodev.com> parents: 308 diff changeset	684 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	685 //TODO: Implement half-carry flag
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	686 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	687 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	688 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	689 dst = z80_save_reg(dst, inst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	690 dst = z80_save_ea(dst, inst, opts);
9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	691 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	692 case Z80_AND:
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	693 cycles = 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	694 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	695 cycles += 12;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	696 } else if(inst->addr_mode == Z80_IMMED) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	697 cycles += 3;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	698 } else if(z80_size(inst) == SZ_W) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	699 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	700 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	701 dst = zcycles(dst, cycles);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	702 dst = translate_z80_reg(inst, &dst_op, dst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	703 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	704 if (src_op.mode == MODE_REG_DIRECT) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	705 dst = and_rr(dst, src_op.base, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	706 } else {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	707 dst = and_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	708 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	709 //TODO: Cleanup flags
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	710 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	711 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	712 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	713 if (z80_size(inst) == SZ_B) {
305 a57fac5b3d65 Contrary to the official documenation, OR and AND also set PV based on parity instead of overflow Mike Pavone <pavone@retrodev.com> parents: 304 diff changeset	714 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	715 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	716 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	717 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	718 dst = z80_save_reg(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	719 dst = z80_save_ea(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	720 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	721 case Z80_OR:
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	722 cycles = 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	723 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	724 cycles += 12;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	725 } else if(inst->addr_mode == Z80_IMMED) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	726 cycles += 3;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	727 } else if(z80_size(inst) == SZ_W) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	728 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	729 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	730 dst = zcycles(dst, cycles);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	731 dst = translate_z80_reg(inst, &dst_op, dst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	732 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	733 if (src_op.mode == MODE_REG_DIRECT) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	734 dst = or_rr(dst, src_op.base, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	735 } else {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	736 dst = or_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	737 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	738 //TODO: Cleanup flags
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	739 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	740 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	741 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	742 if (z80_size(inst) == SZ_B) {
305 a57fac5b3d65 Contrary to the official documenation, OR and AND also set PV based on parity instead of overflow Mike Pavone <pavone@retrodev.com> parents: 304 diff changeset	743 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	744 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	745 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	746 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	747 dst = z80_save_reg(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	748 dst = z80_save_ea(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	749 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	750 case Z80_XOR:
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	751 cycles = 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	752 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	753 cycles += 12;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	754 } else if(inst->addr_mode == Z80_IMMED) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	755 cycles += 3;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	756 } else if(z80_size(inst) == SZ_W) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	757 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	758 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	759 dst = zcycles(dst, cycles);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	760 dst = translate_z80_reg(inst, &dst_op, dst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	761 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	762 if (src_op.mode == MODE_REG_DIRECT) {
295 dba661846579 Fix stupid copy-pasta bug in XOR Mike Pavone <pavone@retrodev.com> parents: 294 diff changeset	763 dst = xor_rr(dst, src_op.base, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	764 } else {
295 dba661846579 Fix stupid copy-pasta bug in XOR Mike Pavone <pavone@retrodev.com> parents: 294 diff changeset	765 dst = xor_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	766 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	767 //TODO: Cleanup flags
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	768 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	769 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	770 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	771 if (z80_size(inst) == SZ_B) {
304 8dcc9d14413c Set PV flag based on parity, not overflow for XOR Mike Pavone <pavone@retrodev.com> parents: 303 diff changeset	772 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	773 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	774 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	775 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	776 dst = z80_save_reg(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	777 dst = z80_save_ea(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	778 break;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	779 case Z80_CP:
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	780 cycles = 4;
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	781 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	782 cycles += 12;
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	783 } else if(inst->addr_mode == Z80_IMMED) {
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	784 cycles += 3;
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	785 }
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	786 dst = zcycles(dst, cycles);
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	787 dst = translate_z80_reg(inst, &dst_op, dst, opts);
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	788 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	789 if (src_op.mode == MODE_REG_DIRECT) {
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	790 dst = cmp_rr(dst, src_op.base, dst_op.base, z80_size(inst));
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	791 } else {
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	792 dst = cmp_ir(dst, src_op.disp, dst_op.base, z80_size(inst));
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	793 }
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	794 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	795 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B);
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	796 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	797 //TODO: Implement half-carry flag
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	798 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	799 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	800 dst = z80_save_reg(dst, inst, opts);
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	801 dst = z80_save_ea(dst, inst, opts);
d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	802 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	803 case Z80_INC:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	804 cycles = 4;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	805 if (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	806 cycles += 6;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	807 } else if(z80_size(inst) == SZ_W) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	808 cycles += 2;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	809 } else if(inst->reg == Z80_IXH \|\| inst->reg == Z80_IXL \|\| inst->reg == Z80_IYH \|\| inst->reg == Z80_IYL \|\| inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	810 cycles += 4;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	811 }
373 91d28a868551 Fix cycle count for inc and dec Mike Pavone <pavone@retrodev.com> parents: 372 diff changeset	812 dst = zcycles(dst, cycles);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	813 dst = translate_z80_reg(inst, &dst_op, dst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	814 if (dst_op.mode == MODE_UNUSED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	815 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	816 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	817 dst = add_ir(dst, 1, dst_op.base, z80_size(inst));
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	818 if (z80_size(inst) == SZ_B) {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	819 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	820 //TODO: Implement half-carry flag
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	821 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	822 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	823 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	824 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	825 dst = z80_save_reg(dst, inst, opts);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	826 dst = z80_save_ea(dst, inst, opts);
387 582a68a90708 Fix dec and inc when the operand is in memory Mike Pavone <pavone@retrodev.com> parents: 385 diff changeset	827 dst = z80_save_result(dst, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	828 break;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	829 case Z80_DEC:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	830 cycles = 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	831 if (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	832 cycles += 6;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	833 } else if(z80_size(inst) == SZ_W) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	834 cycles += 2;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	835 } else if(inst->reg == Z80_IXH \|\| inst->reg == Z80_IXL \|\| inst->reg == Z80_IYH \|\| inst->reg == Z80_IYL \|\| inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	836 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	837 }
373 91d28a868551 Fix cycle count for inc and dec Mike Pavone <pavone@retrodev.com> parents: 372 diff changeset	838 dst = zcycles(dst, cycles);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	839 dst = translate_z80_reg(inst, &dst_op, dst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	840 if (dst_op.mode == MODE_UNUSED) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	841 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	842 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	843 dst = sub_ir(dst, 1, dst_op.base, z80_size(inst));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	844 if (z80_size(inst) == SZ_B) {
311 56fcbfb8767a Set the N flag to the correct value for DEC instructions Mike Pavone <pavone@retrodev.com> parents: 310 diff changeset	845 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	846 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	847 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	848 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	849 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	850 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	851 dst = z80_save_reg(dst, inst, opts);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	852 dst = z80_save_ea(dst, inst, opts);
387 582a68a90708 Fix dec and inc when the operand is in memory Mike Pavone <pavone@retrodev.com> parents: 385 diff changeset	853 dst = z80_save_result(dst, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	854 break;
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	855 //case Z80_DAA:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	856 case Z80_CPL:
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	857 dst = zcycles(dst, 4);
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	858 dst = not_r(dst, opts->regs[Z80_A], SZ_B);
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	859 //TODO: Implement half-carry flag
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	860 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B);
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	861 break;
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	862 case Z80_NEG:
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	863 dst = zcycles(dst, 8);
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	864 dst = neg_r(dst, opts->regs[Z80_A], SZ_B);
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	865 //TODO: Implement half-carry flag
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	866 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	867 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	868 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	869 dst = setcc_rdisp8(dst, CC_O, CONTEXT, zf_off(ZF_PV));
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	870 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_N), SZ_B);
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	871 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	872 case Z80_CCF:
257 4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	873 dst = zcycles(dst, 4);
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	874 dst = xor_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B);
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	875 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	876 //TODO: Implement half-carry flag
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	877 break;
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	878 case Z80_SCF:
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	879 dst = zcycles(dst, 4);
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	880 dst = mov_irdisp8(dst, 1, CONTEXT, zf_off(ZF_C), SZ_B);
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	881 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	882 //TODO: Implement half-carry flag
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	883 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	884 case Z80_NOP:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	885 if (inst->immed == 42) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	886 dst = call(dst, (uint8_t *)z80_save_context);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	887 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	888 dst = jmp(dst, (uint8_t *)z80_print_regs_exit);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	889 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	890 dst = zcycles(dst, 4 * inst->immed);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	891 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	892 break;
285 021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	893 case Z80_HALT:
021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	894 dst = zcycles(dst, 4);
021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	895 dst = mov_ir(dst, address, SCRATCH1, SZ_W);
021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	896 uint8_t * call_inst = dst;
021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	897 dst = call(dst, (uint8_t *)z80_halt);
021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	898 dst = jmp(dst, call_inst);
021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	899 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	900 case Z80_DI:
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	901 dst = zcycles(dst, 4);
2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	902 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff1), SZ_B);
2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	903 dst = mov_irdisp8(dst, 0, CONTEXT, offsetof(z80_context, iff2), SZ_B);
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	904 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, sync_cycle), ZLIMIT, SZ_D);
401 f54af24aad1d Fix DI Mike Pavone <pavone@retrodev.com> parents: 399 diff changeset	905 dst = mov_irdisp8(dst, 0xFFFFFFFF, CONTEXT, offsetof(z80_context, int_cycle), SZ_D);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	906 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	907 case Z80_EI:
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	908 dst = zcycles(dst, 4);
420 9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 401 diff changeset	909 dst = mov_rrdisp32(dst, ZCYCLES, CONTEXT, offsetof(z80_context, int_enable_cycle), SZ_D);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	910 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff1), SZ_B);
2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	911 dst = mov_irdisp8(dst, 1, CONTEXT, offsetof(z80_context, iff2), SZ_B);
335 14a937097c2b Some Z80 interrupt fixes Mike Pavone <pavone@retrodev.com> parents: 315 diff changeset	912 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles
420 9fb111b5641f Fix access to int_enable_cycle in EI Mike Pavone <pavone@retrodev.com> parents: 401 diff changeset	913 dst = add_irdisp32(dst, 4, CONTEXT, offsetof(z80_context, int_enable_cycle), SZ_D);
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	914 dst = call(dst, (uint8_t *)z80_do_sync);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	915 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	916 case Z80_IM:
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	917 dst = zcycles(dst, 4);
2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	918 dst = mov_irdisp8(dst, inst->immed, CONTEXT, offsetof(z80_context, im), SZ_B);
2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	919 break;
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	920 case Z80_RLC:
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	921 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	922 dst = zcycles(dst, cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	923 if (inst->addr_mode != Z80_UNUSED) {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	924 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	925 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	926 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	927 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	928 src_op.mode = MODE_UNUSED;
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	929 dst = translate_z80_reg(inst, &dst_op, dst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	930 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	931 dst = rol_ir(dst, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	932 if (src_op.mode != MODE_UNUSED) {
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	933 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	934 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	935 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	936 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	937 //TODO: Implement half-carry flag
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	938 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	939 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	940 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	941 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	942 if (inst->addr_mode != Z80_UNUSED) {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	943 dst = z80_save_result(dst, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	944 if (src_op.mode != MODE_UNUSED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	945 dst = z80_save_reg(dst, inst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	946 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	947 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	948 dst = z80_save_reg(dst, inst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	949 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	950 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	951 case Z80_RL:
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	952 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	953 dst = zcycles(dst, cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	954 if (inst->addr_mode != Z80_UNUSED) {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	955 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	956 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	957 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	958 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	959 src_op.mode = MODE_UNUSED;
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	960 dst = translate_z80_reg(inst, &dst_op, dst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	961 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	962 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	963 dst = rcl_ir(dst, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	964 if (src_op.mode != MODE_UNUSED) {
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	965 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	966 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	967 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	968 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	969 //TODO: Implement half-carry flag
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	970 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	971 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	972 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	973 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	974 if (inst->addr_mode != Z80_UNUSED) {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	975 dst = z80_save_result(dst, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	976 if (src_op.mode != MODE_UNUSED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	977 dst = z80_save_reg(dst, inst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	978 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	979 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	980 dst = z80_save_reg(dst, inst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	981 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	982 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	983 case Z80_RRC:
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	984 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	985 dst = zcycles(dst, cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	986 if (inst->addr_mode != Z80_UNUSED) {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	987 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	988 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	989 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	990 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	991 src_op.mode = MODE_UNUSED;
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	992 dst = translate_z80_reg(inst, &dst_op, dst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	993 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	994 dst = ror_ir(dst, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	995 if (src_op.mode != MODE_UNUSED) {
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	996 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	997 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	998 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	999 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1000 //TODO: Implement half-carry flag
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1001 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1002 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1003 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1004 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1005 if (inst->addr_mode != Z80_UNUSED) {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1006 dst = z80_save_result(dst, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1007 if (src_op.mode != MODE_UNUSED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1008 dst = z80_save_reg(dst, inst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1009 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1010 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1011 dst = z80_save_reg(dst, inst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1012 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1013 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1014 case Z80_RR:
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1015 cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1016 dst = zcycles(dst, cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1017 if (inst->addr_mode != Z80_UNUSED) {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1018 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1019 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1020 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1021 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1022 src_op.mode = MODE_UNUSED;
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1023 dst = translate_z80_reg(inst, &dst_op, dst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1024 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1025 dst = bt_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1026 dst = rcr_ir(dst, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	1027 if (src_op.mode != MODE_UNUSED) {
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1028 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1029 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1030 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1031 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1032 //TODO: Implement half-carry flag
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1033 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1034 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1035 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1036 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1037 if (inst->addr_mode != Z80_UNUSED) {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1038 dst = z80_save_result(dst, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1039 if (src_op.mode != MODE_UNUSED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1040 dst = z80_save_reg(dst, inst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1041 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1042 } else {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1043 dst = z80_save_reg(dst, inst, opts);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1044 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1045 break;
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1046 case Z80_SLA:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1047 case Z80_SLL:
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1048 cycles = inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8;
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1049 dst = zcycles(dst, cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1050 if (inst->addr_mode != Z80_UNUSED) {
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1051 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1052 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1053 dst = zcycles(dst, 1);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1054 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1055 src_op.mode = MODE_UNUSED;
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1056 dst = translate_z80_reg(inst, &dst_op, dst, opts);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1057 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1058 dst = shl_ir(dst, 1, dst_op.base, SZ_B);
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1059 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1060 if (inst->op == Z80_SLL) {
bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1061 dst = or_ir(dst, 1, dst_op.base, SZ_B);
bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1062 }
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	1063 if (src_op.mode != MODE_UNUSED) {
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1064 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1065 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1066 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1067 //TODO: Implement half-carry flag
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1068 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1069 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1070 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1071 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1072 if (inst->addr_mode != Z80_UNUSED) {
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1073 dst = z80_save_result(dst, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1074 if (src_op.mode != MODE_UNUSED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1075 dst = z80_save_reg(dst, inst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1076 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1077 } else {
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1078 dst = z80_save_reg(dst, inst, opts);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1079 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1080 break;
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1081 case Z80_SRA:
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1082 cycles = inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8;
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1083 dst = zcycles(dst, cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1084 if (inst->addr_mode != Z80_UNUSED) {
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1085 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1086 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1087 dst = zcycles(dst, 1);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1088 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1089 src_op.mode = MODE_UNUSED;
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1090 dst = translate_z80_reg(inst, &dst_op, dst, opts);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1091 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1092 dst = sar_ir(dst, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	1093 if (src_op.mode != MODE_UNUSED) {
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1094 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1095 }
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1096 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1097 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1098 //TODO: Implement half-carry flag
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1099 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1100 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1101 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1102 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1103 if (inst->addr_mode != Z80_UNUSED) {
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1104 dst = z80_save_result(dst, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1105 if (src_op.mode != MODE_UNUSED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1106 dst = z80_save_reg(dst, inst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1107 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1108 } else {
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1109 dst = z80_save_reg(dst, inst, opts);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1110 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1111 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1112 case Z80_SRL:
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1113 cycles = inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8;
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1114 dst = zcycles(dst, cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1115 if (inst->addr_mode != Z80_UNUSED) {
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1116 dst = translate_z80_ea(inst, &dst_op, dst, opts, READ, MODIFY);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1117 dst = translate_z80_reg(inst, &src_op, dst, opts); //For IX/IY variants that also write to a register
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1118 dst = zcycles(dst, 1);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1119 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1120 src_op.mode = MODE_UNUSED;
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1121 dst = translate_z80_reg(inst, &dst_op, dst, opts);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1122 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1123 dst = shr_ir(dst, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	1124 if (src_op.mode != MODE_UNUSED) {
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1125 dst = mov_rr(dst, dst_op.base, src_op.base, SZ_B);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1126 }
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1127 dst = setcc_rdisp8(dst, CC_C, CONTEXT, zf_off(ZF_C));
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1128 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1129 //TODO: Implement half-carry flag
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1130 dst = cmp_ir(dst, 0, dst_op.base, SZ_B);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1131 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1132 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1133 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1134 if (inst->addr_mode != Z80_UNUSED) {
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1135 dst = z80_save_result(dst, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1136 if (src_op.mode != MODE_UNUSED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1137 dst = z80_save_reg(dst, inst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1138 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1139 } else {
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1140 dst = z80_save_reg(dst, inst, opts);
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1141 }
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1142 break;
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1143 case Z80_RLD:
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1144 dst = zcycles(dst, 8);
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1145 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W);
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1146 dst = call(dst, (uint8_t *)z80_read_byte);
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1147 //Before: (HL) = 0x12, A = 0x34
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1148 //After: (HL) = 0x24, A = 0x31
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1149 dst = mov_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B);
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1150 dst = shl_ir(dst, 4, SCRATCH1, SZ_W);
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1151 dst = and_ir(dst, 0xF, SCRATCH2, SZ_W);
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1152 dst = and_ir(dst, 0xFFF, SCRATCH1, SZ_W);
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1153 dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B);
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1154 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_W);
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1155 //SCRATCH1 = 0x0124
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1156 dst = ror_ir(dst, 8, SCRATCH1, SZ_W);
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1157 dst = zcycles(dst, 4);
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1158 dst = or_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1159 //set flags
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1160 //TODO: Implement half-carry flag
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1161 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1162 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1163 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1164 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1165
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1166 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W);
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1167 dst = ror_ir(dst, 8, SCRATCH1, SZ_W);
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1168 dst = call(dst, (uint8_t *)z80_write_byte);
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1169 break;
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1170 case Z80_RRD:
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1171 dst = zcycles(dst, 8);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1172 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH1, SZ_W);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1173 dst = call(dst, (uint8_t *)z80_read_byte);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1174 //Before: (HL) = 0x12, A = 0x34
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1175 //After: (HL) = 0x41, A = 0x32
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1176 dst = movzx_rr(dst, opts->regs[Z80_A], SCRATCH2, SZ_B, SZ_W);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1177 dst = ror_ir(dst, 4, SCRATCH1, SZ_W);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1178 dst = shl_ir(dst, 4, SCRATCH2, SZ_W);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1179 dst = and_ir(dst, 0xF00F, SCRATCH1, SZ_W);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1180 dst = and_ir(dst, 0xF0, opts->regs[Z80_A], SZ_B);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1181 //SCRATCH1 = 0x2001
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1182 //SCRATCH2 = 0x0040
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1183 dst = or_rr(dst, SCRATCH2, SCRATCH1, SZ_W);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1184 //SCRATCH1 = 0x2041
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1185 dst = ror_ir(dst, 8, SCRATCH1, SZ_W);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1186 dst = zcycles(dst, 4);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1187 dst = shr_ir(dst, 4, SCRATCH1, SZ_B);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1188 dst = or_rr(dst, SCRATCH1, opts->regs[Z80_A], SZ_B);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1189 //set flags
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1190 //TODO: Implement half-carry flag
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1191 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1192 dst = setcc_rdisp8(dst, CC_P, CONTEXT, zf_off(ZF_PV));
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1193 dst = setcc_rdisp8(dst, CC_Z, CONTEXT, zf_off(ZF_Z));
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1194 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1195
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1196 dst = mov_rr(dst, opts->regs[Z80_HL], SCRATCH2, SZ_W);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1197 dst = ror_ir(dst, 8, SCRATCH1, SZ_W);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1198 dst = call(dst, (uint8_t *)z80_write_byte);
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1199 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1200 case Z80_BIT: {
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1201 cycles = (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1202 dst = zcycles(dst, cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1203 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1204 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1205 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1206 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1207 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1208 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1209 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1210 bit = inst->immed;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1211 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, DONT_MODIFY);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1212 }
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1213 if (inst->addr_mode != Z80_REG) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1214 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1215 dst = zcycles(dst, 1);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1216 }
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1217 dst = bt_ir(dst, bit, src_op.base, size);
303 8290d3086ff0 BIT was setting the zero flag to the opposite of what it should have. This is now fixed. Mike Pavone <pavone@retrodev.com> parents: 302 diff changeset	1218 dst = setcc_rdisp8(dst, CC_NC, CONTEXT, zf_off(ZF_Z));
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1219 dst = setcc_rdisp8(dst, CC_NC, CONTEXT, zf_off(ZF_PV));
b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1220 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_N), SZ_B);
b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1221 if (inst->immed == 7) {
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1222 dst = cmp_ir(dst, 0, src_op.base, size);
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1223 dst = setcc_rdisp8(dst, CC_S, CONTEXT, zf_off(ZF_S));
b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1224 } else {
b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1225 dst = mov_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B);
b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1226 }
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1227 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1228 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1229 case Z80_SET: {
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1230 cycles = (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1231 dst = zcycles(dst, cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1232 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1233 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1234 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1235 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1236 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1237 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1238 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1239 bit = inst->immed;
384 5500d1d1269e Fix set/res when the operand is in memory Mike Pavone <pavone@retrodev.com> parents: 373 diff changeset	1240 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, MODIFY);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1241 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1242 if (inst->reg != Z80_USE_IMMED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1243 dst = translate_z80_reg(inst, &dst_op, dst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1244 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1245 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1246 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1247 dst = zcycles(dst, 1);
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1248 }
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1249 dst = bts_ir(dst, bit, src_op.base, size);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1250 if (inst->reg != Z80_USE_IMMED) {
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1251 if (size == SZ_W) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1252 if (dst_op.base >= R8) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1253 dst = ror_ir(dst, 8, src_op.base, SZ_W);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1254 dst = mov_rr(dst, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1255 dst = ror_ir(dst, 8, src_op.base, SZ_W);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1256 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1257 dst = mov_rr(dst, opts->regs[inst->ea_reg], dst_op.base, SZ_B);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1258 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1259 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1260 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_B);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1261 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1262 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1263 if ((inst->addr_mode & 0x1F) != Z80_REG) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1264 dst = z80_save_result(dst, inst);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1265 if (inst->reg != Z80_USE_IMMED) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1266 dst = z80_save_reg(dst, inst, opts);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1267 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1268 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1269 break;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1270 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1271 case Z80_RES: {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1272 cycles = (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1273 dst = zcycles(dst, cycles);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1274 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1275 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1276 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1277 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1278 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1279 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1280 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1281 bit = inst->immed;
384 5500d1d1269e Fix set/res when the operand is in memory Mike Pavone <pavone@retrodev.com> parents: 373 diff changeset	1282 dst = translate_z80_ea(inst, &src_op, dst, opts, READ, MODIFY);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1283 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1284 if (inst->reg != Z80_USE_IMMED) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1285 dst = translate_z80_reg(inst, &dst_op, dst, opts);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1286 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1287 if (inst->addr_mode != Z80_REG) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1288 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1289 dst = zcycles(dst, 1);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1290 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1291 dst = btr_ir(dst, bit, src_op.base, size);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1292 if (inst->reg != Z80_USE_IMMED) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1293 if (size == SZ_W) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1294 if (dst_op.base >= R8) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1295 dst = ror_ir(dst, 8, src_op.base, SZ_W);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1296 dst = mov_rr(dst, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1297 dst = ror_ir(dst, 8, src_op.base, SZ_W);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1298 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1299 dst = mov_rr(dst, opts->regs[inst->ea_reg], dst_op.base, SZ_B);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1300 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1301 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1302 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_B);
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1303 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1304 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1305 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1306 dst = z80_save_result(dst, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1307 if (inst->reg != Z80_USE_IMMED) {
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1308 dst = z80_save_reg(dst, inst, opts);
42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1309 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1310 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1311 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1312 }
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1313 case Z80_JP: {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1314 cycles = 4;
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1315 if (inst->addr_mode != Z80_REG) {
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1316 cycles += 6;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1317 } else if(inst->ea_reg == Z80_IX \|\| inst->ea_reg == Z80_IY) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1318 cycles += 4;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1319 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1320 dst = zcycles(dst, cycles);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1321 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) {
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1322 uint8_t * call_dst = z80_get_native_address(context, inst->immed);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1323 if (!call_dst) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1324 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1325 //fake address to force large displacement
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1326 call_dst = dst + 256;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1327 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1328 dst = jmp(dst, call_dst);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1329 } else {
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1330 if (inst->addr_mode == Z80_REG_INDIRECT) {
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1331 dst = mov_rr(dst, opts->regs[inst->ea_reg], SCRATCH1, SZ_W);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1332 } else {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1333 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1334 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1335 dst = call(dst, (uint8_t *)z80_native_addr);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1336 dst = jmp_r(dst, SCRATCH1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1337 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1338 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1339 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1340 case Z80_JPCC: {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1341 dst = zcycles(dst, 7);//T States: 4,3
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1342 uint8_t cond = CC_Z;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1343 switch (inst->reg)
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1344 {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1345 case Z80_CC_NZ:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1346 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1347 case Z80_CC_Z:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1348 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1349 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1350 case Z80_CC_NC:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1351 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1352 case Z80_CC_C:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1353 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1354 break;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1355 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1356 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1357 case Z80_CC_PE:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1358 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1359 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1360 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	1361 cond = CC_NZ;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1362 case Z80_CC_M:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1363 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1364 break;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1365 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1366 uint8_t *no_jump_off = dst+1;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1367 dst = jcc(dst, cond, dst+2);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1368 dst = zcycles(dst, 5);//T States: 5
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1369 uint16_t dest_addr = inst->immed;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1370 if (dest_addr < 0x4000) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1371 uint8_t * call_dst = z80_get_native_address(context, dest_addr);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1372 if (!call_dst) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1373 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1374 //fake address to force large displacement
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1375 call_dst = dst + 256;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1376 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1377 dst = jmp(dst, call_dst);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1378 } else {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1379 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1380 dst = call(dst, (uint8_t *)z80_native_addr);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1381 dst = jmp_r(dst, SCRATCH1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1382 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1383 *no_jump_off = dst - (no_jump_off+1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1384 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1385 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1386 case Z80_JR: {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1387 dst = zcycles(dst, 12);//T States: 4,3,5
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1388 uint16_t dest_addr = address + inst->immed + 2;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1389 if (dest_addr < 0x4000) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1390 uint8_t * call_dst = z80_get_native_address(context, dest_addr);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1391 if (!call_dst) {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1392 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1393 //fake address to force large displacement
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1394 call_dst = dst + 256;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1395 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1396 dst = jmp(dst, call_dst);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1397 } else {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1398 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1399 dst = call(dst, (uint8_t *)z80_native_addr);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1400 dst = jmp_r(dst, SCRATCH1);
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1401 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1402 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1403 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1404 case Z80_JRCC: {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1405 dst = zcycles(dst, 7);//T States: 4,3
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1406 uint8_t cond = CC_Z;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1407 switch (inst->reg)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1408 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1409 case Z80_CC_NZ:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1410 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1411 case Z80_CC_Z:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1412 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1413 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1414 case Z80_CC_NC:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1415 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1416 case Z80_CC_C:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1417 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1418 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1419 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1420 uint8_t *no_jump_off = dst+1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1421 dst = jcc(dst, cond, dst+2);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1422 dst = zcycles(dst, 5);//T States: 5
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1423 uint16_t dest_addr = address + inst->immed + 2;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1424 if (dest_addr < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1425 uint8_t * call_dst = z80_get_native_address(context, dest_addr);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1426 if (!call_dst) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1427 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1428 //fake address to force large displacement
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1429 call_dst = dst + 256;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1430 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1431 dst = jmp(dst, call_dst);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1432 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1433 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1434 dst = call(dst, (uint8_t *)z80_native_addr);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1435 dst = jmp_r(dst, SCRATCH1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1436 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1437 *no_jump_off = dst - (no_jump_off+1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1438 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1439 }
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1440 case Z80_DJNZ:
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1441 dst = zcycles(dst, 8);//T States: 5,3
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1442 dst = sub_ir(dst, 1, opts->regs[Z80_B], SZ_B);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1443 uint8_t *no_jump_off = dst+1;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1444 dst = jcc(dst, CC_Z, dst+2);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1445 dst = zcycles(dst, 5);//T States: 5
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1446 uint16_t dest_addr = address + inst->immed + 2;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1447 if (dest_addr < 0x4000) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1448 uint8_t * call_dst = z80_get_native_address(context, dest_addr);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1449 if (!call_dst) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1450 opts->deferred = defer_address(opts->deferred, dest_addr, dst + 1);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1451 //fake address to force large displacement
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1452 call_dst = dst + 256;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1453 }
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1454 dst = jmp(dst, call_dst);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1455 } else {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1456 dst = mov_ir(dst, dest_addr, SCRATCH1, SZ_W);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1457 dst = call(dst, (uint8_t *)z80_native_addr);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1458 dst = jmp_r(dst, SCRATCH1);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1459 }
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1460 *no_jump_off = dst - (no_jump_off+1);
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1461 break;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1462 case Z80_CALL: {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1463 dst = zcycles(dst, 11);//T States: 4,3,4
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1464 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	1465 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	1466 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1467 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1468 if (inst->immed < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1469 uint8_t * call_dst = z80_get_native_address(context, inst->immed);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1470 if (!call_dst) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1471 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1472 //fake address to force large displacement
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1473 call_dst = dst + 256;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1474 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1475 dst = jmp(dst, call_dst);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1476 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1477 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1478 dst = call(dst, (uint8_t *)z80_native_addr);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1479 dst = jmp_r(dst, SCRATCH1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1480 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1481 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1482 }
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1483 case Z80_CALLCC:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1484 dst = zcycles(dst, 10);//T States: 4,3,3 (false case)
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1485 uint8_t cond = CC_Z;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1486 switch (inst->reg)
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1487 {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1488 case Z80_CC_NZ:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1489 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1490 case Z80_CC_Z:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1491 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1492 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1493 case Z80_CC_NC:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1494 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1495 case Z80_CC_C:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1496 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1497 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1498 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1499 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1500 case Z80_CC_PE:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1501 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1502 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1503 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	1504 cond = CC_NZ;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1505 case Z80_CC_M:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1506 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1507 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1508 }
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1509 uint8_t *no_call_off = dst+1;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1510 dst = jcc(dst, cond, dst+2);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1511 dst = zcycles(dst, 1);//Last of the above T states takes an extra cycle in the true case
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1512 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	1513 dst = mov_ir(dst, address + 3, SCRATCH1, SZ_W);
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	1514 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1515 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1516 if (inst->immed < 0x4000) {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1517 uint8_t * call_dst = z80_get_native_address(context, inst->immed);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1518 if (!call_dst) {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1519 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1520 //fake address to force large displacement
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1521 call_dst = dst + 256;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1522 }
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1523 dst = jmp(dst, call_dst);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1524 } else {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1525 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_W);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1526 dst = call(dst, (uint8_t *)z80_native_addr);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1527 dst = jmp_r(dst, SCRATCH1);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1528 }
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1529 *no_call_off = dst - (no_call_off+1);
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1530 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1531 case Z80_RET:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1532 dst = zcycles(dst, 4);//T States: 4
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1533 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1534 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1535 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1536 dst = call(dst, (uint8_t *)z80_native_addr);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1537 dst = jmp_r(dst, SCRATCH1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1538 break;
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1539 case Z80_RETCC: {
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1540 dst = zcycles(dst, 5);//T States: 5
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1541 uint8_t cond = CC_Z;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1542 switch (inst->reg)
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1543 {
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1544 case Z80_CC_NZ:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1545 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1546 case Z80_CC_Z:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1547 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_Z), SZ_B);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1548 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1549 case Z80_CC_NC:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1550 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1551 case Z80_CC_C:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1552 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_C), SZ_B);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1553 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1554 case Z80_CC_PO:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1555 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1556 case Z80_CC_PE:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1557 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_PV), SZ_B);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1558 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1559 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	1560 cond = CC_NZ;
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1561 case Z80_CC_M:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1562 dst = cmp_irdisp8(dst, 0, CONTEXT, zf_off(ZF_S), SZ_B);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1563 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1564 }
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1565 uint8_t *no_call_off = dst+1;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1566 dst = jcc(dst, cond, dst+2);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1567 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1568 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1569 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1570 dst = call(dst, (uint8_t *)z80_native_addr);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1571 dst = jmp_r(dst, SCRATCH1);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1572 *no_call_off = dst - (no_call_off+1);
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1573 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1574 }
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1575 case Z80_RETI:
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1576 //For some systems, this may need a callback for signalling interrupt routine completion
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1577 dst = zcycles(dst, 8);//T States: 4, 4
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1578 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1579 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1580 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1581 dst = call(dst, (uint8_t *)z80_native_addr);
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1582 dst = jmp_r(dst, SCRATCH1);
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1583 break;
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1584 case Z80_RETN:
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1585 dst = zcycles(dst, 8);//T States: 4, 4
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1586 dst = mov_rdisp8r(dst, CONTEXT, offsetof(z80_context, iff2), SCRATCH2, SZ_B);
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1587 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH1, SZ_W);
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1588 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(z80_context, iff1), SZ_B);
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1589 dst = call(dst, (uint8_t *)z80_read_word);//T STates: 3, 3
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1590 dst = add_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1591 dst = call(dst, (uint8_t *)z80_native_addr);
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1592 dst = jmp_r(dst, SCRATCH1);
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1593 break;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1594 case Z80_RST: {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1595 //RST is basically CALL to an address in page 0
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1596 dst = zcycles(dst, 5);//T States: 5
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1597 dst = sub_ir(dst, 2, opts->regs[Z80_SP], SZ_W);
315 684e71e9f0d0 Fix return address for RST Mike Pavone <pavone@retrodev.com> parents: 314 diff changeset	1598 dst = mov_ir(dst, address + 1, SCRATCH1, SZ_W);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	1599 dst = mov_rr(dst, opts->regs[Z80_SP], SCRATCH2, SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1600 dst = call(dst, (uint8_t *)z80_write_word_highfirst);//T States: 3, 3
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1601 uint8_t * call_dst = z80_get_native_address(context, inst->immed);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1602 if (!call_dst) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1603 opts->deferred = defer_address(opts->deferred, inst->immed, dst + 1);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1604 //fake address to force large displacement
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1605 call_dst = dst + 256;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1606 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1607 dst = jmp(dst, call_dst);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1608 break;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1609 }
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1610 case Z80_IN:
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1611 dst = zcycles(dst, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1612 if (inst->addr_mode == Z80_IMMED_INDIRECT) {
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1613 dst = mov_ir(dst, inst->immed, SCRATCH1, SZ_B);
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1614 } else {
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1615 dst = mov_rr(dst, opts->regs[Z80_C], SCRATCH1, SZ_B);
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1616 }
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1617 dst = call(dst, (uint8_t *)z80_io_read);
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1618 translate_z80_reg(inst, &dst_op, dst, opts);
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1619 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_B);
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1620 dst = z80_save_reg(dst, inst, opts);
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1621 break;
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1622 /*case Z80_INI:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1623 case Z80_INIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1624 case Z80_IND:
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1625 case Z80_INDR:*/
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1626 case Z80_OUT:
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1627 dst = zcycles(dst, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1628 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) {
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1629 dst = mov_ir(dst, inst->immed, SCRATCH2, SZ_B);
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1630 } else {
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1631 dst = mov_rr(dst, opts->regs[Z80_C], SCRATCH2, SZ_B);
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1632 }
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1633 translate_z80_reg(inst, &src_op, dst, opts);
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1634 dst = mov_rr(dst, dst_op.base, SCRATCH1, SZ_B);
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1635 dst = call(dst, (uint8_t *)z80_io_write);
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1636 dst = z80_save_reg(dst, inst, opts);
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1637 break;
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1638 /*case Z80_OUTI:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1639 case Z80_OTIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1640 case Z80_OUTD:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1641 case Z80_OTDR:*/
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1642 default: {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1643 char disbuf[80];
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	1644 z80_disasm(inst, disbuf, address);
424 7e8e179116af Add support for loading GST format savestates Mike Pavone <pavone@retrodev.com> parents: 420 diff changeset	1645 fprintf(stderr, "unimplemented instruction: %s at %X\n", disbuf, address);
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1646 FILE * f = fopen("zram.bin", "wb");
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1647 fwrite(context->mem_pointers[0], 1, 8 * 1024, f);
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1648 fclose(f);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1649 exit(1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1650 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1651 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1652 return dst;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1653 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1654
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1655 uint8_t * z80_get_native_address(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1656 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1657 native_map_slot *map;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1658 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1659 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1660 map = context->static_code_map;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1661 } else if (address >= 0x8000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1662 address &= 0x7FFF;
279 6be6056735a9 Fix native address lookup in bannked memory area Mike Pavone <pavone@retrodev.com> parents: 277 diff changeset	1663 map = context->banked_code_map + context->bank_reg;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1664 } else {
313 a13329645ea3 Fix terminal instruction detection in disassembler Mike Pavone <pavone@retrodev.com> parents: 312 diff changeset	1665 //dprintf("z80_get_native_address: %X NULL\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1666 return NULL;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1667 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1668 if (!map->base \|\| !map->offsets \|\| map->offsets[address] == INVALID_OFFSET \|\| map->offsets[address] == EXTENSION_WORD) {
313 a13329645ea3 Fix terminal instruction detection in disassembler Mike Pavone <pavone@retrodev.com> parents: 312 diff changeset	1669 //dprintf("z80_get_native_address: %X NULL\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1670 return NULL;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1671 }
313 a13329645ea3 Fix terminal instruction detection in disassembler Mike Pavone <pavone@retrodev.com> parents: 312 diff changeset	1672 //dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1673 return map->base + map->offsets[address];
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1674 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1675
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1676 uint8_t z80_get_native_inst_size(x86_z80_options * opts, uint32_t address)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1677 {
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1678 if (address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1679 return 0;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1680 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1681 return opts->ram_inst_sizes[address & 0x1FFF];
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1682 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1683
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1684 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1685 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1686 uint32_t orig_address = address;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1687 native_map_slot *map;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1688 x86_z80_options * opts = context->options;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1689 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1690 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1691 map = context->static_code_map;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1692 opts->ram_inst_sizes[address] = native_size;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1693 context->ram_code_flags[(address & 0x1C00) >> 10] \|= 1 << ((address & 0x380) >> 7);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1694 context->ram_code_flags[((address + size) & 0x1C00) >> 10] \|= 1 << (((address + size) & 0x380) >> 7);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1695 } else if (address >= 0x8000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1696 address &= 0x7FFF;
279 6be6056735a9 Fix native address lookup in bannked memory area Mike Pavone <pavone@retrodev.com> parents: 277 diff changeset	1697 map = context->banked_code_map + context->bank_reg;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1698 if (!map->offsets) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1699 map->offsets = malloc(sizeof(int32_t) * 0x8000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1700 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1701 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1702 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1703 return;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1704 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1705 if (!map->base) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1706 map->base = native_address;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1707 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1708 map->offsets[address] = native_address - map->base;
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	1709 for(--size, orig_address++; size; --size, orig_address++) {
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1710 address = orig_address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1711 if (address < 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1712 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1713 map = context->static_code_map;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1714 } else if (address >= 0x8000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1715 address &= 0x7FFF;
279 6be6056735a9 Fix native address lookup in bannked memory area Mike Pavone <pavone@retrodev.com> parents: 277 diff changeset	1716 map = context->banked_code_map + context->bank_reg;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1717 } else {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1718 return;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1719 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1720 if (!map->offsets) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1721 map->offsets = malloc(sizeof(int32_t) * 0x8000);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1722 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1723 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1724 map->offsets[address] = EXTENSION_WORD;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1725 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1726 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1727
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1728 #define INVALID_INSTRUCTION_START 0xFEEDFEED
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1729
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1730 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1731 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1732 if (!static_code_map->base \|\| address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1733 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1734 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1735 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1736 if (static_code_map->offsets[address] == INVALID_OFFSET) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1737 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1738 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1739 while (static_code_map->offsets[address] == EXTENSION_WORD) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1740 --address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1741 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1742 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1743 return address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1744 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1745
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1746 z80_context * z80_handle_code_write(uint32_t address, z80_context * context)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1747 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1748 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1749 if (inst_start != INVALID_INSTRUCTION_START) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1750 uint8_t * dst = z80_get_native_address(context, inst_start);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1751 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", dst, inst_start, address);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1752 dst = mov_ir(dst, inst_start, SCRATCH1, SZ_D);
390 561fe3ea3fc8 Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word Mike Pavone <pavone@retrodev.com> parents: 389 diff changeset	1753 dst = call(dst, (uint8_t *)z80_retrans_stub);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1754 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1755 return context;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1756 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1757
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1758 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address)
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1759 {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1760 uint8_t * addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1761 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1762 translate_z80_stream(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1763 addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1764 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1765 printf("Failed to translate %X to native code\n", address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1766 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1767 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1768 return addr;
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1769 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1770
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1771 void z80_handle_deferred(z80_context * context)
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1772 {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1773 x86_z80_options * opts = context->options;
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1774 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address);
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1775 if (opts->deferred) {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1776 translate_z80_stream(context, opts->deferred->address);
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1777 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1778 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1779
390 561fe3ea3fc8 Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word Mike Pavone <pavone@retrodev.com> parents: 389 diff changeset	1780 void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start)
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1781 {
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1782 char disbuf[80];
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1783 x86_z80_options * opts = context->options;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1784 uint8_t orig_size = z80_get_native_inst_size(opts, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1785 uint32_t orig = address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1786 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1787 uint8_t * dst = opts->cur_code;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1788 uint8_t * dst_end = opts->code_end;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1789 uint8_t after, inst = context->mem_pointers[0] + address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1790 z80inst instbuf;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1791 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1792 after = z80_decode(inst, &instbuf);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1793 #ifdef DO_DEBUG_PRINT
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	1794 z80_disasm(&instbuf, disbuf, address);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1795 if (instbuf.op == Z80_NOP) {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1796 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed);
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1797 } else {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1798 printf("%X\t%s\n", address, disbuf);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	1799 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1800 #endif
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1801 if (orig_size != ZMAX_NATIVE_SIZE) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1802 if (dst_end - dst < ZMAX_NATIVE_SIZE) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1803 size_t size = 1024*1024;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1804 dst = alloc_code(&size);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1805 opts->code_end = dst_end = dst + size;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1806 opts->cur_code = dst;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1807 }
282 7b8a49220e3b Remove deferred address entries from abandoned translations inside z80_retrans_inst Mike Pavone <pavone@retrodev.com> parents: 279 diff changeset	1808 deferred_addr * orig_deferred = opts->deferred;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1809 uint8_t * native_end = translate_z80inst(&instbuf, dst, context, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1810 if ((native_end - dst) <= orig_size) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1811 uint8_t * native_next = z80_get_native_address(context, address + after-inst);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1812 if (native_next && ((native_next == orig_start + orig_size) \|\| (orig_size - (native_end - dst)) > 5)) {
282 7b8a49220e3b Remove deferred address entries from abandoned translations inside z80_retrans_inst Mike Pavone <pavone@retrodev.com> parents: 279 diff changeset	1813 remove_deferred_until(&opts->deferred, orig_deferred);
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1814 native_end = translate_z80inst(&instbuf, orig_start, context, address);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1815 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1816 while (native_end < orig_start + orig_size) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1817 *(native_end++) = 0x90; //NOP
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1818 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1819 } else {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1820 jmp(native_end, native_next);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1821 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1822 z80_handle_deferred(context);
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1823 return orig_start;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1824 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1825 }
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1826 z80_map_native_address(context, address, dst, after-inst, ZMAX_NATIVE_SIZE);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1827 opts->cur_code = dst+ZMAX_NATIVE_SIZE;
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1828 jmp(orig_start, dst);
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1829 if (!z80_is_terminal(&instbuf)) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1830 jmp(native_end, z80_get_native_address_trans(context, address + after-inst));
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1831 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1832 z80_handle_deferred(context);
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1833 return dst;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1834 } else {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1835 dst = translate_z80inst(&instbuf, orig_start, context, address);
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1836 if (!z80_is_terminal(&instbuf)) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1837 dst = jmp(dst, z80_get_native_address_trans(context, address + after-inst));
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1838 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1839 z80_handle_deferred(context);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1840 return orig_start;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1841 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1842 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1843
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1844 void translate_z80_stream(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1845 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1846 char disbuf[80];
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1847 if (z80_get_native_address(context, address)) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1848 return;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1849 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1850 x86_z80_options * opts = context->options;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1851 uint8_t * encoded = NULL, *next;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1852 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1853 encoded = context->mem_pointers[0] + (address & 0x1FFF);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1854 } else if(address >= 0x8000 && context->mem_pointers[1]) {
394 d5f1840273b5 Bail out on attempt to run code from bank area until it is properly supported Mike Pavone <pavone@retrodev.com> parents: 390 diff changeset	1855 printf("attempt to translate Z80 code from banked area at address %X\n", address);
d5f1840273b5 Bail out on attempt to run code from bank area until it is properly supported Mike Pavone <pavone@retrodev.com> parents: 390 diff changeset	1856 exit(1);
d5f1840273b5 Bail out on attempt to run code from bank area until it is properly supported Mike Pavone <pavone@retrodev.com> parents: 390 diff changeset	1857 //encoded = context->mem_pointers[1] + (address & 0x7FFF);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1858 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1859 while (encoded != NULL)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1860 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1861 z80inst inst;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1862 dprintf("translating Z80 code at address %X\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1863 do {
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1864 if (opts->code_end-opts->cur_code < ZMAX_NATIVE_SIZE) {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1865 if (opts->code_end-opts->cur_code < 5) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1866 puts("out of code memory, not enough space for jmp to next chunk");
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1867 exit(1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1868 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1869 size_t size = 1024*1024;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1870 opts->cur_code = alloc_code(&size);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1871 opts->code_end = opts->cur_code + size;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1872 jmp(opts->cur_code, opts->cur_code);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1873 }
255 572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1874 if (address > 0x4000 && address < 0x8000) {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1875 opts->cur_code = xor_rr(opts->cur_code, RDI, RDI, SZ_D);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1876 opts->cur_code = call(opts->cur_code, (uint8_t *)exit);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1877 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1878 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1879 uint8_t * existing = z80_get_native_address(context, address);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1880 if (existing) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1881 opts->cur_code = jmp(opts->cur_code, existing);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1882 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1883 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1884 next = z80_decode(encoded, &inst);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1885 #ifdef DO_DEBUG_PRINT
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	1886 z80_disasm(&inst, disbuf, address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1887 if (inst.op == Z80_NOP) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1888 printf("%X\t%s(%d)\n", address, disbuf, inst.immed);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1889 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1890 printf("%X\t%s\n", address, disbuf);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1891 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1892 #endif
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	1893 uint8_t *after = translate_z80inst(&inst, opts->cur_code, context, address);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1894 z80_map_native_address(context, address, opts->cur_code, next-encoded, after - opts->cur_code);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	1895 opts->cur_code = after;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1896 address += next-encoded;
255 572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1897 if (address > 0xFFFF) {
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1898 address &= 0xFFFF;
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1899
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1900 } else {
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1901 encoded = next;
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1902 }
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1903 } while (!z80_is_terminal(&inst));
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1904 process_deferred(&opts->deferred, context, (native_addr_func)z80_get_native_address);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1905 if (opts->deferred) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1906 address = opts->deferred->address;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1907 dprintf("defferred address: %X\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1908 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1909 encoded = context->mem_pointers[0] + (address & 0x1FFF);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1910 } else if (address > 0x8000 && context->mem_pointers[1]) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1911 encoded = context->mem_pointers[1] + (address & 0x7FFF);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1912 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1913 printf("attempt to translate non-memory address: %X\n", address);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1914 exit(1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1915 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1916 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1917 encoded = NULL;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1918 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1919 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1920 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1921
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1922 void init_x86_z80_opts(x86_z80_options * options)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1923 {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1924 options->flags = 0;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1925 options->regs[Z80_B] = BH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1926 options->regs[Z80_C] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1927 options->regs[Z80_D] = CH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1928 options->regs[Z80_E] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1929 options->regs[Z80_H] = AH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1930 options->regs[Z80_L] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1931 options->regs[Z80_IXH] = DH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1932 options->regs[Z80_IXL] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1933 options->regs[Z80_IYH] = -1;
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1934 options->regs[Z80_IYL] = R8;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1935 options->regs[Z80_I] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1936 options->regs[Z80_R] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1937 options->regs[Z80_A] = R10;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1938 options->regs[Z80_BC] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1939 options->regs[Z80_DE] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1940 options->regs[Z80_HL] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1941 options->regs[Z80_SP] = R9;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1942 options->regs[Z80_AF] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1943 options->regs[Z80_IX] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1944 options->regs[Z80_IY] = R8;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1945 size_t size = 1024 * 1024;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1946 options->cur_code = alloc_code(&size);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1947 options->code_end = options->cur_code + size;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1948 options->ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1949 memset(options->ram_inst_sizes, 0, sizeof(uint8_t) * 0x2000);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1950 options->deferred = NULL;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1951 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1952
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1953 void init_z80_context(z80_context * context, x86_z80_options * options)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1954 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1955 memset(context, 0, sizeof(*context));
360 c42fae88d346 Fix sizeof expression passed to malloc in z80_init to avoid a minor memory error Mike Pavone <pavone@retrodev.com> parents: 335 diff changeset	1956 context->static_code_map = malloc(sizeof(*context->static_code_map));
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1957 context->static_code_map->base = NULL;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1958 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1959 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1960 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9));
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1961 memset(context->banked_code_map, 0, sizeof(native_map_slot) * (1 << 9));
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1962 context->options = options;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1963 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1964
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1965 void z80_reset(z80_context * context)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1966 {
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1967 context->im = 0;
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1968 context->iff1 = context->iff2 = 0;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1969 context->native_pc = z80_get_native_address_trans(context, 0);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1970 context->extra_pc = NULL;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1971 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1972
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1973 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler)
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1974 {
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1975 static uint8_t * bp_stub = NULL;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1976 uint8_t * native = z80_get_native_address_trans(context, address);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1977 uint8_t * start_native = native;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1978 native = mov_ir(native, address, SCRATCH1, SZ_W);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1979 if (!bp_stub) {
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1980 x86_z80_options * opts = context->options;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1981 uint8_t * dst = opts->cur_code;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1982 uint8_t * dst_end = opts->code_end;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1983 if (dst_end - dst < 128) {
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1984 size_t size = 1024*1024;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1985 dst = alloc_code(&size);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1986 opts->code_end = dst_end = dst + size;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1987 }
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1988 bp_stub = dst;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1989 native = call(native, bp_stub);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1990
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1991 //Calculate length of prologue
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1992 dst = z80_check_cycles_int(dst, address);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1993 int check_int_size = dst-bp_stub;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1994 dst = bp_stub;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1995
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1996 //Save context and call breakpoint handler
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1997 dst = call(dst, (uint8_t *)z80_save_context);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1998 dst = push_r(dst, SCRATCH1);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	1999 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2000 dst = mov_rr(dst, SCRATCH1, RSI, SZ_W);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2001 dst = call(dst, bp_handler);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2002 dst = mov_rr(dst, RAX, CONTEXT, SZ_Q);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2003 //Restore context
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2004 dst = call(dst, (uint8_t *)z80_load_context);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2005 dst = pop_r(dst, SCRATCH1);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2006 //do prologue stuff
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2007 dst = cmp_rr(dst, ZCYCLES, ZLIMIT, SZ_D);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2008 uint8_t * jmp_off = dst+1;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2009 dst = jcc(dst, CC_NC, dst + 7);
372 5dcf7551bb36 Bunch of Z80 debugger improvements Mike Pavone <pavone@retrodev.com> parents: 367 diff changeset	2010 dst = pop_r(dst, SCRATCH1);
5dcf7551bb36 Bunch of Z80 debugger improvements Mike Pavone <pavone@retrodev.com> parents: 367 diff changeset	2011 dst = add_ir(dst, check_int_size - (native-start_native), SCRATCH1, SZ_Q);
5dcf7551bb36 Bunch of Z80 debugger improvements Mike Pavone <pavone@retrodev.com> parents: 367 diff changeset	2012 dst = push_r(dst, SCRATCH1);
5dcf7551bb36 Bunch of Z80 debugger improvements Mike Pavone <pavone@retrodev.com> parents: 367 diff changeset	2013 dst = jmp(dst, (uint8_t *)z80_handle_cycle_limit_int);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2014 *jmp_off = dst - (jmp_off+1);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2015 //jump back to body of translated instruction
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2016 dst = pop_r(dst, SCRATCH1);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2017 dst = add_ir(dst, check_int_size - (native-start_native), SCRATCH1, SZ_Q);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2018 dst = jmp_r(dst, SCRATCH1);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2019 opts->cur_code = dst;
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2020 } else {
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2021 native = call(native, bp_stub);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2022 }
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2023 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2024
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2025 void zremove_breakpoint(z80_context * context, uint16_t address)
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2026 {
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2027 uint8_t * native = z80_get_native_address(context, address);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2028 z80_check_cycles_int(native, address);
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2029 }
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2030
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2031

Mercurial > repos > blastem

annotate z80_to_x86.c @ 467:140af5509ce7