Mercurial > repos > blastem

annotate 68kinst.c @ 2214:7591c67b8d1e

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Support for loading symbols in debugger for use during name resolution and disassembly
author Michael Pavone <pavone@retrodev.com>
date Mon, 29 Aug 2022 23:01:46 -0700
parents 53411df7fc71
children d8b0244101c4
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
467
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents: 412
diff changeset
1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents: 412
diff changeset
2 Copyright 2013 Michael Pavone
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
3 This file is part of BlastEm.
467
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents: 412
diff changeset
4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING
Mike Pavone <pavone@retrodev.com>
parents: 412
diff changeset
5 */
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
6 #include "68kinst.h"
2213
53411df7fc71 More 68K disassembler refactoring and fix Windows build failure
Michael Pavone <pavone@retrodev.com>
parents: 2133
diff changeset
7 #include "disasm.h"
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
8 #include <string.h>
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
9 #include <stdio.h>
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
10
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
11 uint32_t sign_extend16(uint32_t val)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
12 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
13 return (val & 0x8000) ? val | 0xFFFF0000 : val;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
14 }
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
15
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
16 uint32_t sign_extend8(uint32_t val)
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
17 {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
18 return (val & 0x80) ? val | 0xFFFFFF00 : val;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
19 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
20
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
21 #define INVALID_ADDRESS 0xFFFFFFFF
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
22
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
23 uint32_t m68k_decode_op_ex(uint16_t opcode, uint32_t address, m68k_fetch_fun fetch, void *data, uint8_t mode, uint8_t reg, uint8_t size, m68k_op_info *dst)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
24 {
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
25 uint16_t ext, tmp;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
26 dst->addr_mode = mode;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
27 switch(mode)
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
28 {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
29 case MODE_REG:
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
30 case MODE_AREG:
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
31 case MODE_AREG_INDIRECT:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
32 case MODE_AREG_POSTINC:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
33 case MODE_AREG_PREDEC:
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
34 dst->params.regs.pri = reg;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
35 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
36 case MODE_AREG_DISPLACE:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
37 ext = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
38 address += 2;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
39 dst->params.regs.pri = reg;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
40 dst->params.regs.displacement = sign_extend16(ext);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
41 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
42 case MODE_AREG_INDEX_MEM:
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
43 dst->params.regs.pri = reg;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
44 ext = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
45 address += 2;
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
46 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
47 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
48 dst->params.regs.scale = ext >> 9 & 3;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
49 if (ext & 0x100)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
50 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
51 dst->params.regs.disp_sizes = ext >> 4 & 3;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
52 switch (dst->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
53 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
54 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
55 //reserved
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
56 return INVALID_ADDRESS;
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
57 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
58 dst->params.regs.displacement = 0;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
59 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
60 case 2:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
61 dst->params.regs.displacement = sign_extend16(fetch(address, data));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
62 address += 2;
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
63 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
64 case 3:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
65 tmp = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
66 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
67 dst->params.regs.displacement = tmp << 16 | fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
68 address += 2;
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
69 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
70 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
71 if (ext & 0x3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
72 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
73 //memory indirect
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
74 switch (ext & 0xC4)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
75 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
76 case 0x00:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
77 dst->addr_mode = MODE_AREG_PREINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
78 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
79 case 0x04:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
80 dst->addr_mode = MODE_AREG_POSTINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
81 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
82 case 0x40:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
83 dst->addr_mode = MODE_AREG_MEM_INDIRECT;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
84 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
85 case 0x80:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
86 dst->addr_mode = MODE_PREINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
87 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
88 case 0x84:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
89 dst->addr_mode = MODE_POSTINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
90 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
91 case 0xC0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
92 dst->addr_mode = MODE_MEM_INDIRECT;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
93 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
94 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
95 dst->params.regs.disp_sizes |= ext << 4 & 0x30;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
96 switch (ext & 0x3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
97 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
98 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
99 //reserved
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
100 return INVALID_ADDRESS;
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
101 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
102 dst->params.regs.outer_disp = 0;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
103 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
104 case 2:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
105 dst->params.regs.outer_disp = sign_extend16(fetch(address, data));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
106 address += 2;
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
107 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
108 case 3:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
109 tmp = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
110 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
111 dst->params.regs.outer_disp = tmp << 16 | fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
112 address += 2;
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
113 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
114 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
115 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
116 switch (ext >> 6 & 3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
117 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
118 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
119 dst->addr_mode = MODE_AREG_INDEX_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
120 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
121 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
122 dst->addr_mode = MODE_AREG_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
123 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
124 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
125 dst->addr_mode = MODE_INDEX_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
126 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
127 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
128 dst->addr_mode = MODE_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
129 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
130 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
131 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
132 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
133 #endif
79
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 69
diff changeset
134 dst->addr_mode = MODE_AREG_INDEX_DISP8;
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 69
diff changeset
135 dst->params.regs.displacement = sign_extend8(ext&0xFF);
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
136 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
137 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
138 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
139 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
140 case MODE_PC_INDIRECT_ABS_IMMED:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
141 switch(reg)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
142 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
143 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
144 dst->addr_mode = MODE_ABSOLUTE_SHORT;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
145 ext = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
146 address += 2;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
147 dst->params.immed = sign_extend16(ext);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
148 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
149 case 1:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
150 dst->addr_mode = MODE_ABSOLUTE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
151 ext = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
152 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
153 dst->params.immed = ext << 16 | fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
154 address += 2;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
155 break;
79
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 69
diff changeset
156 case 3:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
157 ext = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
158 address += 2;
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
159 dst->params.regs.sec = ext >> 11;//includes areg/dreg bit, reg num and word/long bit
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
160 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
161 dst->params.regs.scale = ext >> 9 & 3;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
162 if (ext & 0x100)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
163 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
164 dst->params.regs.disp_sizes = ext >> 4 & 3;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
165 switch (dst->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
166 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
167 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
168 //reserved
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
169 return INVALID_ADDRESS;
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
170 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
171 dst->params.regs.displacement = 0;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
172 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
173 case 2:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
174 dst->params.regs.displacement = sign_extend16(fetch(address, data));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
175 address += 2;
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
176 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
177 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
178 tmp = *(cur++);
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
179 dst->params.regs.displacement = tmp << 16 | fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
180 address += 2;
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
181 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
182 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
183 if (ext & 0x3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
184 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
185 //memory indirect
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
186 switch (ext & 0xC4)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
187 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
188 case 0x00:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
189 dst->addr_mode = MODE_PC_PREINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
190 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
191 case 0x04:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
192 dst->addr_mode = MODE_PC_POSTINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
193 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
194 case 0x40:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
195 dst->addr_mode = MODE_PC_MEM_INDIRECT;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
196 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
197 case 0x80:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
198 dst->addr_mode = MODE_ZPC_PREINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
199 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
200 case 0x84:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
201 dst->addr_mode = MODE_ZPC_POSTINDEX;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
202 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
203 case 0xC0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
204 dst->addr_mode = MODE_ZPC_MEM_INDIRECT;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
205 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
206 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
207 dst->params.regs.disp_sizes |= ext << 4 & 0x30;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
208 switch (ext & 0x3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
209 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
210 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
211 //reserved
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
212 return INVALID_ADDRESS;
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
213 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
214 dst->params.regs.outer_disp = 0;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
215 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
216 case 2:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
217 dst->params.regs.outer_disp = sign_extend16(fetch(address, data));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
218 address += 2;
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
219 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
220 case 3:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
221 tmp = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
222 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
223 dst->params.regs.outer_disp = tmp << 16 | fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
224 address += 2;
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
225 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
226 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
227 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
228 switch (ext >> 6 & 3)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
229 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
230 case 0:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
231 dst->addr_mode = MODE_PC_INDEX_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
232 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
233 case 1:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
234 dst->addr_mode = MODE_PC_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
235 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
236 case 2:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
237 dst->addr_mode = MODE_ZPC_INDEX_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
238 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
239 case 3:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
240 dst->addr_mode = MODE_ZPC_BASE_DISP;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
241 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
242 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
243 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
244 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
245 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
246 dst->addr_mode = MODE_PC_INDEX_DISP8;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
247 dst->params.regs.displacement = sign_extend8(ext&0xFF);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
248 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
249 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
250 #endif
95
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding
Mike Pavone <pavone@retrodev.com>
parents: 94
diff changeset
251 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
252 case 2:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
253 dst->addr_mode = MODE_PC_DISPLACE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
254 ext = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
255 address += 2;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
256 dst->params.regs.displacement = sign_extend16(ext);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
257 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
258 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
259 dst->addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
260 ext = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
261 address += 2;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
262 switch (size)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
263 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
264 case OPSIZE_BYTE:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
265 dst->params.immed = ext & 0xFF;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
266 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
267 case OPSIZE_WORD:
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
268 dst->params.immed = ext;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
269 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
270 case OPSIZE_LONG:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
271 dst->params.immed = ext << 16 | fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
272 address += 2;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
273 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
274 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
275 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
276 default:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
277 return INVALID_ADDRESS;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
278 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
279 break;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
280 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
281 return address;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
282 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
283
823
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
284 uint8_t m68k_valid_immed_dst(m68k_op_info *dst)
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
285 {
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
286 if (dst->addr_mode == MODE_AREG || dst->addr_mode == MODE_IMMEDIATE) {
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
287 return 0;
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
288 }
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
289 return 1;
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
290 }
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
291
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
292 uint8_t m68k_valid_immed_limited_dst(m68k_op_info *dst)
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
293 {
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
294 if (dst->addr_mode == MODE_AREG || dst->addr_mode > MODE_ABSOLUTE) {
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
295 return 0;
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
296 }
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
297 return 1;
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
298 }
b1b5a7e7d955 Detect invalid destination modes for immediate variant opcodes. This fixes a crash bug in Bill's Tomato Game on Windows
Michael Pavone <pavone@retrodev.com>
parents: 652
diff changeset
299
1462
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
300 uint8_t m68k_valid_full_arith_dst(m68k_op_info *dst)
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
301 {
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
302 if (dst->addr_mode < MODE_AREG_INDIRECT || dst->addr_mode > MODE_ABSOLUTE) {
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
303 return 0;
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
304 }
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
305 return 1;
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
306 }
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
307
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
308 uint8_t m68k_valid_movem_dst(m68k_op_info *dst)
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
309 {
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
310 if (dst->addr_mode == MODE_REG || dst->addr_mode == MODE_AREG_POSTINC) {
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
311 return 0;
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
312 }
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
313 return m68k_valid_immed_limited_dst(dst);
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
314 }
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
315
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
316 uint32_t m68k_decode_op(uint16_t opcode, uint32_t address, m68k_fetch_fun fetch, void *data, uint8_t size, m68k_op_info *dst)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
317 {
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
318 uint8_t mode = (opcode >> 3) & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
319 uint8_t reg = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
320 return m68k_decode_op_ex(opcode, address, fetch, data, mode, reg, size, dst);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
321 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
322
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
323 void m68k_decode_cond(uint16_t op, m68kinst * decoded)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
324 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
325 decoded->extra.cond = (op >> 0x8) & 0xF;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
326 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
327
18
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes
Mike Pavone <pavone@retrodev.com>
parents: 15
diff changeset
328 uint8_t m68k_reg_quick_field(uint16_t op)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
329 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
330 return (op >> 9) & 0x7;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
331 }
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
332
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
333 uint32_t m68k_decode(m68k_fetch_fun fetch, void *data, m68kinst * decoded, uint32_t address)
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
334 {
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
335 uint32_t start_address = address;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
336 uint16_t opcode = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
337 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
338 uint8_t optype = opcode >> 12;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
339 uint8_t size;
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
340 uint8_t reg;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
341 uint8_t opmode;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
342 uint32_t immed;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
343 decoded->op = M68K_INVALID;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
344 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_UNUSED;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
345 decoded->variant = VAR_NORMAL;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
346 decoded->address = start_address;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
347 switch(optype)
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
348 {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
349 case BIT_MOVEP_IMMED:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
350 if ((opcode & 0x138) == 0x108) {
163
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
351 //MOVEP
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
352 decoded->op = M68K_MOVEP;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
353 decoded->extra.size = opcode & 0x40 ? OPSIZE_LONG : OPSIZE_WORD;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
354 if (opcode & 0x80) {
163
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
355 //memory dest
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
356 decoded->src.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
357 decoded->src.params.regs.pri = m68k_reg_quick_field(opcode);
163
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
358 decoded->dst.addr_mode = MODE_AREG_DISPLACE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
359 decoded->dst.params.regs.pri = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
360 decoded->dst.params.regs.displacement = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
361 address += 2;
163
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
362 } else {
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
363 //memory source
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
364 decoded->dst.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
365 decoded->dst.params.regs.pri = m68k_reg_quick_field(opcode);
163
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
366 decoded->src.addr_mode = MODE_AREG_DISPLACE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
367 decoded->src.params.regs.pri = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
368 decoded->src.params.regs.displacement = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
369 address += 2;
163
5559616e6bd8 Fix decoding of movep
Mike Pavone <pavone@retrodev.com>
parents: 154
diff changeset
370 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
371 } else if (opcode & 0x100) {
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
372 //BTST, BCHG, BCLR, BSET
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
373 switch ((opcode >> 6) & 0x3)
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
374 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
375 case 0:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
376 decoded->op = M68K_BTST;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
377 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
378 case 1:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
379 decoded->op = M68K_BCHG;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
380 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
381 case 2:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
382 decoded->op = M68K_BCLR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
383 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
384 case 3:
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
385 decoded->op = M68K_BSET;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
386 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
387 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
388 decoded->src.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
389 decoded->src.params.regs.pri = m68k_reg_quick_field(opcode);
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
390 decoded->extra.size = OPSIZE_BYTE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
391 address = m68k_decode_op(opcode, address, fetch, data, decoded->extra.size, &(decoded->dst));
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
392 if (
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
393 address == INVALID_ADDRESS || decoded->dst.addr_mode == MODE_AREG
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
394 || (decoded->op != M68K_BTST && !m68k_valid_immed_limited_dst(&decoded->dst))
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
395 ) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
396 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
397 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
398 }
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
399 if (decoded->dst.addr_mode == MODE_REG) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
400 decoded->extra.size = OPSIZE_LONG;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
401 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
402 } else if ((opcode & 0xF00) == 0x800) {
12
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
403 //BTST, BCHG, BCLR, BSET
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
404 switch ((opcode >> 6) & 0x3)
12
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
405 {
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
406 case 0:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
407 decoded->op = M68K_BTST;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
408 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
409 case 1:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
410 decoded->op = M68K_BCHG;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
411 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
412 case 2:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
413 decoded->op = M68K_BCLR;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
414 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
415 case 3:
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
416 decoded->op = M68K_BSET;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
417 break;
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
418 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
419 opmode = (opcode >> 3) & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
420 reg = opcode & 0x7;
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
421 decoded->src.addr_mode = MODE_IMMEDIATE_WORD;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
422 decoded->src.params.immed = fetch(address, data) & 0xFF;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
423 address += 2;
12
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
424 decoded->extra.size = OPSIZE_BYTE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
425 address = m68k_decode_op_ex(opcode, address, fetch, data, opmode, reg, decoded->extra.size, &(decoded->dst));
1463
63f309cfbef9 Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1462
diff changeset
426 if (
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
427 address == INVALID_ADDRESS || !m68k_valid_immed_dst(&decoded->dst)
1463
63f309cfbef9 Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1462
diff changeset
428 || (decoded->op != M68K_BTST && !m68k_valid_immed_limited_dst(&decoded->dst))
63f309cfbef9 Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1462
diff changeset
429 ) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
430 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
431 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
432 }
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
433 if (decoded->dst.addr_mode == MODE_REG) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
434 decoded->extra.size = OPSIZE_LONG;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
435 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
436 } else if ((opcode & 0xC0) == 0xC0) {
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
437 #ifdef M68020
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
438 //CMP2, CHK2, CAS, CAS2, RTM, CALLM
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
439 #endif
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
440 } else {
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
441 switch ((opcode >> 9) & 0x7)
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
442 {
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
443 case 0:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
444 if ((opcode & 0xFF) == 0x3C) {
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
445 decoded->op = M68K_ORI_CCR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
446 decoded->extra.size = OPSIZE_BYTE;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
447 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
448 decoded->src.params.immed = fetch(address, data) & 0xFF;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
449 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
450 } else if((opcode & 0xFF) == 0x7C) {
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
451 decoded->op = M68K_ORI_SR;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
452 decoded->extra.size = OPSIZE_WORD;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
453 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
454 decoded->src.params.immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
455 address += 2;
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
456 } else {
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
457 decoded->op = M68K_OR;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
458 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
459 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
460 decoded->extra.size = size = (opcode >> 6) & 3;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
461 reg = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
462 opmode = (opcode >> 3) & 0x7;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
463 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
464 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
465 case OPSIZE_BYTE:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
466 decoded->src.params.immed = fetch(address, data) & 0xFF;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
467 address += 2;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
468 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
469 case OPSIZE_WORD:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
470 decoded->src.params.immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
471 address += 2;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
472 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
473 case OPSIZE_LONG:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
474 immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
475 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
476 decoded->src.params.immed = immed << 16 | fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
477 address += 2;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
478 break;
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
479 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
480 address = m68k_decode_op_ex(opcode, address, fetch, data, opmode, reg, size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
481 if (address == INVALID_ADDRESS || !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
482 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
483 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
484 }
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
485 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
486 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
487 case 1:
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
488 //ANDI, ANDI to CCR, ANDI to SR
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
489 if ((opcode & 0xFF) == 0x3C) {
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
490 decoded->op = M68K_ANDI_CCR;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
491 decoded->extra.size = OPSIZE_BYTE;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
492 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
493 decoded->src.params.immed = fetch(address, data) & 0xFF;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
494 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
495 } else if((opcode & 0xFF) == 0x7C) {
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
496 decoded->op = M68K_ANDI_SR;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
497 decoded->extra.size = OPSIZE_WORD;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
498 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
499 decoded->src.params.immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
500 address += 2;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
501 } else {
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
502 decoded->op = M68K_AND;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
503 decoded->variant = VAR_IMMEDIATE;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
504 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
505 decoded->extra.size = size = (opcode >> 6) & 3;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
506 reg = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
507 opmode = (opcode >> 3) & 0x7;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
508 switch (size)
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
509 {
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
510 case OPSIZE_BYTE:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
511 decoded->src.params.immed = fetch(address, data) & 0xFF;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
512 address += 2;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
513 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
514 case OPSIZE_WORD:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
515 decoded->src.params.immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
516 address += 2;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
517 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
518 case OPSIZE_LONG:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
519 immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
520 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
521 decoded->src.params.immed = immed << 16 | fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
522 address += 2;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
523 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
524 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
525 address = m68k_decode_op_ex(opcode, address, fetch, data, opmode, reg, size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
526 if (address == INVALID_ADDRESS || !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
527 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
528 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
529 }
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
530 }
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
531 break;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
532 case 2:
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
533 decoded->op = M68K_SUB;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
534 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
535 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
536 decoded->extra.size = size = (opcode >> 6) & 3;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
537 reg = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
538 opmode = (opcode >> 3) & 0x7;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
539 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
540 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
541 case OPSIZE_BYTE:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
542 decoded->src.params.immed = fetch(address, data) & 0xFF;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
543 address += 2;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
544 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
545 case OPSIZE_WORD:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
546 decoded->src.params.immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
547 address += 2;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
548 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
549 case OPSIZE_LONG:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
550 immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
551 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
552 decoded->src.params.immed = immed << 16 | fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
553 address += 2;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
554 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
555 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
556 address = m68k_decode_op_ex(opcode, address, fetch, data, opmode, reg, size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
557 if (address == INVALID_ADDRESS || !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
558 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
559 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
560 }
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
561 break;
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
562 case 3:
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
563 decoded->op = M68K_ADD;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
564 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
565 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
566 decoded->extra.size = size = (opcode >> 6) & 3;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
567 reg = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
568 opmode = (opcode >> 3) & 0x7;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
569 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
570 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
571 case OPSIZE_BYTE:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
572 decoded->src.params.immed = fetch(address, data) & 0xFF;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
573 address += 2;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
574 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
575 case OPSIZE_WORD:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
576 decoded->src.params.immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
577 address += 2;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
578 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
579 case OPSIZE_LONG:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
580 immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
581 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
582 decoded->src.params.immed = immed << 16 | fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
583 address += 2;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
584 break;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
585 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
586 address = m68k_decode_op_ex(opcode, address, fetch, data, opmode, reg, size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
587 if (address == INVALID_ADDRESS || !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
588 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
589 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
590 }
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
591 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
592 case 4:
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
593 //BTST, BCHG, BCLR, BSET
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
594 //Seems like this should be unnecessary since bit instructions are explicitly handled above
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
595 //Possible this is redundant or the case above is overly restrictive
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
596 //TODO: Investigate whether this can be removed
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
597 switch ((opcode >> 6) & 0x3)
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
598 {
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
599 case 0:
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
600 decoded->op = M68K_BTST;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
601 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
602 case 1:
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
603 decoded->op = M68K_BCHG;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
604 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
605 case 2:
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
606 decoded->op = M68K_BCLR;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
607 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
608 case 3:
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
609 decoded->op = M68K_BSET;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
610 break;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
611 }
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
612 decoded->src.addr_mode = MODE_IMMEDIATE_WORD;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
613 decoded->src.params.immed = fetch(address, data) & 0xFF;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
614 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
615 address = m68k_decode_op(opcode, address, fetch, data, OPSIZE_BYTE, &(decoded->dst));
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
616 if (
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
617 address == INVALID_ADDRESS || !m68k_valid_immed_dst(&decoded->dst)
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
618 || (decoded->op != M68K_BTST && !m68k_valid_immed_limited_dst(&decoded->dst))
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
619 ) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
620 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
621 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
622 }
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
623 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
624 case 5:
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
625 //EORI, EORI to CCR, EORI to SR
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
626 if ((opcode & 0xFF) == 0x3C) {
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
627 decoded->op = M68K_EORI_CCR;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
628 decoded->extra.size = OPSIZE_BYTE;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
629 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
630 decoded->src.params.immed = fetch(address, data) & 0xFF;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
631 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
632 } else if((opcode & 0xFF) == 0x7C) {
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
633 decoded->op = M68K_EORI_SR;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
634 decoded->extra.size = OPSIZE_WORD;
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
635 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
636 decoded->src.params.immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
637 address += 2;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
638 } else {
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
639 decoded->op = M68K_EOR;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
640 decoded->variant = VAR_IMMEDIATE;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
641 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
642 decoded->extra.size = size = (opcode >> 6) & 3;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
643 reg = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
644 opmode = (opcode >> 3) & 0x7;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
645 switch (size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
646 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
647 case OPSIZE_BYTE:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
648 decoded->src.params.immed = fetch(address, data) & 0xFF;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
649 address += 2;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
650 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
651 case OPSIZE_WORD:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
652 decoded->src.params.immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
653 address += 2;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
654 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
655 case OPSIZE_LONG:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
656 immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
657 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
658 decoded->src.params.immed = immed << 16 | fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
659 address += 2;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
660 break;
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
661 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
662 address = m68k_decode_op_ex(opcode, address, fetch, data, opmode, reg, size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
663 if (address == INVALID_ADDRESS || !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
664 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
665 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
666 }
5
85699517043f More bit and immediate instructions
Mike Pavone <pavone@retrodev.com>
parents: 4
diff changeset
667 }
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
668 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
669 case 6:
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
670 decoded->op = M68K_CMP;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
671 decoded->variant = VAR_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
672 decoded->extra.size = (opcode >> 6) & 0x3;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
673 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
674 reg = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
675 opmode = (opcode >> 3) & 0x7;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
676 switch (decoded->extra.size)
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
677 {
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
678 case OPSIZE_BYTE:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
679 decoded->src.params.immed = fetch(address, data) & 0xFF;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
680 address += 2;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
681 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
682 case OPSIZE_WORD:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
683 decoded->src.params.immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
684 address += 2;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
685 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
686 case OPSIZE_LONG:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
687 immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
688 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
689 decoded->src.params.immed = (immed << 16) | fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
690 address += 2;
8
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
691 break;
23b83d94c633 Finish bit/movep/immediate group except for 68020 instructions
Mike Pavone <pavone@retrodev.com>
parents: 5
diff changeset
692 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
693 address = m68k_decode_op_ex(opcode, address, fetch, data, opmode, reg, decoded->extra.size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
694 if (address == INVALID_ADDRESS || !m68k_valid_immed_limited_dst(&(decoded->dst))) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
695 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
696 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
697 }
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
698 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
699 case 7:
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
700 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
701 decoded->op = M68K_MOVES;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
702 decoded->extra.size = opcode >> 6 & 0x3;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
703 immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
704 address += 2;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
705 reg = immed >> 12 & 0x7;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
706 opmode = immed & 0x8000 ? MODE_AREG : MODE_REG;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
707 if (immed & 0x800) {
642
08d0e3e7d0d8 Fix interpretation of moves direction field
Michael Pavone <pavone@retrodev.com>
parents: 641
diff changeset
708 decoded->src.addr_mode = opmode;
08d0e3e7d0d8 Fix interpretation of moves direction field
Michael Pavone <pavone@retrodev.com>
parents: 641
diff changeset
709 decoded->src.params.regs.pri = reg;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
710 address = m68k_decode_op_ex(opcode, address, fetch, data, *start >> 3 & 0x7, *start & 0x7, decoded->extra.size, &(decoded->dst));
642
08d0e3e7d0d8 Fix interpretation of moves direction field
Michael Pavone <pavone@retrodev.com>
parents: 641
diff changeset
711 } else {
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
712 address = m68k_decode_op_ex(opcode, address, fetch, data, *start >> 3 & 0x7, *start & 0x7, decoded->extra.size, &(decoded->src));
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
713 decoded->dst.addr_mode = opmode;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
714 decoded->dst.params.regs.pri = reg;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
715 }
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
716 #endif
4
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
717 break;
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
718 }
6f6a2d7cc889 Add support for some bit instructions and a few others in the same "category"
Mike Pavone <pavone@retrodev.com>
parents: 3
diff changeset
719 }
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
720 break;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
721 case MOVE_BYTE:
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
722 case MOVE_LONG:
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
723 case MOVE_WORD:
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
724 decoded->op = M68K_MOVE;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
725 decoded->extra.size = optype == MOVE_BYTE ? OPSIZE_BYTE : (optype == MOVE_WORD ? OPSIZE_WORD : OPSIZE_LONG);
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
726 opmode = (opcode >> 6) & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
727 reg = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
728 address = m68k_decode_op(opcode, address, fetch, data, decoded->extra.size, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
729 if (address == INVALID_ADDRESS || (decoded->src.addr_mode == MODE_AREG && optype == MOVE_BYTE)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
730 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
731 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
732 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
733 address = m68k_decode_op_ex(opcode, address, fetch, data, opmode, reg, decoded->extra.size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
734 if (address == INVALID_ADDRESS || decoded->dst.addr_mode > MODE_ABSOLUTE || (decoded->dst.addr_mode == MODE_AREG && optype == MOVE_BYTE)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
735 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
736 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
737 }
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
738 break;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
739 case MISC:
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
740
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
741 if ((opcode & 0x1C0) == 0x1C0) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
742 decoded->op = M68K_LEA;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
743 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
744 decoded->dst.addr_mode = MODE_AREG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
745 decoded->dst.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
746 address = m68k_decode_op(opcode, address, fetch, data, decoded->extra.size, &(decoded->src));
1277
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
747 if (
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
748 address == INVALID_ADDRESS || decoded->src.addr_mode == MODE_REG || decoded->src.addr_mode == MODE_AREG
1277
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
749 || decoded->src.addr_mode == MODE_AREG_POSTINC || decoded->src.addr_mode == MODE_AREG_PREDEC
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
750 || decoded->src.addr_mode == MODE_IMMEDIATE
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
751 ) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
752 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
753 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
754 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
755 } else {
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
756 if (opcode & 0x100) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
757 decoded->op = M68K_CHK;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
758 if ((opcode & 0x180) == 0x180) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
759 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
760 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
761 //only on M68020+
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
762 #ifdef M68020
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
763 decoded->extra.size = OPSIZE_LONG;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
764 #else
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
765 decoded->op = M68K_INVALID;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
766 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
767 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
768 }
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
769 decoded->dst.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
770 decoded->dst.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
771 address = m68k_decode_op(opcode, address, fetch, data, decoded->extra.size, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
772 if (address == INVALID_ADDRESS || decoded->src.addr_mode == MODE_AREG) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
773 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
774 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
775 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
776 } else {
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
777 opmode = (opcode >> 3) & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
778 if ((opcode & 0xB80) == 0x880 && opmode != MODE_REG && opmode != MODE_AREG) {
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
779 //TODO: Check for invalid modes that are dependent on direction
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
780 decoded->op = M68K_MOVEM;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
781 decoded->extra.size = opcode & 0x40 ? OPSIZE_LONG : OPSIZE_WORD;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
782 reg = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
783 if(opcode & 0x400) {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
784 decoded->dst.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
785 decoded->dst.params.immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
786 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
787 address = m68k_decode_op_ex(opcode, address, fetch, data, opmode, reg, decoded->extra.size, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
788 if (address == INVALID_ADDRESS || decoded->src.addr_mode == MODE_AREG_PREDEC || decoded->src.addr_mode == MODE_IMMEDIATE) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
789 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
790 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
791 }
412
00d5a2b532f4 Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
792 if (decoded->src.addr_mode == MODE_PC_DISPLACE || decoded->src.addr_mode == MODE_PC_INDEX_DISP8) {
00d5a2b532f4 Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
793 //adjust displacement to account for extra instruction word
00d5a2b532f4 Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
794 decoded->src.params.regs.displacement += 2;
00d5a2b532f4 Fix movem with pc displacement or pc indexed source
Mike Pavone <pavone@retrodev.com>
parents: 325
diff changeset
795 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
796 } else {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
797 decoded->src.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
798 decoded->src.params.immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
799 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
800 address = m68k_decode_op_ex(opcode, address, fetch, data, opmode, reg, decoded->extra.size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
801 if (address == INVALID_ADDRESS || !m68k_valid_movem_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
802 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
803 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
804 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
805 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
806 } else {
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
807 optype = (opcode >> 9) & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
808 size = (opcode >> 6) & 0x3;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
809 switch(optype)
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
810 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
811 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
812 //Move from SR or NEGX
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
813 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
814 decoded->op = M68K_MOVE_FROM_SR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
815 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
816 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
817 decoded->op = M68K_NEGX;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
818 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
819 decoded->extra.size = size;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
820 address = m68k_decode_op(opcode, address, fetch, data, size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
821 if (address == INVALID_ADDRESS || !m68k_valid_immed_limited_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
822 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
823 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
824 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
825 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
826 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
827 //MOVE from CCR or CLR
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
828 if (size == OPSIZE_INVALID) {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
829 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
830 decoded->op = M68K_MOVE_FROM_CCR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
831 size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
832 #else
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
833 break;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
834 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
835 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
836 decoded->op = M68K_CLR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
837 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
838 decoded->extra.size = size;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
839 address = m68k_decode_op(opcode, address, fetch, data, size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
840 if (address == INVALID_ADDRESS || !m68k_valid_immed_limited_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
841 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
842 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
843 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
844 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
845 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
846 //MOVE to CCR or NEG
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
847 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
848 decoded->op = M68K_MOVE_CCR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
849 size = OPSIZE_WORD;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
850 address = m68k_decode_op(opcode, address, fetch, data, size, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
851 if (address == INVALID_ADDRESS || decoded->src.addr_mode == MODE_AREG) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
852 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
853 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
854 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
855 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
856 decoded->op = M68K_NEG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
857 address = m68k_decode_op(opcode, address, fetch, data, size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
858 if (address == INVALID_ADDRESS || !m68k_valid_immed_limited_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
859 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
860 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
861 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
862 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
863 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
864 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
865 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
866 //MOVE to SR or NOT
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
867 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
868 decoded->op = M68K_MOVE_SR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
869 size = OPSIZE_WORD;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
870 address = m68k_decode_op(opcode, address, fetch, data, size, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
871 if (address == INVALID_ADDRESS || decoded->src.addr_mode == MODE_AREG) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
872 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
873 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
874 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
875 } else {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
876 decoded->op = M68K_NOT;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
877 address = m68k_decode_op(opcode, address, fetch, data, size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
878 if (address == INVALID_ADDRESS || !m68k_valid_immed_limited_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
879 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
880 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
881 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
882 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
883 decoded->extra.size = size;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
884 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
885 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
886 //EXT, EXTB, LINK.l, NBCD, SWAP, BKPT, PEA
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
887 switch((opcode >> 3) & 0x3F)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
888 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
889 case 1:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
890 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
891 decoded->op = M68K_LINK;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
892 decoded->extra.size = OPSIZE_LONG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
893 reg = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
894 immed = fetch(address, data) << 16;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
895 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
896 immed |= fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
897 address += 2;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
898 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
899 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
900 case 8:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
901 decoded->op = M68K_SWAP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
902 decoded->src.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
903 decoded->src.params.regs.pri = opcode & 0x7;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
904 decoded->extra.size = OPSIZE_WORD;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
905 break;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
906 case 9:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
907 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
908 decoded->op = M68K_BKPT;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
909 decoded->src.addr_mode = MODE_IMMEDIATE;
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
910 decoded->extra.size = OPSIZE_UNSIZED;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
911 decoded->src.params.immed = opcode & 0x7;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
912 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
913 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
914 case 0x10:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
915 decoded->op = M68K_EXT;
93
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 91
diff changeset
916 decoded->dst.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
917 decoded->dst.params.regs.pri = opcode & 0x7;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
918 decoded->extra.size = OPSIZE_WORD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
919 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
920 case 0x18:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
921 decoded->op = M68K_EXT;
93
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK
Mike Pavone <pavone@retrodev.com>
parents: 91
diff changeset
922 decoded->dst.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
923 decoded->dst.params.regs.pri = opcode & 0x7;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
924 decoded->extra.size = OPSIZE_LONG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
925 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
926 case 0x38:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
927 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
928 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
929 break;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
930 default:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
931 if (!(opcode & 0x1C0)) {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
932 decoded->op = M68K_NBCD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
933 decoded->extra.size = OPSIZE_BYTE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
934 address = m68k_decode_op(opcode, address, fetch, data, OPSIZE_BYTE, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
935 if (address == INVALID_ADDRESS || !m68k_valid_immed_limited_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
936 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
937 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
938 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
939 } else if((opcode & 0x1C0) == 0x40) {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
940 decoded->op = M68K_PEA;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
941 decoded->extra.size = OPSIZE_LONG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
942 address = m68k_decode_op(opcode, address, fetch, data, OPSIZE_LONG, &(decoded->src));
1277
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
943 if (
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
944 address == INVALID_ADDRESS || decoded->src.addr_mode == MODE_REG || decoded->src.addr_mode == MODE_AREG
1277
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
945 || decoded->src.addr_mode == MODE_AREG_POSTINC || decoded->src.addr_mode == MODE_AREG_PREDEC
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
946 || decoded->src.addr_mode == MODE_IMMEDIATE
78416556ae02 Properly treat invalid addressing modes for PEA/LEA as invalid instructinos
Michael Pavone <pavone@retrodev.com>
parents: 1253
diff changeset
947 ) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
948 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
949 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
950 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
951 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
952 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
953 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
954 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
955 //BGND, ILLEGAL, TAS, TST
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
956 optype = opcode & 0xFF;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
957 if (optype == 0xFA) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
958 //BGND - CPU32 only
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
959 } else if (optype == 0xFC) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
960 decoded->op = M68K_ILLEGAL;
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
961 decoded->extra.size = OPSIZE_UNSIZED;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
962 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
963 if (size == OPSIZE_INVALID) {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
964 decoded->op = M68K_TAS;
835
b4cf6573a3f8 Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents: 823
diff changeset
965 decoded->extra.size = OPSIZE_BYTE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
966 address = m68k_decode_op(opcode, address, fetch, data, decoded->extra.size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
967 if (address == INVALID_ADDRESS || !m68k_valid_immed_limited_dst(&decoded->dst)) {
835
b4cf6573a3f8 Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents: 823
diff changeset
968 decoded->op = M68K_INVALID;
b4cf6573a3f8 Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents: 823
diff changeset
969 break;
b4cf6573a3f8 Decode operand for TAS
Michael Pavone <pavone@retrodev.com>
parents: 823
diff changeset
970 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
971 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
972 decoded->op = M68K_TST;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
973 decoded->extra.size = size;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
974 address = m68k_decode_op(opcode, address, fetch, data, decoded->extra.size, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
975 if (address == INVALID_ADDRESS) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
976 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
977 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
978 }
1458
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
979 #ifndef M68020
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
980 if (!m68k_valid_immed_limited_dst(&decoded->src)) {
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
981 decoded->op = M68K_INVALID;
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
982 break;
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
983 }
b81428ef0396 Fix a bunch of 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1345
diff changeset
984 #endif
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
985 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
986 }
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
987 break;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
988 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
989 //MULU, MULS, DIVU, DIVUL, DIVS, DIVSL
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
990 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
991 //TODO: Implement these for 68020+ support
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
992 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
993 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
994 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
995 //TRAP, LINK.w, UNLNK, MOVE USP, RESET, NOP, STOP, RTE, RTD, RTS, TRAPV, RTR, MOVEC, JSR, JMP
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
996 if (opcode & 0x80) {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
997 //JSR, JMP
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
998 if (opcode & 0x40) {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
999 decoded->op = M68K_JMP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1000 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1001 decoded->op = M68K_JSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1002 }
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
1003 decoded->extra.size = OPSIZE_UNSIZED;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1004 address = m68k_decode_op(opcode, address, fetch, data, OPSIZE_UNSIZED, &(decoded->src));
1345
696a029d09e9 Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents: 1330
diff changeset
1005 if (
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1006 address == INVALID_ADDRESS
1345
696a029d09e9 Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents: 1330
diff changeset
1007 || (decoded->src.addr_mode < MODE_AREG_DISPLACE && decoded->src.addr_mode != MODE_AREG_INDIRECT)
696a029d09e9 Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents: 1330
diff changeset
1008 || decoded->src.addr_mode == MODE_IMMEDIATE
696a029d09e9 Decode JMP or JSR with an invalid addressing mode as an invalid instruction
Michael Pavone <pavone@retrodev.com>
parents: 1330
diff changeset
1009 ) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1010 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1011 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1012 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1013 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1014 //it would appear bit 6 needs to be set for it to be a valid instruction here
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1015 if (!(opcode & 0x40)) {
1462
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
1016 decoded->op = M68K_INVALID;
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
1017 break;
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
1018 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1019 switch((opcode >> 3) & 0x7)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1020 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1021 case 0:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1022 case 1:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1023 //TRAP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1024 decoded->op = M68K_TRAP;
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
1025 decoded->extra.size = OPSIZE_UNSIZED;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1026 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1027 decoded->src.params.immed = opcode & 0xF;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1028 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1029 case 2:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1030 //LINK.w
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1031 decoded->op = M68K_LINK;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1032 decoded->extra.size = OPSIZE_WORD;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1033 decoded->src.addr_mode = MODE_AREG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1034 decoded->src.params.regs.pri = opcode & 0x7;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1035 decoded->dst.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1036 decoded->dst.params.immed = sign_extend16(fetch(address, data));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1037 address += 2;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1038 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1039 case 3:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1040 //UNLK
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1041 decoded->op = M68K_UNLK;
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
1042 decoded->extra.size = OPSIZE_UNSIZED;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1043 decoded->dst.addr_mode = MODE_AREG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1044 decoded->dst.params.regs.pri = opcode & 0x7;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1045 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1046 case 4:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1047 case 5:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1048 //MOVE USP
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1049 decoded->op = M68K_MOVE_USP;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1050 if (opcode & 0x8) {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1051 decoded->dst.addr_mode = MODE_AREG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1052 decoded->dst.params.regs.pri = opcode & 0x7;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1053 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1054 decoded->src.addr_mode = MODE_AREG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1055 decoded->src.params.regs.pri = opcode & 0x7;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1056 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1057 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1058 case 6:
10
4553fc97b15e Added new OPSIZE for unsized instructions so they can be properly disassembled without making them special cases
Mike Pavone <pavone@retrodev.com>
parents: 9
diff changeset
1059 decoded->extra.size = OPSIZE_UNSIZED;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1060 switch(opcode & 0x7)
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1061 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1062 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1063 decoded->op = M68K_RESET;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1064 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1065 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1066 decoded->op = M68K_NOP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1067 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1068 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1069 decoded->op = M68K_STOP;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1070 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1071 decoded->src.params.immed =fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1072 address += 2;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1073 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1074 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1075 decoded->op = M68K_RTE;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1076 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1077 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1078 #ifdef M68010
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1079 decoded->op = M68K_RTD;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1080 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1081 decoded->src.params.immed =fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1082 address += 2;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1083 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1084 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1085 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1086 decoded->op = M68K_RTS;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1087 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1088 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1089 decoded->op = M68K_TRAPV;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1090 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1091 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1092 decoded->op = M68K_RTR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1093 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1094 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1095 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1096 case 7:
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1097 //MOVEC
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1098 #ifdef M68010
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1099 decoded->op = M68K_MOVEC;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1100 immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1101 address += 2;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1102 reg = immed >> 12 & 0x7;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1103 opmode = immed & 0x8000 ? MODE_AREG : MODE_REG;
641
66857bd2df0b Fix decoding of movec
Michael Pavone <pavone@retrodev.com>
parents: 638
diff changeset
1104 immed &= 0xFFF;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1105 if (immed & 0x800) {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1106 if (immed > MAX_HIGH_CR) {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1107 decoded->op = M68K_INVALID;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1108 break;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1109 } else {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1110 immed = immed - 0x800 + CR_USP;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1111 }
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1112 } else {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1113 if (immed > MAX_LOW_CR) {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1114 decoded->op = M68K_INVALID;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1115 break;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1116 }
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1117 }
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1118 if (*start & 1) {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1119 decoded->src.addr_mode = opmode;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1120 decoded->src.params.regs.pri = reg;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1121 decoded->dst.params.immed = immed;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1122 } else {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1123 decoded->dst.addr_mode = opmode;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1124 decoded->dst.params.regs.pri = reg;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1125 decoded->src.params.immed = immed;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1126 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1127 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1128 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1129 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1130 }
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1131 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1132 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1133 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1134 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1135 }
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1136 break;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1137 case QUICK_ARITH_LOOP:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1138 size = (opcode >> 6) & 3;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1139 if (size == 0x3) {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1140 //DBcc, TRAPcc or Scc
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1141 m68k_decode_cond(opcode, decoded);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1142 if (((opcode >> 3) & 0x7) == 1) {
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1143 decoded->op = M68K_DBCC;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1144 decoded->src.addr_mode = MODE_IMMEDIATE;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1145 decoded->dst.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1146 decoded->dst.params.regs.pri = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1147 decoded->src.params.immed = sign_extend16(fetch(address, data));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1148 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1149 } else if(((opcode >> 3) & 0x7) == 1 && (opcode & 0x7) > 1 && (opcode & 0x7) < 5) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1150 #ifdef M68020
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1151 decoded->op = M68K_TRAPCC;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1152 decoded->src.addr_mode = MODE_IMMEDIATE;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1153 //TODO: Figure out what to do with OPMODE and optional extention words
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1154 #endif
111
8b50d2c975b2 Fix decoding of Scc
Mike Pavone <pavone@retrodev.com>
parents: 101
diff changeset
1155 } else {
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1156 decoded->op = M68K_SCC;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1157 decoded->extra.cond = (opcode >> 8) & 0xF;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1158 address = m68k_decode_op(opcode, address, fetch, data, OPSIZE_BYTE, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1159 if (address == INVALID_ADDRESS || !m68k_valid_immed_limited_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1160 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1161 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1162 }
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1163 }
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1164 } else {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1165 //ADDQ, SUBQ
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1166 decoded->variant = VAR_QUICK;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1167 decoded->extra.size = size;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1168 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1169 immed = m68k_reg_quick_field(opcode);
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1170 if (!immed) {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1171 immed = 8;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1172 }
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
1173 decoded->src.params.immed = immed;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1174 if (opcode & 0x100) {
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1175 decoded->op = M68K_SUB;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1176 } else {
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1177 decoded->op = M68K_ADD;
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1178 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1179 address = m68k_decode_op(opcode, address, fetch, data, size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1180 if (address == INVALID_ADDRESS || decoded->dst.addr_mode > MODE_ABSOLUTE || (size == OPSIZE_BYTE && decoded->dst.addr_mode == MODE_AREG)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1181 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1182 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1183 }
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1184 }
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1185 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1186 case BRANCH:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1187 m68k_decode_cond(opcode, decoded);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1188 decoded->op = decoded->extra.cond == COND_FALSE ? M68K_BSR : M68K_BCC;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1189 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1190 immed = opcode & 0xFF;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1191 if (immed == 0) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1192 decoded->variant = VAR_WORD;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1193 immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1194 address += 2;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1195 immed = sign_extend16(immed);
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 140
diff changeset
1196 #ifdef M68020
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1197 } else if (immed == 0xFF) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1198 decoded->variant = VAR_LONG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1199 immed = fetch(address, data) << 16;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1200 address += 2;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1201 immed |= fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1202 address += 2;
154
4791c0204410 Small fix for bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 140
diff changeset
1203 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1204 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1205 decoded->variant = VAR_BYTE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1206 immed = sign_extend8(immed);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1207 }
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
1208 decoded->src.params.immed = immed;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1209 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1210 case MOVEQ:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1211 if (opcode & 0x100) {
208
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 197
diff changeset
1212 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1213 break;
208
3457dc6fd558 Tweaks to make blastem compatible with m68k-tester
Mike Pavone <pavone@retrodev.com>
parents: 197
diff changeset
1214 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1215 decoded->op = M68K_MOVE;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1216 decoded->variant = VAR_QUICK;
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
1217 decoded->extra.size = OPSIZE_LONG;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1218 decoded->src.addr_mode = MODE_IMMEDIATE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1219 decoded->src.params.immed = sign_extend8(opcode & 0xFF);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1220 decoded->dst.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1221 decoded->dst.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1222 immed = opcode & 0xFF;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1223 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1224 case OR_DIV_SBCD:
11
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1225 //for OR, if opmode bit 2 is 1, then src = Dn, dst = <ea>
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1226 opmode = (opcode >> 6) & 0x7;
11
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1227 size = opmode & 0x3;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1228 if (size == OPSIZE_INVALID || (opmode & 0x4 && !(opcode & 0x30))) {
11
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1229 switch(opmode)
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1230 {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1231 case 3:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1232 decoded->op = M68K_DIVU;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1233 decoded->extra.size = OPSIZE_WORD;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1234 decoded->dst.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1235 decoded->dst.params.regs.pri = (opcode >> 9) & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1236 address = m68k_decode_op(opcode, address, fetch, data, OPSIZE_WORD, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1237 if (address == INVALID_ADDRESS || decoded->src.addr_mode == MODE_AREG) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1238 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1239 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1240 }
11
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1241 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1242 case 4:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1243 decoded->op = M68K_SBCD;
613
09d5adf8d1ca Fix opsize for sbcd in 68K instruction decoder. This fixes the timer bug in Strider 2
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1244 decoded->extra.size = OPSIZE_BYTE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1245 decoded->dst.addr_mode = decoded->src.addr_mode = opcode & 0x8 ? MODE_AREG_PREDEC : MODE_REG;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1246 decoded->src.params.regs.pri = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1247 decoded->dst.params.regs.pri = (opcode >> 9) & 0x7;
11
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1248 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1249 case 5:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1250 #ifdef M68020
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1251 #endif
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1252 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1253 case 6:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1254 #ifdef M68020
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1255 #endif
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1256 break;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1257 case 7:
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1258 decoded->op = M68K_DIVS;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1259 decoded->extra.size = OPSIZE_WORD;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1260 decoded->dst.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1261 decoded->dst.params.regs.pri = (opcode >> 9) & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1262 address = m68k_decode_op(opcode, address, fetch, data, OPSIZE_WORD, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1263 if (address == INVALID_ADDRESS || decoded->src.addr_mode == MODE_AREG) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1264 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1265 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1266 }
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1267 break;
11
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1268 }
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1269 } else {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1270 decoded->op = M68K_OR;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1271 decoded->extra.size = size;
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1272 if (opmode & 0x4) {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1273 decoded->src.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1274 decoded->src.params.regs.pri = (opcode >> 9) & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1275 address = m68k_decode_op(opcode, address, fetch, data, size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1276 if (address == INVALID_ADDRESS || !m68k_valid_full_arith_dst(&(decoded->dst))) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1277 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1278 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1279 }
11
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1280 } else {
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1281 decoded->dst.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1282 decoded->dst.params.regs.pri = (opcode >> 9) & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1283 address = m68k_decode_op(opcode, address, fetch, data, size, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1284 if (address == INVALID_ADDRESS || decoded->src.addr_mode == MODE_AREG) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1285 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1286 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1287 }
11
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1288 }
d5e9bac9ebdf Implement OR_DIV_SBCD group in decoder
Mike Pavone <pavone@retrodev.com>
parents: 10
diff changeset
1289 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1290 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1291 case SUB_SUBX:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1292 size = (opcode >> 6) & 0x3;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1293 decoded->op = M68K_SUB;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1294 if (opcode & 0x100) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1295 //<ea> destination, SUBA.l or SUBX
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1296 if (opcode & 0x30 || size == OPSIZE_INVALID) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1297 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1298 //SUBA.l
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1299 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1300 decoded->dst.addr_mode = MODE_AREG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1301 decoded->dst.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1302 address = m68k_decode_op(opcode, address, fetch, data, OPSIZE_LONG, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1303 if (address == INVALID_ADDRESS) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1304 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1305 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1306 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1307 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1308 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1309 decoded->src.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1310 decoded->src.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1311 address = m68k_decode_op(opcode, address, fetch, data, size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1312 if (address == INVALID_ADDRESS || !m68k_valid_full_arith_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1313 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1314 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1315 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1316 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1317 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1318 //SUBX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1319 decoded->op = M68K_SUBX;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1320 decoded->extra.size = size;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1321 decoded->dst.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1322 decoded->src.params.regs.pri = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1323 if (opcode & 0x8) {
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1324 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_AREG_PREDEC;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1325 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1326 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_REG;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1327 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1328 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1329 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1330 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1331 //SUBA.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1332 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1333 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1334 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1335 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1336 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1337 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1338 decoded->dst.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1339 address = m68k_decode_op(opcode, address, fetch, data, decoded->extra.size, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1340 if (address == INVALID_ADDRESS || (decoded->src.addr_mode == MODE_AREG && decoded->extra.size == OPSIZE_BYTE)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1341 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1342 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1343 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1344 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1345 break;
992
261995d06897 Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
1346 case A_LINE:
261995d06897 Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
1347 decoded->op = M68K_A_LINE_TRAP;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1348 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1349 case CMP_XOR:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1350 size = (opcode >> 6) & 0x3;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1351 decoded->op = M68K_CMP;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1352 if (opcode & 0x100) {
120
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1353 //CMPM or CMPA.l or EOR
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1354 if (size == OPSIZE_INVALID) {
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1355 decoded->extra.size = OPSIZE_LONG;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1356 decoded->dst.addr_mode = MODE_AREG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1357 decoded->dst.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1358 address = m68k_decode_op(opcode, address, fetch, data, decoded->extra.size, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1359 if (address == INVALID_ADDRESS) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1360 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1361 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1362 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1363 } else {
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1364 reg = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1365 address = m68k_decode_op(opcode, address, fetch, data, size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1366 if (address == INVALID_ADDRESS) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1367 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1368 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1369 }
181
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
1370 decoded->extra.size = size;
3b4ef459aa8d Fix signed division with negative result, fix address reg destination with word-sized operand, fix cmpm decoding and code generation, fix unbalanced pop in bit instructions
Mike Pavone <pavone@retrodev.com>
parents: 176
diff changeset
1371 if (decoded->dst.addr_mode == MODE_AREG) {
120
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1372 //CMPM
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1373 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG_POSTINC;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1374 decoded->src.params.regs.pri = decoded->dst.params.regs.pri;
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1375 decoded->dst.params.regs.pri = reg;
1462
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
1376 } else if (!m68k_valid_immed_limited_dst(&decoded->dst)){
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
1377 decoded->op = M68K_INVALID;
d276ec2fff11 More instruction decoder fixes
Michael Pavone <pavone@retrodev.com>
parents: 1458
diff changeset
1378 break;
120
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1379 } else {
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1380 //EOR
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1381 decoded->op = M68K_EOR;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1382 decoded->src.addr_mode = MODE_REG;
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1383 decoded->src.params.regs.pri = reg;
120
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1384 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1385 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1386 } else {
120
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1387 //CMP or CMPA.w
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1388 if (size == OPSIZE_INVALID) {
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1389 decoded->extra.size = OPSIZE_WORD;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1390 decoded->dst.addr_mode = MODE_AREG;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1391 } else {
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1392 decoded->extra.size = size;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1393 decoded->dst.addr_mode = MODE_REG;
3648abc45aec Fix decoding of CMPA
Mike Pavone <pavone@retrodev.com>
parents: 116
diff changeset
1394 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1395 decoded->dst.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1396 address = m68k_decode_op(opcode, address, fetch, data, decoded->extra.size, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1397 if (address == INVALID_ADDRESS || (decoded->src.addr_mode == MODE_AREG && decoded->extra.size == OPSIZE_BYTE)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1398 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1399 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1400 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1401 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1402 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1403 case AND_MUL_ABCD_EXG:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1404 //page 575 for summary
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1405 //EXG opmodes:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1406 //01000 -data regs
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1407 //01001 -addr regs
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1408 //10001 -one of each
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1409 //AND opmodes:
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1410 //operand order bit + 2 size bits (00 - 10)
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1411 //no address register direct addressing
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1412 //data register direct not allowed when <ea> is the source (operand order bit of 1)
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1413 if (opcode & 0x100) {
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1414 if ((opcode & 0xC0) == 0xC0) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1415 decoded->op = M68K_MULS;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1416 decoded->extra.size = OPSIZE_WORD;
3
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents: 2
diff changeset
1417 decoded->dst.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1418 decoded->dst.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1419 address = m68k_decode_op(opcode, address, fetch, data, OPSIZE_WORD, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1420 if (address == INVALID_ADDRESS || decoded->src.addr_mode == MODE_AREG) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1421 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1422 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1423 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1424 } else if(!(opcode & 0xF0)) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1425 decoded->op = M68K_ABCD;
3
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents: 2
diff changeset
1426 decoded->extra.size = OPSIZE_BYTE;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1427 decoded->src.params.regs.pri = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1428 decoded->dst.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1429 decoded->dst.addr_mode = decoded->src.addr_mode = (opcode & 8) ? MODE_AREG_PREDEC : MODE_REG;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1430 } else if(!(opcode & 0x30)) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1431 decoded->op = M68K_EXG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1432 decoded->extra.size = OPSIZE_LONG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1433 decoded->src.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1434 decoded->dst.params.regs.pri = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1435 if (opcode & 0x8) {
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1436 if (opcode & 0x80) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1437 decoded->src.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1438 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1439 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1440 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1441 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1442 } else if (opcode & 0x40) {
1463
63f309cfbef9 Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1462
diff changeset
1443 decoded->src.addr_mode = decoded->dst.addr_mode = MODE_REG;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1444 } else {
1463
63f309cfbef9 Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1462
diff changeset
1445 decoded->op = M68K_INVALID;
63f309cfbef9 Fix what are hopefully th elast of the 68K instruction decoder bugs revealed by r57shell/realmonster's test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1462
diff changeset
1446 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1447 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1448 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1449 decoded->op = M68K_AND;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1450 decoded->extra.size = (opcode >> 6) & 0x3;
60
6ffea8607730 Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1451 decoded->src.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1452 decoded->src.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1453 address = m68k_decode_op(opcode, address, fetch, data, decoded->extra.size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1454 if (address == INVALID_ADDRESS || !m68k_valid_full_arith_dst(&(decoded->dst))) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1455 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1456 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1457 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1458 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1459 } else {
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1460 if ((opcode & 0xC0) == 0xC0) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1461 decoded->op = M68K_MULU;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1462 decoded->extra.size = OPSIZE_WORD;
3
a4ad0e3e3e0e Finish mulu.w, muls.w and abcd parameter decoding
Mike Pavone <pavone@retrodev.com>
parents: 2
diff changeset
1463 decoded->dst.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1464 decoded->dst.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1465 address = m68k_decode_op(opcode, address, fetch, data, OPSIZE_WORD, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1466 if (address == INVALID_ADDRESS || decoded->src.addr_mode == MODE_AREG) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1467 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1468 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1469 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1470 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1471 decoded->op = M68K_AND;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1472 decoded->extra.size = (opcode >> 6) & 0x3;
60
6ffea8607730 Fix operand order for AND instructions
Mike Pavone <pavone@retrodev.com>
parents: 54
diff changeset
1473 decoded->dst.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1474 decoded->dst.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1475 address = m68k_decode_op(opcode, address, fetch, data, decoded->extra.size, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1476 if (address == INVALID_ADDRESS || decoded->src.addr_mode == MODE_AREG) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1477 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1478 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1479 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1480 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1481 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1482 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1483 case ADD_ADDX:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1484 size = (opcode >> 6) & 0x3;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1485 decoded->op = M68K_ADD;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1486 if (opcode & 0x100) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1487 //<ea> destination, ADDA.l or ADDX
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1488 if (opcode & 0x30 || size == OPSIZE_INVALID) {
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1489 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1490 //ADDA.l
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1491 decoded->extra.size = OPSIZE_LONG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1492 decoded->dst.addr_mode = MODE_AREG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1493 decoded->dst.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1494 address = m68k_decode_op(opcode, address, fetch, data, OPSIZE_LONG, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1495 if (address == INVALID_ADDRESS) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1496 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1497 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1498 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1499 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1500 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1501 decoded->src.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1502 decoded->src.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1503 address = m68k_decode_op(opcode, address, fetch, data, size, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1504 if (address == INVALID_ADDRESS || !m68k_valid_full_arith_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1505 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1506 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1507 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1508 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1509 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1510 //ADDX
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1511 decoded->op = M68K_ADDX;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1512 decoded->extra.size = size;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1513 decoded->dst.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1514 decoded->src.params.regs.pri = opcode & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1515 if (opcode & 0x8) {
184
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1516 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_AREG_PREDEC;
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1517 } else {
ebcbdd1c4cc8 Fix a bunch of bugs in the CPU core, add a 68K debugger
Mike Pavone <pavone@retrodev.com>
parents: 183
diff changeset
1518 decoded->dst.addr_mode = decoded->src.addr_mode = MODE_REG;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1519 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1520 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1521 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1522 if (size == OPSIZE_INVALID) {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1523 //ADDA.w
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1524 decoded->extra.size = OPSIZE_WORD;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1525 decoded->dst.addr_mode = MODE_AREG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1526 } else {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1527 decoded->extra.size = size;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1528 decoded->dst.addr_mode = MODE_REG;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1529 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1530 decoded->dst.params.regs.pri = m68k_reg_quick_field(opcode);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1531 address = m68k_decode_op(opcode, address, fetch, data, decoded->extra.size, &(decoded->src));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1532 if (address == INVALID_ADDRESS || (decoded->src.addr_mode == MODE_AREG && decoded->extra.size == OPSIZE_BYTE)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1533 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1534 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1535 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1536 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1537 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1538 case SHIFT_ROTATE:
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1539 if ((opcode & 0x8C0) == 0xC0) {
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1540 switch((opcode >> 8) & 0x7)
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1541 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1542 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1543 decoded->op = M68K_ASR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1544 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1545 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1546 decoded->op = M68K_ASL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1547 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1548 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1549 decoded->op = M68K_LSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1550 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1551 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1552 decoded->op = M68K_LSL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1553 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1554 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1555 decoded->op = M68K_ROXR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1556 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1557 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1558 decoded->op = M68K_ROXL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1559 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1560 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1561 decoded->op = M68K_ROR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1562 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1563 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1564 decoded->op = M68K_ROL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1565 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1566 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1567 decoded->extra.size = OPSIZE_WORD;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1568 address = m68k_decode_op(opcode, address, fetch, data, OPSIZE_WORD, &(decoded->dst));
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1569 if (address == INVALID_ADDRESS || !m68k_valid_full_arith_dst(&decoded->dst)) {
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1570 decoded->op = M68K_INVALID;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1571 break;
176
e2918b5208eb Print a message when we try to run an invalid instruction, not when we try to translate it
Mike Pavone <pavone@retrodev.com>
parents: 163
diff changeset
1572 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1573 } else if((opcode & 0xC0) != 0xC0) {
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1574 switch(((opcode >> 2) & 0x6) | ((opcode >> 8) & 1))
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1575 {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1576 case 0:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1577 decoded->op = M68K_ASR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1578 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1579 case 1:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1580 decoded->op = M68K_ASL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1581 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1582 case 2:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1583 decoded->op = M68K_LSR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1584 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1585 case 3:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1586 decoded->op = M68K_LSL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1587 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1588 case 4:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1589 decoded->op = M68K_ROXR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1590 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1591 case 5:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1592 decoded->op = M68K_ROXL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1593 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1594 case 6:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1595 decoded->op = M68K_ROR;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1596 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1597 case 7:
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1598 decoded->op = M68K_ROL;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1599 break;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1600 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1601 decoded->extra.size = (opcode >> 6) & 0x3;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1602 immed = (opcode >> 9) & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1603 if (opcode & 0x20) {
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1604 decoded->src.addr_mode = MODE_REG;
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1605 decoded->src.params.regs.pri = immed;
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1606 } else {
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1607 decoded->src.addr_mode = MODE_IMMEDIATE;
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1608 if (!immed) {
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1609 immed = 8;
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1610 }
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1611 decoded->src.params.immed = immed;
1627
dc1eab3ec092 Fix cycle count for shift/rotate instructions with a static shift ammount
Michael Pavone <pavone@retrodev.com>
parents: 1463
diff changeset
1612 decoded->variant = VAR_QUICK;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1613 }
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1614 decoded->dst.addr_mode = MODE_REG;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1615 decoded->dst.params.regs.pri = opcode & 0x7;
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1616
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1617 } else {
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1618 #ifdef M68020
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1619 //TODO: Implement bitfield instructions for M68020+ support
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1620 switch (opcode >> 8 & 7)
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1621 {
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1622 case 0:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1623 decoded->op = M68K_BFTST; //<ea>
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1624 break;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1625 case 1:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1626 decoded->op = M68K_BFEXTU; //<ea>, Dn
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1627 break;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1628 case 2:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1629 decoded->op = M68K_BFCHG; //<ea>
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1630 break;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1631 case 3:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1632 decoded->op = M68K_BFEXTS; //<ea>, Dn
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1633 break;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1634 case 4:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1635 decoded->op = M68K_BFCLR; //<ea>
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1636 break;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1637 case 5:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1638 decoded->op = M68K_BFFFO; //<ea>, Dn
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1639 break;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1640 case 6:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1641 decoded->op = M68K_BFSET; //<ea>
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1642 break;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1643 case 7:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1644 decoded->op = M68K_BFINS; //Dn, <ea>
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1645 break;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1646 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1647 opmode = opcode >> 3 & 0x7;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1648 reg = opcode & 0x7;
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1649 m68k_op_info *ea, *other;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1650 if (decoded->op == M68K_BFEXTU || decoded->op == M68K_BFEXTS || decoded->op == M68K_BFFFO)
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1651 {
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1652 ea = &(decoded->src);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1653 other = &(decoded->dst);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1654 } else {
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1655 ea = &(decoded->dst);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1656 other = &(decoded->dst);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1657 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1658 if (opcode & 0x100)
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1659 {
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1660 immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1661 address += 2;
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1662 other->addr_mode = MODE_REG;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1663 other->params.regs.pri = immed >> 12 & 0x7;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1664 } else {
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1665 immed = fetch(address, data);
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1666 address += 2;
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1667 }
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1668 decoded->extra.size = OPSIZE_UNSIZED;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1669 address = m68k_decode_op_ex(opcode, address, fetch, data, opmode, reg, decoded->extra.size, ea);
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1670 ea->addr_mode |= M68K_FLAG_BITFIELD;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1671 ea->bitfield = immed & 0xFFF;
9
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1672 #endif
0a0cd3705c19 Implement (possibly broken) decoding of all M68000 instructions not in the OR_DIV_SBCD group
Mike Pavone <pavone@retrodev.com>
parents: 8
diff changeset
1673 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1674 break;
992
261995d06897 Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
1675 case F_LINE:
261995d06897 Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
1676 //TODO: Decode FPU instructions for members of the 68K family with an FPU
261995d06897 Implemented A line and F line traps.
Michael Pavone <pavone@retrodev.com>
parents: 981
diff changeset
1677 decoded->op = M68K_F_LINE_TRAP;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1678 break;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1679 }
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1680 if (decoded->op == M68K_INVALID) {
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1681 decoded->src.params.immed = opcode;
981
902c53d9c16f Half assed, prefetch based open bus value emulation. Gets BlastEm up to 119/122 in VDP FIFO Testing
Michael Pavone <pavone@retrodev.com>
parents: 835
diff changeset
1682 decoded->bytes = 2;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1683 return start_address + 2;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1684 }
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1685 decoded->bytes = address - start_address;
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
1686 return address;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1687 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1688
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1689 uint32_t m68k_branch_target(m68kinst * inst, uint32_t *dregs, uint32_t *aregs)
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1690 {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1691 if(inst->op == M68K_BCC || inst->op == M68K_BSR || inst->op == M68K_DBCC) {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1692 return inst->address + 2 + inst->src.params.immed;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1693 } else if(inst->op == M68K_JMP || inst->op == M68K_JSR) {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1694 uint32_t ret = 0;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1695 switch(inst->src.addr_mode)
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1696 {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1697 case MODE_AREG_INDIRECT:
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1698 ret = aregs[inst->src.params.regs.pri];
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1699 break;
1330
af26a1ce92f7 Handle address register displacement when calculating branch targets in debugger
Michael Pavone <pavone@retrodev.com>
parents: 1277
diff changeset
1700 case MODE_AREG_DISPLACE:
af26a1ce92f7 Handle address register displacement when calculating branch targets in debugger
Michael Pavone <pavone@retrodev.com>
parents: 1277
diff changeset
1701 ret = aregs[inst->src.params.regs.pri] + inst->src.params.regs.displacement;
af26a1ce92f7 Handle address register displacement when calculating branch targets in debugger
Michael Pavone <pavone@retrodev.com>
parents: 1277
diff changeset
1702 break;
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1703 case MODE_AREG_INDEX_DISP8: {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1704 uint8_t sec_reg = inst->src.params.regs.sec >> 1 & 0x7;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1705 ret = aregs[inst->src.params.regs.pri];
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1706 uint32_t * regfile = inst->src.params.regs.sec & 0x10 ? aregs : dregs;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1707 if (inst->src.params.regs.sec & 1) {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1708 //32-bit index register
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1709 ret += regfile[sec_reg];
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1710 } else {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1711 //16-bit index register
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1712 if (regfile[sec_reg] & 0x8000) {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1713 ret += (0xFFFF0000 | regfile[sec_reg]);
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1714 } else {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1715 ret += regfile[sec_reg];
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1716 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1717 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1718 ret += inst->src.params.regs.displacement;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1719 break;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1720 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1721 case MODE_PC_DISPLACE:
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1722 ret = inst->src.params.regs.displacement + inst->address + 2;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1723 break;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1724 case MODE_PC_INDEX_DISP8: {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1725 uint8_t sec_reg = inst->src.params.regs.sec >> 1 & 0x7;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1726 ret = inst->address + 2;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1727 uint32_t * regfile = inst->src.params.regs.sec & 0x10 ? aregs : dregs;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1728 if (inst->src.params.regs.sec & 1) {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1729 //32-bit index register
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1730 ret += regfile[sec_reg];
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1731 } else {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1732 //16-bit index register
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1733 if (regfile[sec_reg] & 0x8000) {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1734 ret += (0xFFFF0000 | regfile[sec_reg]);
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1735 } else {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1736 ret += regfile[sec_reg];
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1737 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1738 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1739 ret += inst->src.params.regs.displacement;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1740 break;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1741 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1742 case MODE_ABSOLUTE:
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1743 case MODE_ABSOLUTE_SHORT:
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1744 ret = inst->src.params.immed;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1745 break;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1746 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1747 return ret;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1748 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1749 return 0;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1750 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1751
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1752 uint8_t m68k_is_branch(m68kinst * inst)
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1753 {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1754 return (inst->op == M68K_BCC && inst->extra.cond != COND_FALSE)
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1755 || (inst->op == M68K_DBCC && inst->extra.cond != COND_TRUE)
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1756 || inst->op == M68K_BSR || inst->op == M68K_JMP || inst->op == M68K_JSR;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1757 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1758
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1759 uint8_t m68k_is_noncall_branch(m68kinst * inst)
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1760 {
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1761 return m68k_is_branch(inst) && inst->op != M68K_BSR && inst->op != M68K_JSR;
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1762 }
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1763
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
1764
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1765 char * mnemonics[] = {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1766 "abcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1767 "add",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1768 "addx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1769 "and",
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1770 "andi",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1771 "andi",//sr
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1772 "asl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1773 "asr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1774 "bcc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1775 "bchg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1776 "bclr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1777 "bset",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1778 "bsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1779 "btst",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1780 "chk",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1781 "clr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1782 "cmp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1783 "dbcc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1784 "divs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1785 "divu",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1786 "eor",
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1787 "eori",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1788 "eori",//sr
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1789 "exg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1790 "ext",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1791 "illegal",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1792 "jmp",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1793 "jsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1794 "lea",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1795 "link",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1796 "lsl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1797 "lsr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1798 "move",
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1799 "move",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1800 "move",//from_sr
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1801 "move",//sr
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
1802 "move",//usp
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1803 "movem",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1804 "movep",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1805 "muls",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1806 "mulu",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1807 "nbcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1808 "neg",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1809 "negx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1810 "nop",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1811 "not",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1812 "or",
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1813 "ori",//ccr
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1814 "ori",//sr
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1815 "pea",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1816 "reset",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1817 "rol",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1818 "ror",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1819 "roxl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1820 "roxr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1821 "rte",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1822 "rtr",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1823 "rts",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1824 "sbcd",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1825 "scc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1826 "stop",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1827 "sub",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1828 "subx",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1829 "swap",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1830 "tas",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1831 "trap",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1832 "trapv",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1833 "tst",
12
db60ed283d8d Add mising bit instructions to decoder. Add test assembly file containing most distinct instructions.
Mike Pavone <pavone@retrodev.com>
parents: 11
diff changeset
1834 "unlk",
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1835 "invalid",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1836 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1837 "bkpt",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1838 "move", //from ccr
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1839 "movec",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1840 "moves",
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1841 "rtd",
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1842 #endif
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1843 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1844 "bfchg",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1845 "bfclr",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1846 "bfexts",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1847 "bfextu",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1848 "bfffo",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1849 "bfins",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1850 "bfset",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1851 "bftst",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1852 "callm",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1853 "cas",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1854 "cas2",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1855 "chk2",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1856 "cmp2",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1857 "cpbcc",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1858 "cpdbcc",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1859 "cpgen",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1860 "cprestore",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1861 "cpsave",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1862 "cpscc",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1863 "cptrapcc",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1864 "divsl",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1865 "divul",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1866 "extb",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1867 "pack",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1868 "rtm",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1869 "trapcc",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1870 "unpk"
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1871 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1872 };
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1873
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1874 char * cond_mnem[] = {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1875 "ra",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1876 "f",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1877 "hi",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1878 "ls",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1879 "cc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1880 "cs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1881 "ne",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1882 "eq",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1883 "vc",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1884 "vs",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1885 "pl",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1886 "mi",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1887 "ge",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1888 "lt",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1889 "gt",
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1890 "le"
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1891 };
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1892 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1893 char * cr_mnem[] = {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1894 "SFC",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1895 "DFC",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1896 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1897 "CACR",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1898 #endif
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1899 "USP",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1900 "VBR",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1901 #ifdef M68020
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1902 "CAAR",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1903 "MSP",
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1904 "ISP"
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1905 #endif
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1906 };
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
1907 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1908
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
1909 int m68k_disasm_op(m68k_op_info *decoded, char *dst, int need_comma, uint8_t labels, uint32_t address, format_label_fun label_fun, void * data)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1910 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1911 char * c = need_comma ? "," : "";
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1912 int ret = 0;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1913 #ifdef M68020
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1914 uint8_t addr_mode = decoded->addr_mode & (~M68K_FLAG_BITFIELD);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1915 #else
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1916 uint8_t addr_mode = decoded->addr_mode;
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1917 #endif
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1918 switch(addr_mode)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1919 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1920 case MODE_REG:
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1921 ret = sprintf(dst, "%s d%d", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1922 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1923 case MODE_AREG:
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1924 ret = sprintf(dst, "%s a%d", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1925 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1926 case MODE_AREG_INDIRECT:
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1927 ret = sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1928 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1929 case MODE_AREG_POSTINC:
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1930 ret = sprintf(dst, "%s (a%d)+", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1931 break;
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
1932 case MODE_AREG_PREDEC:
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1933 ret = sprintf(dst, "%s -(a%d)", c, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1934 break;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
1935 case MODE_AREG_DISPLACE:
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1936 ret = sprintf(dst, "%s (%d, a%d)", c, decoded->params.regs.displacement, decoded->params.regs.pri);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
1937 break;
79
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 69
diff changeset
1938 case MODE_AREG_INDEX_DISP8:
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1939 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1940 if (decoded->params.regs.scale)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1941 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1942 ret = sprintf(dst, "%s (%d, a%d, %c%d.%c*%d)", c, decoded->params.regs.displacement, decoded->params.regs.pri, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1943 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1944 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1945 ret = sprintf(dst, "%s (%d, a%d, %c%d.%c)", c, decoded->params.regs.displacement, decoded->params.regs.pri, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1946 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1947 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1948 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1949 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1950 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1951 case MODE_AREG_INDEX_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1952 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1953 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1954 ret = sprintf(dst, "%s (%d.%c, a%d, %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1955 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1956 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1957 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1958 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1959 ret = sprintf(dst, "%s (a%d, %c%d.%c*%d)", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1960 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1961 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1962 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1963 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1964 case MODE_AREG_PREINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1965 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1966 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1967 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1968 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1969 ret = sprintf(dst, "%s ([a%d, %c%d.%c*%d])", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1970 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1971 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1972 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1973 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1974 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1975 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1976 ret = sprintf(dst, "%s ([%d.%c, a%d, %c%d.%c*%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1977 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1978 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1979 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1980 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1981 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1982 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1983 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1984 ret = sprintf(dst, "%s ([a%d, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1985 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1986 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1987 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1988 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1989 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1990 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1991 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1992 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1993 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1994 ret = sprintf(dst, "%s ([%d.%c, a%d, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1995 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1996 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1997 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1998 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
1999 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2000 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2001 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2002 case MODE_AREG_POSTINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2003 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2004 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2005 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2006 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2007 ret = sprintf(dst, "%s ([a%d], %c%d.%c*%d)", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2008 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2009 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2010 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2011 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2012 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2013 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2014 ret = sprintf(dst, "%s ([%d.%c, a%d], %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2015 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2016 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2017 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2018 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2019 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2020 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2021 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2022 ret = sprintf(dst, "%s ([a%d], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2023 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2024 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2025 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2026 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2027 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2028 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2029 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2030 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2031 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2032 ret = sprintf(dst, "%s ([%d.%c, a%d], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2033 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2034 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2035 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2036 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2037 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2038 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2039 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2040 case MODE_AREG_MEM_INDIRECT:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2041 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2042 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2043 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2044 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2045 ret = sprintf(dst, "%s ([a%d])", c, decoded->params.regs.pri);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2046 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2047 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2048 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2049 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2050 ret = sprintf(dst, "%s ([%d.%c, a%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2051 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2052 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2053 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2054 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2055 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2056 ret = sprintf(dst, "%s ([a%d], %d.%c)", c, decoded->params.regs.pri, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2057 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2058 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2059 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2060 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2061 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2062 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2063 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2064 ret = sprintf(dst, "%s ([%d.%c, a%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2065 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.pri,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2066 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2067 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2068 }
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2069 break;
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2070 case MODE_AREG_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2071 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2072 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2073 ret = sprintf(dst, "%s (%d.%c, a%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2074 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l', decoded->params.regs.pri);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2075 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2076 //this is a lossy representation of the encoded instruction
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2077 //not sure if there's a better way to print it though
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2078 ret = sprintf(dst, "%s (a%d)", c, decoded->params.regs.pri);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2079 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2080 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2081 case MODE_INDEX_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2082 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2083 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2084 ret = sprintf(dst, "%s (%d.%c, %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2085 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2086 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2087 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2088 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2089 ret = sprintf(dst, "%s (%c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2090 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2091 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2092 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2093 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2094 case MODE_PREINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2095 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2096 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2097 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2098 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2099 ret = sprintf(dst, "%s ([%c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2100 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2101 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2102 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2103 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2104 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2105 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2106 ret = sprintf(dst, "%s ([%d.%c, %c%d.%c*%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2107 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2108 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2109 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2110 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2111 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2112 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2113 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2114 ret = sprintf(dst, "%s ([%c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2115 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2116 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2117 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2118 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2119 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2120 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2121 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2122 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2123 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2124 ret = sprintf(dst, "%s ([%d.%c, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2125 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2126 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2127 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2128 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2129 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2130 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2131 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2132 case MODE_POSTINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2133 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2134 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2135 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2136 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2137 ret = sprintf(dst, "%s ([], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2138 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2139 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2140 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2141 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2142 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2143 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2144 ret = sprintf(dst, "%s ([%d.%c], %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2145 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2146 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2147 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2148 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2149 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2150 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2151 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2152 ret = sprintf(dst, "%s ([], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2153 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2154 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2155 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2156 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2157 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2158 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2159 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2160 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2161 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2162 ret = sprintf(dst, "%s ([%d.%c], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2163 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2164 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2165 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2166 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2167 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2168 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2169 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2170 case MODE_MEM_INDIRECT:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2171 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2172 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2173 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2174 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2175 ret = sprintf(dst, "%s ([])", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2176 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2177 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2178 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2179 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2180 ret = sprintf(dst, "%s ([%d.%c])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2181 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2182 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2183 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2184 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2185 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2186 ret = sprintf(dst, "%s ([], %d.%c)", c, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2187 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2188 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2189 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2190 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2191 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2192 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2193 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2194 ret = sprintf(dst, "%s ([%d.%c], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2195 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2196 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2197 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2198 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2199 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2200 case MODE_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2201 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2202 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2203 ret = sprintf(dst, "%s (%d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2204 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2205 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2206 ret = sprintf(dst, "%s ()", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2207 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2208 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2209 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2210 case MODE_IMMEDIATE:
61
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM.
Mike Pavone <pavone@retrodev.com>
parents: 60
diff changeset
2211 case MODE_IMMEDIATE_WORD:
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2212 ret = sprintf(dst, (decoded->params.immed <= 128 ? "%s #%d" : "%s #$%X"), c, decoded->params.immed);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2213 break;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2214 case MODE_ABSOLUTE_SHORT:
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2215 if (labels) {
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2216 ret = sprintf(dst, "%s ", c);
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2217 ret += label_fun(dst+ret, decoded->params.immed, data);
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2218 strcat(dst+ret, ".w");
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2219 ret = ret + 2;
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2220 } else {
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2221 ret = sprintf(dst, "%s $%X.w", c, decoded->params.immed);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2222 }
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2223 break;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2224 case MODE_ABSOLUTE:
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2225 if (labels) {
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2226 ret = sprintf(dst, "%s ", c);
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2227 ret += label_fun(dst+ret, decoded->params.immed, data);
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2228 strcat(dst+ret, ".l");
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2229 ret = ret + 2;
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2230 } else {
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2231 ret = sprintf(dst, "%s $%X", c, decoded->params.immed);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2232 }
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2233 break;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2234 case MODE_PC_DISPLACE:
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2235 if (labels) {
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2236 ret = sprintf(dst, "%s ", c);
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2237 ret += label_fun(dst+ret, address + 2 + decoded->params.regs.displacement, data);
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2238 strcat(dst+ret, "(pc)");
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2239 ret = ret + 4;
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2240 } else {
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2241 ret = sprintf(dst, "%s (%d, pc)", c, decoded->params.regs.displacement);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2242 }
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2243 break;
79
d212e0cd0b7e Implement indexed with 8-bit displacement addressing modes in decoder and disassembler
Mike Pavone <pavone@retrodev.com>
parents: 69
diff changeset
2244 case MODE_PC_INDEX_DISP8:
638
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2245 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2246 if (decoded->params.regs.scale)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2247 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2248 ret = sprintf(dst, "%s (%d, pc, %c%d.%c*%d)", c, decoded->params.regs.displacement, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2249 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2250 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2251 ret = sprintf(dst, "%s (%d, pc, %c%d.%c)", c, decoded->params.regs.displacement, (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2252 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2253 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2254 #endif
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2255 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2256 #ifdef M68020
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2257 case MODE_PC_INDEX_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2258 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2259 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2260 ret = sprintf(dst, "%s (%d.%c, pc, %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2261 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2262 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2263 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2264 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2265 ret = sprintf(dst, "%s (pc, %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2266 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2267 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2268 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2269 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2270 case MODE_PC_PREINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2271 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2272 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2273 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2274 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2275 ret = sprintf(dst, "%s ([pc, %c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2276 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2277 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2278 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2279 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2280 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2281 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2282 ret = sprintf(dst, "%s ([%d.%c, pc, %c%d.%c*%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2283 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2284 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2285 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2286 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2287 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2288 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2289 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2290 ret = sprintf(dst, "%s ([pc, %c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2291 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2292 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2293 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2294 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2295 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2296 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2297 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2298 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2299 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2300 ret = sprintf(dst, "%s ([%d.%c, pc, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2301 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2302 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2303 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2304 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2305 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2306 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2307 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2308 case MODE_PC_POSTINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2309 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2310 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2311 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2312 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2313 ret = sprintf(dst, "%s ([pc], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2314 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2315 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2316 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2317 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2318 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2319 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2320 ret = sprintf(dst, "%s ([%d.%c, pc], %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2321 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2322 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2323 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2324 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2325 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2326 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2327 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2328 ret = sprintf(dst, "%s ([pc], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2329 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2330 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2331 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2332 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2333 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2334 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2335 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2336 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2337 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2338 ret = sprintf(dst, "%s ([%d.%c, pc], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2339 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2340 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2341 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2342 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2343 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2344 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2345 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2346 case MODE_PC_MEM_INDIRECT:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2347 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2348 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2349 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2350 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2351 ret = sprintf(dst, "%s ([pc])", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2352 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2353 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2354 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2355 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2356 ret = sprintf(dst, "%s ([%d.%c, pc])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2357 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2358 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2359 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2360 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2361 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2362 ret = sprintf(dst, "%s ([pc], %d.%c)", c, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2363 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2364 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2365 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2366 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2367 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2368 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2369 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2370 ret = sprintf(dst, "%s ([%d.%c, pc], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2371 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2372 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2373 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2374 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2375 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2376 case MODE_PC_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2377 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2378 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2379 ret = sprintf(dst, "%s (%d.%c, pc)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2380 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2381 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2382 ret = sprintf(dst, "%s (pc)", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2383 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2384 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2385 case MODE_ZPC_INDEX_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2386 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2387 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2388 ret = sprintf(dst, "%s (%d.%c, zpc, %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2389 decoded->params.regs.disp_sizes == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2390 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2391 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2392 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2393 ret = sprintf(dst, "%s (zpc, %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2394 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2395 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2396 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2397 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2398 case MODE_ZPC_PREINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2399 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2400 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2401 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2402 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2403 ret = sprintf(dst, "%s ([zpc, %c%d.%c*%d])", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2404 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2405 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2406 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2407 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2408 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2409 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2410 ret = sprintf(dst, "%s ([%d.%c, zpc, %c%d.%c*%d])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2411 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2412 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2413 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2414 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2415 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2416 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2417 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2418 ret = sprintf(dst, "%s ([zpc, %c%d.%c*%d], %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2419 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2420 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2421 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2422 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2423 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2424 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2425 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2426 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2427 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2428 ret = sprintf(dst, "%s ([%d.%c, zpc, %c%d.%c*%d], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2429 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2430 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2431 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2432 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2433 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2434 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2435 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2436 case MODE_ZPC_POSTINDEX:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2437 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2438 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2439 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2440 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2441 ret = sprintf(dst, "%s ([zpc], %c%d.%c*%d)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2442 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2443 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2444 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2445 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2446 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2447 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2448 ret = sprintf(dst, "%s ([%d.%c, zpc], %c%d.%c*%d)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2449 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2450 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2451 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2452 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2453 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2454 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2455 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2456 ret = sprintf(dst, "%s ([zpc], %c%d.%c*%d, %d.%c)", c, (decoded->params.regs.sec & 0x10) ? 'a': 'd',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2457 (decoded->params.regs.sec >> 1) & 0x7, (decoded->params.regs.sec & 1) ? 'l': 'w',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2458 1 << decoded->params.regs.scale, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2459 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2460 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2461 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2462 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2463 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2464 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2465 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2466 ret = sprintf(dst, "%s ([%d.%c, zpc], %c%d.%c*%d, %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2467 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l',
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2468 (decoded->params.regs.sec & 0x10) ? 'a': 'd', (decoded->params.regs.sec >> 1) & 0x7,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2469 (decoded->params.regs.sec & 1) ? 'l': 'w', 1 << decoded->params.regs.scale,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2470 decoded->params.regs.outer_disp, decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2471 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2472 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2473 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2474 case MODE_ZPC_MEM_INDIRECT:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2475 switch (decoded->params.regs.disp_sizes)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2476 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2477 case 0x11:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2478 //no base displacement or outer displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2479 ret = sprintf(dst, "%s ([zpc])", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2480 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2481 case 0x12:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2482 case 0x13:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2483 //base displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2484 ret = sprintf(dst, "%s ([%d.%c, zpc])", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2485 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2486 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2487 case 0x21:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2488 case 0x31:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2489 //outer displacement only
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2490 ret = sprintf(dst, "%s ([zpc], %d.%c)", c, decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2491 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2492 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2493 case 0x22:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2494 case 0x23:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2495 case 0x32:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2496 case 0x33:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2497 //both outer and inner displacement
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2498 ret = sprintf(dst, "%s ([%d.%c, zpc], %d.%c)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2499 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l', decoded->params.regs.outer_disp,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2500 decoded->params.regs.disp_sizes & 0x30 == 0x20 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2501 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2502 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2503 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2504 case MODE_ZPC_BASE_DISP:
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2505 if (decoded->params.regs.disp_sizes > 1)
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2506 {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2507 ret = sprintf(dst, "%s (%d.%c, zpc)", c, decoded->params.regs.displacement,
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2508 decoded->params.regs.disp_sizes & 3 == 2 ? 'w' : 'l');
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2509 } else {
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2510 ret = sprintf(dst, "%s (zpc)", c);
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2511 }
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2512 break;
8a3198c17207 Add support for 68020 addressing modes in decoder and disassembler
Michael Pavone <pavone@retrodev.com>
parents: 636
diff changeset
2513 #endif
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2514 default:
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2515 ret = 0;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2516 }
636
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2517 #ifdef M68020
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2518 if (decoded->addr_mode & M68K_FLAG_BITFIELD)
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2519 {
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2520 switch (decoded->bitfield & 0x820)
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2521 {
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2522 case 0:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2523 return ret + sprintf(dst+ret, " {$%X:%d}", decoded->bitfield >> 6 & 0x1F, decoded->bitfield & 0x1F ? decoded->bitfield & 0x1F : 32);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2524 case 0x20:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2525 return ret + sprintf(dst+ret, " {$%X:d%d}", decoded->bitfield >> 6 & 0x1F, decoded->bitfield & 0x7);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2526 case 0x800:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2527 return ret + sprintf(dst+ret, " {d%d:%d}", decoded->bitfield >> 6 & 0x7, decoded->bitfield & 0x1F ? decoded->bitfield & 0x1F : 32);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2528 case 0x820:
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2529 return ret + sprintf(dst+ret, " {d%d:d%d}", decoded->bitfield >> 6 & 0x7, decoded->bitfield & 0x7);
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2530 }
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2531 }
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2532 #endif
22e357678fad Add support for 68020 bitfield instructions
Michael Pavone <pavone@retrodev.com>
parents: 634
diff changeset
2533 return ret;
0
2432d177e1ac Initial work on M68K instruction decoding
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
2534 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2535
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2536 int m68k_disasm_movem_op(m68k_op_info *decoded, m68k_op_info *other, char *dst, int need_comma, uint8_t labels, uint32_t address, format_label_fun label_fun, void * data)
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2537 {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2538 int8_t dir, reg, bit, regnum, last=-1, lastreg, first=-1;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2539 char *rtype, *last_rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2540 int oplen;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2541 if (decoded->addr_mode == MODE_REG) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2542 if (other->addr_mode == MODE_AREG_PREDEC) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2543 bit = 15;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2544 dir = -1;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2545 } else {
69
36f1133837d0 Fix disassembly of reg list in MOVEM when the reg list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 68
diff changeset
2546 dir = 1;
36f1133837d0 Fix disassembly of reg list in MOVEM when the reg list is the destination
Mike Pavone <pavone@retrodev.com>
parents: 68
diff changeset
2547 bit = 0;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2548 }
68
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
2549 if (need_comma) {
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
2550 strcat(dst, ", ");
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
2551 oplen = 2;
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
2552 } else {
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
2553 strcat(dst, " ");
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
2554 oplen = 1;
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
2555 }
1c9a4052a2c0 Fix decoding and disassembly of MOVEM
Mike Pavone <pavone@retrodev.com>
parents: 62
diff changeset
2556 for (reg=0; bit < 16 && bit > -1; bit += dir, reg++) {
15
c0f339564819 Make x86 generator generic with respect to operand size for immediate parameters.
Mike Pavone <pavone@retrodev.com>
parents: 13
diff changeset
2557 if (decoded->params.immed & (1 << bit)) {
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2558 if (reg > 7) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2559 rtype = "a";
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2560 regnum = reg - 8;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2561 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2562 rtype = "d";
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2563 regnum = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2564 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2565 if (last >= 0 && last == regnum - 1 && lastreg == reg - 1) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2566 last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2567 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2568 } else if(last >= 0) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2569 if (first != last) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2570 oplen += sprintf(dst + oplen, "-%s%d/%s%d",last_rtype, last, rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2571 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2572 oplen += sprintf(dst + oplen, "/%s%d", rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2573 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2574 first = last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2575 last_rtype = rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2576 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2577 } else {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2578 oplen += sprintf(dst + oplen, "%s%d", rtype, regnum);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2579 first = last = regnum;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2580 last_rtype = rtype;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2581 lastreg = reg;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2582 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2583 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2584 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2585 if (last >= 0 && last != first) {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2586 oplen += sprintf(dst + oplen, "-%s%d", last_rtype, last);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2587 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2588 return oplen;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2589 } else {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2590 return m68k_disasm_op(decoded, dst, need_comma, labels, address, label_fun, data);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2591 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2592 }
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2593
2213
53411df7fc71 More 68K disassembler refactoring and fix Windows build failure
Michael Pavone <pavone@retrodev.com>
parents: 2133
diff changeset
2594 int m68k_disasm_ex(m68kinst * decoded, char * dst, uint8_t labels, format_label_fun label_fun, disasm_context *data)
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2595 {
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2596 int ret,op1len;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2597 uint8_t size;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2598 char * special_op = "CCR";
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2599 switch (decoded->op)
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2600 {
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2601 case M68K_BCC:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2602 case M68K_DBCC:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2603 case M68K_SCC:
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2604 ret = strlen(mnemonics[decoded->op]) - 2;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2605 memcpy(dst, mnemonics[decoded->op], ret);
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2606 dst[ret] = 0;
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2607 strcpy(dst+ret, cond_mnem[decoded->extra.cond]);
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2608 ret = strlen(dst);
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2609 if (decoded->op != M68K_SCC) {
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2610 if (labels) {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2611 if (decoded->op == M68K_DBCC) {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2612 ret += sprintf(dst+ret, " d%d, ", decoded->dst.params.regs.pri);
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2613 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2614 } else {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2615 dst[ret++] = ' ';
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2616 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2617 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
2618 } else {
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2619 if (decoded->op == M68K_DBCC) {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2620 ret += sprintf(dst+ret, " d%d, #%d <%X>", decoded->dst.params.regs.pri, decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2621 } else {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2622 ret += sprintf(dst+ret, " #%d <%X>", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2623 }
54
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents: 51
diff changeset
2624 }
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2625 return ret;
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2626 }
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2627 break;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2628 case M68K_BSR:
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2629 if (labels) {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2630 ret = sprintf(dst, "bsr%s ", decoded->variant == VAR_BYTE ? ".s" : "");
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2631 ret += label_fun(dst+ret, decoded->address + 2 + decoded->src.params.immed, data);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2632 } else {
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2633 ret = sprintf(dst, "bsr%s #%d <%X>", decoded->variant == VAR_BYTE ? ".s" : "", decoded->src.params.immed, decoded->address + 2 + decoded->src.params.immed);
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2634 }
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2635 return ret;
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2636 case M68K_MOVE_FROM_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2637 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2638 ret += sprintf(dst + ret, " SR");
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2639 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 1, labels, decoded->address, label_fun, data);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2640 return ret;
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2641 case M68K_ANDI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2642 case M68K_EORI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2643 case M68K_MOVE_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2644 case M68K_ORI_SR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2645 special_op = "SR";
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2646 case M68K_ANDI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2647 case M68K_EORI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2648 case M68K_MOVE_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2649 case M68K_ORI_CCR:
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2650 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2651 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2652 ret += sprintf(dst + ret, ", %s", special_op);
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2653 return ret;
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2654 case M68K_MOVE_USP:
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2655 ret = sprintf(dst, "%s", mnemonics[decoded->op]);
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2656 if (decoded->src.addr_mode != MODE_UNUSED) {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2657 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data);
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2658 ret += sprintf(dst + ret, ", USP");
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2659 } else {
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2660 ret += sprintf(dst + ret, "USP, ");
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2661 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data);
50
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2662 }
4836d1f3841a Fix shift rotate instruction decoding and improve disassembly of move USP and conditional branch instructions
Mike Pavone <pavone@retrodev.com>
parents: 46
diff changeset
2663 return ret;
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2664 case M68K_INVALID:
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2665 ret = sprintf(dst, "dc.w $%X", decoded->src.params.immed);
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2666 return ret;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2667 #ifdef M68010
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2668 case M68K_MOVEC:
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2669 ret = sprintf(dst, "%s ", mnemonics[decoded->op]);
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2670 if (decoded->src.addr_mode == MODE_UNUSED) {
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2671 ret += sprintf(dst + ret, "%s, ", cr_mnem[decoded->src.params.immed]);
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2672 ret += m68k_disasm_op(&(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data);
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2673 } else {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2674 ret += m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data);
630
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2675 ret += sprintf(dst + ret, ", %s", cr_mnem[decoded->dst.params.immed]);
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2676 }
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2677 return ret;
47123183c336 Improve support for disassembling 68010+ binaries
Michael Pavone <pavone@retrodev.com>
parents: 518
diff changeset
2678 #endif
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2679 default:
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2680 size = decoded->extra.size;
2133
8554751f17b5 Remove use of get_native_pointer in 68K instruction decoding in preparation for word RAM interleaving
Michael Pavone <pavone@retrodev.com>
parents: 1627
diff changeset
2681 uint8_t is_quick = decoded->variant == VAR_QUICK && decoded->op != M68K_ASL && decoded->op != M68K_ASR
1627
dc1eab3ec092 Fix cycle count for shift/rotate instructions with a static shift ammount
Michael Pavone <pavone@retrodev.com>
parents: 1463
diff changeset
2682 && decoded->op != M68K_LSL && decoded->op != M68K_LSR && decoded->op != M68K_ROXR && decoded->op != M68K_ROXL
dc1eab3ec092 Fix cycle count for shift/rotate instructions with a static shift ammount
Michael Pavone <pavone@retrodev.com>
parents: 1463
diff changeset
2683 && decoded->op != M68K_ROR && decoded->op != M68K_ROL;
518
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
2684 ret = sprintf(dst, "%s%s%s",
775802dab98f Refactor debugger next command
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
2685 mnemonics[decoded->op],
1627
dc1eab3ec092 Fix cycle count for shift/rotate instructions with a static shift ammount
Michael Pavone <pavone@retrodev.com>
parents: 1463
diff changeset
2686 is_quick ? "q" : (decoded->variant == VAR_IMMEDIATE ? "i" : ""),
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2687 size == OPSIZE_BYTE ? ".b" : (size == OPSIZE_WORD ? ".w" : (size == OPSIZE_LONG ? ".l" : "")));
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2688 }
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2689 if (decoded->op == M68K_MOVEM) {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2690 op1len = m68k_disasm_movem_op(&(decoded->src), &(decoded->dst), dst + ret, 0, labels, decoded->address, label_fun, data);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2691 ret += op1len;
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2692 ret += m68k_disasm_movem_op(&(decoded->dst), &(decoded->src), dst + ret, op1len, labels, decoded->address, label_fun, data);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2693 } else {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2694 op1len = m68k_disasm_op(&(decoded->src), dst + ret, 0, labels, decoded->address, label_fun, data);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2695 ret += op1len;
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2696 ret += m68k_disasm_op(&(decoded->dst), dst + ret, op1len, labels, decoded->address, label_fun, data);
13
168b1a873895 Improve disassembly. FIx some decoding bugs.
Mike Pavone <pavone@retrodev.com>
parents: 12
diff changeset
2697 }
2
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2698 return ret;
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2699 }
5df303bf72e6 Improve 68K instruction decoding. Add simple disassembler.
Mike Pavone <pavone@retrodev.com>
parents: 0
diff changeset
2700
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2701 int m68k_disasm(m68kinst * decoded, char * dst)
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2702 {
634
4a6ec64acd79 Better support for labels sourced from VOS program module header
Michael Pavone <pavone@retrodev.com>
parents: 630
diff changeset
2703 return m68k_disasm_ex(decoded, dst, 0, NULL, NULL);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2704 }
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2705
2213
53411df7fc71 More 68K disassembler refactoring and fix Windows build failure
Michael Pavone <pavone@retrodev.com>
parents: 2133
diff changeset
2706 int m68k_disasm_labels(m68kinst * decoded, char * dst, disasm_context *disasm)
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2707 {
2213
53411df7fc71 More 68K disassembler refactoring and fix Windows build failure
Michael Pavone <pavone@retrodev.com>
parents: 2133
diff changeset
2708 return m68k_disasm_ex(decoded, dst, 1, format_label, disasm);
134
ab50421b1b7a Improve disassembler
Mike Pavone <pavone@retrodev.com>
parents: 120
diff changeset
2709 }