Mercurial > repos > blastem
annotate cpu_dsl.py @ 1707:a16088324f30
Less broken flag calulcation for sub instructions in CPU DSL
author | Michael Pavone <pavone@retrodev.com> |
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date | Mon, 28 Jan 2019 21:30:23 -0800 |
parents | 9ab64ef5cba0 |
children | 5bfed2eedc9d |
rev | line source |
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1 #!/usr/bin/env python3 |
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2 |
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3 |
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4 class Block: |
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5 def addOp(self, op): |
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6 pass |
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7 |
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8 def processLine(self, parts): |
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9 if parts[0] == 'switch': |
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10 o = Switch(self, parts[1]) |
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11 self.addOp(o) |
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12 return o |
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13 elif parts[0] == 'if': |
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14 o = If(self, parts[1]) |
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15 self.addOp(o) |
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16 return o |
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17 elif parts[0] == 'end': |
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18 raise Exception('end is only allowed inside a switch or if block') |
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19 else: |
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20 self.addOp(NormalOp(parts)) |
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21 return self |
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22 |
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23 def processOps(self, prog, fieldVals, output, otype, oplist): |
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24 for i in range(0, len(oplist)): |
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25 if i + 1 < len(oplist) and oplist[i+1].op == 'update_flags': |
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26 flagUpdates, _ = prog.flags.parseFlagUpdate(oplist[i+1].params[0]) |
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27 else: |
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28 flagUpdates = None |
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29 oplist[i].generate(prog, self, fieldVals, output, otype, flagUpdates) |
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30 |
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31 def resolveLocal(self, name): |
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32 return None |
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33 |
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34 class ChildBlock(Block): |
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35 def processLine(self, parts): |
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36 if parts[0] == 'end': |
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37 return self.parent |
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38 return super().processLine(parts) |
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39 |
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40 #Represents an instruction of the emulated CPU |
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41 class Instruction(Block): |
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42 def __init__(self, value, fields, name): |
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43 self.value = value |
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44 self.fields = fields |
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45 self.name = name |
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46 self.implementation = [] |
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47 self.locals = {} |
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48 self.regValues = {} |
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49 self.varyingBits = 0 |
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50 self.invalidFieldValues = {} |
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51 self.newLocals = [] |
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52 for field in fields: |
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53 self.varyingBits += fields[field][1] |
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54 |
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55 def addOp(self, op): |
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56 if op.op == 'local': |
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57 name = op.params[0] |
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58 size = op.params[1] |
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59 self.locals[name] = size |
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60 elif op.op == 'invalid': |
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61 name = op.params[0] |
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62 value = int(op.params[1]) |
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63 self.invalidFieldValues.setdefault(name, set()).add(value) |
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64 else: |
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65 self.implementation.append(op) |
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66 |
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67 def resolveLocal(self, name): |
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68 if name in self.locals: |
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69 return name |
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70 return None |
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71 |
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72 def addLocal(self, name, size): |
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73 self.locals[name] = size |
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74 self.newLocals.append(name) |
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75 |
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76 def localSize(self, name): |
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77 return self.locals.get(name) |
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78 |
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79 def __lt__(self, other): |
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80 if isinstance(other, Instruction): |
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81 if self.varyingBits != other.varyingBits: |
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82 return self.varyingBits < other.varyingBits |
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83 return self.value < other.value |
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84 else: |
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85 return NotImplemented |
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86 |
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87 def allValues(self): |
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88 values = [] |
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89 for i in range(0, 1 << self.varyingBits): |
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90 iword = self.value |
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91 doIt = True |
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92 for field in self.fields: |
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93 shift,bits = self.fields[field] |
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94 val = i & ((1 << bits) - 1) |
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95 if field in self.invalidFieldValues and val in self.invalidFieldValues[field]: |
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96 doIt = False |
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97 break |
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98 i >>= bits |
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99 iword |= val << shift |
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100 if doIt: |
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101 values.append(iword) |
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102 return values |
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103 |
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104 def getFieldVals(self, value): |
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105 fieldVals = {} |
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106 fieldBits = {} |
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107 for field in self.fields: |
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108 shift,bits = self.fields[field] |
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109 val = (value >> shift) & ((1 << bits) - 1) |
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110 fieldVals[field] = val |
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111 fieldBits[field] = bits |
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112 return (fieldVals, fieldBits) |
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113 |
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114 def generateName(self, value): |
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115 fieldVals,fieldBits = self.getFieldVals(value) |
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116 names = list(fieldVals.keys()) |
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117 names.sort() |
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118 funName = self.name |
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119 for name in names: |
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120 funName += '_{0}_{1:0>{2}}'.format(name, bin(fieldVals[name])[2:], fieldBits[name]) |
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121 return funName |
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122 |
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123 def generateBody(self, value, prog, otype): |
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124 output = [] |
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125 prog.meta = {} |
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126 prog.pushScope(self) |
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127 self.regValues = {} |
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128 for var in self.locals: |
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129 output.append('\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var)) |
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130 self.newLocals = [] |
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131 fieldVals,_ = self.getFieldVals(value) |
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132 self.processOps(prog, fieldVals, output, otype, self.implementation) |
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133 begin = '\nvoid ' + self.generateName(value) + '(' + prog.context_type + ' *context)\n{' |
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134 if prog.needFlagCoalesce: |
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135 begin += prog.flags.coalesceFlags(prog, otype) |
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136 if prog.needFlagDisperse: |
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137 output.append(prog.flags.disperseFlags(prog, otype)) |
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138 for var in self.newLocals: |
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139 begin += '\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var) |
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140 prog.popScope() |
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141 return begin + ''.join(output) + '\n}' |
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142 |
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143 def __str__(self): |
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144 pieces = [self.name + ' ' + hex(self.value) + ' ' + str(self.fields)] |
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145 for name in self.locals: |
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146 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name])) |
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147 for op in self.implementation: |
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148 pieces.append(str(op)) |
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149 return ''.join(pieces) |
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150 |
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151 #Represents the definition of a helper function |
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152 class SubRoutine(Block): |
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153 def __init__(self, name): |
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154 self.name = name |
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155 self.implementation = [] |
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156 self.args = [] |
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157 self.arg_map = {} |
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158 self.locals = {} |
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159 self.regValues = {} |
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160 |
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161 def addOp(self, op): |
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162 if op.op == 'arg': |
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163 name = op.params[0] |
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164 size = op.params[1] |
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165 self.arg_map[name] = len(self.args) |
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166 self.args.append((name, size)) |
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167 elif op.op == 'local': |
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168 name = op.params[0] |
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169 size = op.params[1] |
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170 self.locals[name] = size |
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171 else: |
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172 self.implementation.append(op) |
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173 |
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174 def resolveLocal(self, name): |
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175 if name in self.locals: |
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176 return self.name + '_' + name |
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177 return None |
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178 |
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179 def addLocal(self, name, size): |
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180 self.locals[name] = size |
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181 |
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182 def localSize(self, name): |
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183 return self.locals.get(name) |
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184 |
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185 def inline(self, prog, params, output, otype, parent): |
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186 if len(params) != len(self.args): |
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187 raise Exception('{0} expects {1} arguments, but was called with {2}'.format(self.name, len(self.args), len(params))) |
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188 argValues = {} |
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189 if parent: |
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190 self.regValues = parent.regValues |
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191 prog.pushScope(self) |
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192 i = 0 |
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193 for name,size in self.args: |
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194 argValues[name] = params[i] |
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195 i += 1 |
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196 for name in self.locals: |
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197 size = self.locals[name] |
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198 output.append('\n\tuint{size}_t {sub}_{local};'.format(size=size, sub=self.name, local=name)) |
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199 self.processOps(prog, argValues, output, otype, self.implementation) |
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200 prog.popScope() |
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201 |
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202 def __str__(self): |
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203 pieces = [self.name] |
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204 for name,size in self.args: |
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205 pieces.append('\n\targ {0} {1}'.format(name, size)) |
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206 for name in self.locals: |
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207 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name])) |
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208 for op in self.implementation: |
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209 pieces.append(str(op)) |
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210 return ''.join(pieces) |
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211 |
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212 class Op: |
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213 def __init__(self, evalFun = None): |
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214 self.evalFun = evalFun |
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215 self.impls = {} |
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216 self.outOp = () |
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217 def cBinaryOperator(self, op): |
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218 def _impl(prog, params, rawParams, flagUpdates): |
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219 if op == '-': |
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220 a = params[1] |
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221 b = params[0] |
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222 else: |
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223 a = params[0] |
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224 b = params[1] |
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225 needsCarry = needsOflow = needsHalf = False |
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226 if flagUpdates: |
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227 for flag in flagUpdates: |
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228 calc = prog.flags.flagCalc[flag] |
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229 if calc == 'carry': |
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230 needsCarry = True |
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231 elif calc == 'half-carry': |
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232 needsHalf = True |
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233 elif calc == 'overflow': |
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234 needsOflow = True |
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235 decl = '' |
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236 if needsCarry or needsOflow or needsHalf: |
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237 size = prog.paramSize(rawParams[2]) |
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238 if needsCarry: |
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239 size *= 2 |
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240 decl,name = prog.getTemp(size) |
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241 dst = prog.carryFlowDst = name |
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242 prog.lastA = a |
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243 prog.lastB = '(-' + b + ')' if op == '-' else b |
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244 prog.lastWasSub = op == '-' |
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245 else: |
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246 dst = params[2] |
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247 return decl + '\n\t{dst} = {a} {op} {b};'.format( |
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248 dst = dst, a = a, b = b, op = op |
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249 ) |
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250 self.impls['c'] = _impl |
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251 self.outOp = (2,) |
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252 return self |
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253 def cUnaryOperator(self, op): |
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254 def _impl(prog, params): |
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255 return '\n\t{dst} = {op}{a};'.format( |
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256 dst = params[1], a = params[0], op = op |
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257 ) |
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258 self.impls['c'] = _impl |
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259 self.outOp = (1,) |
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260 return self |
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261 def addImplementation(self, lang, outOp, impl): |
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262 self.impls[lang] = impl |
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263 if not outOp is None: |
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264 if type(outOp) is tuple: |
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265 self.outOp = outOp |
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266 else: |
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267 self.outOp = (outOp,) |
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268 return self |
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269 def evaluate(self, params): |
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270 return self.evalFun(*params) |
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271 def canEval(self): |
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272 return not self.evalFun is None |
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273 def numArgs(self): |
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274 return self.evalFun.__code__.co_argcount |
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275 def generate(self, otype, prog, params, rawParams, flagUpdates): |
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276 if self.impls[otype].__code__.co_argcount == 2: |
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277 return self.impls[otype](prog, params) |
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278 elif self.impls[otype].__code__.co_argcount == 3: |
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279 return self.impls[otype](prog, params, rawParams) |
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280 else: |
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281 return self.impls[otype](prog, params, rawParams, flagUpdates) |
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282 |
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283 |
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284 def _xchgCImpl(prog, params, rawParams): |
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285 size = prog.paramSize(rawParams[0]) |
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286 decl,name = prog.getTemp(size) |
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287 return decl + '\n\t{tmp} = {a};\n\t{a} = {b};\n\t{b} = {tmp};'.format(a = params[0], b = params[1], tmp = name) |
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288 |
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289 def _dispatchCImpl(prog, params): |
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290 if len(params) == 1: |
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291 table = 'main' |
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292 else: |
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293 table = params[1] |
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294 return '\n\timpl_{tbl}[{op}](context);'.format(tbl = table, op = params[0]) |
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295 |
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296 def _updateFlagsCImpl(prog, params, rawParams): |
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297 autoUpdate, explicit = prog.flags.parseFlagUpdate(params[0]) |
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298 output = [] |
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299 #TODO: handle autoUpdate flags |
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300 for flag in autoUpdate: |
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301 calc = prog.flags.flagCalc[flag] |
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302 calc,_,resultBit = calc.partition('-') |
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303 if prog.carryFlowDst: |
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304 lastDst = prog.carryFlowDst |
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305 else: |
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306 lastDst = prog.resolveParam(prog.lastDst, None, {}) |
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307 storage = prog.flags.getStorage(flag) |
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308 if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half' or calc == 'overflow': |
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309 myRes = lastDst |
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310 if calc == 'sign': |
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311 resultBit = prog.paramSize(prog.lastDst) - 1 |
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312 elif calc == 'carry': |
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313 resultBit = prog.paramSize(prog.lastDst) |
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314 elif calc == 'half': |
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315 resultBit = 4 |
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316 fmt = '({a} ^ {b} ^ ~{res})' if prog.lastWasSub else '({a} ^ {b} ^ {res})' |
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317 myRes = fmt.format(a = prog.lastA, b = prog.lastB, res = lastDst) |
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318 elif calc == 'overflow': |
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319 resultBit = prog.paramSize(prog.lastDst) - 1 |
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320 myRes = '((~({a} ^ {b})) & ({a} ^ {res}))'.format(a = prog.lastA, b = prog.lastB, res = lastDst) |
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321 else: |
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322 resultBit = int(resultBit) |
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323 if type(storage) is tuple: |
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324 reg,storageBit = storage |
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325 reg = prog.resolveParam(reg, None, {}) |
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326 if storageBit == resultBit: |
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327 #TODO: optimize this case |
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328 output.append('\n\t{reg} = ({reg} & ~{mask}U) | ({res} & {mask}U);'.format( |
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329 reg = reg, mask = 1 << resultBit, res = myRes |
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330 )) |
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331 else: |
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332 if resultBit > storageBit: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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333 op = '>>' |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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334 shift = resultBit - storageBit |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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335 else: |
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336 op = '<<' |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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337 shift = storageBit - resultBit |
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338 output.append('\n\t{reg} = ({reg} & ~{mask}U) | ({res} {op} {shift}U & {mask}U);'.format( |
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339 reg = reg, mask = 1 << storageBit, res = myRes, op = op, shift = shift |
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340 )) |
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341 else: |
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342 reg = prog.resolveParam(storage, None, {}) |
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343 output.append('\n\t{reg} = {res} & {mask}U;'.format(reg=reg, res=myRes, mask = 1 << resultBit)) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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344 elif calc == 'zero': |
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345 if type(storage) is tuple: |
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346 reg,storageBit = storage |
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347 reg = prog.resolveParam(reg, None, {}) |
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348 output.append('\n\t{reg} = {res} ? ({reg} & {mask}U) : ({reg} | {bit}U);'.format( |
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349 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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350 )) |
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351 else: |
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352 reg = prog.resolveParam(storage, None, {}) |
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353 output.append('\n\t{reg} = {res} == 0;'.format( |
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354 reg = reg, res = lastDst |
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355 )) |
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356 elif calc == 'parity': |
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357 pass |
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358 else: |
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359 raise Exception('Unknown flag calc type: ' + calc) |
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360 if prog.carryFlowDst: |
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361 output.append('\n\t{dst} = {tmpdst};'.format(dst = prog.resolveParam(prog.lastDst, None, {}), tmpdst = prog.carryFlowDst)) |
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362 prog.carryFlowDst = None |
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363 #TODO: combine explicit flags targeting the same storage location |
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364 for flag in explicit: |
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365 location = prog.flags.getStorage(flag) |
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366 if type(location) is tuple: |
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367 reg,bit = location |
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368 reg = prog.resolveReg(reg, None, {}) |
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369 value = str(1 << bit) |
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370 if explicit[flag]: |
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371 operator = '|=' |
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372 else: |
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373 operator = '&=' |
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374 value = '~' + value |
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375 output.append('\n\t{reg} {op} {val};'.format(reg=reg, op=operator, val=value)) |
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376 else: |
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377 reg = prog.resolveReg(location, None, {}) |
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378 output.append('\n\t{reg} = {val};'.format(reg=reg, val=explicit[flag])) |
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379 return ''.join(output) |
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380 |
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381 def _cmpCImpl(prog, params): |
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382 size = prog.paramSize(params[1]) |
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383 tmpvar = 'cmp_tmp{sz}__'.format(sz=size) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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384 typename = '' |
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385 scope = prog.getRootScope() |
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386 if not scope.resolveLocal(tmpvar): |
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387 scope.addLocal(tmpvar, size) |
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388 prog.lastDst = tmpvar |
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389 return '\n\t{var} = {b} - {a};'.format(var = tmpvar, a = params[0], b = params[1]) |
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390 |
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391 def _asrCImpl(prog, params, rawParams): |
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392 shiftSize = prog.paramSize(rawParams[0]) |
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393 mask = 1 << (shiftSize - 1) |
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394 return '\n\t{dst} = ({a} >> {b}) | ({a} & {mask});'.format(a = params[0], b = params[1], dst = params[2], mask = mask) |
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395 |
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396 def _sext(size, src): |
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397 if size == 16: |
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398 return src | 0xFF00 if src & 0x80 else src |
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399 else: |
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400 return src | 0xFFFF0000 if src & 0x8000 else src |
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401 |
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402 def _sextCImpl(prog, params, rawParms): |
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403 if params[0] == 16: |
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404 fmt = '\n\t{dst} = {src} & 0x80 ? {src} | 0xFF00 : {src};' |
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405 else: |
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406 fmt = '\n\t{dst} = {src} & 0x8000 ? {src} | 0xFFFF0000 : {src};' |
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407 return fmt.format(src=params[1], dst=params[2]) |
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408 |
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409 def _getCarryCheck(prog): |
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410 carryFlag = None |
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411 for flag in prog.flags.flagCalc: |
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412 if prog.flags.flagCalc[flag] == 'carry': |
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413 carryFlag = flag |
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414 if carryFlag is None: |
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415 raise Exception('adc requires a defined carry flag') |
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416 carryStorage = prog.flags.getStorage(carryFlag) |
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417 if type(carryStorage) is tuple: |
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418 reg,bit = carryStorage |
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419 reg = prog.resolveReg(reg, None, (), False) |
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420 return '({reg} & 1 << {bit})'.format(reg=reg, bit=bit) |
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|
421 else: |
1702
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422 return prog.resolveReg(carryStorage, None, (), False) |
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|
423 |
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|
424 def _adcCImpl(prog, params, rawParams): |
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|
425 |
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|
426 return '\n\t{dst} = {a} + {b} + ({check} ? 1 : 0);'.format(dst = params[2], |
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|
427 a = params[0], b = params[1], check=_getCarryCheck(prog) |
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|
428 ) |
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|
429 |
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|
430 def _sbcCImpl(prog, params, rawParams): |
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431 return '\n\t{dst} = {a} - {b} - ({check} ? 1 : 0);'.format(dst = params[2], |
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|
432 a = params[0], b = params[1], check=_getCarryCheck(prog) |
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|
433 ) |
1701
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|
434 |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
435 _opMap = { |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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diff
changeset
|
436 'mov': Op(lambda val: val).cUnaryOperator(''), |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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diff
changeset
|
437 'not': Op(lambda val: ~val).cUnaryOperator('~'), |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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diff
changeset
|
438 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'), |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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diff
changeset
|
439 'neg': Op(lambda val: -val).cUnaryOperator('-'), |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
440 'add': Op(lambda a, b: a + b).cBinaryOperator('+'), |
1701
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diff
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|
441 'adc': Op().addImplementation('c', 2, _adcCImpl), |
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442 'sub': Op(lambda a, b: b - a).cBinaryOperator('-'), |
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443 'sbc': Op().addImplementation('c', 2, _sbcCImpl), |
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444 'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'), |
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445 'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'), |
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446 'asr': Op(lambda a, b: a >> b).addImplementation('c', 2, _asrCImpl), |
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447 'and': Op(lambda a, b: a & b).cBinaryOperator('&'), |
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448 'or': Op(lambda a, b: a | b).cBinaryOperator('|'), |
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449 'xor': Op(lambda a, b: a ^ b).cBinaryOperator('^'), |
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450 'abs': Op(lambda val: abs(val)).addImplementation( |
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451 'c', 1, lambda prog, params: '\n\t{dst} = abs({src});'.format(dst=params[1], src=params[0]) |
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452 ), |
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453 'cmp': Op().addImplementation('c', None, _cmpCImpl), |
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Added new sext instruction for sign extension to CPU sdl
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454 'sext': Op(_sext).addImplementation('c', 2, _sextCImpl), |
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455 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format( |
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456 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]]) |
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457 )), |
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458 'cycles': Op().addImplementation('c', None, |
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459 lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format( |
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460 params[0] |
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461 ) |
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462 ), |
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463 'addsize': Op( |
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464 lambda a, b: b + (2 * a if a else 1) |
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465 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} + {sz} ? {sz} * 2 : 1;'.format( |
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466 dst = params[2], sz = params[0], val = params[1] |
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467 )), |
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468 'decsize': Op( |
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469 lambda a, b: b - (2 * a if a else 1) |
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470 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} - {sz} ? {sz} * 2 : 1;'.format( |
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471 dst = params[2], sz = params[0], val = params[1] |
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472 )), |
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473 'xchg': Op().addImplementation('c', (0,1), _xchgCImpl), |
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474 'dispatch': Op().addImplementation('c', None, _dispatchCImpl), |
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475 'update_flags': Op().addImplementation('c', None, _updateFlagsCImpl) |
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476 } |
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477 |
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478 #represents a simple DSL instruction |
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479 class NormalOp: |
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480 def __init__(self, parts): |
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481 self.op = parts[0] |
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482 self.params = parts[1:] |
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483 |
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484 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates): |
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485 procParams = [] |
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486 allParamsConst = flagUpdates is None |
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487 opDef = _opMap.get(self.op) |
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488 for param in self.params: |
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489 allowConst = (self.op in prog.subroutines or len(procParams) != len(self.params) - 1) and param in parent.regValues |
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490 isDst = (not opDef is None) and len(procParams) in opDef.outOp |
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491 param = prog.resolveParam(param, parent, fieldVals, allowConst, isDst) |
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492 |
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493 if (not type(param) is int) and len(procParams) != len(self.params) - 1: |
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494 allParamsConst = False |
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495 procParams.append(param) |
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496 |
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497 if self.op == 'meta': |
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498 param,_,index = self.params[1].partition('.') |
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499 if index: |
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500 index = (parent.resolveLocal(index) or index) |
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501 if index in fieldVals: |
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502 index = str(fieldVals[index]) |
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503 param = param + '.' + index |
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504 else: |
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505 param = parent.resolveLocal(param) or param |
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506 if param in fieldVals: |
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507 param = fieldVals[index] |
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508 prog.meta[self.params[0]] = param |
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509 elif self.op == 'dis': |
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510 #TODO: Disassembler |
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511 pass |
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512 elif not opDef is None: |
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513 if opDef.canEval() and allParamsConst: |
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514 #do constant folding |
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515 if opDef.numArgs() >= len(procParams): |
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516 raise Exception('Insufficient args for ' + self.op + ' (' + ', '.join(self.params) + ')') |
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517 dst = self.params[opDef.numArgs()] |
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518 result = opDef.evaluate(procParams[:opDef.numArgs()]) |
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519 while dst in prog.meta: |
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520 dst = prog.meta[dst] |
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521 maybeLocal = parent.resolveLocal(dst) |
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522 if maybeLocal: |
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523 dst = maybeLocal |
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524 parent.regValues[dst] = result |
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525 if prog.isReg(dst): |
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526 shortProc = (procParams[0], procParams[-1]) |
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527 shortParams = (self.params[0], self.params[-1]) |
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528 output.append(_opMap['mov'].generate(otype, prog, shortProc, shortParams, None)) |
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529 else: |
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530 output.append(opDef.generate(otype, prog, procParams, self.params, flagUpdates)) |
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531 elif self.op in prog.subroutines: |
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532 prog.subroutines[self.op].inline(prog, procParams, output, otype, parent) |
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533 else: |
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534 output.append('\n\t' + self.op + '(' + ', '.join([str(p) for p in procParams]) + ');') |
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535 prog.lastOp = self |
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536 |
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537 def __str__(self): |
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538 return '\n\t' + self.op + ' ' + ' '.join(self.params) |
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539 |
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540 #represents a DSL switch construct |
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541 class Switch(ChildBlock): |
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542 def __init__(self, parent, param): |
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543 self.op = 'switch' |
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544 self.parent = parent |
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545 self.param = param |
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546 self.cases = {} |
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547 self.regValues = None |
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548 self.current_locals = {} |
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549 self.case_locals = {} |
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550 self.current_case = None |
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551 self.default = None |
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552 self.default_locals = None |
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553 |
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554 def addOp(self, op): |
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555 if op.op == 'case': |
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556 val = int(op.params[0], 16) if op.params[0].startswith('0x') else int(op.params[0]) |
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557 self.cases[val] = self.current_case = [] |
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558 self.case_locals[val] = self.current_locals = {} |
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559 elif op.op == 'default': |
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560 self.default = self.current_case = [] |
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561 self.default_locals = self.current_locals = {} |
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562 elif self.current_case == None: |
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563 raise ion('Orphan instruction in switch') |
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564 elif op.op == 'local': |
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565 name = op.params[0] |
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566 size = op.params[1] |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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567 self.current_locals[name] = size |
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568 else: |
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569 self.current_case.append(op) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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570 |
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571 def resolveLocal(self, name): |
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572 if name in self.current_locals: |
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573 return name |
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574 return self.parent.resolveLocal(name) |
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575 |
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576 def addLocal(self, name, size): |
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577 self.current_locals[name] = size |
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578 |
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579 def localSize(self, name): |
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580 if name in self.current_locals: |
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581 return self.current_locals[name] |
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582 return self.parent.localSize(name) |
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583 |
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584 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates): |
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585 prog.pushScope(self) |
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586 param = prog.resolveParam(self.param, parent, fieldVals) |
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587 if type(param) is int: |
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588 self.regValues = self.parent.regValues |
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589 if param in self.cases: |
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590 self.current_locals = self.case_locals[param] |
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591 output.append('\n\t{') |
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592 for local in self.case_locals[param]: |
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593 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[param][local], local)) |
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594 self.processOps(prog, fieldVals, output, otype, self.cases[param]) |
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595 output.append('\n\t}') |
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596 elif self.default: |
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597 self.current_locals = self.default_locals |
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598 output.append('\n\t{') |
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599 for local in self.default_locals: |
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600 output.append('\n\tuint{0}_t {1};'.format(self.default[local], local)) |
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601 self.processOps(prog, fieldVals, output, otype, self.default) |
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602 output.append('\n\t}') |
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603 else: |
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604 output.append('\n\tswitch(' + param + ')') |
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605 output.append('\n\t{') |
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606 for case in self.cases: |
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607 self.current_locals = self.case_locals[case] |
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608 self.regValues = dict(self.parent.regValues) |
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609 output.append('\n\tcase {0}U: '.format(case) + '{') |
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610 for local in self.case_locals[case]: |
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611 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[case][local], local)) |
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612 self.processOps(prog, fieldVals, output, otype, self.cases[case]) |
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613 output.append('\n\tbreak;') |
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614 output.append('\n\t}') |
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615 if self.default: |
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616 self.current_locals = self.default_locals |
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617 self.regValues = dict(self.parent.regValues) |
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618 output.append('\n\tdefault: {') |
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619 for local in self.default_locals: |
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620 output.append('\n\tuint{0}_t {1};'.format(self.default_locals[local], local)) |
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621 self.processOps(prog, fieldVals, output, otype, self.default) |
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622 output.append('\n\t}') |
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623 prog.popScope() |
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624 |
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|
625 def __str__(self): |
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626 keys = self.cases.keys() |
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627 keys.sort() |
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628 lines = ['\n\tswitch'] |
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|
629 for case in keys: |
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630 lines.append('\n\tcase {0}'.format(case)) |
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631 lines.append(''.join([str(op) for op in self.cases[case]])) |
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632 lines.append('\n\tend') |
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633 return ''.join(lines) |
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634 |
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|
635 |
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|
636 def _geuCImpl(prog, parent, fieldVals, output): |
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|
637 if prog.lastOp.op == 'cmp': |
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|
638 output.pop() |
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639 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params] |
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640 return '\n\tif ({a} >= {b}) '.format(a=params[1], b = params[0]) + '{' |
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641 else: |
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|
642 raise ion(">=U not implemented in the general case yet") |
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|
643 |
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644 _ifCmpImpl = { |
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|
645 'c': { |
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|
646 '>=U': _geuCImpl |
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647 } |
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648 } |
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649 #represents a DSL conditional construct |
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|
650 class If(ChildBlock): |
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651 def __init__(self, parent, cond): |
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652 self.op = 'if' |
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653 self.parent = parent |
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654 self.cond = cond |
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655 self.body = [] |
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656 self.elseBody = [] |
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657 self.curBody = self.body |
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658 self.locals = {} |
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659 self.elseLocals = {} |
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660 self.curLocals = self.locals |
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661 self.regValues = None |
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662 |
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|
663 def addOp(self, op): |
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|
664 if op.op in ('case', 'arg'): |
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|
665 raise Exception(self.op + ' is not allows inside an if block') |
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|
666 if op.op == 'local': |
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667 name = op.params[0] |
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|
668 size = op.params[1] |
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|
669 self.locals[name] = size |
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670 elif op.op == 'else': |
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671 self.curLocals = self.elseLocals |
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672 self.curBody = self.elseBody |
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673 else: |
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|
674 self.curBody.append(op) |
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|
675 |
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676 def localSize(self, name): |
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677 return self.curLocals.get(name) |
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678 |
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679 def resolveLocal(self, name): |
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680 if name in self.locals: |
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681 return name |
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682 return self.parent.resolveLocal(name) |
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|
683 |
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|
684 def _genTrueBody(self, prog, fieldVals, output, otype): |
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685 self.curLocals = self.locals |
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|
686 for local in self.locals: |
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687 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.locals[local], nm=local)) |
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688 self.processOps(prog, fieldVals, output, otype, self.body) |
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|
689 |
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|
690 def _genFalseBody(self, prog, fieldVals, output, otype): |
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|
691 self.curLocals = self.elseLocals |
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|
692 for local in self.elseLocals: |
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|
693 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.elseLocals[local], nm=local)) |
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|
694 self.processOps(prog, fieldVals, output, otype, self.elsebody) |
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|
695 |
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|
696 def _genConstParam(self, param, prog, fieldVals, output, otype): |
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|
697 if param: |
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|
698 self._genTrueBody(prog, fieldVals, output, otype) |
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|
699 else: |
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|
700 self._genFalseBody(prog, fieldVals, output, otype) |
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|
701 |
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|
702 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates): |
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|
703 self.regValues = parent.regValues |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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diff
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|
704 try: |
1618
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Getting SVP core closer to compiling
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|
705 self._genConstParam(prog.checkBool(self.cond), prog, fieldVals, output, otype) |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
706 except Exception: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
707 if self.cond in _ifCmpImpl[otype]: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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diff
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|
708 output.append(_ifCmpImpl[otype][self.cond](prog, parent, fieldVals, output)) |
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diff
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|
709 self._genTrueBody(prog, fieldVals, output, otype) |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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changeset
|
710 if self.elseBody: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
711 output.append('\n\t} else {') |
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diff
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|
712 self._genFalseBody(prog, fieldVals, output, otype) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
713 output.append('\n\t}') |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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diff
changeset
|
714 else: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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diff
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|
715 cond = prog.resolveParam(self.cond, parent, fieldVals) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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|
716 if type(cond) is int: |
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|
717 self._genConstParam(cond, prog, fieldVals, output, otype) |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
718 else: |
1614
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Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result
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1613
diff
changeset
|
719 output.append('\n\tif ({cond}) '.format(cond=cond) + '{') |
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|
720 self._genTrueBody(prog, fieldVals, output, otype) |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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changeset
|
721 if self.elseBody: |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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diff
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|
722 output.append('\n\t} else {') |
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Getting SVP core closer to compiling
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1616
diff
changeset
|
723 self._genFalseBody(prog, fieldVals, output, otype) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
724 output.append('\n\t}') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
725 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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changeset
|
726 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
727 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
728 lines = ['\n\tif'] |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
729 for op in self.body: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
730 lines.append(str(op)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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diff
changeset
|
731 lines.append('\n\tend') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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diff
changeset
|
732 return ''.join(lines) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
733 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
changeset
|
734 class Registers: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
735 def __init__(self): |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
736 self.regs = {} |
1621
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|
737 self.pointers = {} |
1613
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|
738 self.regArrays = {} |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
739 self.regToArray = {} |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
740 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
741 def addReg(self, name, size): |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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changeset
|
742 self.regs[name] = size |
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|
743 |
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|
744 def addPointer(self, name, size): |
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|
745 self.pointers[name] = size |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
746 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
747 def addRegArray(self, name, size, regs): |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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parents:
diff
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|
748 self.regArrays[name] = (size, regs) |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
749 idx = 0 |
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1614
diff
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|
750 if not type(regs) is int: |
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|
751 for reg in regs: |
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752 self.regs[reg] = size |
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|
753 self.regToArray[reg] = (name, idx) |
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|
754 idx += 1 |
1613
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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changeset
|
755 |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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changeset
|
756 def isReg(self, name): |
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Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
757 return name in self.regs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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|
758 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
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diff
changeset
|
759 def isRegArray(self, name): |
2d9e8a7b8ba2
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|
760 return name in self.regArrays |
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Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
761 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
762 def isRegArrayMember(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
763 return name in self.regToArray |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
764 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
765 def arrayMemberParent(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
766 return self.regToArray[name][0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
767 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
768 def arrayMemberIndex(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
769 return self.regToArray[name][1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
770 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
771 def arrayMemberName(self, array, index): |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
772 if type(index) is int and not type(self.regArrays[array][1]) is int: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
773 return self.regArrays[array][1][index] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
774 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
775 return None |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
776 |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
777 def isNamedArray(self, array): |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
778 return array in self.regArrays and type(self.regArrays[array][1]) is int |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
779 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
780 def processLine(self, parts): |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
781 if len(parts) == 3: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
782 self.addRegArray(parts[0], int(parts[1]), int(parts[2])) |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
783 elif len(parts) > 2: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
784 self.addRegArray(parts[0], int(parts[1]), parts[2:]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
785 else: |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
786 if parts[1].startswith('ptr'): |
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
787 self.addPointer(parts[0], int(parts[1][3:])) |
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
788 else: |
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
789 self.addReg(parts[0], int(parts[1])) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
790 return self |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
791 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
792 def writeHeader(self, otype, hFile): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
793 fieldList = [] |
1621
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
794 for pointer in self.pointers: |
ca158bc091f9
Implement program ROM reads
Michael Pavone <pavone@retrodev.com>
parents:
1620
diff
changeset
|
795 hFile.write('\n\tuint{sz}_t *{nm};'.format(nm=pointer, sz=self.pointers[pointer])) |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
796 for reg in self.regs: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
797 if not self.isRegArrayMember(reg): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
798 fieldList.append((self.regs[reg], 1, reg)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
799 for arr in self.regArrays: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
800 size,regs = self.regArrays[arr] |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
801 if not type(regs) is int: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
802 regs = len(regs) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
803 fieldList.append((size, regs, arr)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
804 fieldList.sort() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
805 fieldList.reverse() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
806 for size, count, name in fieldList: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
807 if count > 1: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
808 hFile.write('\n\tuint{sz}_t {nm}[{ct}];'.format(sz=size, nm=name, ct=count)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
809 else: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
810 hFile.write('\n\tuint{sz}_t {nm};'.format(sz=size, nm=name)) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
811 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
812 class Flags: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
813 def __init__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
814 self.flagBits = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
815 self.flagCalc = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
816 self.flagStorage = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
817 self.flagReg = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
818 self.maxBit = -1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
819 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
820 def processLine(self, parts): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
821 if parts[0] == 'register': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
822 self.flagReg = parts[1] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
823 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
824 flag,bit,calc,storage = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
825 bit,_,top = bit.partition('-') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
826 bit = int(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
827 if top: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
828 top = int(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
829 if top > self.maxBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
830 self.maxBit = top |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
831 self.flagBits[flag] = (bit,top) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
832 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
833 if bit > self.maxBit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
834 self.maxBit = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
835 self.flagBits[flag] = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
836 self.flagCalc[flag] = calc |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
837 self.flagStorage[flag] = storage |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
838 return self |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
839 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
840 def getStorage(self, flag): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
841 if not flag in self.flagStorage: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
842 raise Exception('Undefined flag ' + flag) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
843 loc,_,bit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
844 if bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
845 return (loc, int(bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
846 else: |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
847 return loc |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
848 |
1704
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
849 def parseFlagUpdate(self, flagString): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
850 last = '' |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
851 autoUpdate = set() |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
852 explicit = {} |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
853 for c in flagString: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
854 if c.isdigit(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
855 if last.isalpha(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
856 num = int(c) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
857 if num > 1: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
858 raise Exception(c + ' is not a valid digit for update_flags') |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
859 explicit[last] = num |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
860 last = c |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
861 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
862 raise Exception('Digit must follow flag letter in update_flags') |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
863 else: |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
864 if last.isalpha(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
865 autoUpdate.add(last) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
866 last = c |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
867 if last.isalpha(): |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
868 autoUpdate.add(last) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
869 return (autoUpdate, explicit) |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
870 |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
871 def disperseFlags(self, prog, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
872 bitToFlag = [None] * (self.maxBit+1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
873 src = prog.resolveReg(self.flagReg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 output = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 for flag in self.flagBits: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
876 bit = self.flagBits[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
877 if type(bit) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 bot,top = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 mask = ((1 << (top + 1 - bot)) - 1) << bot |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 output.append('\n\t{dst} = {src} & mask;'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 dst=prog.resolveReg(self.flagStorage[flag], None, {}), src=src, mask=mask |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
882 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
883 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
884 bitToFlag[self.flagBits[flag]] = flag |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
885 multi = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
886 for bit in range(len(bitToFlag)-1,-1,-1): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 flag = bitToFlag[bit] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
888 if not flag is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
889 field,_,dstbit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 dst = prog.resolveReg(field, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 if dstbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 dstbit = int(dstbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 multi.setdefault(dst, []).append((dstbit, bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=(1 << bit))) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 for dst in multi: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 didClear = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 direct = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 for dstbit, bit in multi[dst]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 if dstbit == bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 direct.append(bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
903 if not didClear: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
904 output.append('\n\t{dst} = 0;'.format(dst=dst)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
905 didClear = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 if dstbit > bit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 shift = '<<' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 diff = dstbit - bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 shift = '>>' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 diff = bit - dstbit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
912 output.append('\n\t{dst} |= {src} {shift} {diff} & {mask};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
913 src=src, dst=dst, shift=shift, diff=diff, mask=(1 << dstbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
914 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 if direct: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 if len(direct) == len(multi[dst]): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
917 output.append('\n\t{dst} = {src};'.format(dst=dst, src=src)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
918 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
919 mask = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
920 for bit in direct: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
921 mask = mask | (1 << bit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
922 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=mask)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
923 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
925 def coalesceFlags(self, prog, otype): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
926 dst = prog.resolveReg(self.flagReg, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
927 output = ['\n\t{dst} = 0;'.format(dst=dst)] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
928 bitToFlag = [None] * (self.maxBit+1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
929 for flag in self.flagBits: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
930 bit = self.flagBits[flag] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
931 if type(bit) is tuple: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
932 bot,_ = bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
933 src = prog.resolveReg(self.flagStorage[flag], None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
934 if bot: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
935 output.append('\n\t{dst} |= {src} << {shift};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
936 dst=dst, src = src, shift = bot |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
937 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
938 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
939 output.append('\n\t{dst} |= {src};'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
940 dst=dst, src = src |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
941 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
942 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
943 bitToFlag[bit] = flag |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
944 multi = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
945 for bit in range(len(bitToFlag)-1,-1,-1): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
946 flag = bitToFlag[bit] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
947 if not flag is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
948 field,_,srcbit = self.flagStorage[flag].partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
949 src = prog.resolveReg(field, None, {}) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
950 if srcbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 srcbit = int(srcbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
952 multi.setdefault(src, []).append((srcbit,bit)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
953 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
954 output.append('\n\tif ({src}) {{\n\t\t{dst} |= 1 << {bit};\n\t}}'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
955 dst=dst, src=src, bit=bit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
956 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 for src in multi: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
958 direct = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
959 for srcbit, dstbit in multi[src]: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
960 if srcbit == dstbit: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
961 direct = direct | (1 << srcbit) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
962 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
963 output.append('\n\tif ({src} & (1 << {srcbit})) {{\n\t\t{dst} |= 1 << {dstbit};\n\t}}'.format( |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
964 src=src, dst=dst, srcbit=srcbit, dstbit=dstbit |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
965 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
966 if direct: |
1698
90272218469c
Fixed missing semicolon in coalesceFlags
Michael Pavone <pavone@retrodev.com>
parents:
1697
diff
changeset
|
967 output.append('\n\t{dst} |= {src} & {mask};'.format( |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
968 dst=dst, src=src, mask=direct |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
969 )) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
970 return ''.join(output) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
971 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
972 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
973 class Program: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
974 def __init__(self, regs, instructions, subs, info, flags): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
975 self.regs = regs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
976 self.instructions = instructions |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
977 self.subroutines = subs |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
978 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
979 self.booleans = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
980 self.prefix = info.get('prefix', [''])[0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
981 self.opsize = int(info.get('opcode_size', ['8'])[0]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
982 self.extra_tables = info.get('extra_tables', []) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
983 self.context_type = self.prefix + 'context' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
984 self.body = info.get('body', [None])[0] |
1620
a172f97d873f
Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16
Michael Pavone <pavone@retrodev.com>
parents:
1619
diff
changeset
|
985 self.includes = info.get('include', []) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
986 self.flags = flags |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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changeset
|
987 self.lastDst = None |
1618
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Getting SVP core closer to compiling
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1616
diff
changeset
|
988 self.scopes = [] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
989 self.currentScope = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
990 self.lastOp = None |
1704
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First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
991 self.carryFlowDst = None |
89932fd29abd
First stab at carry and half-carry calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1703
diff
changeset
|
992 self.lastA = None |
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First stab at carry and half-carry calculation in CPU DSL
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parents:
1703
diff
changeset
|
993 self.lastB = None |
1707
a16088324f30
Less broken flag calulcation for sub instructions in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1705
diff
changeset
|
994 self.lastWasSub = False |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
995 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
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changeset
|
996 def __str__(self): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
997 pieces = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
998 for reg in self.regs: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
999 pieces.append(str(self.regs[reg])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1000 for name in self.subroutines: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1001 pieces.append('\n'+str(self.subroutines[name])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1002 for instruction in self.instructions: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1003 pieces.append('\n'+str(instruction)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1004 return ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 |
1618
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Getting SVP core closer to compiling
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parents:
1616
diff
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|
1006 def writeHeader(self, otype, header): |
5dbc453cd345
Getting SVP core closer to compiling
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parents:
1616
diff
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|
1007 hFile = open(header, 'w') |
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Getting SVP core closer to compiling
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diff
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|
1008 macro = header.upper().replace('.', '_') |
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Getting SVP core closer to compiling
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1616
diff
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|
1009 hFile.write('#ifndef {0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
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parents:
1616
diff
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|
1010 hFile.write('\n#define {0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
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|
1011 hFile.write('\n#include "backend.h"') |
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Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
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|
1012 hFile.write('\n\ntypedef struct {') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
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|
1013 hFile.write('\n\tcpu_options gen;') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1014 hFile.write('\n}} {0}options;'.format(self.prefix)) |
5dbc453cd345
Getting SVP core closer to compiling
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parents:
1616
diff
changeset
|
1015 hFile.write('\n\ntypedef struct {') |
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Getting SVP core closer to compiling
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1616
diff
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|
1016 hFile.write('\n\t{0}options *opts;'.format(self.prefix)) |
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Getting SVP core closer to compiling
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parents:
1616
diff
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|
1017 hFile.write('\n\tuint32_t cycles;') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1018 self.regs.writeHeader(otype, hFile) |
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Getting SVP core closer to compiling
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parents:
1616
diff
changeset
|
1019 hFile.write('\n}} {0}context;'.format(self.prefix)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1020 hFile.write('\n') |
1703
49a52c737bf0
Fix zero flag calculation in CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
1702
diff
changeset
|
1021 hFile.write('\nvoid {pre}execute({type} *context, uint32_t target_cycle);'.format(pre = self.prefix, type = self.context_type)) |
1618
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Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1022 hFile.write('\n#endif //{0}_'.format(macro)) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1023 hFile.write('\n') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1024 hFile.close() |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1025 |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1026 def _buildTable(self, otype, table, body): |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1027 pieces = [] |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1028 opmap = [None] * (1 << self.opsize) |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1029 bodymap = {} |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1030 if table in self.instructions: |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1031 instructions = self.instructions[table] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1032 instructions.sort() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1033 for inst in instructions: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1034 for val in inst.allValues(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1035 if opmap[val] is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1036 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1037 self.temp = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1038 self.needFlagCoalesce = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1039 self.needFlagDisperse = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1040 self.lastOp = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1041 opmap[val] = inst.generateName(val) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1042 bodymap[val] = inst.generateBody(val, self, otype) |
1700
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1043 |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1044 pieces.append('\ntypedef void (*impl_fun)({pre}context *context);'.format(pre=self.prefix)) |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1045 pieces.append('\nstatic impl_fun impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap))) |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1046 for inst in range(0, len(opmap)): |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1047 op = opmap[inst] |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1048 if op is None: |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1049 pieces.append('\n\tunimplemented,') |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1050 else: |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1051 pieces.append('\n\t' + op + ',') |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1052 body.append(bodymap[inst]) |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1053 pieces.append('\n};') |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1054 body.extend(pieces) |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1055 |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1056 def build(self, otype): |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1057 body = [] |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1058 pieces = [] |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1059 for include in self.includes: |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1060 body.append('#include "{0}"\n'.format(include)) |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1061 body.append('\nstatic void unimplemented({pre}context *context)'.format(pre = self.prefix)) |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1062 body.append('\n{') |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1063 body.append('\n\tfatal_error("Unimplemented instruction");') |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1064 body.append('\n}\n') |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1065 for table in self.extra_tables: |
e4b4e21a37fa
Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1066 self._buildTable(otype, table, body) |
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Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables
Michael Pavone <pavone@retrodev.com>
parents:
1699
diff
changeset
|
1067 self._buildTable(otype, 'main', body) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
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diff
changeset
|
1068 if self.body in self.subroutines: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1069 pieces.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1070 pieces.append('\n{') |
1618
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Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1071 pieces.append('\n\twhile (context->cycles < target_cycle)') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1072 pieces.append('\n\t{') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1073 self.meta = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1074 self.temp = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1075 self.subroutines[self.body].inline(self, [], pieces, otype, None) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1076 pieces.append('\n\t}') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1077 pieces.append('\n}') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1078 return ''.join(body) + ''.join(pieces) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1079 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1080 def checkBool(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1081 if not name in self.booleans: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1082 raise Exception(name + ' is not a defined boolean flag') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1083 return self.booleans[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1084 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1085 def getTemp(self, size): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1086 if size in self.temp: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1087 return ('', self.temp[size]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1088 self.temp[size] = 'tmp{sz}'.format(sz=size); |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1089 return ('\n\tuint{sz}_t tmp{sz};'.format(sz=size), self.temp[size]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1090 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1091 def resolveParam(self, param, parent, fieldVals, allowConstant=True, isdst=False): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1092 keepGoing = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1093 while keepGoing: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1094 keepGoing = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1095 try: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1096 if type(param) is int: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1097 pass |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1098 elif param.startswith('0x'): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1099 param = int(param, 16) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1100 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1101 param = int(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1102 except ValueError: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1103 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1104 if parent: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1105 if param in parent.regValues and allowConstant: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1106 return parent.regValues[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1107 maybeLocal = parent.resolveLocal(param) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1108 if maybeLocal: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1109 return maybeLocal |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1110 if param in fieldVals: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1111 param = fieldVals[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1112 elif param in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1113 param = self.meta[param] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1114 keepGoing = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1115 elif self.isReg(param): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1116 param = self.resolveReg(param, parent, fieldVals, isdst) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1117 return param |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1118 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1119 def isReg(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1120 if not type(name) is str: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1121 return False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1122 begin,sep,_ = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1123 if sep: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1124 if begin in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1125 begin = self.meta[begin] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1126 return self.regs.isRegArray(begin) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
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|
1127 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1128 return self.regs.isReg(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1129 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1130 def resolveReg(self, name, parent, fieldVals, isDst=False): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1131 begin,sep,end = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1132 if sep: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1133 if begin in self.meta: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1134 begin = self.meta[begin] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1135 if not self.regs.isRegArrayMember(end): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1136 end = self.resolveParam(end, parent, fieldVals) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1137 if not type(end) is int and self.regs.isRegArrayMember(end): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1138 arrayName = self.regs.arrayMemberParent(end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1139 end = self.regs.arrayMemberIndex(end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1140 if arrayName != begin: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1141 end = 'context->{0}[{1}]'.format(arrayName, end) |
1615
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1142 if self.regs.isNamedArray(begin): |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1143 regName = self.regs.arrayMemberName(begin, end) |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1144 else: |
28f80d1b343e
Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes
Michael Pavone <pavone@retrodev.com>
parents:
1614
diff
changeset
|
1145 regName = '{0}.{1}'.format(begin, end) |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1146 ret = 'context->{0}[{1}]'.format(begin, end) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1147 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1148 regName = name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1149 if self.regs.isRegArrayMember(name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1150 arr,idx = self.regs.regToArray[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1151 ret = 'context->{0}[{1}]'.format(arr, idx) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1152 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1153 ret = 'context->' + name |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1154 if regName == self.flags.flagReg: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1155 if isDst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1156 self.needFlagDisperse = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1157 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1158 self.needFlagCoalesce = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1159 if isDst: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1160 self.lastDst = regName |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1161 return ret |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1162 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1163 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1164 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1165 def paramSize(self, name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1166 size = self.currentScope.localSize(name) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1167 if size: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1168 return size |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1169 begin,sep,_ = name.partition('.') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1170 if sep and self.regs.isRegArray(begin): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1171 return self.regs.regArrays[begin][0] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1172 if self.regs.isReg(name): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1173 return self.regs.regs[name] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1174 return 32 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1175 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1176 def pushScope(self, scope): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1177 self.scopes.append(scope) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1178 self.currentScope = scope |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1179 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1180 def popScope(self): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1181 ret = self.scopes.pop() |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1182 self.currentScope = self.scopes[-1] if self.scopes else None |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1183 return ret |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1184 |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1185 def getRootScope(self): |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1186 return self.scopes[0] |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1187 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1188 def parse(f): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1189 instructions = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1190 subroutines = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1191 registers = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1192 flags = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1193 errors = [] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1194 info = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1195 line_num = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1196 cur_object = None |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1197 for line in f: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1198 line_num += 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1199 line,_,comment = line.partition('#') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1200 if not line.strip(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1201 continue |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1202 if line[0].isspace(): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1203 if not cur_object is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1204 parts = [el.strip() for el in line.split(' ')] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1205 if type(cur_object) is dict: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1206 cur_object[parts[0]] = parts[1:] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1207 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1208 cur_object = cur_object.processLine(parts) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1209 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1210 # if type(cur_object) is Registers: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1211 # if len(parts) > 2: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1212 # cur_object.addRegArray(parts[0], int(parts[1]), parts[2:]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1213 # else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1214 # cur_object.addReg(parts[0], int(parts[1])) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1215 # elif type(cur_object) is dict: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1216 # cur_object[parts[0]] = parts[1:] |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1217 # elif parts[0] == 'switch': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1218 # o = Switch(cur_object, parts[1]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1219 # cur_object.addOp(o) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1220 # cur_object = o |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1221 # elif parts[0] == 'if': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1222 # o = If(cur_object, parts[1]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1223 # cur_object.addOp(o) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1224 # cur_object = o |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1225 # elif parts[0] == 'end': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1226 # cur_object = cur_object.parent |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1227 # else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1228 # cur_object.addOp(NormalOp(parts)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1229 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1230 errors.append("Orphan instruction on line {0}".format(line_num)) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1231 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1232 parts = line.split(' ') |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1233 if len(parts) > 1: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1234 if len(parts) > 2: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1235 table,bitpattern,name = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1236 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1237 bitpattern,name = parts |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1238 table = 'main' |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1239 value = 0 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1240 fields = {} |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1241 curbit = len(bitpattern) - 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1242 for char in bitpattern: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1243 value <<= 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1244 if char in ('0', '1'): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1245 value |= int(char) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1246 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1247 if char in fields: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1248 fields[char] = (curbit, fields[char][1] + 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1249 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1250 fields[char] = (curbit, 1) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1251 curbit -= 1 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1252 cur_object = Instruction(value, fields, name.strip()) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1253 instructions.setdefault(table, []).append(cur_object) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1254 elif line.strip() == 'regs': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1255 if registers is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1256 registers = Registers() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1257 cur_object = registers |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1258 elif line.strip() == 'info': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1259 cur_object = info |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1260 elif line.strip() == 'flags': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1261 if flags is None: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1262 flags = Flags() |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1263 cur_object = flags |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1264 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1265 cur_object = SubRoutine(line.strip()) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1266 subroutines[cur_object.name] = cur_object |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1267 if errors: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1268 print(errors) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1269 else: |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1270 p = Program(registers, instructions, subroutines, info, flags) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1271 p.booleans['dynarec'] = False |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1272 p.booleans['interp'] = True |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1273 |
1618
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1274 if 'header' in info: |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1275 print('#include "{0}"'.format(info['header'][0])) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1276 p.writeHeader('c', info['header'][0]) |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1277 print('#include "util.h"') |
5dbc453cd345
Getting SVP core closer to compiling
Michael Pavone <pavone@retrodev.com>
parents:
1616
diff
changeset
|
1278 print('#include <stdlib.h>') |
1613
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1279 print(p.build('c')) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1280 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1281 def main(argv): |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1282 f = open(argv[1]) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1283 parse(f) |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1284 |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1285 if __name__ == '__main__': |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1286 from sys import argv |
2d9e8a7b8ba2
Initial commit of CPU DSL and a WIP SVP implementation written in that DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1287 main(argv) |