repos/blastem: m68k_to_x86.c annotate

annotate m68k_to_x86.c @ 124:da95566514f3

Some fixes for translating code in located in RAM

author	Mike Pavone <pavone@retrodev.com>
date	Sat, 29 Dec 2012 21:55:42 -0800
parents	bd3858121ab0
children	dc5fc3adf705

rev	line source
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1 #include "gen_x86.h"
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2 #include "m68k_to_x86.h"
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3 #include "mem.h"
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4 #include <stdio.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	5 #include <stddef.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	6 #include <stdlib.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	7 #include <string.h>
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	8
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	9 #define BUS 4
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	10 #define PREDEC_PENALTY 2
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	11 #define CYCLES RAX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	12 #define LIMIT RBP
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	13 #define SCRATCH1 RCX
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	14 #define SCRATCH2 RDI
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 #define CONTEXT RSI
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	16
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 #define FLAG_N RBX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	18 #define FLAG_V BH
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 #define FLAG_Z RDX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 #define FLAG_C DH
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	21
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 typedef struct {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	23 int32_t disp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	24 uint8_t mode;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 uint8_t base;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	26 uint8_t index;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	27 uint8_t cycles;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	28 } x86_ea;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	29
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	30 void handle_cycle_limit_int();
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	31 void m68k_read_word_scratch1();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	32 void m68k_read_long_scratch1();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	33 void m68k_read_byte_scratch1();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	34 void m68k_write_word();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	35 void m68k_write_long_lowfirst();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	36 void m68k_write_long_highfirst();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	37 void m68k_write_byte();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	38 void m68k_save_context();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	39 void m68k_modified_ret_addr();
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	40 void m68k_native_addr();
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	41 void m68k_native_addr_and_sync();
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	42 void set_sr();
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	43 void set_ccr();
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	44 void get_sr();
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	45 void m68k_start_context(uint8_t * addr, m68k_context * context);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	46
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	47 uint8_t * cycles(uint8_t * dst, uint32_t num)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	48 {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	49 dst = add_ir(dst, num, CYCLES, SZ_D);
118 d9ff99ef5533 cycles should return dst Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	50 return dst;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	52
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	53 uint8_t * check_cycles_int(uint8_t * dst, uint32_t address)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	54 {
87 60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	55 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	56 uint8_t * jmp_off = dst+1;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	57 dst = jcc(dst, CC_NC, dst + 7);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	58 dst = mov_ir(dst, address, SCRATCH1, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	59 dst = call(dst, (uint8_t *)handle_cycle_limit_int);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	60 *jmp_off = dst - (jmp_off+1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	61 return dst;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	62 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	63
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	64 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	65 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	66 if (op->addr_mode == MODE_REG) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	67 return opts->dregs[op->params.regs.pri];
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	68 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	69 if (op->addr_mode == MODE_AREG) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	70 return opts->aregs[op->params.regs.pri];
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	71 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	72 return -1;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	73 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	74
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	75 //must be called with an m68k_op_info that uses a register
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	76 size_t reg_offset(m68k_op_info *op)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	77 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	78 if (op->addr_mode == MODE_REG) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	79 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	80 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	81 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	82 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	83
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	84 void print_regs_exit(m68k_context * context)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	85 {
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	86 printf("XNVZC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	87 for (int i = 0; i < 8; i++) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	88 printf("d%d: %X\n", i, context->dregs[i]);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	89 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	90 for (int i = 0; i < 8; i++) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	91 printf("a%d: %X\n", i, context->aregs[i]);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	92 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	93 exit(0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	94 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	95
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	96 uint8_t * translate_m68k_src(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	97 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	98 int8_t reg = native_reg(&(inst->src), opts);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	99 uint8_t sec_reg;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	100 int32_t dec_amount,inc_amount;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	101 if (reg >= 0) {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	102 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	103 ea->base = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	104 return out;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	105 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	106 switch (inst->src.addr_mode)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	107 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	108 case MODE_REG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	109 case MODE_AREG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	110 //We only get one memory parameter, so if the dst operand is a register in memory,
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	111 //we need to copy this to a temp register first
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	112 reg = native_reg(&(inst->dst), opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	113 if (reg >= 0 \|\| inst->dst.addr_mode == MODE_UNUSED \|\| (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode == MODE_AREG)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	114 \|\| inst->op == M68K_EXG) {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	115
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	116 ea->mode = MODE_REG_DISPLACE8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	117 ea->base = CONTEXT;
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	118 ea->disp = reg_offset(&(inst->src));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	119 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	120 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	121 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	122 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	123 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	124 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	125 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	126 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	127 out = cycles(out, PREDEC_PENALTY);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	128 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	129 out = sub_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	130 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	131 out = sub_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	132 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	133 case MODE_AREG_INDIRECT:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	134 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	135 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	136 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	137 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	138 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	139 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	140 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	141 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	142 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	143 out = call(out, (char *)m68k_read_byte_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	144 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	145 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	146 out = call(out, (char *)m68k_read_word_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	147 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	148 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	149 out = call(out, (char *)m68k_read_long_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	150 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	151 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	152
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	153 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	154 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	155 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	156 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	157 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	158 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	159 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	160 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	161 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	162 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	163 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	164 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	165 out = cycles(out, BUS);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	166 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	167 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	168 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	169 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	170 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	171 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	172 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	173 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	174 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	175 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	176 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	177 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	178 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	179 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	180 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	181 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	182 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	183 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	184 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	185 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	186 break;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	187 case MODE_AREG_INDEX_DISP8:
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	188 out = cycles(out, 6);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	189 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	190 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	191 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	192 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	193 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	194 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	195 if (inst->src.params.regs.sec & 1) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	196 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	197 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	198 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	199 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	200 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	201 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	202 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	203 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	204 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	205 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	206 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	207 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	208 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	209 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	210 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	211 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	212 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	213 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	214 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	215 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	216 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	217 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	218 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	219 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	220 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	221 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	222 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	223 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	224 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	225 if (inst->src.params.regs.displacement) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	226 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	227 }
97 c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	228 switch (inst->extra.size)
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	229 {
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	230 case OPSIZE_BYTE:
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	231 out = call(out, (char *)m68k_read_byte_scratch1);
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	232 break;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	233 case OPSIZE_WORD:
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	234 out = call(out, (char *)m68k_read_word_scratch1);
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	235 break;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	236 case OPSIZE_LONG:
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	237 out = call(out, (char *)m68k_read_long_scratch1);
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	238 break;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	239 }
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	240 ea->mode = MODE_REG_DIRECT;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	241 ea->base = SCRATCH1;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	242 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	243 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	244 out = cycles(out, BUS);
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	245 out = mov_ir(out, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	246 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	247 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	248 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	249 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	250 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	251 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	252 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	253 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	254 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	255 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	256 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	257 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	258 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	259 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	260 break;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	261 case MODE_PC_INDEX_DISP8:
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	262 out = cycles(out, 6);
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	263 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	264 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	265 if (inst->src.params.regs.sec & 1) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	266 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	267 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	268 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	269 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	270 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	271 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	272 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	273 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	274 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	275 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	276 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	277 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	278 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	279 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	280 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	281 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	282 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	283 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	284 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	285 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	286 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	287 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	288 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	289 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	290 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	291 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	292 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	293 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	294 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	295 if (inst->src.params.regs.displacement) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	296 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	297 }
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	298 switch (inst->extra.size)
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	299 {
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	300 case OPSIZE_BYTE:
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	301 out = call(out, (char *)m68k_read_byte_scratch1);
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	302 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	303 case OPSIZE_WORD:
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	304 out = call(out, (char *)m68k_read_word_scratch1);
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	305 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	306 case OPSIZE_LONG:
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	307 out = call(out, (char *)m68k_read_long_scratch1);
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	308 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	309 }
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	310 ea->mode = MODE_REG_DIRECT;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	311 ea->base = SCRATCH1;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	312 break;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	313 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	314 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	315 if (inst->src.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	316 out = cycles(out, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	317 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	318 out = cycles(out, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	319 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	320 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	321 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	322 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	323 case OPSIZE_BYTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	324 out = call(out, (char *)m68k_read_byte_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	325 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	326 case OPSIZE_WORD:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	327 out = call(out, (char *)m68k_read_word_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	328 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	329 case OPSIZE_LONG:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	330 out = call(out, (char *)m68k_read_long_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	331 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	332 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	333 ea->mode = MODE_REG_DIRECT;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	334 ea->base = SCRATCH1;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	335 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	336 case MODE_IMMEDIATE:
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	337 case MODE_IMMEDIATE_WORD:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	338 if (inst->variant != VAR_QUICK) {
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	339 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	340 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	341 ea->mode = MODE_IMMED;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	342 ea->disp = inst->src.params.immed;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	343 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	344 default:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	345 printf("address mode %d not implemented (src)\n", inst->src.addr_mode);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	346 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	347 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	348 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	349 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	350
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	351 uint8_t * translate_m68k_dst(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts, uint8_t fake_read)
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	352 {
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	353 int8_t reg = native_reg(&(inst->dst), opts), sec_reg;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	354 int32_t dec_amount, inc_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	355 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	356 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	357 ea->base = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	358 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	359 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	360 switch (inst->dst.addr_mode)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	361 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	362 case MODE_REG:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	363 case MODE_AREG:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	364 ea->mode = MODE_REG_DISPLACE8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	365 ea->base = CONTEXT;
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	366 ea->disp = reg_offset(&(inst->dst));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	367 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	368 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	369 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	370 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	371 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	372 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	373 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	374 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	375 case MODE_AREG_INDIRECT:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	376 case MODE_AREG_POSTINC:
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	377 if (fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	378 out = cycles(out, inst->extra.size == OPSIZE_LONG ? 8 : 4);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	379 } else {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	380 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	381 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	382 } else {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	383 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	384 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	385 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	386 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	387 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	388 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	389 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	390 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	391 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	392 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	393 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	394 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	395 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	396 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	397 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	398 //save reg value in SCRATCH2 so we can use it to save the result in memory later
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	399 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	400 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	401 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	402 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	403 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	404
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	405 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	406 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	407 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	408 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	409 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	410 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	411 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	412 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	413 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	414 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	415 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	416 case MODE_AREG_DISPLACE:
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	417 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	418 reg = fake_read ? SCRATCH2 : SCRATCH1;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	419 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	420 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], reg, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	421 } else {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	422 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), reg, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	423 }
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	424 out = add_ir(out, inst->dst.params.regs.displacement, reg, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	425 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	426 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	427 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	428 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	429 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	430 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	431 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	432 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	433 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	434 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	435 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	436 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	437 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	438 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	439 out = pop_r(out, SCRATCH2);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	440 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	441 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	442 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	443 break;
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	444 case MODE_AREG_INDEX_DISP8:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	445 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	446 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	447 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	448 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	449 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	450 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	451 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	452 if (inst->dst.params.regs.sec & 1) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	453 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	454 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	455 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	456 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	457 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	458 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	459 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	460 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	461 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	462 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	463 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	464 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	465 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	466 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	467 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	468 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	469 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	470 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	471 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	472 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	473 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	474 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	475 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	476 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	477 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	478 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	479 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	480 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	481 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	482 if (inst->dst.params.regs.displacement) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	483 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	484 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	485 if (fake_read) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	486 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	487 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	488 out = push_r(out, SCRATCH1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	489 switch (inst->extra.size)
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	490 {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	491 case OPSIZE_BYTE:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	492 out = call(out, (char *)m68k_read_byte_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	493 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	494 case OPSIZE_WORD:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	495 out = call(out, (char *)m68k_read_word_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	496 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	497 case OPSIZE_LONG:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	498 out = call(out, (char *)m68k_read_long_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	499 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	500 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	501 out = pop_r(out, SCRATCH2);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	502 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	503 ea->mode = MODE_REG_DIRECT;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	504 ea->base = SCRATCH1;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	505 case MODE_PC_DISPLACE:
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	506 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	507 out = mov_ir(out, inst->dst.params.regs.displacement + inst->address+2, fake_read ? SCRATCH2 : SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	508 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	509 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	510 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	511 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	512 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	513 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	514 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	515 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	516 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	517 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	518 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	519 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	520 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	521 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	522 out = pop_r(out, SCRATCH2);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	523 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	524 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	525 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	526 break;
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	527 case MODE_PC_INDEX_DISP8:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	528 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	529 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	530 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	531 if (inst->dst.params.regs.sec & 1) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	532 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	533 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	534 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	535 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	536 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	537 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	538 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	539 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	540 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	541 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	542 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	543 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	544 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	545 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	546 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	547 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	548 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	549 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	550 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	551 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	552 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	553 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	554 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	555 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	556 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	557 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	558 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	559 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	560 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	561 if (inst->dst.params.regs.displacement) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	562 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	563 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	564 if (fake_read) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	565 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	566 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	567 out = push_r(out, SCRATCH1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	568 switch (inst->extra.size)
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	569 {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	570 case OPSIZE_BYTE:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	571 out = call(out, (char *)m68k_read_byte_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	572 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	573 case OPSIZE_WORD:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	574 out = call(out, (char *)m68k_read_word_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	575 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	576 case OPSIZE_LONG:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	577 out = call(out, (char *)m68k_read_long_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	578 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	579 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	580 out = pop_r(out, SCRATCH2);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	581 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	582 ea->mode = MODE_REG_DIRECT;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	583 ea->base = SCRATCH1;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	584 break;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	585 case MODE_ABSOLUTE:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	586 case MODE_ABSOLUTE_SHORT:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	587 //Add cycles for reading address from instruction stream
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	588 out = cycles(out, (inst->dst.addr_mode == MODE_ABSOLUTE ? BUS2 : BUS) + (fake_read ? (inst->extra.size == OPSIZE_LONG ? BUS2 : BUS) : 0));
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	589 out = mov_ir(out, inst->dst.params.immed, fake_read ? SCRATCH2 : SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	590 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	591 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	592 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	593 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	594 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	595 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	596 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	597 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	598 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	599 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	600 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	601 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	602 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	603 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	604 out = pop_r(out, SCRATCH2);
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	605 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	606 ea->mode = MODE_REG_DIRECT;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	607 ea->base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	608 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	609 default:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	610 printf("address mode %d not implemented (dst)\n", inst->dst.addr_mode);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	611 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	612 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	613 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	614 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	615
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	616 uint8_t * m68k_save_result(m68kinst * inst, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	617 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	618 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	619 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	620 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	621 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	622 out = call(out, (char *)m68k_write_byte);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	623 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	624 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	625 out = call(out, (char *)m68k_write_word);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	626 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	627 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	628 out = call(out, (char *)m68k_write_long_lowfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	629 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	630 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	631 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	632 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	633 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	634
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	635 uint8_t * get_native_address(native_map_slot * native_code_map, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	636 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	637 address &= 0xFFFFFF;
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	638 if (address > 0x400000) {
86 3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	639 printf("get_native_address: %X\n", address);
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	640 }
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	641 address /= 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	642 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	643 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	644 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	645 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	646 uint32_t offset = address % NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	647 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	648 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	649 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	650 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset];
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	651 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	652
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	653 deferred_addr * defer_address(deferred_addr * old_head, uint32_t address, uint8_t *dest)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	654 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	655 deferred_addr * new_head = malloc(sizeof(deferred_addr));
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	656 new_head->next = old_head;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	657 new_head->address = address & 0xFFFFFF;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	658 new_head->dest = dest;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	659 return new_head;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	660 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	661
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	662 void process_deferred(x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	663 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	664 deferred_addr * cur = opts->deferred;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	665 deferred_addr **last_next = &(opts->deferred);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	666 while(cur)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	667 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	668 uint8_t * native = get_native_address(opts->native_code_map, cur->address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	669 if (native) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	670 int32_t disp = native - (cur->dest + 4);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	671 uint8_t * out = cur->dest;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	672 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	673 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	674 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	675 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	676 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	677 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	678 *out = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	679 *last_next = cur->next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	680 free(cur);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	681 cur = *last_next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	682 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	683 last_next = &(cur->next);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	684 cur = cur->next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	685 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	686 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	687 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	688
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	689 void map_native_address(native_map_slot * native_code_map, uint32_t address, uint8_t * native_addr)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	690 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	691 address &= 0xFFFFFF;
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	692 address/= 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	693 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	694 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	695 native_code_map[chunk].base = native_addr;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	696 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	697 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	698 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	699 uint32_t offset = address % NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	700 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	701 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	702
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	703 uint8_t * translate_m68k_move(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	704 {
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	705 int8_t reg, flags_reg, sec_reg;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	706 uint8_t dir = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	707 int32_t offset;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	708 int32_t inc_amount, dec_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	709 x86_ea src;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	710 dst = translate_m68k_src(inst, &src, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	711 reg = native_reg(&(inst->dst), opts);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	712 //update statically set flags
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	713 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	714 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	715
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	716 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	717 flags_reg = src.base;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	718 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	719 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	720 flags_reg = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	721 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	722 dst = mov_ir(dst, src.disp, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	723 src.mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	724 flags_reg = src.base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	725 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	726 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	727 switch(inst->dst.addr_mode)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	728 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	729 case MODE_REG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	730 case MODE_AREG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	731 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	732 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	733 dst = mov_rr(dst, src.base, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	734 } else if (src.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	735 dst = mov_rdisp8r(dst, src.base, src.disp, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	736 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	737 dst = mov_ir(dst, src.disp, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	738 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	739 } else if(src.mode == MODE_REG_DIRECT) {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	740 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	741 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	742 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	743 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	744 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	745 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	746 dst = setcc_r(dst, CC_S, FLAG_N);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	747 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	748 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	749 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	750 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	751 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	752 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	753 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	754 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	755 case MODE_AREG_INDIRECT:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	756 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	757 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	758 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	759 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	760 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	761 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	762 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	763 if (src.base != SCRATCH1) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	764 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	765 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	766 } else if (src.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	767 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	768 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	769 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	770 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	771 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	772 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	773 dst = setcc_r(dst, CC_S, FLAG_N);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	774 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	775 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	776 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	777 dst = call(dst, (char *)m68k_write_byte);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	778 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	779 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	780 dst = call(dst, (char *)m68k_write_word);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	781 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	782 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	783 dst = call(dst, (char *)m68k_write_long_highfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	784 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	785 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	786 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	787 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	788 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	789 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	790 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	791 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	792 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	793 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	794 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	795 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	796 dst = cycles(dst, BUS);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	797 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	798 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	799 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	800 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	801 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	802 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	803 if (src.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	804 if (src.base != SCRATCH1) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	805 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	806 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	807 } else if (src.mode == MODE_REG_DISPLACE8) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	808 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	809 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	810 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	811 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	812 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	813 dst = setcc_r(dst, CC_Z, FLAG_Z);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	814 dst = setcc_r(dst, CC_S, FLAG_N);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	815 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	816 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	817 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	818 dst = call(dst, (char *)m68k_write_byte);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	819 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	820 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	821 dst = call(dst, (char *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	822 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	823 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	824 dst = call(dst, (char *)m68k_write_long_highfirst);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	825 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	826 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	827 break;
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	828 case MODE_AREG_INDEX_DISP8:
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	829 dst = cycles(dst, 6);//TODO: Check to make sure this is correct
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	830 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	831 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	832 } else {
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	833 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	834 }
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	835 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	836 if (inst->dst.params.regs.sec & 1) {
9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	837 if (inst->dst.params.regs.sec & 0x10) {
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	838 if (opts->aregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	839 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	840 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	841 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	842 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	843 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	844 if (opts->dregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	845 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	846 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	847 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	848 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	849 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	850 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	851 if (src.base == SCRATCH1) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	852 dst = push_r(dst, SCRATCH1);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	853 }
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	854 if (inst->dst.params.regs.sec & 0x10) {
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	855 if (opts->aregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	856 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	857 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	858 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	859 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	860 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	861 if (opts->dregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	862 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	863 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	864 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	865 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	866 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	867 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	868 if (src.base == SCRATCH1) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	869 dst = pop_r(dst, SCRATCH1);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	870 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	871 }
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	872 if (inst->dst.params.regs.displacement) {
9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	873 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	874 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	875 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	876 dst = setcc_r(dst, CC_Z, FLAG_Z);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	877 dst = setcc_r(dst, CC_S, FLAG_N);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	878 switch (inst->extra.size)
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	879 {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	880 case OPSIZE_BYTE:
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	881 dst = call(dst, (char *)m68k_write_byte);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	882 break;
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	883 case OPSIZE_WORD:
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	884 dst = call(dst, (char *)m68k_write_word);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	885 break;
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	886 case OPSIZE_LONG:
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	887 dst = call(dst, (char *)m68k_write_long_highfirst);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	888 break;
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	889 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	890 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	891 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	892 dst = cycles(dst, BUS);
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	893 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	894 if (src.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	895 if (src.base != SCRATCH1) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	896 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	897 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	898 } else if (src.mode == MODE_REG_DISPLACE8) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	899 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	900 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	901 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	902 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	903 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	904 dst = setcc_r(dst, CC_Z, FLAG_Z);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	905 dst = setcc_r(dst, CC_S, FLAG_N);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	906 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	907 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	908 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	909 dst = call(dst, (char *)m68k_write_byte);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	910 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	911 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	912 dst = call(dst, (char *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	913 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	914 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	915 dst = call(dst, (char *)m68k_write_long_highfirst);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	916 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	917 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	918 break;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	919 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	920 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	921 if (src.mode == MODE_REG_DIRECT) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	922 if (src.base != SCRATCH1) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	923 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	924 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	925 } else if (src.mode == MODE_REG_DISPLACE8) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	926 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	927 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	928 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	929 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	930 if (inst->dst.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	931 dst = cycles(dst, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	932 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	933 dst = cycles(dst, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	934 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	935 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	936 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	937 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	938 dst = setcc_r(dst, CC_S, FLAG_N);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	939 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	940 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	941 case OPSIZE_BYTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	942 dst = call(dst, (char *)m68k_write_byte);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	943 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	944 case OPSIZE_WORD:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	945 dst = call(dst, (char *)m68k_write_word);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	946 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	947 case OPSIZE_LONG:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	948 dst = call(dst, (char *)m68k_write_long_highfirst);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	949 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	950 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	951 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	952 default:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	953 printf("address mode %d not implemented (move dst)\n", inst->dst.addr_mode);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	954 exit(1);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	955 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	956
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	957 //add cycles for prefetch
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	958 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	959 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	960 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	961
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	962 uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	963 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	964 int8_t bit,reg;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	965 uint8_t early_cycles;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	966 if(inst->src.addr_mode == MODE_REG) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	967 //reg to mem
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	968 early_cycles = 8;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	969 int8_t dir;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	970 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	971 reg = 15;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	972 dir = -1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	973 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	974 reg = 0;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	975 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	976 switch (inst->dst.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	977 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	978 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	979 case MODE_AREG_PREDEC:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	980 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	981 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	982 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	983 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	984 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	985 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	986 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	987 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	988 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	989 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	990 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	991 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	992 default:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	993 printf("address mode %d not implemented (movem dst)\n", inst->dst.addr_mode);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	994 exit(1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	995 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	996 dst = cycles(dst, early_cycles);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	997 for(bit=0; reg < 16 && reg >= 0; reg += dir, bit++) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	998 if (inst->src.params.immed & (1 << bit)) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	999 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1000 dst = sub_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1001 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1002 dst = push_r(dst, SCRATCH2);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1003 if (reg > 7) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1004 if (opts->aregs[reg-8] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1005 dst = mov_rr(dst, opts->aregs[reg-8], SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1006 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1007 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1008 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1009 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1010 if (opts->dregs[reg] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1011 dst = mov_rr(dst, opts->dregs[reg], SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1012 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1013 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1014 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1015 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1016 if (inst->extra.size == OPSIZE_LONG) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1017 dst = call(dst, (uint8_t *)m68k_write_long_lowfirst);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1018 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1019 dst = call(dst, (uint8_t *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1020 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1021 dst = pop_r(dst, SCRATCH2);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1022 if (inst->dst.addr_mode != MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1023 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1024 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1025 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1026 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1027 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1028 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1029 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->dst.params.regs.pri], SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1030 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1031 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1032 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1033 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1034 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1035 //mem to reg
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1036 early_cycles = 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1037 switch (inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1038 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1039 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1040 case MODE_AREG_POSTINC:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1041 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1042 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1043 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1044 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1045 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1046 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1047 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1048 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1049 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1050 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1051 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1052 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1053 default:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1054 printf("address mode %d not implemented (movem src)\n", inst->src.addr_mode);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1055 exit(1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1056 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1057 dst = cycles(dst, early_cycles);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1058 for(reg = 0; reg < 16; reg ++) {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1059 if (inst->dst.params.immed & (1 << reg)) {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1060 dst = push_r(dst, SCRATCH1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1061 if (inst->extra.size == OPSIZE_LONG) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1062 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1063 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1064 dst = call(dst, (uint8_t *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1065 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1066 if (reg > 7) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1067 if (opts->aregs[reg-8] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1068 dst = mov_rr(dst, SCRATCH1, opts->aregs[reg-8], inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1069 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1070 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1071 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1072 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1073 if (opts->dregs[reg] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1074 dst = mov_rr(dst, SCRATCH1, opts->dregs[reg], inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1075 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1076 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1077 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1078 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1079 dst = pop_r(dst, SCRATCH1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1080 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1081 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1082 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1083 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1084 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1085 dst = mov_rr(dst, SCRATCH1, opts->aregs[inst->src.params.regs.pri], SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1086 } else {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1087 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->src)), SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1088 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1089 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1090 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1091 //prefetch
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1092 dst = cycles(dst, 4);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1093 return dst;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1094 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1095
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1096 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1097 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1098 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1099 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1100 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1101 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1102 int8_t reg = native_reg(&(inst->dst), opts);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1103 if (reg >= 0) {
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1104 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4));
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1105 return xor_rr(dst, reg, reg, inst->extra.size);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1106 }
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1107 x86_ea dst_op;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1108 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1109 if (dst_op.mode == MODE_REG_DIRECT) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1110 dst = xor_rr(dst, dst_op.base, dst_op.base, inst->extra.size);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1111 } else {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1112 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1113 }
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1114 dst = m68k_save_result(inst, dst, opts);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1115 return dst;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1116 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1117
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1118 uint8_t * translate_m68k_ext(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1119 {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1120 x86_ea dst_op;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1121 uint8_t dst_size = inst->extra.size;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1122 inst->extra.size--;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1123 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1124 if (dst_op.mode == MODE_REG_DIRECT) {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1125 dst = movsx_rr(dst, dst_op.base, dst_op.base, inst->extra.size, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1126 dst = cmp_ir(dst, 0, dst_op.base, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1127 } else {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1128 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1129 dst = cmp_ir(dst, 0, SCRATCH1, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1130 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1131 }
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1132 inst->extra.size = dst_size;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1133 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1134 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1135 dst = setcc_r(dst, CC_Z, FLAG_Z);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1136 dst = setcc_r(dst, CC_S, FLAG_N);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1137 //M68K EXT only operates on registers so no need for a call to save result here
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1138 return dst;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1139 }
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1140
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1141 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1142 {
100 45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1143 int8_t dst_reg = native_reg(&(inst->dst), opts), sec_reg;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1144 switch(inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1145 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1146 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1147 dst = cycles(dst, BUS);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1148 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1149 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1150 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1151 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1152 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1153 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1154 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1155 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1156 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1157 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1158 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1159 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1160 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1161 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1162 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1163 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1164 dst = cycles(dst, 8);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1165 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1166 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1167 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1168 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1169 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1170 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1171 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1172 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1173 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1174 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1175 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1176 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1177 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1178 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1179 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->src)), SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1180 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1181 break;
100 45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1182 case MODE_AREG_INDEX_DISP8:
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1183 dst = cycles(dst, 6);//TODO: Check to make sure this is correct
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1184 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1185 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1186 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1187 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1188 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1189 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1190 if (inst->src.params.regs.sec & 1) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1191 if (inst->src.params.regs.sec & 0x10) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1192 if (opts->aregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1193 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1194 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1195 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1196 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1197 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1198 if (opts->dregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1199 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1200 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1201 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1202 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1203 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1204 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1205 if (inst->src.params.regs.sec & 0x10) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1206 if (opts->aregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1207 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1208 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1209 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1210 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1211 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1212 if (opts->dregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1213 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1214 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1215 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1216 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1217 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1218 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1219 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1220 if (inst->src.params.regs.displacement) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1221 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1222 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1223 if (dst_reg >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1224 dst = mov_rr(dst, SCRATCH2, dst_reg, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1225 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1226 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->src)), SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1227 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1228 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1229 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1230 dst = cycles(dst, 8);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1231 if (dst_reg >= 0) {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1232 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, dst_reg, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1233 } else {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1234 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1235 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1236 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1237 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1238 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1239 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1240 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1241 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1242 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1243 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1244 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1245 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1246 default:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1247 printf("address mode %d not implemented (lea src)\n", inst->src.addr_mode);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1248 exit(1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1249 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1250 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1251 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1252
116 9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1253 uint8_t * translate_m68k_pea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1254 {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1255 uint8_t sec_reg;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1256 switch(inst->src.addr_mode)
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1257 {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1258 case MODE_AREG_INDIRECT:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1259 dst = cycles(dst, BUS);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1260 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1261 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1262 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1263 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1264 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1265 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1266 case MODE_AREG_DISPLACE:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1267 dst = cycles(dst, 8);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1268 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1269 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1270 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1271 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1272 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1273 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1274 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1275 case MODE_AREG_INDEX_DISP8:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1276 dst = cycles(dst, 6);//TODO: Check to make sure this is correct
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1277 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1278 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1279 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1280 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1281 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1282 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1283 if (inst->src.params.regs.sec & 1) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1284 if (inst->src.params.regs.sec & 0x10) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1285 if (opts->aregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1286 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1287 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1288 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1289 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1290 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1291 if (opts->dregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1292 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1293 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1294 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1295 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1296 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1297 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1298 if (inst->src.params.regs.sec & 0x10) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1299 if (opts->aregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1300 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1301 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1302 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1303 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1304 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1305 if (opts->dregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1306 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1307 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1308 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1309 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1310 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1311 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1312 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1313 if (inst->src.params.regs.displacement) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1314 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1315 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1316 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1317 case MODE_PC_DISPLACE:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1318 dst = cycles(dst, 8);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1319 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1320 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1321 case MODE_ABSOLUTE:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1322 case MODE_ABSOLUTE_SHORT:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1323 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1324 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1325 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1326 default:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1327 printf("address mode %d not implemented (lea src)\n", inst->src.addr_mode);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1328 exit(1);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1329 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1330 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1331 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1332 dst = call(dst, (uint8_t *)m68k_write_long_lowfirst);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1333 return dst;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1334 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1335
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1336 uint8_t * translate_m68k_bsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1337 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1338 int32_t disp = inst->src.params.immed;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1339 uint32_t after = inst->address + 2;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1340 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1341 dst = cycles(dst, 10);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1342 dst = mov_ir(dst, after, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1343 dst = push_r(dst, SCRATCH1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1344 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1345 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1346 dst = call(dst, (char *)m68k_write_long_highfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1347 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1348 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1349 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1350 //dummy address to be replaced later
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1351 dest_addr = dst + 5;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1352 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1353 dst = call(dst, (char *)dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1354 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1355 dst = pop_r(dst, SCRATCH1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1356 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1357 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1358
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1359 uint8_t * translate_m68k_bcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1360 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1361 //TODO: Add cycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1362 int32_t disp = inst->src.params.immed;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1363 uint32_t after = inst->address + 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1364 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1365 if (inst->extra.cond == COND_TRUE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1366 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1367 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1368 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1369 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1370 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1371 dst = jmp(dst, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1372 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1373 uint8_t cond = CC_NZ;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1374 switch (inst->extra.cond)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1375 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1376 case COND_HIGH:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1377 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1378 case COND_LOW_SAME:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1379 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1380 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1381 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1382 case COND_CARRY_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1383 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1384 case COND_CARRY_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1385 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1386 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1387 case COND_NOT_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1388 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1389 case COND_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1390 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1391 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1392 case COND_OVERF_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1393 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1394 case COND_OVERF_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1395 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1396 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1397 case COND_PLUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1398 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1399 case COND_MINUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1400 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1401 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1402 case COND_GREATER_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1403 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1404 case COND_LESS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1405 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1406 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1407 case COND_GREATER:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1408 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1409 case COND_LESS_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1410 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1411 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1412 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1413 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1414 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1415 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1416 opts->deferred = defer_address(opts->deferred, after + disp, dst + 2);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1417 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1418 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1419 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1420 dst = jcc(dst, cond, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1421 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1422 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1423 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1424
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1425 uint8_t * translate_m68k_scc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1426 {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1427 uint8_t cond = inst->extra.cond;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1428 x86_ea dst_op;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1429 inst->extra.size = OPSIZE_BYTE;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1430 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1431 if (cond == COND_TRUE \|\| cond == COND_FALSE) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1432 if ((inst->dst.addr_mode == MODE_REG \|\| inst->dst.addr_mode == MODE_AREG) && inst->extra.cond == COND_TRUE) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1433 dst = cycles(dst, 6);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1434 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1435 dst = cycles(dst, BUS);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1436 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1437 if (dst_op.mode == MODE_REG_DIRECT) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1438 dst = mov_ir(dst, cond == COND_TRUE, dst_op.base, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1439 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1440 dst = mov_irdisp8(dst, cond == COND_TRUE, dst_op.base, dst_op.disp, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1441 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1442 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1443 uint8_t cc = CC_NZ;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1444 switch (cond)
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1445 {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1446 case COND_HIGH:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1447 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1448 case COND_LOW_SAME:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1449 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1450 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1451 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1452 case COND_CARRY_CLR:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1453 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1454 case COND_CARRY_SET:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1455 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1456 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1457 case COND_NOT_EQ:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1458 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1459 case COND_EQ:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1460 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1461 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1462 case COND_OVERF_CLR:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1463 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1464 case COND_OVERF_SET:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1465 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1466 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1467 case COND_PLUS:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1468 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1469 case COND_MINUS:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1470 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1471 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1472 case COND_GREATER_EQ:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1473 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1474 case COND_LESS:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1475 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1476 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1477 case COND_GREATER:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1478 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1479 case COND_LESS_EQ:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1480 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1481 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1482 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1483 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1484 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1485 if ((inst->dst.addr_mode == MODE_REG \|\| inst->dst.addr_mode == MODE_AREG)) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1486 uint8_t *true_off = dst + 1;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1487 dst = jcc(dst, cc, dst+2);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1488 dst = cycles(dst, BUS);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1489 if (dst_op.mode == MODE_REG_DIRECT) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1490 dst = mov_ir(dst, 0, dst_op.base, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1491 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1492 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1493 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1494 uint8_t *end_off = dst+1;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1495 dst = jmp(dst, dst+2);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1496 *true_off = dst - (true_off+1);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1497 dst = cycles(dst, 6);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1498 if (dst_op.mode == MODE_REG_DIRECT) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1499 dst = mov_ir(dst, 1, dst_op.base, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1500 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1501 dst = mov_irdisp8(dst, 1, dst_op.base, dst_op.disp, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1502 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1503 *end_off = dst - (end_off+1);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1504 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1505 dst = cycles(dst, BUS);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1506 if (dst_op.mode == MODE_REG_DIRECT) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1507 dst = setcc_r(dst, cc, dst_op.base);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1508 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1509 dst = setcc_rdisp8(dst, cc, dst_op.base, dst_op.disp);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1510 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1511 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1512 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1513 dst = m68k_save_result(inst, dst, opts);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1514 return dst;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1515 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1516
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1517 uint8_t * translate_m68k_jmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1518 {
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1519 uint8_t * dest_addr;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1520 uint32_t m68k_addr;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1521 switch(inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1522 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1523 case MODE_AREG_INDIRECT:
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1524 dst = cycles(dst, BUS*2);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1525 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1526 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1527 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1528 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1529 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1530 dst = call(dst, (uint8_t *)m68k_native_addr);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1531 dst = jmp_r(dst, SCRATCH1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1532 break;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1533 case MODE_PC_DISPLACE:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1534 dst = cycles(dst, 10);
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1535 m68k_addr = inst->src.params.regs.displacement + inst->address + 2;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1536 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1537 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1538 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1539 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1540 //dummy address to be replaced later, make sure it generates a 4-byte displacement
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1541 dest_addr = dst + 256;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1542 }
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1543 dst = jmp(dst, dest_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1544 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1545 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1546 dst = call(dst, (uint8_t *)m68k_native_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1547 dst = jmp_r(dst, SCRATCH1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1548 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1549 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1550 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1551 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1552 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1553 m68k_addr = inst->src.params.immed;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1554 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1555 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1556 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1557 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1558 //dummy address to be replaced later, make sure it generates a 4-byte displacement
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1559 dest_addr = dst + 256;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1560 }
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1561 dst = jmp(dst, dest_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1562 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1563 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1564 dst = call(dst, (uint8_t *)m68k_native_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1565 dst = jmp_r(dst, SCRATCH1);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1566 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1567 break;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1568 default:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1569 printf("address mode %d not yet supported (jmp)\n", inst->src.addr_mode);
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 102 diff changeset	1570 exit(1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1571 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1572 return dst;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1573 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1574
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1575 uint8_t * translate_m68k_jsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1576 {
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1577 uint8_t * dest_addr, sec_reg;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1578 uint32_t after;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1579 uint32_t m68k_addr;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1580 switch(inst->src.addr_mode)
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1581 {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1582 case MODE_AREG_INDIRECT:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1583 dst = cycles(dst, BUS*2);
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	1584 dst = mov_ir(dst, inst->address + 2, SCRATCH1, SZ_D);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1585 dst = push_r(dst, SCRATCH1);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1586 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1587 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1588 dst = call(dst, (char *)m68k_write_long_highfirst);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1589 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1590 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1591 } else {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1592 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1593 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1594 dst = call(dst, (uint8_t *)m68k_native_addr);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1595 dst = call_r(dst, SCRATCH1);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1596 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1597 dst = pop_r(dst, SCRATCH1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1598 break;
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1599 case MODE_AREG_INDEX_DISP8:
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1600 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	1601 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1602 dst = push_r(dst, SCRATCH1);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1603 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1604 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1605 dst = call(dst, (char *)m68k_write_long_highfirst);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1606 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1607 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1608 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1609 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1610 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1611 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1612 if (inst->src.params.regs.sec & 1) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1613 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1614 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1615 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1616 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1617 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1618 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1619 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1620 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1621 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1622 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1623 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1624 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1625 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1626 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1627 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1628 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1629 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1630 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1631 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1632 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1633 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1634 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1635 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1636 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1637 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1638 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1639 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1640 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1641 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1642 if (inst->src.params.regs.displacement) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1643 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1644 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1645 dst = call(dst, (uint8_t *)m68k_native_addr);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1646 dst = call_r(dst, SCRATCH1);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1647 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1648 dst = pop_r(dst, SCRATCH1);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1649 break;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1650 case MODE_PC_DISPLACE:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1651 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1652 dst = cycles(dst, 10);
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	1653 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1654 dst = push_r(dst, SCRATCH1);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1655 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1656 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1657 dst = call(dst, (char *)m68k_write_long_highfirst);
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1658 m68k_addr = inst->src.params.regs.displacement + inst->address + 2;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1659 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1660 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1661 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1662 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1663 //dummy address to be replaced later, make sure it generates a 4-byte displacement
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1664 dest_addr = dst + 5;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1665 }
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1666 dst = call(dst, (char *)dest_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1667 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1668 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1669 dst = call(dst, (uint8_t *)m68k_native_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1670 dst = call_r(dst, SCRATCH1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1671 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1672 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1673 dst = pop_r(dst, SCRATCH1);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1674 break;
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1675 case MODE_PC_INDEX_DISP8:
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1676 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	1677 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1678 dst = push_r(dst, SCRATCH1);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1679 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1680 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1681 dst = call(dst, (char *)m68k_write_long_highfirst);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1682 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1683 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1684 if (inst->src.params.regs.sec & 1) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1685 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1686 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1687 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1688 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1689 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1690 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1691 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1692 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1693 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1694 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1695 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1696 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1697 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1698 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1699 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1700 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1701 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1702 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1703 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1704 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1705 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1706 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1707 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1708 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1709 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1710 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1711 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1712 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1713 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1714 if (inst->src.params.regs.displacement) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1715 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1716 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1717 dst = call(dst, (uint8_t *)m68k_native_addr);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1718 dst = call_r(dst, SCRATCH1);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1719 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1720 dst = pop_r(dst, SCRATCH1);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1721 break;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1722 case MODE_ABSOLUTE:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1723 case MODE_ABSOLUTE_SHORT:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1724 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1725 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	1726 dst = mov_ir(dst, inst->address + (inst->src.addr_mode == MODE_ABSOLUTE ? 6 : 4), SCRATCH1, SZ_D);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1727 dst = push_r(dst, SCRATCH1);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1728 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1729 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1730 dst = call(dst, (char *)m68k_write_long_highfirst);
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1731 m68k_addr = inst->src.params.immed;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1732 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1733 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1734 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1735 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1736 //dummy address to be replaced later, make sure it generates a 4-byte displacement
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1737 dest_addr = dst + 5;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1738 }
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1739 dst = call(dst, (char *)dest_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1740 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1741 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1742 dst = call(dst, (uint8_t *)m68k_native_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1743 dst = call_r(dst, SCRATCH1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1744 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1745 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1746 dst = pop_r(dst, SCRATCH1);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1747 break;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1748 default:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1749 printf("address mode %d not yet supported (jsr)\n", inst->src.addr_mode);
105 1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	1750 exit(1);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1751 }
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1752 return dst;
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1753 }
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1754
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1755 uint8_t * translate_m68k_rts(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1756 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1757 //TODO: Add cycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1758 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1759 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1760 dst = call(dst, (char *)m68k_read_long_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1761 dst = cmp_rdisp8r(dst, RSP, 8, SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1762 dst = jcc(dst, CC_NZ, dst+3);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1763 dst = retn(dst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1764 dst = jmp(dst, (char *)m68k_modified_ret_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1765 return dst;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1766 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1767
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1768 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1769 {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1770 //best case duration
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1771 dst = cycles(dst, 10);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1772 uint8_t * skip_loc = NULL;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1773 //TODO: Check if COND_TRUE technically valid here even though
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1774 //it's basically a slow NOP
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1775 if (inst->extra.cond != COND_FALSE) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1776 uint8_t cond = CC_NZ;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1777 switch (inst->extra.cond)
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1778 {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1779 case COND_HIGH:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1780 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1781 case COND_LOW_SAME:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1782 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1783 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1784 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1785 case COND_CARRY_CLR:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1786 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1787 case COND_CARRY_SET:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1788 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1789 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1790 case COND_NOT_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1791 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1792 case COND_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1793 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1794 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1795 case COND_OVERF_CLR:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1796 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1797 case COND_OVERF_SET:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1798 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1799 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1800 case COND_PLUS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1801 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1802 case COND_MINUS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1803 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1804 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1805 case COND_GREATER_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1806 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1807 case COND_LESS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1808 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1809 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1810 case COND_GREATER:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1811 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1812 case COND_LESS_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1813 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1814 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1815 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1816 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1817 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1818 skip_loc = dst + 1;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1819 dst = jcc(dst, cond, dst + 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1820 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1821 if (opts->dregs[inst->dst.params.regs.pri] >= 0) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1822 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1823 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1824 } else {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1825 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1826 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1827 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1828 uint8_t *loop_end_loc = dst+1;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1829 dst = jcc(dst, CC_Z, dst+2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1830 uint32_t after = inst->address + 2;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1831 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + inst->src.params.immed);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1832 if (!dest_addr) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1833 opts->deferred = defer_address(opts->deferred, after + inst->src.params.immed, dst + 1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1834 //dummy address to be replaced later, make sure it generates a 4-byte displacement
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1835 dest_addr = dst + 256;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1836 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1837 dst = jmp(dst, dest_addr);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1838 *loop_end_loc = dst - (loop_end_loc+1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1839 if (skip_loc) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1840 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1841 *skip_loc = dst - (skip_loc+1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1842 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1843 } else {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1844 dst = cycles(dst, 4);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1845 }
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1846 return dst;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1847 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1848
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1849 uint8_t * translate_m68k_link(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1850 {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1851 int8_t reg = native_reg(&(inst->src), opts);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1852 //compensate for displacement word
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1853 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1854 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1855 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1856 if (reg >= 0) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1857 dst = mov_rr(dst, reg, SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1858 } else {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1859 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1860 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1861 dst = call(dst, (char *)m68k_write_long_highfirst);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1862 if (reg >= 0) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1863 dst = mov_rr(dst, opts->aregs[7], reg, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1864 } else {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1865 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, reg_offset(&(inst->src)), SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1866 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1867 dst = add_ir(dst, inst->dst.params.immed, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1868 //prefetch
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1869 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1870 return dst;
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1871 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	1872
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1873 typedef uint8_t * (shift_ir_t)(uint8_t out, uint8_t val, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1874 typedef uint8_t * (shift_irdisp8_t)(uint8_t out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1875 typedef uint8_t * (shift_clr_t)(uint8_t out, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1876 typedef uint8_t * (shift_clrdisp8_t)(uint8_t out, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1877
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1878 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea src_op, x86_ea dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1879 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1880 uint8_t * end_off = NULL;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1881 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1882 dst = cycles(dst, BUS);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1883 //Memory shift
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1884 dst = shift_ir(dst, 1, dst_op->base, SZ_W);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1885 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1886 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1887 if (src_op->mode == MODE_IMMED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1888 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1889 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1890 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1891 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1892 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1893 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1894 if (src_op->base != RCX) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1895 if (src_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1896 dst = mov_rr(dst, src_op->base, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1897 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1898 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1899 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1900 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1901 dst = and_ir(dst, 63, RCX, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1902 //add 2 cycles for every bit shifted
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1903 dst = add_rr(dst, RCX, CYCLES, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1904 dst = add_rr(dst, RCX, CYCLES, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1905 //x86 shifts modulo 32 for operand sizes less than 64-bits
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1906 //but M68K shifts modulo 64, so we need to check for large shifts here
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1907 dst = cmp_ir(dst, 32, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1908 uint8_t * norm_shift_off = dst + 1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1909 dst = jcc(dst, CC_L, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1910 if (special) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1911 if (inst->extra.size == OPSIZE_LONG) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1912 uint8_t * neq_32_off = dst + 1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1913 dst = jcc(dst, CC_NZ, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1914
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1915 //set the carry bit to the lsb
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1916 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1917 dst = special(dst, 1, dst_op->base, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1918 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1919 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1920 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1921 dst = setcc_r(dst, CC_C, FLAG_C);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1922 dst = jmp(dst, dst+4);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1923 *neq_32_off = dst - (neq_32_off+1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1924 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1925 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1926 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1927 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1928 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1929 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1930 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1931 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1932 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1933 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1934 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1935 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1936 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1937 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1938 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1939 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1940 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1941
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1942 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1943 end_off = dst+1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1944 dst = jmp(dst, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1945 *norm_shift_off = dst - (norm_shift_off+1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1946 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1947 dst = shift_clr(dst, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1948 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1949 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1950 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1951
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1952 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1953
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1954 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1955 if (!special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1956 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1957 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1958 dst = setcc_r(dst, CC_C, FLAG_C);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1959 dst = setcc_r(dst, CC_Z, FLAG_Z);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1960 dst = setcc_r(dst, CC_S, FLAG_N);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1961 if (special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1962 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1963 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1964 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1965 //set X flag to same as C flag
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1966 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1967 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1968 dst = m68k_save_result(inst, dst, opts);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1969 }
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	1970 return dst;
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1971 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	1972
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1973 #define BIT_SUPERVISOR 5
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	1974
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1975 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1976 {
122 0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	1977 uint8_t * end_off, zero_off, norm_off;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1978 map_native_address(opts->native_code_map, inst->address, dst);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	1979 dst = check_cycles_int(dst, inst->address);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1980 if (inst->op == M68K_MOVE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1981 return translate_m68k_move(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1982 } else if(inst->op == M68K_LEA) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1983 return translate_m68k_lea(dst, inst, opts);
116 9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1984 } else if(inst->op == M68K_PEA) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1985 return translate_m68k_pea(dst, inst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1986 } else if(inst->op == M68K_BSR) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1987 return translate_m68k_bsr(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1988 } else if(inst->op == M68K_BCC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1989 return translate_m68k_bcc(dst, inst, opts);
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1990 } else if(inst->op == M68K_JMP) {
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1991 return translate_m68k_jmp(dst, inst, opts);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1992 } else if(inst->op == M68K_JSR) {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1993 return translate_m68k_jsr(dst, inst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1994 } else if(inst->op == M68K_RTS) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1995 return translate_m68k_rts(dst, inst, opts);
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1996 } else if(inst->op == M68K_DBCC) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1997 return translate_m68k_dbcc(dst, inst, opts);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1998 } else if(inst->op == M68K_CLR) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1999 return translate_m68k_clr(dst, inst, opts);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2000 } else if(inst->op == M68K_MOVEM) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2001 return translate_m68k_movem(dst, inst, opts);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2002 } else if(inst->op == M68K_LINK) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2003 return translate_m68k_link(dst, inst, opts);
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	2004 } else if(inst->op == M68K_EXT) {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	2005 return translate_m68k_ext(dst, inst, opts);
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	2006 } else if(inst->op == M68K_SCC) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	2007 return translate_m68k_scc(dst, inst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2008 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2009 x86_ea src_op, dst_op;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2010 if (inst->src.addr_mode != MODE_UNUSED) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2011 dst = translate_m68k_src(inst, &src_op, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2012 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2013 if (inst->dst.addr_mode != MODE_UNUSED) {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	2014 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2015 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2016 switch(inst->op)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2017 {
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2018 //case M68K_ABCD:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2019 // break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2020 case M68K_ADD:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2021 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2022 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2023 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2024 dst = add_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2025 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2026 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2027 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2028 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2029 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2030 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2031 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2032 dst = add_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2033 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2034 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2035 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2036 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2037 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2038 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2039 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2040 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2041 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2042 dst = m68k_save_result(inst, dst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2043 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2044 //case M68K_ADDX:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2045 // break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2046 case M68K_AND:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2047 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2048 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2049 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2050 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2051 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2052 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2053 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2054 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2055 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2056 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2057 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2058 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2059 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2060 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2061 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2062 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2063 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2064 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2065 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2066 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2067 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2068 break;
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2069 case M68K_ANDI_CCR:
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2070 case M68K_ANDI_SR:
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2071 dst = cycles(dst, 20);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2072 //TODO: If ANDI to SR, trap if not in supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2073 if (!(inst->src.params.immed & 0x1)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2074 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2075 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2076 if (!(inst->src.params.immed & 0x2)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2077 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2078 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2079 if (!(inst->src.params.immed & 0x4)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2080 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2081 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2082 if (!(inst->src.params.immed & 0x8)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2083 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2084 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2085 if (!(inst->src.params.immed & 0x10)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2086 dst = mov_irind(dst, 0, CONTEXT, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2087 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2088 if (inst->op == M68K_ANDI_SR) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2089 dst = and_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2090 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2091 //leave supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2092 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2093 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2094 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2095 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2096 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2097 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2098 case M68K_ASL:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2099 case M68K_LSL:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2100 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2101 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2102 case M68K_ASR:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2103 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2104 break;
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2105 case M68K_LSR:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2106 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2107 break;
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2108 case M68K_BCHG:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2109 case M68K_BCLR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2110 case M68K_BSET:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2111 case M68K_BTST:
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2112 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : 6);
67 534eb4976423 Fix BTST Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	2113 if (src_op.mode == MODE_IMMED) {
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2114 if (inst->extra.size == OPSIZE_BYTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2115 src_op.disp &= 0x7;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2116 }
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2117 if (inst->op == M68K_BTST) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2118 if (dst_op.mode == MODE_REG_DIRECT) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2119 dst = bt_ir(dst, src_op.disp, dst_op.base, SZ_D);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2120 } else {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2121 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, SZ_D);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2122 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2123 } else if (inst->op == M68K_BSET) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2124 if (dst_op.mode == MODE_REG_DIRECT) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2125 dst = bts_ir(dst, src_op.disp, dst_op.base, SZ_D);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2126 } else {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2127 dst = bts_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, SZ_D);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2128 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2129 } else if (inst->op == M68K_BCLR) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2130 if (dst_op.mode == MODE_REG_DIRECT) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2131 dst = btr_ir(dst, src_op.disp, dst_op.base, SZ_D);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2132 } else {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2133 dst = btr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, SZ_D);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2134 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2135 } else {
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2136 if (dst_op.mode == MODE_REG_DIRECT) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2137 dst = btc_ir(dst, src_op.disp, dst_op.base, SZ_D);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2138 } else {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2139 dst = btc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, SZ_D);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2140 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2141 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2142 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2143 if (src_op.mode == MODE_REG_DISPLACE8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2144 if (dst_op.base == SCRATCH1) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2145 dst = push_r(dst, SCRATCH2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2146 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2147 src_op.base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2148 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2149 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2150 src_op.base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2151 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2152 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2153 if (inst->extra.size == OPSIZE_BYTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2154 dst = and_ir(dst, 0x7, src_op.base, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2155 }
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2156 if (inst->op == M68K_BTST) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2157 if (dst_op.mode == MODE_REG_DIRECT) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2158 dst = bt_rr(dst, src_op.base, dst_op.base, SZ_D);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2159 } else {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2160 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2161 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2162 } else if (inst->op == M68K_BSET) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2163 if (dst_op.mode == MODE_REG_DIRECT) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2164 dst = bts_rr(dst, src_op.base, dst_op.base, SZ_D);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2165 } else {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2166 dst = bts_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2167 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2168 } else if (inst->op == M68K_BCLR) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2169 if (dst_op.mode == MODE_REG_DIRECT) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2170 dst = btr_rr(dst, src_op.base, dst_op.base, SZ_D);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2171 } else {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2172 dst = btr_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2173 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2174 } else {
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2175 if (dst_op.mode == MODE_REG_DIRECT) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2176 dst = btc_rr(dst, src_op.base, dst_op.base, SZ_D);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2177 } else {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2178 dst = btc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2179 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2180 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2181 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2182 //x86 sets the carry flag to the value of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2183 //68K sets the zero flag to the complement of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2184 dst = setcc_r(dst, CC_NC, FLAG_Z);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2185 if (src_op.base == SCRATCH2) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2186 dst = pop_r(dst, SCRATCH2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2187 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2188 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2189 /*case M68K_CHK:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2190 break;*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2191 case M68K_CMP:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2192 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2193 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2194 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2195 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2196 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2197 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2198 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2199 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2200 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2201 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2202 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2203 dst = cmp_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2204 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2205 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2206 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2207 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2208 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2209 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2210 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2211 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2212 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2213 /*case M68K_DIVS:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2214 case M68K_DIVU:
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2215 break;*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2216 case M68K_EOR:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2217 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2218 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2219 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2220 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2221 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2222 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2223 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2224 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2225 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2226 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2227 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2228 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2229 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2230 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2231 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2232 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2233 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2234 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2235 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2236 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2237 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2238 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2239 /*case M68K_EORI_CCR:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2240 case M68K_EORI_SR:*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2241 case M68K_EXG:
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2242 dst = cycles(dst, 6);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2243 if (dst_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2244 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2245 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2246 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2247 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2248 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2249 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2250 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2251 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2252 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2253 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2254 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2255 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2256 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2257 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2258 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2259 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2260 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2261 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2262 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2263 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2264 case M68K_ILLEGAL:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2265 dst = call(dst, (uint8_t *)m68k_save_context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2266 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2267 dst = call(dst, (uint8_t *)print_regs_exit);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2268 break;
105 1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2269 case M68K_MOVE_FROM_SR:
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2270 //TODO: Trap if not in system mode
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2271 dst = call(dst, (uint8_t *)get_sr);
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2272 if (dst_op.mode == MODE_REG_DIRECT) {
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2273 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_W);
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2274 } else {
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2275 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_W);
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2276 }
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2277 dst = m68k_save_result(inst, dst, opts);
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2278 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2279 case M68K_MOVE_CCR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2280 case M68K_MOVE_SR:
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2281 //TODO: Privilege check for MOVE to SR
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2282 if (src_op.mode == MODE_IMMED) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2283 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2284 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2285 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2286 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2287 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2288 if (inst->op == M68K_MOVE_SR) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2289 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B);
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2290 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2291 //leave supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2292 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2293 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2294 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2295 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2296 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2297 dst = cycles(dst, 12);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2298 } else {
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2299 if (src_op.base != SCRATCH1) {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2300 if (src_op.mode == MODE_REG_DIRECT) {
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2301 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2302 } else {
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2303 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2304 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2305 }
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2306 dst = call(dst, (uint8_t *)(inst->op == M68K_MOVE_SR ? set_sr : set_ccr));
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2307 dst = cycles(dst, 12);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2308
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2309 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2310 break;
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2311 case M68K_MOVE_USP:
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2312 dst = cycles(dst, BUS);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2313 //TODO: Trap if not in supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2314 //dst = bt_irdisp8(dst, BIT_SUPERVISOR, CONTEXT, offsetof(m68k_context, status), SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2315 if (inst->src.addr_mode == MODE_UNUSED) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2316 if (dst_op.mode == MODE_REG_DIRECT) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2317 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, dst_op.base, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2318 } else {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2319 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2320 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2321 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2322 } else {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2323 if (src_op.mode == MODE_REG_DIRECT) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2324 dst = mov_rrdisp8(dst, src_op.base, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2325 } else {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2326 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2327 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2328 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2329 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2330 break;
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2331 /*case M68K_MOVEP:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2332 case M68K_MULS:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2333 case M68K_MULU:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2334 case M68K_NBCD:*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2335 case M68K_NEG:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2336 if (dst_op.mode == MODE_REG_DIRECT) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2337 dst = neg_r(dst, dst_op.base, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2338 } else {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2339 dst = not_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2340 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2341 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2342 dst = setcc_r(dst, CC_Z, FLAG_Z);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2343 dst = setcc_r(dst, CC_S, FLAG_N);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2344 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2345 dst = m68k_save_result(inst, dst, opts);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2346 break;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2347 /*case M68K_NEGX:
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2348 break;*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2349 case M68K_NOP:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2350 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2351 break;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2352 case M68K_NOT:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2353 if (dst_op.mode == MODE_REG_DIRECT) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2354 dst = not_r(dst, dst_op.base, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2355 } else {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2356 dst = not_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2357 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2358 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2359 dst = setcc_r(dst, CC_Z, FLAG_Z);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2360 dst = setcc_r(dst, CC_S, FLAG_N);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2361 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2362 dst = m68k_save_result(inst, dst, opts);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2363 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2364 case M68K_OR:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2365 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2366 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2367 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2368 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2369 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2370 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2371 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2372 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2373 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2374 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2375 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2376 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2377 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2378 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2379 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2380 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2381 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2382 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2383 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2384 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2385 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2386 break;
106 1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2387 case M68K_ORI_CCR:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2388 case M68K_ORI_SR:
106 1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2389 dst = cycles(dst, 20);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2390 //TODO: If ANDI to SR, trap if not in supervisor mode
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2391 if (inst->src.params.immed & 0x1) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2392 dst = mov_ir(dst, 1, FLAG_C, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2393 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2394 if (inst->src.params.immed & 0x2) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2395 dst = mov_ir(dst, 1, FLAG_V, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2396 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2397 if (inst->src.params.immed & 0x4) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2398 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2399 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2400 if (inst->src.params.immed & 0x8) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2401 dst = mov_ir(dst, 1, FLAG_N, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2402 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2403 if (inst->src.params.immed & 0x10) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2404 dst = mov_irind(dst, 1, CONTEXT, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2405 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2406 if (inst->op == M68K_ANDI_SR) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2407 dst = or_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2408 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2409 break;
122 0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2410 /case M68K_RESET:/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2411 case M68K_ROL:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2412 case M68K_ROR:
122 0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2413 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2414 if (inst->src.addr_mode == MODE_UNUSED) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2415 dst = cycles(dst, BUS);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2416 //Memory rotate
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2417 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2418 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2419 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2420 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2421 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2422 dst = setcc_r(dst, CC_C, FLAG_C);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2423 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2424 dst = setcc_r(dst, CC_Z, FLAG_Z);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2425 dst = setcc_r(dst, CC_S, FLAG_N);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2426 dst = m68k_save_result(inst, dst, opts);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2427 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2428 if (src_op.mode == MODE_IMMED) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2429 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2430 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2431 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2432 dst = rol_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2433 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2434 dst = ror_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2435 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2436 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2437 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2438 dst = rol_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2439 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2440 dst = ror_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2441 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2442 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2443 dst = setcc_r(dst, CC_C, FLAG_C);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2444 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2445 if (src_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2446 if (src_op.base != SCRATCH1) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2447 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2448 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2449 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2450 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2451 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2452 dst = and_ir(dst, 63, SCRATCH1, SZ_D);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2453 zero_off = dst+1;
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2454 dst = jcc(dst, CC_NZ, dst+2);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2455 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2456 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2457 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2458 norm_off = dst+1;
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2459 dst = jcc(dst, CC_L, dst+2);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2460 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2461 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2462 dst = rol_ir(dst, 31, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2463 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2464 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2465 dst = ror_ir(dst, 31, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2466 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2467 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2468 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2469 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2470 dst = rol_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2471 dst = rol_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2472 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2473 dst = ror_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2474 dst = ror_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2475 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2476 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2477 dst = sub_ir(dst, 32, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2478 *norm_off = dst - (norm_off+1);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2479 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2480 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2481 dst = rol_clr(dst, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2482 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2483 dst = ror_clr(dst, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2484 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2485 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2486 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2487 dst = rol_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2488 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2489 dst = ror_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2490 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2491 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2492 dst = setcc_r(dst, CC_C, FLAG_C);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2493 end_off = dst + 1;
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2494 dst = jmp(dst, dst+2);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2495 *zero_off = dst - (zero_off+1);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2496 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2497 *end_off = dst - (end_off+1);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2498 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2499 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2500 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2501 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2502 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2503 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2504 dst = setcc_r(dst, CC_Z, FLAG_Z);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2505 dst = setcc_r(dst, CC_S, FLAG_N);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2506 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2507 break;
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2508 /*case M68K_ROXL:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2509 case M68K_ROXR:*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2510 case M68K_RTE:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2511 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2512 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2513 dst = push_r(dst, SCRATCH1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2514 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2515 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2516 dst = call(dst, (uint8_t *)m68k_read_word_scratch1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2517 dst = add_ir(dst, 2, opts->aregs[7], SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2518 dst = call(dst, (uint8_t *)set_sr);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2519 dst = pop_r(dst, SCRATCH1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2520 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2521 end_off = dst+1;
121 f848aad2abef Fix logic for switching between USP and SSP Mike Pavone <pavone@retrodev.com> parents: 119 diff changeset	2522 dst = jcc(dst, CC_C, dst+2);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2523 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2524 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2525 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2526 *end_off = dst - (end_off+1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2527 dst = call(dst, (uint8_t *)m68k_native_addr_and_sync);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2528 dst = jmp_r(dst, SCRATCH1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2529 break;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2530 /*case M68K_RTR:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2531 case M68K_SBCD:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2532 case M68K_STOP:
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2533 break;*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2534 case M68K_SUB:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2535 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2536 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2537 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2538 dst = sub_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2539 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2540 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2541 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2542 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2543 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2544 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2545 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2546 dst = sub_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2547 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2548 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2549 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2550 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2551 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2552 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2553 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2554 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2555 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2556 dst = m68k_save_result(inst, dst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2557 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2558 //case M68K_SUBX:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2559 // break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2560 case M68K_SWAP:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2561 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2562 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2563 dst = rol_ir(dst, 16, src_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2564 } else{
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2565 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2566 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2567 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2568 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2569 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2570 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2571 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2572 /*case M68K_TAS:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2573 case M68K_TRAP:
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2574 case M68K_TRAPV:*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2575 case M68K_TST:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2576 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2577 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2578 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2579 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2580 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2581 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2582 dst = setcc_r(dst, CC_C, FLAG_C);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2583 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2584 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2585 dst = setcc_r(dst, CC_O, FLAG_V);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2586 break;
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2587 case M68K_UNLK:
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2588 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2589 if (dst_op.mode == MODE_REG_DIRECT) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2590 dst = mov_rr(dst, dst_op.base, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2591 } else {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2592 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2593 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2594 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2595 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2596 if (dst_op.mode == MODE_REG_DIRECT) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2597 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2598 } else {
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	2599 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2600 }
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	2601 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2602 break;
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2603 /*case M68K_INVALID:
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2604 break;*/
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2605 default:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2606 printf("instruction %d not yet implemented\n", inst->op);
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2607 exit(1);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2608 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2609 return dst;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2610 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2611
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2612 uint8_t * translate_m68k_stream(uint32_t address, m68k_context * context)
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2613 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2614 m68kinst instbuf;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2615 x86_68k_options * opts = context->options;
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2616 uint8_t * dst = opts->cur_code;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2617 uint8_t * dst_end = opts->code_end;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2618 if(get_native_address(opts->native_code_map, address)) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2619 return dst;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2620 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2621 char disbuf[1024];
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2622 uint16_t encoded, next;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2623 if ((address & 0xFFFFFF) < 0x400000) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2624 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2625 } else if ((address & 0xFFFFFF) > 0xE00000) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2626 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2627 } else {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2628 printf("attempt to translate non-memory address: %X\n", address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2629 exit(1);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2630 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2631 do {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2632 do {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2633 if (dst_end-dst < 128) {
102 bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	2634 if (dst_end-dst < 5) {
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	2635 puts("out of code memory, not enough space for jmp to next chunk");
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	2636 exit(1);
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	2637 }
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	2638 size_t size = 1024*1024;
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	2639 opts->cur_code = alloc_code(&size);
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	2640 opts->code_end = opts->cur_code + size;
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	2641 jmp(dst, opts->cur_code);
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	2642 dst = opts->cur_code;
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	2643 dst_end = opts->code_end;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2644 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2645 next = m68k_decode(encoded, &instbuf, address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2646 address += (next-encoded)*2;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2647 encoded = next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2648 m68k_disasm(&instbuf, disbuf);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2649 printf("%X: %s\n", instbuf.address, disbuf);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2650 dst = translate_m68k(dst, &instbuf, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2651 } while(instbuf.op != M68K_ILLEGAL && instbuf.op != M68K_RTS && instbuf.op != M68K_RTE && !(instbuf.op == M68K_BCC && instbuf.extra.cond == COND_TRUE) && instbuf.op != M68K_JMP);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2652 process_deferred(opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2653 if (opts->deferred) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2654 address = opts->deferred->address;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2655 if ((address & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2656 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2657 } else if ((address & 0xFFFFFF) > 0xE00000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2658 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2659 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2660 printf("attempt to translate non-memory address: %X\n", address);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2661 exit(1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2662 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2663 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2664 encoded = NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2665 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2666 } while(encoded != NULL);
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2667 opts->cur_code = dst;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2668 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2669 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2670
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2671 uint8_t * get_native_address_trans(m68k_context * context, uint32_t address)
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2672 {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2673 address &= 0xFFFFFF;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2674 uint8_t * ret = get_native_address(context->native_code_map, address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2675 if (!ret) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2676 translate_m68k_stream(address, context);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2677 ret = get_native_address(context->native_code_map, address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2678 }
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2679 return ret;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2680 }
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2681
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2682 void start_68k_context(m68k_context * context, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2683 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2684 uint8_t * addr = get_native_address(context->native_code_map, address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2685 m68k_start_context(addr, context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2686 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2687
19 4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	2688 void m68k_reset(m68k_context * context)
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	2689 {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2690 //TODO: Make this actually use the normal read functions
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2691 context->aregs[7] = context->mem_pointers[0][0] << 16 \| context->mem_pointers[0][1];
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2692 uint32_t address = context->mem_pointers[0][2] << 16 \| context->mem_pointers[0][3];
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2693 start_68k_context(context, address);
19 4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	2694 }
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	2695
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2696 void init_x86_68k_opts(x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2697 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2698 opts->flags = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2699 for (int i = 0; i < 8; i++)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2700 opts->dregs[i] = opts->aregs[i] = -1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2701 opts->dregs[0] = R10;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2702 opts->dregs[1] = R11;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2703 opts->dregs[2] = R12;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2704 opts->aregs[0] = R13;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2705 opts->aregs[1] = R14;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2706 opts->aregs[7] = R15;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2707 opts->native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2708 memset(opts->native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2709 opts->deferred = NULL;
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2710 size_t size = 1024 * 1024;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2711 opts->cur_code = alloc_code(&size);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	2712 opts->code_end = opts->cur_code + size;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2713 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2714
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2715 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2716 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2717 memset(context, 0, sizeof(m68k_context));
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2718 context->native_code_map = native_code_map;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2719 context->options = opts;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2720 context->int_cycle = 0xFFFFFFFF;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2721 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2722

Mercurial > repos > blastem

annotate m68k_to_x86.c @ 124:da95566514f3