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Fix default target. Ensure m68k.h and z80.h are built before anything else when no dep info is available
author Michael Pavone <pavone@retrodev.com>
date Mon, 31 Mar 2025 21:06:18 -0700
parents 7e86ec94c899
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
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1 info
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2 prefix m68k_
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3 opcode_size 16
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4 body m68k_run_op
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5 header m68k.h
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6 interrupt m68k_interrupt
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7 include m68k_util.c
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8 sync_cycle m68k_sync_cycle
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9 pc_reg pc
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10 pc_offset 2
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11
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12 declare
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13 typedef m68k_context *(sync_fun)(m68k_context * context, uint32_t address);
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14 typedef m68k_context *(*int_ack_fun)(m68k_context * context);
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15 typedef m68k_context *(*m68k_reset_handler)(m68k_context *context);
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16 void init_m68k_opts(m68k_options *opts, memmap_chunk * memmap, uint32_t num_chunks, uint32_t clock_divider, sync_fun *sync_components, int_ack_fun int_ack);
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17 m68k_context *init_68k_context(m68k_options * opts, m68k_reset_handler *reset_handler);
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18 void m68k_reset(m68k_context *context);
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19 void m68k_print_regs(m68k_context *context);
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20 void m68k_serialize(m68k_context *context, uint32_t pc, serialize_buffer *buf);
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21 void m68k_deserialize(deserialize_buffer *buf, void *vcontext);
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22 void start_68k_context(m68k_context *context, uint32_t pc);
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23 void insert_breakpoint(m68k_context *context, uint32_t address, debug_handler handler);
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24 void remove_breakpoint(m68k_context *context, uint32_t address);
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25 uint16_t m68k_instruction_fetch(uint32_t address, void *vcontext);
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26 define NUM_MEM_AREAS 10
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27 define M68K_OPT_BROKEN_READ_MODIFY 1
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28 define INT_PENDING_SR_CHANGE 254
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29 define INT_PENDING_NONE 255
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30 define M68K_STATUS_TRACE 0x80
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31 define m68k_invalidate_code_range(context, start, end)
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32 define m68k_options_free free
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33 define m68k_handle_code_write(address, context)
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34 define resume_68k(context) m68k_execute(context, context->target_cycle)
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35 define m68k_add_watchpoint(context, address, size)
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36 define m68k_remove_watchpoint(context, address, size)
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37
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38 regs
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39 dregs 32 d0 d1 d2 d3 d4 d5 d6 d7
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40 aregs 32 a0 a1 a2 a3 a4 a5 a6 a7
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41 pc 32
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42 other_sp 32
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43 scratch1 32
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44 scratch2 32
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45 int_cycle 32
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46 target_cycle 32
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47 wp_hit_address 32
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48 prefetch 16
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49 wp_hit_value 16
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50 wp_old_value 16
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51 int_priority 8
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52 int_num 8
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53 int_pending 8
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54 int_pending_num 8
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55 int_ack 8
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56 status 8
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57 ccr 8
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58 xflag 8
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59 nflag 8
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60 zflag 8
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61 vflag 8
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62 cflag 8
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63 wp_hit 8
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64 trace_pending 8
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65 should_return 8
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66 stopped 8
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67 system ptrvoid
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68 reset_handler ptrvoid
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69 int_ack_handler ptrvoid
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70 sync_components ptrsync_fun
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71 mem_pointers ptr16 10
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72 read16 interp_read_16 256
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73 read8 interp_read_8 256
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74 write16 interp_write_16 256
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75 write8 interp_write_8 256
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76 read16_data ptrvoid 256
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77 read8_data ptrvoid 256
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78 write16_data ptrvoid 256
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79 write8_data ptrvoid 256
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80
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81 flags
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82 register ccr
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83 X 4 carry xflag
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84 N 3 sign nflag
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85 Z 2 zero zflag
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86 V 1 overflow vflag
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87 C 0 carry cflag
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88
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89 m68k_prefetch
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90 if dynarec
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91
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92 ccall m68k_read16_noinc context pc
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93 mov result prefetch
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94
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95 end
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96
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97 if interp
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98
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99 mov pc scratch1
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100 ocall read_16
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101 mov scratch1 prefetch
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102
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103 end
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104
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105 add 2 pc pc
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106
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107 check_user_mode_swap_ssp_usp
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108 local tmp 8
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109 and 0x20 status tmp
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110 if tmp
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111 else
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112 xchg other_sp a7
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113 end
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114
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115 m68k_get_sr
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116 lsl status 8 scratch1
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117 or ccr scratch1 scratch1
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118
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119 m68k_write32_lowfirst
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120 arg value 32
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121 add 2 scratch2 scratch2
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122 mov value scratch1
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123 ocall write_16
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124
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125 sub 2 scratch2 scratch2
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126 lsr value 16 scratch1
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127 ocall write_16
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128
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129 m68k_write32
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130 arg value 32
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131 local tmp 32
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132 mov value tmp
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133 lsr value 16 scratch1
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134 ocall write_16
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135
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136 add 2 scratch2 scratch2
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137 mov tmp scratch1
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138 ocall write_16
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139
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140 m68k_read32
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
141 local tmp 32
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
142 add 2 scratch1 tmp
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
143 ocall read_16
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
144 xchg scratch1 tmp
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
145 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
146 lsl tmp 16 tmp
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Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
147 or tmp scratch1 scratch1
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
148
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
149 m68k_trap
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
150 arg vector 32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
151 check_user_mode_swap_ssp_usp
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
152 #save PC
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
153 a7 -= 4
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
154 scratch2 = a7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
155 m68k_write32_lowfirst pc
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
156 #save SR
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
157 a7 -= 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
158 scratch2 = a7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
159 m68k_get_sr
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
160 ocall write_16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
161 #set supervisor bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
162 status |= 0x20
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
163 #clear trace bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
164 status &= 0x7F
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
165 trace_pending = 0
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
166 scratch1 = vector << 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
167 m68k_read32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
168 pc = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
169 cycles 10
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
170 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
171
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
172
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
173
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
174 m68k_interrupt
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
175 if cycles >=U int_cycle
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
176
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
177 #INT_PENDING_NONE
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
178 if 255 = int_pending
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
179 int_pending = int_priority
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
180 int_pending_num = int_num
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
181 else
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
182 #INT_PENDING_SR_CHANGE
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Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
183 if 254 = int_pending
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
184 int_pending = int_priority
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
185 int_pending_num = int_num
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
186
2580
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
187 end
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
188
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
189 check_user_mode_swap_ssp_usp
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
190
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
191 cycles 6
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
192 #save status reg
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
193 a7 -= 6
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
194 m68k_get_sr
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
195 scratch2 = a7
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
196 ocall write_16
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
197
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
198 #update status register
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
199 status &= 0x78
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
200 status |= int_pending
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
201 status |= 0x20
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
202
2580
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
203 #Interrupt ack cycle
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
204 int_ack = int_pending
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
205 cycles 4
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
206 if int_ack_handler
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
207 pcall int_ack_handler int_ack_fun context
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
208 end
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
209 if int_pending_num
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
210 else
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
211 int_pending_num = int_pending + 24
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
212 end
2580
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
213
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
214 #save pc
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
215 scratch2 = a7 + 2
2618
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
216 if stopped
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
217 scratch1 = pc
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
218 stopped = 0
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
219 else
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
220 scratch1 = pc - 2
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
221 end
2580
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
222 m68k_write32_lowfirst scratch1
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
223
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
224 scratch1 = int_pending_num << 2
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
225 int_pending = 255 #INT_PENDING_NONE
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
226 int_pending_num = 0
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
227 m68k_read32
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
228 mov scratch1 pc
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
229 m68k_prefetch
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
230 update_sync
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
231 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
232 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
233
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
234 m68k_run_op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235 dispatch prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
236
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
237 m68k_mem_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238 arg address 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
239 arg size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
240 arg isdst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
241 mov address scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
242 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
243 mov address scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
244 meta ismem 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
245 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
246 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
247
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
248 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
249 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
250
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
251 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
252 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
253
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
254 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
255 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
256
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
257 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
258 meta op scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
259
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
260 m68k_write_size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
261 arg size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
262 arg lowfirst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
263 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
264 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
265 ocall write_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
266
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
267 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
268 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
269
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
270 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
271 if lowfirst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
272 m68k_write32_lowfirst scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
273 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
274 m68k_write32 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
275 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
276 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
277
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
278 m68k_index_word
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
279 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
280 local disp 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
281 and prefetch 255 disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
282 sext 16 disp disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
283 sext 32 disp disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
284 local index 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
285 lsr prefetch 12 index
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
286 local isareg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
287 and index 8 isareg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
288 and index 7 index
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
289 local islong 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
290 and prefetch 2048 islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
291
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
292 switch isareg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
293 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
294 switch islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
295 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
296 sext 32 dregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
297 case 2048
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
298 mov dregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
299 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
300 case 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
301 switch islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
302 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
303 sext 32 aregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
304 case 2048
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
305 mov aregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
306 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
307 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
308 add disp scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
309
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
310 m68k_fetch_op_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
311 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
312 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
313 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
314 arg isdst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
315 switch mode
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
316
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
317 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
318 #data reg direct
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
319 meta op dregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
320 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
321 meta ismem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
322 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
323
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
324 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
325 #address reg direct
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
326 meta op aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
327 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
328 meta ismem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
329 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
330
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
331 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
332 #address reg indirect
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
333 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
334
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
335 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
336 #postincrement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
337 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
338 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
339 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
340 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
341 addsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
342 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
343 addsize 1 aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
344 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
345 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
346 addsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
347 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
348
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
349 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
350 #predecrement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
351 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
352 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
353 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
354 decsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
355 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
356 decsize 1 aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
357 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
358 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
359 decsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
360 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
361 cycles 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
362 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
363
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
364 case 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
365 #displacement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
366 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
367 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
368 add scratch1 aregs.reg scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
369 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
370
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
371 case 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
372 #indexed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
373 m68k_index_word
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
374 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
375 add aregs.reg scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
376
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
377 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
378 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
379 #pc-relative and absolute modes
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
380
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
381 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
382 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
383 #absolute short
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
384 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
385 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
386 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
387
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
388 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
389 #absolute long
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
390 local address 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
391 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
392 lsl prefetch 16 address
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
393 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
394 or prefetch address scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
395 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
396
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
397 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
398 #pc displaceent
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
399 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
400 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
401 add scratch1 pc scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
402 sub 2 scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
403 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
404
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
405 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
406 #pc indexed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
407 m68k_index_word
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
408 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
409 add pc scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
410 sub 2 scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
411 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
412
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
413 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
414 #immediate
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
415 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
416 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
417 local tmp32 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
418 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
419 lsl prefetch 16 tmp32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
420 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
421 or prefetch tmp32 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
422
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
423 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
424 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
425 mov prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
426 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
427 meta op scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
428
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
429 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
430
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
431 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
432
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
433 m68k_fetch_src_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
434 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
435 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
436 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
437 m68k_fetch_op_ea mode reg Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
438 meta src op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
439 switch mode
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
440 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
441 meta src_is_mem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
442 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
443 meta src_is_mem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
444 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
445 meta src_is_mem 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
446 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
447
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
448 m68k_fetch_dst_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
449 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
450 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
451 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
452 m68k_fetch_op_ea mode reg Z 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
453 meta dst op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
454
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
455 m68k_save_dst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
456 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
457 if ismem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
458 m68k_write_size Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
459 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
460
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
461 1101DDD0ZZMMMRRR add_ea_dn
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
462 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
463 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
464 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
465 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
466 m68k_fetch_src_ea M R Z
2671
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
467 if Z = 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
468 switch M
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
469 case 0
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
470 #dreg src
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
471 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
472 case 1
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
473 #areg src
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
474 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
475 case 7
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
476 if R = 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
477 #immediate
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
478 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
479 else
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
480 cycles 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
481 end
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
482 default
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
483 cycles 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
484 end
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
485 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
486
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
487 add src dregs.D dregs.D Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
488 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
489 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
490
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
491 1101DDD1ZZMMMRRR add_dn_ea
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
492 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
493 invalid M 1
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
494 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
495 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
496 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
497 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
498 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
499 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
500 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
501 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
502
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
503 add dregs.D dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
505 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
506 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
507
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
508 1101AAAZ11MMMRRR adda
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
509 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
510 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
511 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
512 local size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
513 local ext_src 32
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
514 #TODO: ensure "penalty" cycles are in the right place
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
515 if Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
516 size = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
517 switch M
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
518 case 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
519 #dreg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
520 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
521 case 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
522 #areg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
523 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
524 case 7
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
525 if R = 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
526 #immediate
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
527 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
528 else
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
529 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
530 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
531 default
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
532 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
533 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
534 else
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
535 size = 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
536 cycles 4
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
537 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
538 m68k_fetch_src_ea M R size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
539 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
540 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
541 sext 32 src ext_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
542 meta src ext_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
543 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
544
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
545 add src aregs.A aregs.A
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
546 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
547
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
548 00000110ZZMMMRRR addi
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
549 local immed 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
550 invalid Z 3
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
551 invalid M 1
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
552 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
553 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
554 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
555 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
556 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
557 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
558 #fetch immediate operand
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
559 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
560 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
561 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
562 lsl prefetch 16 immed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
563 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
564 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
565 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
566 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
567 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
568 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
569 mov prefetch immed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
570 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
571 #fetch dst EA
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
572 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
573
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
574 add immed dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
575 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
576 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
577 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
578
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
579 0101III0ZZMMMRRR addq
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
580 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
581 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
582 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
583 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
584 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
585 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
586 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
587 local src 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
588 switch I
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
589 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
590 mov 8 src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
591 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
592 mov I src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
593 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
594
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
595 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
596 switch M
2671
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
597 case 0
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
598 if Z = 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
599 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
600 end
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
601 add src dst dst Z
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
602 update_flags XNZVC
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
603 case 1
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
604 cycles 4
2647
3c689000e571 Fix addq.w and subq.w with address register destination in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2646
diff changeset
605 add src dst dst 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
606 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
607 add src dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
608 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
609 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
610 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
611 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
612
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
613 1101DDD1ZZ000SSS addx_dy_dx
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
614 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
615 adc dregs.S dregs.D dregs.D Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
616 update_flags XNVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
617 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
618 case 0
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
619 local tmp8 8
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
620 mov dregs.D tmp8
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
621 if tmp8
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
622 update_flags Z0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
623 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
624 case 1
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
625 local tmp16 16
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
626 mov dregs.D tmp16
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
627 if tmp16
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
628 update_flags Z0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
629 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
630 case 2
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
631 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
632 if dregs.D
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
633 update_flags Z0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
634 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
635 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
636 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
637
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
638 1101DDD1ZZ001SSS addx_ay_ax
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
639 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
640 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
641 decsize Z aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
642 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
643 switch S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
644 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
645 sub 2 aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
646 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
647 decsize Z aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
648 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
649 end
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
650 #predec penalty on src only
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
651 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
652 mov aregs.S scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
653 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
654 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
655 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
656 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
657 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
658 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
659 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
660 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
661 mov scratch1 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
662 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
663 decsize Z aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
664 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
665 switch D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
666 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
667 sub 2 aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
668 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
669 decsize Z aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
670 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
671 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
672 mov aregs.D scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
673 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
674 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
675 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
676 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
677 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
678 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
679 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
680 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
681 adc scratch2 scratch1 scratch1 Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
682 update_flags XNVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
683 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
684 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
685 local tmp8 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
686 mov dregs.D tmp8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
687 if tmp8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
688 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
689 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
690 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
691 local tmp16 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
692 mov dregs.D tmp16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
693 if tmp16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
694 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
695 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
696 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
697 if dregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
698 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
699 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
700 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
701 mov aregs.D scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
702 m68k_write_size Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
703 m68k_prefetch
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
704
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
705 1100DDD0ZZMMMRRR and_ea_dn
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
706 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
707 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
708 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
709 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
710 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
711 m68k_fetch_src_ea M R Z
2671
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
712 if Z = 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
713 switch M
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
714 case 0
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
715 #dreg src
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
716 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
717 case 1
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
718 #areg src
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
719 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
720 case 7
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
721 if R = 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
722 #immediate
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
723 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
724 else
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
725 cycles 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
726 end
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
727 default
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
728 cycles 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
729 end
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
730 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
731
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
732 and src dregs.D dregs.D Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
733 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
734 m68k_prefetch
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
735
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
736 1100XXX100000YYY abcd_dy_dx
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
737 local lowx_corf 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
738 local lowy_cmp 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
739 local res 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
740 lowx_corf = dregs.X & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
741 lowy_cmp = dregs.Y & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
742 adc lowx_corf lowy_cmp lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
743 if lowy_cmp >=U 0xA
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
744 lowx_corf = 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
745 lowy_cmp = 0x9A
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
746 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
747 lowx_corf = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
748 lowy_cmp = 0xA0
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
749 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
750 adc dregs.Y dregs.X res 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
751 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
752 if cflag
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
753 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
754 res += lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
755 update_flags NV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
756 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
757 if res >=U lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
758 lowx_corf |= 0x60
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
759 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
760 res += lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
761 update_flags XCNV
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
762 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
763 if res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
764 update_flags Z0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
765 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
766 dregs.X:0 = res
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
767 cycles 2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
768 m68k_prefetch
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
769
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
770 1100XXX100001YYY abcd_ay_ax
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
771 local lowx_corf 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
772 local lowy_cmp 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
773 local res 8
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
774 if Y = 7
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
775 aregs.Y -= 2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
776 else
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
777 aregs.Y -= 1
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
778 end
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
779 #predec penalty on src only
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
780 cycles 2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
781 scratch1 = aregs.Y
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
782 ocall read_8
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
783 scratch2 = scratch1
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
784 if X = 7
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
785 aregs.X -= 2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
786 else
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
787 aregs.X -= 1
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
788 end
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
789 scratch1 = aregs.X
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
790 ocall read_8
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
791 lowx_corf = scratch1 & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
792 lowy_cmp = scratch2 & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
793 adc lowx_corf lowy_cmp lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
794 if lowy_cmp >=U 0xA
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
795 lowx_corf = 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
796 lowy_cmp = 0x9A
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
797 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
798 lowx_corf = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
799 lowy_cmp = 0xA0
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
800 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
801 adc scratch2 scratch1 res 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
802 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
803 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
804 if cflag
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
805 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
806 res += lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
807 update_flags NV
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
808 else
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
809 if res >=U lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
810 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
811 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
812 res += lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
813 update_flags XCNV
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
814 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
815 if res
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
816 update_flags Z0
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
817 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
818 scratch1 = res
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
819 scratch2 = aregs.X
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
820 ocall write_8
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
821 m68k_prefetch
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
822
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
823 1100XXX101000YYY exg_dn_dn
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
824 scratch1 = dregs.X
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
825 dregs.X = dregs.Y
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
826 dregs.Y = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
827 cycles 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
828 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
829
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
830 1100XXX101001YYY exg_an_an
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
831 scratch1 = aregs.X
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
832 aregs.X = aregs.Y
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
833 aregs.Y = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
834 cycles 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
835 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
836
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
837 1100XXX110001YYY exg_dn_an
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
838 scratch1 = dregs.X
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
839 dregs.X = aregs.Y
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
840 aregs.Y = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
841 cycles 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
842 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
843
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
844 1100DDD011MMMRRR mulu
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
845 local a 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
846 local b 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
847 invalid M 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
848 invalid M 7 R 5
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
849 invalid M 7 R 6
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
850 invalid M 7 R 7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
851
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
852 m68k_fetch_src_ea M R 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
853 #2-cycles per bit x 16, 2 for cleanup
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
854 cycles 34
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
855 #popcnt
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
856 a = src & 0b1010101010101010
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
857 a >>= 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
858 b = src & 0b0101010101010101
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
859 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
860 a = b & 0b1100110011001100
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
861 a >>= 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
862 b &= 0b0011001100110011
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
863 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
864 a = b & 0b1111000011110000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
865 a >>= 4
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
866 b &= 0b0000111100001111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
867 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
868 a = b & 0b1111111100000000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
869 a >>= 8
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
870 b &= 0b0000000011111111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
871 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
872 #2 cycles per set bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
873 b += b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
874 cycles b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
875 dregs.D = src * dregs.D
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
876 update_flags NZV0C0
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
877 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
878
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
879 1100DDD111MMMRRR muls
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
880 local a 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
881 local b 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
882 invalid M 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
883 invalid M 7 R 5
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
884 invalid M 7 R 6
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
885 invalid M 7 R 7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
886
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
887 m68k_fetch_src_ea M R 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
888 #2-cycles per bit x 16, 2 for cleanup
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
889 cycles 34
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
890 #muls timing is essentially the same as muls, but it's based on the number of 0/1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
891 #transitions rather than the number of 1 bits. xoring the value with itself shifted
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
892 #by one effectively sets one bit for every transition
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
893 b = src << 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
894 b ^= src
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
895 #popcnt
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
896 a = b & 0b1010101010101010
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
897 a >>= 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
898 b &= 0b0101010101010101
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
899 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
900 a = b & 0b1100110011001100
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
901 a >>= 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
902 b &= 0b0011001100110011
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
903 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
904 a = b & 0b1111000011110000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
905 a >>= 4
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
906 b &= 0b0000111100001111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
907 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
908 a = b & 0b1111111100000000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
909 a >>= 8
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
910 b &= 0b0000000011111111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
911 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
912 #2 cycles per set bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
913 b += b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
914 cycles b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
915 dregs.D = src *S dregs.D
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
916 update_flags NZV0C0
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
917 m68k_prefetch
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
918
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
919 1100DDD1ZZMMMRRR and_dn_ea
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
920 invalid M 0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
921 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
922 invalid M 7 R 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
923 invalid M 7 R 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
924 invalid M 7 R 4
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
925 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
926 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
927 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
928 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
929 m68k_fetch_dst_ea M R Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
930
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
931 and dregs.D dst dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
932 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
933 m68k_save_dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
934 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
935
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
936 00000010ZZMMMRRR andi
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
937 local immed 32
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
938 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
939 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
940 invalid M 7 R 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
941 invalid M 7 R 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
942 invalid M 7 R 4
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
943 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
944 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
945 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
946 #fetch immediate operand
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
947 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
948 switch Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
949 case 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
950 lsl prefetch 16 immed
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
951 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
952 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
953 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
954 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
955 end
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
956 default
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
957 mov prefetch immed
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
958 end
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
959 #fetch dst EA
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
960 m68k_fetch_dst_ea M R Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
961
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
962 and immed dst dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
963 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
964 m68k_save_dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
965 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
966
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
967 0000001000111100 andi_to_ccr
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
968 #fetch immediate operand
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
969 m68k_prefetch
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
970 ccr &= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
971 cycles 12 #TODO: where do these occur relative to fetches
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
972 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
973
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
974 0000001001111100 andi_to_sr
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
975 #TODO: privilege violation exception if in user mode
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
976 #fetch immediate operand
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
977 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
978 ccr &= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
979 scratch1 = prefetch >> 8
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
980 status &= scratch1
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
981 check_user_mode_swap_ssp_usp
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
982 update_sync
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
983 cycles 12 #TODO: where do these occur relative to fetches
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
984 m68k_prefetch
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
985
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
986 1011DDD1ZZMMMRRR eor_dn_ea
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
987 invalid M 1
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
988 invalid M 7 R 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
989 invalid M 7 R 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
990 invalid M 7 R 4
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
991 invalid M 7 R 5
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
992 invalid M 7 R 6
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
993 invalid M 7 R 7
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
994 invalid Z 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
995 m68k_fetch_dst_ea M R Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
996
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
997 if Z = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
998 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
999 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1000 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1001 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1002
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1003 xor dregs.D dst dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1004 update_flags NZV0C0
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1005 m68k_save_dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1006 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1007
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1008 00001010ZZMMMRRR eori
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1009 local immed 32
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1010 invalid Z 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1011 invalid M 1
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1012 invalid M 7 R 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1013 invalid M 7 R 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1014 invalid M 7 R 4
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1015 invalid M 7 R 5
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1016 invalid M 7 R 6
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1017 invalid M 7 R 7
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1018 #fetch immediate operand
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1019 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1020 switch Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1021 case 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1022 lsl prefetch 16 immed
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1023 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1024 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1025 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1026 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1027 end
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1028 default
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1029 mov prefetch immed
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1030 end
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1031 #fetch dst EA
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1032 m68k_fetch_dst_ea M R Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1033
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1034 xor immed dst dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1035 update_flags NZV0C0
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1036 m68k_save_dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1037 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1038
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1039 0000101000111100 eori_to_ccr
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1040 #fetch immediate operand
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1041 m68k_prefetch
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1042 ccr ^= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1043 cycles 12 #TODO: where do these occur relative to fetches
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1044 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1045
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1046 0000101001111100 eori_to_sr
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1047 #TODO: privilege violation exception if in user mode
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1048 #fetch immediate operand
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1049 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1050 ccr ^= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1051 scratch1 = prefetch >> 8
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1052 status ^= scratch1
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1053 check_user_mode_swap_ssp_usp
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1054 update_sync
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1055 cycles 12 #TODO: where do these occur relative to fetches
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1056 m68k_prefetch
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1057
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1058 1000DDD0ZZMMMRRR or_ea_dn
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1059 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1060 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1061 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1062 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1063 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1064 m68k_fetch_src_ea M R Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1065
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1066 if Z = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1067 switch M
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1068 case 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1069 #dreg
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1070 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1071 case 7
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1072 if R = 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1073 #immediate
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1074 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1075 else
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1076 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1077 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1078 default
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1079 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1080 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1081 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1082
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1083 or src dregs.D dregs.D Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1084 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1085 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1086
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1087 1000DDD1ZZMMMRRR or_dn_ea
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1088 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1089 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1090 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1091 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1092 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1093 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1094 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1095 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1096 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1097 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1098
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1099 or dregs.D dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1100 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1101 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1102 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1103
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1104 00000000ZZMMMRRR ori
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1105 local immed 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1106 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1107 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1108 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1109 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1110 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1111 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1112 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1113 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1114 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1115 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1116 switch Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1117 case 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1118 lsl prefetch 16 immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1119 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1120 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1121 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1122 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1123 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1124 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1125 mov prefetch immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1126 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1127 #fetch dst EA
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1128 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1129
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1130 or immed dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1131 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1132 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1133 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1134
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1135 0000000000111100 ori_to_ccr
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1136 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1137 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1138 or prefetch ccr ccr
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1139 cycles 12 #TODO: where do these occur relative to fetches
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1140 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1141
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1142 0000000001111100 ori_to_sr
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1143 #TODO: privilege violation exception if in user mode
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1144 #fetch immediate operand
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1145 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1146 ccr |= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1147 scratch1 = prefetch >> 8
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1148 status |= scratch1
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1149 update_sync
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1150 cycles 12 #TODO: where do these occur relative to fetches
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1151 m68k_prefetch
2587
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1152
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1153 1000YYY100000XXX sbcd_dx_dy
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1154 local lowx_corf 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1155 local lowy 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1156 local res 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1157 lowx_corf = dregs.X & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1158 lowy = dregs.Y & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1159 sbc lowx_corf lowy lowy
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1160 if lowy >=U 0x10
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1161 lowx_corf = 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1162 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1163 lowx_corf = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1164 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1165 sbc dregs.X dregs.Y res 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1166 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1167 if cflag
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1168 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1169 res -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1170 update_flags NV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1171 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1172 res -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1173 update_flags XCNV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1174 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1175 if res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1176 update_flags Z0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1177 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1178 dregs.Y:0 = res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1179 cycles 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1180 m68k_prefetch
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1181
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1182 1000YYY100001XXX sbcd_ax_ay
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1183 local lowx_corf 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1184 local lowy 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1185 if X = 7
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1186 aregs.X -= 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1187 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1188 aregs.X -= 1
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1189 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1190 #predec penalty on src only
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1191 cycles 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1192 scratch1 = aregs.X
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1193 ocall read_8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1194 scratch2 = scratch1
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1195 if Y = 7
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1196 aregs.Y -= 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1197 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1198 aregs.Y -= 1
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1199 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1200 scratch1 = aregs.Y
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1201 ocall read_8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1202 lowy = scratch1 & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1203 lowx_corf = scratch2 & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1204 sbc lowx_corf lowy lowy
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1205 if lowy >=U 0x10
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1206 lowx_corf = 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1207 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1208 lowx_corf = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1209 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1210 sbc scratch2 scratch1 scratch1 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1211 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1212 if cflag
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1213 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1214 scratch1:0 -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1215 update_flags NV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1216 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1217 scratch1:0 -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1218 update_flags XCNV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1219 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1220 scratch1 &= 0xFF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1221 if scratch1
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1222 update_flags Z0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1223 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1224 scratch2 = aregs.Y
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1225 ocall write_8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1226 m68k_prefetch
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1227
2587
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1228 1000DDD011MMMRRR divu
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1229 invalid M 1
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1230 invalid M 7 R 5
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1231 invalid M 7 R 6
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1232 invalid M 7 R 7
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1233 m68k_fetch_src_ea M R 1
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1234
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1235 if src = 0
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1236 cycles 4
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1237 update_flags N0Z0V0
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1238 m68k_trap 5
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1239 else
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1240 ccall divu context D src
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1241 m68k_prefetch
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1242 end
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1243
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1244
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1245 1000DDD111MMMRRR divs
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1246 invalid M 1
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1247 invalid M 7 R 5
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1248 invalid M 7 R 6
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1249 invalid M 7 R 7
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1250 local tmp 32
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1251 m68k_fetch_src_ea M R 1
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1252
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1253 if src = 0
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1254 cycles 4
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1255 update_flags N0Z0V0
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1256 m68k_trap 5
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1257 else
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1258 ccall divs context D src
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1259 m68k_prefetch
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1260 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1261
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1262 1001DDD0ZZMMMRRR sub_ea_dn
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1263 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1264 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1265 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1266 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1267 m68k_fetch_src_ea M R Z
2671
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1268 if Z = 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1269 switch M
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1270 case 0
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1271 #dreg src
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1272 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1273 case 1
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1274 #areg src
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1275 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1276 case 7
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1277 if R = 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1278 #immediate
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1279 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1280 else
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1281 cycles 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1282 end
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1283 default
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1284 cycles 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1285 end
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1286 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1287
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1288 sub src dregs.D dregs.D Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1289 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1290 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1291
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1292 1001DDD1ZZMMMRRR sub_dn_ea
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1293 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1294 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1295 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1296 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1297 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1298 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1299 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1300 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1301 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1302 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1303
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1304 sub dregs.D dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1305 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1306 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1307 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1308
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1309 1001AAAZ11MMMRRR suba
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1310 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1311 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1312 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1313 local size 16
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1314 local ext_src 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1315 if Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1316 size = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1317 switch M
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1318 case 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1319 #dreg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1320 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1321 case 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1322 #areg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1323 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1324 case 7
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1325 if R = 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1326 #immediate
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1327 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1328 else
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1329 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1330 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1331 default
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1332 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1333 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1334 else
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1335 size = 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1336 cycles 4
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1337 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1338 m68k_fetch_src_ea M R size
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1339 switch size
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1340 case 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1341 sext 32 src ext_src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1342 meta src ext_src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1343 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1344
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1345 sub src aregs.A aregs.A
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1346 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1347
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1348 00000100ZZMMMRRR subi
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1349 local immed 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1350 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1351 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1352 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1353 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1354 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1355 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1356 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1357 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1358 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1359 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1360 switch Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1361 case 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1362 lsl prefetch 16 immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1363 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1364 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1365 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1366 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1367 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1368 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1369 mov prefetch immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1370 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1371 #fetch dst EA
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1372 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1373
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1374 sub immed dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1375 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1376 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1377 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1378
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1379 0101III1ZZMMMRRR subq
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1380 invalid Z 3
2647
3c689000e571 Fix addq.w and subq.w with address register destination in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2646
diff changeset
1381 invalid M 1 Z 0
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1382 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1383 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1384 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1385 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1386 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1387 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1388 local src 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1389 switch I
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1390 case 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1391 mov 8 src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1392 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1393 mov I src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1394 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1395
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1396 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1397 switch M
2671
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1398 case 0
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1399 if Z = 2
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1400 cycles 4
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1401 end
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1402 sub src dst dst Z
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1403 update_flags XNZVC
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1404 case 1
2671
e0935d5878c3 Fix some cycle timing issues in the new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2670
diff changeset
1405 cycles 4
2647
3c689000e571 Fix addq.w and subq.w with address register destination in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2646
diff changeset
1406 sub src dst dst 2
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1407 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1408 sub src dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1409 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1410 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1411 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1412 m68k_prefetch
2586
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1413
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1414 1001DDD1ZZ000SSS subx_dy_dx
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1415 invalid Z 3
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1416 sbc dregs.S dregs.D dregs.D Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1417 update_flags XNVC
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1418 switch Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1419 case 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1420 local tmp8 8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1421 mov dregs.D tmp8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1422 if tmp8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1423 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1424 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1425 case 1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1426 local tmp16 16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1427 mov dregs.D tmp16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1428 if tmp16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1429 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1430 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1431 case 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1432 cycles 4
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1433 if dregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1434 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1435 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1436 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1437 m68k_prefetch
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1438
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1439 1001DDD1ZZ001SSS subx_ay_ax
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1440 invalid Z 3
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1441 if Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1442 decsize Z aregs.S aregs.S
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1443 else
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1444 switch S
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1445 case 7
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1446 sub 2 aregs.S aregs.S
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1447 default
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1448 decsize Z aregs.S aregs.S
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1449 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1450 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1451 #predec penalty on src only
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1452 cycles 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1453 mov aregs.S scratch1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1454 switch Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1455 case 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1456 ocall read_8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1457 case 1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1458 ocall read_16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1459 case 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1460 m68k_read32
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1461 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1462 mov scratch1 scratch2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1463 if Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1464 decsize Z aregs.D aregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1465 else
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1466 switch D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1467 case 7
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1468 sub 2 aregs.D aregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1469 default
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1470 decsize Z aregs.D aregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1471 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1472 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1473 mov aregs.D scratch1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1474 switch Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1475 case 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1476 ocall read_8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1477 case 1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1478 ocall read_16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1479 case 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1480 m68k_read32
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1481 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1482 sbc scratch2 scratch1 scratch1 Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1483 update_flags XNVC
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1484 switch Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1485 case 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1486 local tmp8 8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1487 mov dregs.D tmp8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1488 if tmp8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1489 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1490 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1491 case 1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1492 local tmp16 16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1493 mov dregs.D tmp16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1494 if tmp16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1495 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1496 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1497 case 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1498 if dregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1499 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1500 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1501 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1502 mov aregs.D scratch2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1503 m68k_write_size Z 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1504 m68k_prefetch
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1505
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1506 1110CCC0ZZ001RRR lsri
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1507 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1508 switch C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1509 case 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1510 meta shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1511 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1512 meta shift C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1513 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1514 lsr dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1515 update_flags XNZV0C
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1516 local cyc 32
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1517 cyc = shift + shift
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1518 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1519 case 2
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1520 cyc += 4
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1521 default
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1522 cyc += 2
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1523 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1524 cycles cyc
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1525 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1526 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1527
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1528 1110CCC0ZZ101RRR lsr_dn
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1529 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1530 local shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1531 and dregs.C 63 shift
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1532 switch Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1533 case 2
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1534 if shift >=U 32
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1535 if shift = 32
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1536 lsr dregs.R 31 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1537 lsr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1538 update_flags XN0Z1V0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1539 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1540 dregs.R:Z = 0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1541 update_flags X0N0Z1V0C0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1542 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1543 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1544 lsr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1545 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1546 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1547 xflag = cflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1548 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1549 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1550 case 1
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1551 if shift >=U 16
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1552 if shift = 16
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1553 lsr dregs.R 15 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1554 lsr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1555 update_flags XN0Z1V0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1556 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1557 dregs.R:Z = 0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1558 update_flags X0N0Z1V0C0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1559 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1560 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1561 lsr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1562 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1563 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1564 xflag = cflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1565 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1566 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1567 case 0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1568 if shift >=U 8
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1569 if shift = 8
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1570 lsr dregs.R 7 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1571 lsr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1572 update_flags XN0Z1V0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1573 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1574 dregs.R:Z = 0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1575 update_flags X0N0Z1V0C0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1576 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1577 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1578 lsr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1579 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1580 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1581 xflag = cflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1582 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1583 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1584 end
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1585 add shift shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1586 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1587 case 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1588 add 4 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1589 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1590 add 2 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1591 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1592 cycles shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1593 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1594 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1595
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1596 1110001011MMMRRR lsr_ea
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1597 invalid M 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1598 invalid M 1
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1599 invalid M 7 R 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1600 invalid M 7 R 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1601 invalid M 7 R 4
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1602 invalid M 7 R 5
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1603 invalid M 7 R 6
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1604 invalid M 7 R 7
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1605
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1606 m68k_fetch_dst_ea M R 1
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1607 lsr dst 1 dst 1
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1608 update_flags XNZV0C
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1609 m68k_save_dst 1
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1610 m68k_prefetch
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1611
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1612 1110CCC0ZZ000RRR asri
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1613 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1614 switch C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1615 case 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1616 meta shift 8
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1617 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1618 meta shift C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1619 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1620 asr dregs.R shift dregs.R Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1621 update_flags XNZV0C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1622 local cyc 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1623 cyc = shift + shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1624 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1625 case 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1626 cyc += 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1627 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1628 cyc += 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1629 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1630 cycles cyc
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1631 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1632 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1633
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1634 1110CCC0ZZ100RRR asr_dn
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1635 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1636 local shift 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1637 and dregs.C 63 shift
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1638 switch Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1639 case 2
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1640 if shift >=U 32
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1641 asr dregs.R 31 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1642 asr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1643 update_flags NZV0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1644 cflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1645 xflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1646 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1647 asr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1648 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1649 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1650 xflag = cflag
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1651 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1652 end
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1653 case 1
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1654 if shift >=U 16
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1655 asr dregs.R 15 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1656 asr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1657 update_flags NZV0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1658 cflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1659 xflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1660 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1661 asr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1662 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1663 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1664 xflag = cflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1665 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1666 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1667 case 0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1668 if shift >=U 8
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1669 asr dregs.R 7 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1670 asr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1671 update_flags NZV0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1672 cflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1673 xflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1674 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1675 asr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1676 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1677 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1678 xflag = cflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1679 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1680 end
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1681 end
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1682 shift += shift
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1683 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1684 case 2
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1685 shift += 4
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1686 default
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1687 shift += 2
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1688 end
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1689 cycles shift
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1690 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1691 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1692
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1693 1110000011MMMRRR asr_ea
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1694 invalid M 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1695 invalid M 1
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1696 invalid M 7 R 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1697 invalid M 7 R 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1698 invalid M 7 R 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1699 invalid M 7 R 5
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1700 invalid M 7 R 6
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1701 invalid M 7 R 7
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1702
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1703 m68k_fetch_dst_ea M R 1
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1704 asr dst 1 dst 1
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1705 update_flags XNZV0C
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1706 m68k_save_dst 1
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1707 m68k_prefetch
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1708
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1709 1110CCC1ZZ001RRR lsli
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1710 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1711 switch C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1712 case 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1713 meta shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1714 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1715 meta shift C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1716 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1717 lsl dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1718 update_flags XNZV0C
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1719 local cyc 32
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1720 cyc = shift + shift
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1721 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1722 case 2
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1723 cyc += 4
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1724 default
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1725 cyc += 2
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1726 end
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1727 cycles cyc
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1728 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1729 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1730
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1731 1110CCC1ZZ101RRR lsl_dn
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1732 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1733 local shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1734 and dregs.C 63 shift
2610
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1735 switch Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1736 case 2
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1737 if shift >=U 32
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1738 if shift = 32
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1739 lsl dregs.R 31 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1740 lsl dregs.R 1 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1741 update_flags XN0Z1V0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1742 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1743 dregs.R:Z = 0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1744 update_flags X0N0Z1V0C0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1745 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1746 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1747 lsl dregs.R shift dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1748 update_flags NZV0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1749 if shift
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1750 xflag = cflag
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1751 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1752 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1753 case 1
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1754 if shift >=U 16
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1755 if shift = 16
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1756 lsl dregs.R 15 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1757 lsl dregs.R 1 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1758 update_flags XN0Z1V0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1759 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1760 dregs.R:Z = 0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1761 update_flags X0N0Z1V0C0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1762 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1763 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1764 lsl dregs.R shift dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1765 update_flags NZV0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1766 if shift
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1767 xflag = cflag
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1768 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1769 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1770 case 0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1771 if shift >=U 8
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1772 if shift = 8
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1773 lsl dregs.R 7 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1774 lsl dregs.R 1 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1775 update_flags XN0Z1V0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1776 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1777 dregs.R:Z = 0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1778 update_flags X0N0Z1V0C0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1779 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1780 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1781 lsl dregs.R shift dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1782 update_flags NZV0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1783 if shift
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1784 xflag = cflag
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1785 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1786 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1787 end
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1788 add shift shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1789 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1790 case 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1791 add 4 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1792 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1793 add 2 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1794 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1795 cycles shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1796 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1797 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1798
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1799 1110001111MMMRRR lsl_ea
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1800 invalid M 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1801 invalid M 1
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1802 invalid M 7 R 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1803 invalid M 7 R 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1804 invalid M 7 R 4
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1805 invalid M 7 R 5
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1806 invalid M 7 R 6
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1807 invalid M 7 R 7
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1808
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1809 m68k_fetch_dst_ea M R 1
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1810 lsl dst 1 dst 1
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1811 update_flags XNZV0C
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1812 m68k_save_dst 1
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1813 m68k_prefetch
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1814
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1815 1110CCC1ZZ000RRR asli
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1816 invalid Z 3
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1817 local vtmp 8
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1818 local shift 8
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1819 vtmp = 0
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1820 switch C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1821 case 0
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1822 shift = 8
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1823 default
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1824 shift = C
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1825 end
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1826 shift -= 1
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1827 loop shift
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1828 lsl dregs.R 1 dregs.R Z
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1829 update_flags V
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1830 vtmp |= vflag
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1831 end
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1832 shift += 1
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1833 lsl dregs.R 1 dregs.R Z
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1834 update_flags XNZVC
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1835 vflag |= vtmp
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1836 local cyc 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1837 cyc = shift + shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1838 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1839 case 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1840 cyc += 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1841 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1842 cyc += 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1843 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1844 cycles cyc
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1845 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1846 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1847
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1848 1110CCC1ZZ100RRR asl_dn
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1849 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1850 local shift 8
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1851 local vtmp 8
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1852 and dregs.C 63 shift
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1853 vtmp = 0
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1854 if shift
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1855 shift -= 1
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1856 loop shift
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1857 lsl dregs.R 1 dregs.R Z
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1858 update_flags V
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1859 vtmp |= vflag
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1860 end
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1861 shift += 1
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1862 lsl dregs.R 1 dregs.R Z
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1863 update_flags XNZVC
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1864 vflag |= vtmp
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1865 else
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1866 cmp 0 dregs.R Z
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1867 update_flags NZV0C
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1868 end
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1869 shift += shift
2610
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1870 switch Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1871 case 2
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1872 shift += 4
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1873 default
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1874 shift += 2
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1875 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1876 cycles shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1877 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1878 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1879
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1880 1110000111MMMRRR asl_ea
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1881 invalid M 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1882 invalid M 1
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1883 invalid M 7 R 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1884 invalid M 7 R 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1885 invalid M 7 R 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1886 invalid M 7 R 5
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1887 invalid M 7 R 6
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1888 invalid M 7 R 7
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1889
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1890 m68k_fetch_dst_ea M R 1
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1891 lsl dst 1 dst 1
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1892 update_flags XNZV0C
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1893 m68k_save_dst 1
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1894 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1895
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1896 00ZZRRRMMMEEESSS move
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1897 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1898 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1899 invalid M 7 #not actually invalid, but will be handled separately due to DSL limitations
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1900 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1901 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1902 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1903 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1904 local memsrc 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1905 #move uses a different size format than most instructions
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1906 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1907 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1908 mov 0 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1909 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1910 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1911 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1912 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1913 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1914 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1915
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1916 if src_is_mem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1917 #avoid clobbering src if we need scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1918 mov src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1919 meta src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1920 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1921
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1922 cmp 0 src size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1923 update_flags NZV0C0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1924
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1925 switch M
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1926 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1927 mov src dregs.R size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1928
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1929 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1930 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1931 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1932 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1933
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1934 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1935 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1936 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1937 switch R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1938 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1939 if size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1940 addsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1941 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1942 addsize 1 aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1943 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1944 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1945 addsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1946 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1947 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1948
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1949 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1950 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1951 switch R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1952 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1953 if size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1954 decsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1955 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1956 decsize 1 aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1957 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1958 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1959 decsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1960 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1961 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1962 m68k_write_size size 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1963
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1964 case 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1965 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1966 sext 32 prefetch scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1967 add aregs.R scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1968 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1969 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1970
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1971 case 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1972 m68k_index_word
2670
9bcfdc1b56bd Fix cycle timing for move with indexed destination
Michael Pavone <pavone@retrodev.com>
parents: 2666
diff changeset
1973 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1974 add aregs.R scratch1 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1975 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1976 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1977 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1978 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1979
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1980
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1981 00ZZ00M111EEESSS move_abs
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1982 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1983 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1984 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1985 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1986 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1987 local memsrc 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1988 #move uses a different size format than most instructions
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1989 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1990 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1991 mov 0 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1992 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1993 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1994 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1995 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1996 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1997 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1998
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1999 if src_is_mem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2000 #avoid clobbering src if we need scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2001 mov src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2002 meta src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2003 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2004
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2005 cmp 0 src size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2006 update_flags NZV0C0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2007
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2008 switch M
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2009 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2010 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2011 sext 32 prefetch scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2012
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2013 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2014 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2015 lsl prefetch 16 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2016 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2017 or prefetch scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2018 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2019 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2020 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2021 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2022
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2023 00ZZRRR001EEESSS movea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2024 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2025 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2026 invalid Z 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2027 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2028 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2029 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2030 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2031 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2032 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2033 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2034 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2035 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2036 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2037 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2038 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2039 mov src aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2040 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2041 sext 32 src aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2042 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2043 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2044
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2045 0100010011MMMRRR move_to_ccr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2046 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2047 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2048 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2049 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2050 m68k_fetch_src_ea M R 1
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2051 mov src ccr
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2052 cycles 8
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2053 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2054
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2055 0100011011MMMRRR move_to_sr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2056 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2057 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2058 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2059 invalid M 7 R 7
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2060 #TODO: privilege violation exception if in user mode
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2061 m68k_fetch_src_ea M R 1
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2062 ccr = src
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2063 status = src >> 8
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
2064 check_user_mode_swap_ssp_usp
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2065 update_sync
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2066 cycles 8
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2067 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2068
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2069 0100000011MMMRRR move_from_sr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2070 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2071 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2072 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2073 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2074 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2075 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2076 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2077 m68k_fetch_dst_ea M R 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2078 lsl status 8 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2079 or ccr scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2080 mov scratch1 dst
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2081 if M
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2082 cycles 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2083 else
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2084 cycles 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2085 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2086 m68k_save_dst 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2087 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2088
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2089 01000000ZZMMMRRR negx
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2090 invalid M 1
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2091 invalid M 7 R 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2092 invalid M 7 R 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2093 invalid M 7 R 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2094 invalid M 7 R 5
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2095 invalid M 7 R 6
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2096 invalid M 7 R 7
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2097 m68k_fetch_dst_ea M R Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2098 sbc dst 0 dst Z
2633
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2099 update_flags XNVC
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2100 switch Z
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2101 case 0
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2102 local tmp8 8
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2103 tmp8 = dst
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2104 if tmp8
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2105 update_flags Z0
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2106 end
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2107 case 1
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2108 local tmp16 16
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2109 tmp16 = dst
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2110 if tmp16
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2111 update_flags Z0
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2112 end
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2113 case 2
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2114 local tmp32 32
2464
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2115 if M = 0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2116 cycles 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2117 end
2633
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2118 tmp32 = dst
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2119 if dst
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2120 update_flags Z0
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2121 end
2464
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2122 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2123 m68k_save_dst Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2124 m68k_prefetch
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2125
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2126 01000010ZZMMMRRR clr
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2127 invalid M 1
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2128 invalid M 7 R 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2129 invalid M 7 R 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2130 invalid M 7 R 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2131 invalid M 7 R 5
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2132 invalid M 7 R 6
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2133 invalid M 7 R 7
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2134 invalid Z 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2135 m68k_fetch_dst_ea M R Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2136 if Z = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2137 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2138 #register clears have 2 cycle penalty for longword size
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2139 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2140 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2141 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2142 dst:Z = 0
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2143 update_flags N0Z1V0C0
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2144 m68k_save_dst Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2145 m68k_prefetch
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2146
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2147 0100100000MMMRRR nbcd
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2148 local lowx_corf 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2149 local lowy_cmp 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2150 local res 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2151 invalid M 1
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2152 invalid M 7 R 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2153 invalid M 7 R 3
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2154 invalid M 7 R 4
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2155 invalid M 7 R 5
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2156 invalid M 7 R 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2157 invalid M 7 R 7
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2158 m68k_fetch_dst_ea M R 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2159 lowx_corf = dst & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2160 lowy_cmp = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2161 sbc lowx_corf lowy_cmp lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2162 if lowy_cmp >= 0xA
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2163 lowx_corf = 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2164 lowy_cmp = 0xA6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2165 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2166 lowx_corf = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2167 lowy_cmp = 0xA0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2168 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2169 res = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2170 sbc dst res res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2171 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2172 if cflag
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2173 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2174 res -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2175 update_flags NV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2176 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2177 if res >=U lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2178 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2179 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2180 res -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2181 update_flags XCNV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2182 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2183 if res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2184 update_flags Z0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2185 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2186 dst:0 = res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2187 if M = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2188 cycles 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2189 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2190 m68k_save_dst 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2191 m68k_prefetch
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2192
2453
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2193 00001100ZZMMMRRR cmpi
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2194 local immed 32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2195 invalid Z 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2196 invalid M 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2197 invalid M 7 R 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2198 invalid M 7 R 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2199 invalid M 7 R 4
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2200 invalid M 7 R 5
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2201 invalid M 7 R 6
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2202 invalid M 7 R 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2203 #fetch immediate operand
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2204 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2205 switch Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2206 case 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2207 immed = prefetch << 16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2208 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2209 immed |= prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2210 if M = 0
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2211 cycles 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2212 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2213 default
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2214 immed = prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2215 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2216 #fetch dst EA
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2217 m68k_fetch_dst_ea M R Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2218
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2219 cmp immed dst Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2220 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2221 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2222
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2223 1011DDD1ZZ001SSS cmpm
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2224 invalid Z 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2225 scratch1 = aregs.S
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2226 switch Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2227 case 0
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2228 ocall read_8
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2229 case 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2230 ocall read_16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2231 case 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2232 m68k_read32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2233 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2234 scratch2 = scratch1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2235 if Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2236 addsize Z aregs.S aregs.S
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2237 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2238 if S = 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2239 aregs.S += 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2240 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2241 aregs.S += 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2242 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2243 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2244 scratch1 = aregs.D
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2245 switch Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2246 case 0
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2247 ocall read_8
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2248 case 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2249 ocall read_16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2250 case 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2251 m68k_read32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2252 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2253 if Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2254 addsize Z aregs.D aregs.D
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2255 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2256 if D = 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2257 aregs.D += 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2258 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2259 aregs.D += 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2260 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2261 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2262 cmp scratch2 scratch1 Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2263 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2264 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2265
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2266 1011DDD0ZZMMMRRR cmp
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2267 invalid M 7 R 5
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2268 invalid M 7 R 6
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2269 invalid M 7 R 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2270 invalid Z 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2271 m68k_fetch_src_ea M R Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2272
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2273 if Z = 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2274 cycles 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2275 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2276
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2277 cmp src dregs.D Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2278 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2279 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2280
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2281 1011DDDZ11MMMRRR cmpa
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2282 invalid M 7 R 5
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2283 invalid M 7 R 6
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2284 invalid M 7 R 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2285 local size 16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2286 local ext_src 32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2287 if Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2288 size = 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2289 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2290 size = 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2291 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2292 m68k_fetch_src_ea M R size
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2293 cycles 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2294 if size = 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2295 sext 32 src ext_src
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2296 meta src ext_src
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2297 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2298 cmp src aregs.D
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2299 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2300 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2301
2454
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2302 0000100000MMMRRR btsti
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2303 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2304 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2305 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2306 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2307
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2308 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2309 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2310 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2311 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2312 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2313 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2314 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2315 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2316 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2317 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2318 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2319 m68k_fetch_src_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2320 tmp &= src
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2321 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2322 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2323
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2324 0000100001MMMRRR bchgi
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2325 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2326 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2327 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2328 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2329 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2330 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2331 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2332
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2333 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2334 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2335 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2336 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2337 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2338 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2339 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2340 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2341 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2342 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2343 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2344 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2345 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2346 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2347 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2348 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2349 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2350 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2351 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2352 dst ^= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2353 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2354 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2355
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2356 0000100010MMMRRR bclri
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2357 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2358 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2359 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2360 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2361 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2362 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2363 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2364
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2365 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2366 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2367 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2368 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2369 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2370 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2371 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2372 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2373 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2374 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2375 cycles 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2376 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2377 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2378 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2379 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2380 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2381 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2382 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2383 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2384 tmp = ~tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2385 dst &= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2386 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2387 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2388
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2389 0000100011MMMRRR bseti
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2390 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2391 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2392 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2393 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2394 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2395 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2396 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2397
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2398 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2399 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2400 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2401 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2402 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2403 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2404 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2405 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2406 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2407 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2408 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2409 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2410 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2411 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2412 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2413 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2414 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2415 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2416 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2417 dst |= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2418 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2419 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2420
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2421 0000SSS100MMMRRR btst_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2422 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2423 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2424 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2425 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2426
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2427 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2428 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2429 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2430 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2431 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2432 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2433 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2434 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2435 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2436 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2437 m68k_fetch_src_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2438 tmp &= src
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2439 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2440 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2441
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2442 0000SSS101MMMRRR bchg_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2443 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2444 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2445 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2446 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2447 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2448 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2449 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2450
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2451 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2452 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2453 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2454 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2455 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2456 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2457 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2458 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2459 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2460 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2461 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2462 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2463 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2464 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2465 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2466 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2467 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2468 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2469 dst ^= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2470 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2471 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2472
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2473 0000SSS110MMMRRR bclr_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2474 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2475 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2476 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2477 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2478 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2479 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2480 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2481
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2482 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2483 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2484 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2485 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2486 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2487 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2488 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2489 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2490 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2491 cycles 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2492 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2493 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2494 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2495 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2496 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2497 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2498 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2499 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2500 tmp = ~tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2501 dst &= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2502 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2503 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2504
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2505 0000SSS111MMMRRR bset_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2506 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2507 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2508 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2509 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2510 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2511 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2512 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2513
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2514 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2515 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2516 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2517 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2518 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2519 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2520 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2521 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2522 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2523 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2524 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2525 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2526 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2527 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2528 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2529 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2530 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2531 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2532 dst |= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2533 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2534 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2535
2456
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2536 0000DDD10Z001AAA movep_ay_dx
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2537 local address 32
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2538 m68k_prefetch
2639
0046305e3fa8 Fix movep with negative displacement
Michael Pavone <pavone@retrodev.com>
parents: 2636
diff changeset
2539 sext 32 scratch1 scratch1
2456
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2540 scratch1 += aregs.A
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2541 address = scratch1 + 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2542 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2543 dregs.D:1 = scratch1 << 8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2544 scratch1 = address
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2545 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2546 dregs.D:0 = scratch1
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2547 if Z
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2548 address += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2549 scratch1 = address
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2550 dregs.D <<= 16
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2551 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2552 dregs.D:1 = scratch1 << 8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2553 scratch1 = address + 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2554 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2555 dregs.D:0 = scratch1
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2556 end
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2557 m68k_prefetch
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2558
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2559 0000DDD11Z001AAA movep_dx_ay
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2560 m68k_prefetch
2639
0046305e3fa8 Fix movep with negative displacement
Michael Pavone <pavone@retrodev.com>
parents: 2636
diff changeset
2561 sext 32 scratch1 scratch1
2456
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2562 scratch2 = scratch1 + aregs.A
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2563 if Z
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2564 scratch1 = dregs.D >> 24
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2565 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2566 scratch2 += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2567 scratch1 = dregs.D >> 16
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2568 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2569 scratch2 += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2570 end
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2571 scratch1 = dregs.D >> 8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2572 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2573 scratch2 += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2574 scratch1 = dregs.D
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2575 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2576 m68k_prefetch
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2577
2464
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2578 01000100ZZMMMRRR neg
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2579 invalid Z 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2580 invalid M 1
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2581 invalid M 7 R 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2582 invalid M 7 R 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2583 invalid M 7 R 4
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2584 invalid M 7 R 5
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2585 invalid M 7 R 6
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2586 invalid M 7 R 7
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2587
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2588 m68k_fetch_dst_ea M R Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2589 dst:Z = -dst
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2590 update_flags XNZVC
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2591 if Z = 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2592 if M = 0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2593 cycles 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2594 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2595 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2596 m68k_save_dst Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2597 m68k_prefetch
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2598
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2599 01000110ZZMMMRRR not
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2600 invalid Z 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2601 invalid M 1
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2602 invalid M 7 R 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2603 invalid M 7 R 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2604 invalid M 7 R 4
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2605 invalid M 7 R 5
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2606 invalid M 7 R 6
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2607 invalid M 7 R 7
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2608
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2609 m68k_fetch_dst_ea M R Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2610 dst:Z = ~dst
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2611 update_flags NZV0C0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2612 if Z = 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2613 if M = 0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2614 cycles 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2615 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2616 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2617 m68k_save_dst Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2618 m68k_prefetch
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2619
2468
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2620 01001000ZZ000RRR ext
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2621 invalid Z 0
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2622 invalid Z 1
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2623 if Z = 3
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2624 meta bits 32
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2625 else
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2626 meta bits 16
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2627 end
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2628 sext bits dregs.R dregs.R
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2629 update_flags NZV0C0
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2630 m68k_prefetch
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2631
2651
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2632 0100101011MMMRRR tas
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2633 invalid M 1
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2634 invalid M 7 R 2
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2635 invalid M 7 R 3
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2636 invalid M 7 R 4
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2637 invalid M 7 R 5
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2638 invalid M 7 R 6
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2639 invalid M 7 R 7
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2640
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2641 m68k_fetch_dst_ea M R 0
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2642 cmp 0 dst 0
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2643 update_flags NZV0C0
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2644 dst |= 0x80
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2645 if M
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2646 cycles 2
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2647 ocall rmw_writeback
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2648 end
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2649 m68k_prefetch
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2650
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2651 010011100100VVVV trap
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2652 local vector 32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2653 scratch1 = pc
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2654 vector = V + 32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2655 m68k_trap vector
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2656
2470
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2657 0100111001010RRR link
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2658 a7 -= 4
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2659 scratch2 = a7
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2660 #TODO: confirm order of fetch and write
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2661 m68k_write32 aregs.R
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2662 m68k_prefetch
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2663 aregs.R = a7
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2664 sext 32 scratch1 scratch1
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2665 a7 += scratch1
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2666 m68k_prefetch
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2667
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2668 0100111001011RRR unlk
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2669 a7 = aregs.R
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2670 scratch1 = a7
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2671 m68k_read32
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2672 a7 += 4
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2673 aregs.R = scratch1
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2674 m68k_prefetch
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2675
2472
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2676 0100100001000RRR swap
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2677 ror dregs.R 16 dregs.R
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2678 update_flags NZV0C0
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2679 m68k_prefetch
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2680
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2681 m68k_calc_ea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2682 arg mode 16
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2683 arg reg 16
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2684 arg index_penalty 32
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2685
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2686 switch mode
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2687 case 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2688 #address reg indirect
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2689 meta ea aregs.reg
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2690 case 3
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2691 #postincrement
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2692 meta ea aregs.reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2693 case 4
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2694 #predecrement
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2695 #note: this case is only used when m68k_calc_ea
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2696 #is called from movem_reg_to_mem which does its own decrementing
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2697 meta ea aregs.reg
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2698 case 5
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2699 #displacement
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2700 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2701 sext 32 prefetch scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2702 scratch1 += aregs.reg
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2703 meta ea scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2704 case 6
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2705 #index
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2706 m68k_index_word
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2707 cycles index_penalty
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2708 scratch1 += aregs.reg
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2709 meta ea scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2710 case 7
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2711 switch reg
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2712 case 0
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2713 #absolute short
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2714 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2715 sext 32 prefetch scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2716 case 1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2717 #absoltue long
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2718 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2719 scratch2 = prefetch << 16
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2720 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2721 scratch1 = scratch2 | prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2722 case 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2723 #pc displacement
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2724 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2725 sext 32 prefetch scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2726 scratch1 += pc
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2727 scratch1 -= 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2728 case 3
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2729 #pc indexed
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2730 m68k_index_word
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2731 cycles index_penalty
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2732 scratch1 += pc
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2733 scratch1 -= 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2734 end
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2735 meta ea scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2736 end
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2737
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2738 0100100001MMMRRR pea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2739 invalid M 0
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2740 invalid M 1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2741 invalid M 3
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2742 invalid M 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2743 invalid M 7 R 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2744 invalid M 7 R 5
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2745 invalid M 7 R 6
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2746 invalid M 7 R 7
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2747
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2748 m68k_calc_ea M R 4
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2749 scratch2 = a7 - 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2750 m68k_write32_lowfirst ea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2751 a7 -= 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2752
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2753 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2754
2622
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2755 0100DDDZZ0MMMRRR chk
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2756 invalid M 1
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2757 invalid M 7 R 5
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2758 invalid M 7 R 6
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2759 invalid M 7 R 7
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2760 invalid Z 0
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2761 invalid Z 1
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2762 local tmp 8
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2763 local src_alt 32
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2764 switch Z
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2765 case 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2766 meta size 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2767 case 3
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2768 meta size 1
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2769 end
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2770 m68k_fetch_src_ea M R size
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2771 if src_is_mem
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2772 src_alt = src
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2773 meta src src_alt
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2774 end
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2775 m68k_prefetch
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2776 cmp dregs.D src size
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2777 update_flags NZVC
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2778 tmp = vflag
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2779 tmp |= nflag
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2780 cmp 0 dregs.D size
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2781 update_flags NZV0C0
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2782 if tmp
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2783 # D > src (signed)
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2784 pc -= 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2785 m68k_trap 6
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2786 else
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2787 cycles 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2788 if nflag
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2789 # D < 0
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2790 pc -= 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2791 m68k_trap 6
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2792 else
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2793 cycles 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2794 end
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2795 end
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2796
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2797 0100DDD111MMMRRR lea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2798 invalid M 0
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2799 invalid M 1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2800 invalid M 3
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2801 invalid M 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2802 invalid M 7 R 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2803 invalid M 7 R 5
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2804 invalid M 7 R 6
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2805 invalid M 7 R 7
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2806
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2807 m68k_calc_ea M R 4
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2808 aregs.D = ea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2809
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2810 m68k_prefetch
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2811
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2812 01001010ZZMMMRRR tst
2653
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
2813 invalid Z 3
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2814 invalid M 7 R 5
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2815 invalid M 7 R 6
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2816 invalid M 7 R 7
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2817
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2818 m68k_fetch_dst_ea M R Z
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2819
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2820 cmp 0 dst Z
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2821 update_flags NZV0C0
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2822 m68k_prefetch
2472
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2823
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2824 0100111001110000 reset
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2825 if reset_handler
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2826 pcall reset_handler m68k_reset_handler context
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2827 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2828 cycles 128
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2829 m68k_prefetch
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2830
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2831 0100111001110001 nop
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2832 m68k_prefetch
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2833
2618
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2834 0100111001110010 stop
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2835 if stopped
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2836 else
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2837 mov pc scratch1
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2838 ocall read_16
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2839 pc += 2
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2840 ccr = scratch1
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2841 status = scratch1 >> 8
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2842 check_user_mode_swap_ssp_usp
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2843 update_sync
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2844 stopped = 1
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2845 end
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2846 loop
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2847 cycles 4
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2848 if cycles >=U int_cycle
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2849 break
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2850 end
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2851 if cycles >=U target_cycle
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2852 break
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2853 end
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2854 end
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2855
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2856 0100111001110011 rte
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2857 #TODO: privilege violation exception if in user mode
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2858 #Read saved SR
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2859 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2860 ocall read_16
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2861 a7 += 2
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2862 ccr = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2863 status = scratch1 >> 8
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2864 #Read saved PC
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2865 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2866 m68k_read32
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2867 a7 += 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2868 pc = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2869
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2870 check_user_mode_swap_ssp_usp
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2871 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2872 update_sync
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2873 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2874
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2875 0100111001110101 m68k_rts
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2876 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2877 m68k_read32
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2878 a7 += 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2879 pc = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2880
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2881 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2882 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2883
2622
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2884 0100111001110110 trapv
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2885 if vflag
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2886 m68k_trap 7
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2887 else
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2888 m68k_prefetch
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2889 end
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2890
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2891 0100111001110111 rtr
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2892 #Read saved CCR
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2893 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2894 ocall read_16
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2895 a7 += 2
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2896 ccr = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2897 #Read saved PC
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2898 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2899 m68k_read32
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2900 a7 += 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2901 pc = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2902
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2903 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2904 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2905
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2906 0100111010MMMRRR jsr
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2907 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2908 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2909 invalid M 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2910 invalid M 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2911 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2912 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2913 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2914 invalid M 7 R 7
2585
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2915 local tmp 32
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2916
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2917 m68k_calc_ea M R 2
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2918 tmp = ea
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2919
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2920 a7 -= 4
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2921 scratch2 = a7
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2922 m68k_write32 pc
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2923
2585
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2924 pc = tmp
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2925
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2926 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2927 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2928
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2929 0100111011MMMRRR jmp
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2930 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2931 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2932 invalid M 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2933 invalid M 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2934 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2935 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2936 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2937 invalid M 7 R 7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2938
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2939 m68k_calc_ea M R 2
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2940 pc = ea
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2941
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2942 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2943 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2944
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2945 m68k_movem_reg_to_mem
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2946 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2947 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2948 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2949 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2950
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2951 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2952 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2953 scratch2 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2954 scratch1 = reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2955 m68k_write_size size 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2956 addsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2957 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2958
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2959 m68k_movem_reg_to_mem_dec
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2960 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2961 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2962 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2963 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2964
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2965 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2966 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2967 decsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2968 scratch2 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2969 scratch1 = reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2970 m68k_write_size size 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2971 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2972
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2973
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2974 010010001ZMMMRRR movem_reg_to_mem
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2975 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2976 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2977 invalid M 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2978 invalid M 7 R 2
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2979 invalid M 7 R 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2980 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2981 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2982 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2983 invalid M 7 R 7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2984 local reglist 16
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2985 local address 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2986 local sz 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2987 sz = Z + 1
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2988
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2989 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2990 reglist = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2991
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2992 m68k_calc_ea M R 2
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2993 address = ea
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2994 meta addr address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2995 if M = 4
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2996 m68k_movem_reg_to_mem_dec reglist 1 a7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2997 m68k_movem_reg_to_mem_dec reglist 2 a6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2998 m68k_movem_reg_to_mem_dec reglist 4 a5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2999 m68k_movem_reg_to_mem_dec reglist 8 a4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3000 m68k_movem_reg_to_mem_dec reglist 16 a3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3001 m68k_movem_reg_to_mem_dec reglist 32 a2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3002 m68k_movem_reg_to_mem_dec reglist 64 a1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3003 m68k_movem_reg_to_mem_dec reglist 128 a0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3004 m68k_movem_reg_to_mem_dec reglist 256 d7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3005 m68k_movem_reg_to_mem_dec reglist 512 d6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3006 m68k_movem_reg_to_mem_dec reglist 1024 d5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3007 m68k_movem_reg_to_mem_dec reglist 2048 d4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3008 m68k_movem_reg_to_mem_dec reglist 4096 d3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3009 m68k_movem_reg_to_mem_dec reglist 8192 d2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3010 m68k_movem_reg_to_mem_dec reglist 16384 d1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3011 m68k_movem_reg_to_mem_dec reglist 32768 d0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3012 ea = address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3013 else
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3014 m68k_movem_reg_to_mem reglist 1 d0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3015 m68k_movem_reg_to_mem reglist 2 d1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3016 m68k_movem_reg_to_mem reglist 4 d2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3017 m68k_movem_reg_to_mem reglist 8 d3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3018 m68k_movem_reg_to_mem reglist 16 d4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3019 m68k_movem_reg_to_mem reglist 32 d5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3020 m68k_movem_reg_to_mem reglist 64 d6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3021 m68k_movem_reg_to_mem reglist 128 d7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3022 m68k_movem_reg_to_mem reglist 256 a0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3023 m68k_movem_reg_to_mem reglist 512 a1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3024 m68k_movem_reg_to_mem reglist 1024 a2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3025 m68k_movem_reg_to_mem reglist 2048 a3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3026 m68k_movem_reg_to_mem reglist 4096 a4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3027 m68k_movem_reg_to_mem reglist 8192 a5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3028 m68k_movem_reg_to_mem reglist 16384 a6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3029 m68k_movem_reg_to_mem reglist 32768 a7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3030 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3031 m68k_prefetch
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3032
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3033 m68k_movem_mem_to_dreg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3034 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3035 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3036 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3037 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3038
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3039 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3040 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3041 scratch1 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3042 if sz = 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3043 ocall read_16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3044 sext 32 scratch1 dregs.reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3045 else
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3046 m68k_read32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3047 dregs.reg = scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3048 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3049 addsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3050 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3051
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3052 m68k_movem_mem_to_areg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3053 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3054 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3055 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3056 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3057
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3058 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3059 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3060 scratch1 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3061 if sz = 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3062 ocall read_16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3063 sext 32 scratch1 aregs.reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3064 else
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3065 m68k_read32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3066 aregs.reg = scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3067 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3068 addsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3069 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3070
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3071 010011001ZMMMRRR movem_mem_to_reg
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3072 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3073 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3074 invalid M 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3075 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3076 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3077 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3078 invalid M 7 R 7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3079 local reglist 16
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3080 local address 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3081 local sz 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3082 sz = Z + 1
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3083
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3084 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3085 reglist = scratch1
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3086
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3087 m68k_calc_ea M R 2
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3088 address = ea
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3089 meta addr address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3090
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3091 m68k_movem_mem_to_dreg reglist 1 0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3092 m68k_movem_mem_to_dreg reglist 2 1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3093 m68k_movem_mem_to_dreg reglist 4 2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3094 m68k_movem_mem_to_dreg reglist 8 3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3095 m68k_movem_mem_to_dreg reglist 16 4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3096 m68k_movem_mem_to_dreg reglist 32 5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3097 m68k_movem_mem_to_dreg reglist 64 6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3098 m68k_movem_mem_to_dreg reglist 128 7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3099 m68k_movem_mem_to_areg reglist 256 0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3100 m68k_movem_mem_to_areg reglist 512 1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3101 m68k_movem_mem_to_areg reglist 1024 2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3102 m68k_movem_mem_to_areg reglist 2048 3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3103 m68k_movem_mem_to_areg reglist 4096 4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3104 m68k_movem_mem_to_areg reglist 8192 5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3105 m68k_movem_mem_to_areg reglist 16384 6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3106 m68k_movem_mem_to_areg reglist 32768 7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3107 #dummy read
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3108 scratch1 = address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3109 ocall read_16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3110 if M = 3
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3111 ea = address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3112 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3113
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3114 m68k_prefetch
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3115
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3116 0100111001100RRR move_to_usp
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3117 #TODO: trap if not in supervisor mode
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3118 other_sp = aregs.R
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3119 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3120
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3121 0100111001101RRR move_from_usp
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3122 #TODO: trap if not in supervisor mode
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3123 aregs.R = other_sp
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3124 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3125
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3126 0111RRR0IIIIIIII moveq
2591
563d05355a12 Cut down on code bloat in 68K core a little
Michael Pavone <pavone@retrodev.com>
parents: 2590
diff changeset
3127 nospecialize I
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3128 local tmp 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3129 sext 16 I tmp
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3130 sext 32 tmp dregs.R
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3131 cmp 0 dregs.R
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3132 update_flags NZV0C0
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3133 m68k_prefetch
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3134
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3135 0110000100000000 bsr_w
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3136 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3137 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3138 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3139 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3140 sext 32 prefetch offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3141
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3142 a7 -= 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3143 scratch2 = a7
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3144 m68k_write32 pc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3145
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3146 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3147 pc -= 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3148
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3149 cycles 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3150 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3151
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3152
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3153 01100001DDDDDDDD bsr
2591
563d05355a12 Cut down on code bloat in 68K core a little
Michael Pavone <pavone@retrodev.com>
parents: 2590
diff changeset
3154 nospecialize D
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3155 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3156 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3157 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3158 sext 16 D offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3159 sext 32 offset offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3160
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3161 a7 -= 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3162 scratch2 = a7
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3163 m68k_write32 pc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3164
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3165 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3166
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3167 cycles 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3168 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3169
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3170 m68k_check_cond
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3171 arg cond 16
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3172 local invert 8
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3173 switch cond
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3174 case 0
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3175 #true
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3176 meta istrue 1
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3177 case 1
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3178 #false
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3179 meta istrue 0
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3180 case 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3181 #high
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3182 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3183 invert = zflag | cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3184 invert = !invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3185 case 3
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3186 #low or same
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3187 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3188 invert = zflag | cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3189 case 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3190 #carry clear
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3191 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3192 invert = !cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3193 case 5
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3194 #carry set
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3195 meta istrue cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3196 case 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3197 #not equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3198 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3199 invert = !zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3200 case 7
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3201 #equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3202 meta istrue zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3203 case 8
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3204 #overflow clear
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3205 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3206 invert = !vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3207 case 9
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3208 #overflow set
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3209 meta istrue vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3210 case 10
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3211 #plus
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3212 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3213 invert = !nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3214 case 11
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3215 #minus
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3216 meta istrue nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3217 case 12
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3218 #greater or equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3219 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3220 invert = nflag - vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3221 invert = !invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3222 case 13
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3223 #less
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3224 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3225 invert = nflag - vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3226 case 14
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3227 #greater
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3228 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3229 invert = vflag ^ nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3230 invert |= zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3231 invert = !invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3232 case 15
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3233 #less or equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3234 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3235 invert = vflag ^ nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3236 invert |= zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3237 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3238
2584
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3239 0101CCCC11MMMDDD scc
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3240 invalid M 1
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3241 invalid M 7 D 2
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3242 invalid M 7 D 3
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3243 invalid M 7 D 4
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3244 invalid M 7 D 5
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3245 invalid M 7 D 6
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3246 invalid M 7 D 7
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3247 m68k_fetch_dst_ea M D 0
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3248 m68k_check_cond C
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3249 if istrue
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3250 if M = 0
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3251 cycles 2
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3252 end
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3253 dst:0 = 0xFF
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3254 else
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3255 dst:0 = 0
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3256 end
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3257 m68k_save_dst 0
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3258 m68k_prefetch
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3259
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3260 0110CCCC00000000 bcc_w
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3261 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3262 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3263 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3264 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3265 m68k_check_cond C
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3266 if istrue
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3267
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3268 sext 32 prefetch offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3269 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3270 pc -= 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3271 cycles 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3272 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3273 cycles 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3274 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3275 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3276
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3277 0110CCCCDDDDDDDD bcc
2591
563d05355a12 Cut down on code bloat in 68K core a little
Michael Pavone <pavone@retrodev.com>
parents: 2590
diff changeset
3278 nospecialize D
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3279 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3280 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3281 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3282 m68k_check_cond C
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3283 if istrue
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3284 sext 16 D offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3285 sext 32 offset offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3286
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3287 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3288
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3289 cycles 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3290 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3291 cycles 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3292 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3293 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3294
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3295 0101CCCC11001RRR dbcc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3296 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3297 local tmp 16
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3298 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3299 m68k_check_cond C
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3300 if istrue
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3301 cycles 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3302 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3303 dregs.R:1 -= 1
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3304 tmp = dregs.R
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3305 if tmp = 65535
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3306 cycles 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3307 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3308 sext 32 prefetch offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3309 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3310 pc -= 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3311 cycles 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3312 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3313 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3314 m68k_prefetch
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3315
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3316 1110CCC0ZZ011RRR rori
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3317 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3318 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3319 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3320 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3321 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3322 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3323 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3324 ror dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3325 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3326 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3327 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3328 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3329 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3330 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3331 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3332 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3333 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3334 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3335 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3336 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3337
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3338 1110CCC0ZZ111RRR ror_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3339 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3340 local shift 8
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3341 shift = dregs.C & 63
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3342 ror dregs.R shift dregs.R Z
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3343 update_flags NZV0C
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3344 shift += shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3345 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3346 case 2
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3347 shift += 4
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3348 default
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3349 shift += 2
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3350 end
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3351 cycles shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3352 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3353 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3354
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3355 1110011011MMMRRR ror_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3356 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3357 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3358 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3359 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3360 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3361 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3362 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3363 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3364
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3365 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3366 ror dst 1 dst 1
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3367 update_flags NZV0C
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3368 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3369 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3370
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3371 1110CCC1ZZ011RRR roli
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3372 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3373 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3374 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3375 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3376 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3377 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3378 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3379 rol dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3380 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3381 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3382 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3383 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3384 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3385 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3386 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3387 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3388 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3389 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3390 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3391 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3392
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3393 1110CCC1ZZ111RRR rol_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3394 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3395 local shift 8
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3396 shift = dregs.C & 63
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3397 rol dregs.R shift dregs.R Z
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3398 update_flags NZV0C
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3399 shift += shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3400 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3401 case 2
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3402 shift += 4
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3403 default
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3404 shift += 2
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3405 end
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3406 cycles shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3407 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3408 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3409
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3410 1110011111MMMRRR rol_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3411 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3412 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3413 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3414 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3415 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3416 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3417 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3418 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3419
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3420 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3421 rol dst 1 dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3422 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3423 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3424 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3425
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3426 1110CCC0ZZ010RRR roxri
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3427 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3428 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3429 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3430 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3431 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3432 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3433 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3434 rrc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3435 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3436 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3437 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3438 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3439 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3440 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3441 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3442 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3443 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3444 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3445 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3446 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3447
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3448 1110CCC0ZZ110RRR roxr_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3449 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3450 local shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3451 local cycle_shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3452 cycle_shift = dregs.C & 63
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3453 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3454 case 2
2631
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3455 meta max_shift 31
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3456 case 1
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3457 meta max_shift 15
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3458 case 0
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3459 meta max_shift 7
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3460 end
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3461 shift = cycle_shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3462 if shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3463 loop
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3464 if max_shift >=U shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3465 rrc dregs.R shift dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3466 update_flags XNZV0C
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3467 break
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3468 else
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3469 rrc dregs.R max_shift dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3470 update_flags X
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3471 shift -= max_shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3472 end
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3473 end
2631
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3474 else
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3475 cflag = xflag
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3476 cmp 0 dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3477 update_flags NZV0
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3478 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3479 cycle_shift += cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3480 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3481 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3482 cycle_shift += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3483 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3484 cycle_shift += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3485 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3486 cycles cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3487 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3488 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3489
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3490 1110010011MMMRRR roxr_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3491 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3492 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3493 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3494 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3495 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3496 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3497 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3498 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3499
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3500 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3501 rrc dst 1 dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3502 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3503 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3504 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3505
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3506 1110CCC1ZZ010RRR roxli
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3507 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3508 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3509 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3510 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3511 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3512 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3513 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3514 rlc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3515 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3516 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3517 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3518 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3519 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3520 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3521 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3522 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3523 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3524 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3525 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3526 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3527
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3528 1110CCC1ZZ110RRR roxl_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3529 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3530 local shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3531 local cycle_shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3532 cycle_shift = dregs.C & 63
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3533 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3534 case 2
2631
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3535 meta max_shift 31
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3536 case 1
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3537 meta max_shift 15
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3538 case 0
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3539 meta max_shift 7
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3540 end
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3541 shift = cycle_shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3542 if shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3543 loop
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3544 if max_shift >=U shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3545 rlc dregs.R shift dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3546 update_flags XNZV0C
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3547 break
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3548 else
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3549 rlc dregs.R max_shift dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3550 update_flags X
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3551 shift -= max_shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3552 end
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3553 end
2631
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3554 else
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3555 cflag = xflag
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3556 cmp 0 dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3557 update_flags NZV0
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3558 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3559 cycle_shift += cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3560 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3561 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3562 cycle_shift += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3563 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3564 cycle_shift += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3565 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3566 cycles cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3567 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3568 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3569
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3570 1110010111MMMRRR roxl_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3571 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3572 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3573 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3574 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3575 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3576 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3577 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3578 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3579
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3580 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3581 rlc dst 1 dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3582 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3583 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3584 m68k_prefetch
2636
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3585
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3586 1010XXXXXXXXXXXX line_a
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3587 nospecialize X
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3588 #TODO cycle counts
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3589 pc -= 2
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3590 m68k_trap 10
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3591
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3592 1111XXXXXXXXXXXX line_f
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3593 nospecialize X
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3594 #TODO cycle counts
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3595 pc -= 2
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3596 m68k_trap 11
2646
bde8ec2d0f83 Implement illegal instruction trap in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2639
diff changeset
3597
2653
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
3598 XXXXXXXXXXXXXXXX illegal
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
3599 nospecialize X
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
3600 #TODO cycle counts
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
3601 pc -= 2
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
3602 m68k_trap 4