Mercurial > repos > blastem

annotate m68k.cpu @ 2656:ec02a08196d5

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Remove some debug cruft
author Michael Pavone <pavone@retrodev.com>
date Mon, 03 Mar 2025 22:11:13 -0800
parents f85208405ae8
children 38c281ef57b0
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1 info
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2 prefix m68k_
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
3 opcode_size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
4 body m68k_run_op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
5 header m68k.h
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
6 interrupt m68k_interrupt
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
7 include m68k_util.c
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
8 sync_cycle m68k_sync_cycle
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
9
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
10 declare
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
11 typedef m68k_context *(sync_fun)(m68k_context * context, uint32_t address);
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
12 typedef m68k_context *(*int_ack_fun)(m68k_context * context);
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
13 typedef m68k_context *(*m68k_reset_handler)(m68k_context *context);
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
14 void init_m68k_opts(m68k_options *opts, memmap_chunk * memmap, uint32_t num_chunks, uint32_t clock_divider, sync_fun *sync_components, int_ack_fun int_ack);
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
15 m68k_context *init_68k_context(m68k_options * opts, m68k_reset_handler *reset_handler);
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
16 void m68k_reset(m68k_context *context);
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
17 void m68k_print_regs(m68k_context *context);
2499
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
18 void m68k_serialize(m68k_context *context, uint32_t pc, serialize_buffer *buf);
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
19 void m68k_deserialize(deserialize_buffer *buf, void *vcontext);
2500
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
20 void start_68k_context(m68k_context *context, uint32_t pc);
2499
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
21 define NUM_MEM_AREAS 10
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
22 define M68K_OPT_BROKEN_READ_MODIFY 1
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
23 define INT_PENDING_SR_CHANGE 254
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
24 define INT_PENDING_NONE 255
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
25 define M68K_STATUS_TRACE 0x80
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
26 define m68k_invalidate_code_range(context, start, end)
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
27 define m68k_options_free free
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
28 define m68k_handle_code_write(address, context)
2500
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
29 define resume_68k(context) m68k_execute(context, context->target_cycle)
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
30 define insert_breakpoint(context, address, handler)
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
31 define remove_breakpoint(context, address)
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
32 define m68k_add_watchpoint(context, address, size)
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
33 define m68k_remove_watchpoint(context, address, size)
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
34
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
35 regs
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
36 dregs 32 d0 d1 d2 d3 d4 d5 d6 d7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
37 aregs 32 a0 a1 a2 a3 a4 a5 a6 a7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
38 pc 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
39 other_sp 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
40 scratch1 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
41 scratch2 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
42 int_cycle 32
2499
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
43 target_cycle 32
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
44 wp_hit_address 32
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
45 prefetch 16
2499
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
46 wp_hit_value 16
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
47 wp_old_value 16
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
48 int_priority 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
49 int_num 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
50 int_pending 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
51 int_pending_num 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
52 int_ack 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
53 status 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
54 ccr 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
55 xflag 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
56 nflag 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
57 zflag 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
58 vflag 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
59 cflag 8
2499
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
60 wp_hit 8
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
61 trace_pending 8
2500
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
62 should_return 8
2618
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
63 stopped 8
2499
d74d3998482c Make some progress on compiling full emulator with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2498
diff changeset
64 system ptrvoid
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
65 reset_handler ptrvoid
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
66 int_ack_handler ptrvoid
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
67 sync_components ptrsync_fun
2500
d44fe974fb85 Get blastem compiling with new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2499
diff changeset
68 mem_pointers ptr16 10
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
69
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
70 flags
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
71 register ccr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
72 X 4 carry xflag
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
73 N 3 sign nflag
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
74 Z 2 zero zflag
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
75 V 1 overflow vflag
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
76 C 0 carry cflag
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
77
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
78 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
79 if dynarec
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
80
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
81 ccall m68k_read16_noinc context pc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
82 mov result prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
83
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
84 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
85
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
86 if interp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
87
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
88 mov pc scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
89 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
90 mov scratch1 prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
91
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
92 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
93
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
94 add 2 pc pc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
95
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
96 check_user_mode_swap_ssp_usp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
97 local tmp 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
98 and 0x20 status tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
99 if tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
100 else
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
101 xchg other_sp a7
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
102 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
103
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
104 m68k_get_sr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
105 lsl status 8 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
106 or ccr scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
107
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
108 m68k_write32_lowfirst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
109 arg value 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
110 add 2 scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
111 mov value scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
112 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
113
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
114 sub 2 scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
115 lsr value 16 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
116 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
117
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
118 m68k_write32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
119 arg value 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
120 local tmp 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
121 mov value tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
122 lsr value 16 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
123 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
124
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
125 add 2 scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
126 mov tmp scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
127 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
128
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
129 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
130 local tmp 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
131 add 2 scratch1 tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
132 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
133 xchg scratch1 tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
134 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
135 lsl tmp 16 tmp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
136 or tmp scratch1 scratch1
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
137
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
138 m68k_trap
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
139 arg vector 32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
140 check_user_mode_swap_ssp_usp
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
141 #save PC
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
142 a7 -= 4
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
143 scratch2 = a7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
144 m68k_write32_lowfirst pc
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
145 #save SR
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
146 a7 -= 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
147 scratch2 = a7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
148 m68k_get_sr
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
149 ocall write_16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
150 #set supervisor bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
151 status |= 0x20
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
152 #clear trace bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
153 status &= 0x7F
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
154 trace_pending = 0
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
155 scratch1 = vector << 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
156 m68k_read32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
157 pc = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
158 cycles 10
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
159 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
160
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
161
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
162
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
163 m68k_interrupt
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
164 if cycles >=U int_cycle
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
165
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
166 #INT_PENDING_NONE
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
167 if 255 = int_pending
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
168 int_pending = int_priority
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
169 int_pending_num = int_num
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
170 else
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
171 #INT_PENDING_SR_CHANGE
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
172 if 254 = int_pending
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
173 int_pending = int_priority
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
174 int_pending_num = int_num
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
175
2580
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
176 end
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
177
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
178 check_user_mode_swap_ssp_usp
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
179
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
180 cycles 6
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
181 #save status reg
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
182 a7 -= 6
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
183 m68k_get_sr
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
184 scratch2 = a7
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
185 ocall write_16
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
186
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
187 #update status register
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
188 status &= 0x78
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
189 status |= int_pending
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
190 status |= 0x20
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
191
2580
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
192 #Interrupt ack cycle
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
193 int_ack = int_pending
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
194 cycles 4
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
195 if int_ack_handler
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
196 pcall int_ack_handler int_ack_fun context
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
197 end
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
198 if int_pending_num
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
199 else
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
200 int_pending_num = int_pending + 24
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
201 end
2580
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
202
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
203 #save pc
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
204 scratch2 = a7 + 2
2618
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
205 if stopped
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
206 scratch1 = pc
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
207 stopped = 0
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
208 else
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
209 scratch1 = pc - 2
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
210 end
2580
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
211 m68k_write32_lowfirst scratch1
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
212
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
213 scratch1 = int_pending_num << 2
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
214 int_pending = 255 #INT_PENDING_NONE
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
215 int_pending_num = 0
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
216 m68k_read32
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
217 mov scratch1 pc
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
218 m68k_prefetch
939b818df589 Get 68K interrupts working in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2578
diff changeset
219 update_sync
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
220 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
221 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
222
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
223 m68k_run_op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
224 dispatch prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
225
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
226 m68k_mem_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
227 arg address 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
228 arg size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
229 arg isdst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
230 mov address scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
231 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
232 mov address scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
233 meta ismem 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
234 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
236
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
237 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
239
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
240 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
241 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
242
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
243 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
244 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
245
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
246 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
247 meta op scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
248
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
249 m68k_write_size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
250 arg size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
251 arg lowfirst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
252 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
253 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
254 ocall write_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
255
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
256 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
257 ocall write_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
258
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
259 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
260 if lowfirst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
261 m68k_write32_lowfirst scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
262 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
263 m68k_write32 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
264 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
265 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
266
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
267 m68k_index_word
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
268 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
269 local disp 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
270 and prefetch 255 disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
271 sext 16 disp disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
272 sext 32 disp disp
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
273 local index 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
274 lsr prefetch 12 index
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
275 local isareg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
276 and index 8 isareg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
277 and index 7 index
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
278 local islong 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
279 and prefetch 2048 islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
280
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
281 switch isareg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
282 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
283 switch islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
284 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
285 sext 32 dregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
286 case 2048
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
287 mov dregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
288 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
289 case 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
290 switch islong
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
291 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
292 sext 32 aregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
293 case 2048
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
294 mov aregs.index scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
295 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
296 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
297 add disp scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
298
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
299 m68k_fetch_op_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
300 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
301 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
302 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
303 arg isdst 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
304 switch mode
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
305
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
306 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
307 #data reg direct
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
308 meta op dregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
309 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
310 meta ismem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
311 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
312
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
313 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
314 #address reg direct
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
315 meta op aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
316 if isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
317 meta ismem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
318 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
319
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
320 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
321 #address reg indirect
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
322 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
323
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
324 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
325 #postincrement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
326 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
327 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
328 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
329 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
330 addsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
331 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
332 addsize 1 aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
333 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
334 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
335 addsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
336 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
337
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
338 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
339 #predecrement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
340 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
341 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
342 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
343 decsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
344 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
345 decsize 1 aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
346 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
347 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
348 decsize Z aregs.reg aregs.reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
349 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
350 cycles 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
351 m68k_mem_src aregs.reg Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
352
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
353 case 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
354 #displacement
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
355 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
356 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
357 add scratch1 aregs.reg scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
358 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
359
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
360 case 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
361 #indexed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
362 m68k_index_word
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
363 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
364 add aregs.reg scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
365
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
366 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
367 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
368 #pc-relative and absolute modes
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
369
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
370 switch reg
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
371 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
372 #absolute short
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
373 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
374 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
375 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
376
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
377 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
378 #absolute long
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
379 local address 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
380 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
381 lsl prefetch 16 address
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
382 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
383 or prefetch address scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
384 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
385
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
386 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
387 #pc displaceent
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
388 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
389 sext 32 prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
390 add scratch1 pc scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
391 sub 2 scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
392 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
393
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
394 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
395 #pc indexed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
396 m68k_index_word
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
397 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
398 add pc scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
399 sub 2 scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
400 m68k_mem_src scratch1 Z isdst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
401
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
402 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
403 #immediate
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
404 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
405 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
406 local tmp32 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
407 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
408 lsl prefetch 16 tmp32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
409 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
410 or prefetch tmp32 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
411
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
412 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
413 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
414 mov prefetch scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
415 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
416 meta op scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
417
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
418 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
419
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
420 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
421
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
422 m68k_fetch_src_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
423 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
424 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
425 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
426 m68k_fetch_op_ea mode reg Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
427 meta src op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
428 switch mode
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
429 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
430 meta src_is_mem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
431 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
432 meta src_is_mem 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
433 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
434 meta src_is_mem 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
435 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
436
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
437 m68k_fetch_dst_ea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
438 arg mode 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
439 arg reg 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
440 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
441 m68k_fetch_op_ea mode reg Z 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
442 meta dst op
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
443
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
444 m68k_save_dst
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
445 arg Z 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
446 if ismem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
447 m68k_write_size Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
448 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
449
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
450 1101DDD0ZZMMMRRR add_ea_dn
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
451 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
452 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
453 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
454 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
455 m68k_fetch_src_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
456
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
457 add src dregs.D dregs.D Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
458 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
459 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
460
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
461 1101DDD1ZZMMMRRR add_dn_ea
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
462 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
463 invalid M 1
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
464 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
465 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
466 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
467 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
468 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
469 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
470 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
471 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
472
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
473 add dregs.D dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
474 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
475 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
476 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
477
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
478 1101AAAZ11MMMRRR adda
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
479 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
480 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
481 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
482 local size 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
483 local ext_src 32
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
484 #TODO: ensure "penalty" cycles are in the right place
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
485 if Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
486 size = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
487 switch M
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
488 case 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
489 #dreg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
490 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
491 case 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
492 #areg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
493 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
494 case 7
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
495 if R = 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
496 #immediate
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
497 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
498 else
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
499 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
500 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
501 default
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
502 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
503 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504 else
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
505 size = 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
506 cycles 4
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
507 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
508 m68k_fetch_src_ea M R size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
509 switch size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
510 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
511 sext 32 src ext_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
512 meta src ext_src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
513 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
514
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
515 add src aregs.A aregs.A
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
516 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
517
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
518 00000110ZZMMMRRR addi
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
519 local immed 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
520 invalid Z 3
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
521 invalid M 1
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
522 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
523 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
524 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
525 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
526 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
527 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
528 #fetch immediate operand
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
529 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
530 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
531 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
532 lsl prefetch 16 immed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
533 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
534 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
535 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
536 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
537 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
538 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
539 mov prefetch immed
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
540 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
541 #fetch dst EA
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
542 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
543
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
544 add immed dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
545 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
546 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
547 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
548
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
549 0101III0ZZMMMRRR addq
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
550 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
551 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
552 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
553 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
554 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
555 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
556 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
557 local src 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
558 switch I
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
559 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
560 mov 8 src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
561 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
562 mov I src
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
563 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
564
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
565 m68k_fetch_dst_ea M R Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
566 switch M
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
567 case 1
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
568 cycles 4
2647
3c689000e571 Fix addq.w and subq.w with address register destination in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2646
diff changeset
569 add src dst dst 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
570 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
571 add src dst dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
572 update_flags XNZVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
573 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
574 m68k_save_dst Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
575 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
576
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
577 1101DDD1ZZ000SSS addx_dy_dx
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
578 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
579 adc dregs.S dregs.D dregs.D Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
580 update_flags XNVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
581 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
582 case 0
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
583 local tmp8 8
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
584 mov dregs.D tmp8
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
585 if tmp8
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
586 update_flags Z0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
587 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
588 case 1
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
589 local tmp16 16
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
590 mov dregs.D tmp16
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
591 if tmp16
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
592 update_flags Z0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
593 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
594 case 2
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
595 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
596 if dregs.D
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
597 update_flags Z0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
598 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
599 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
600 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
601
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
602 1101DDD1ZZ001SSS addx_ay_ax
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
603 invalid Z 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
604 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
605 decsize Z aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
606 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
607 switch S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
608 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
609 sub 2 aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
610 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
611 decsize Z aregs.S aregs.S
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
612 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
613 end
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
614 #predec penalty on src only
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
615 cycles 2
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
616 mov aregs.S scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
617 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
618 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
619 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
620 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
621 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
622 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
623 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
624 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
625 mov scratch1 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
626 if Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
627 decsize Z aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
628 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
629 switch D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
630 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
631 sub 2 aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
632 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
633 decsize Z aregs.D aregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
634 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
635 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
636 mov aregs.D scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
637 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
638 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
639 ocall read_8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
640 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
641 ocall read_16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
642 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
643 m68k_read32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
644 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
645 adc scratch2 scratch1 scratch1 Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
646 update_flags XNVC
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
647 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
648 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
649 local tmp8 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
650 mov dregs.D tmp8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
651 if tmp8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
652 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
653 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
654 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
655 local tmp16 16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
656 mov dregs.D tmp16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
657 if tmp16
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
658 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
659 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
660 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
661 if dregs.D
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
662 update_flags Z0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
663 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
664 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
665 mov aregs.D scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
666 m68k_write_size Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
667 m68k_prefetch
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
668
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
669 1100DDD0ZZMMMRRR and_ea_dn
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
670 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
671 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
672 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
673 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
674 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
675 m68k_fetch_src_ea M R Z
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
676
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
677 and src dregs.D dregs.D Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
678 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
679 m68k_prefetch
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
680
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
681 1100XXX100000YYY abcd_dy_dx
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
682 local lowx_corf 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
683 local lowy_cmp 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
684 local res 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
685 lowx_corf = dregs.X & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
686 lowy_cmp = dregs.Y & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
687 adc lowx_corf lowy_cmp lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
688 if lowy_cmp >=U 0xA
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
689 lowx_corf = 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
690 lowy_cmp = 0x9A
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
691 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
692 lowx_corf = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
693 lowy_cmp = 0xA0
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
694 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
695 adc dregs.Y dregs.X res 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
696 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
697 if cflag
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
698 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
699 res += lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
700 update_flags NV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
701 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
702 if res >=U lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
703 lowx_corf |= 0x60
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
704 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
705 res += lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
706 update_flags XCNV
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
707 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
708 if res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
709 update_flags Z0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
710 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
711 dregs.X:0 = res
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
712 cycles 2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
713 m68k_prefetch
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
714
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
715 1100XXX100001YYY abcd_ay_ax
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
716 local lowx_corf 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
717 local lowy_cmp 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
718 local res 8
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
719 if Y = 7
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
720 aregs.Y -= 2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
721 else
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
722 aregs.Y -= 1
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
723 end
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
724 #predec penalty on src only
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
725 cycles 2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
726 scratch1 = aregs.Y
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
727 ocall read_8
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
728 scratch2 = scratch1
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
729 if X = 7
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
730 aregs.X -= 2
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
731 else
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
732 aregs.X -= 1
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
733 end
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
734 scratch1 = aregs.X
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
735 ocall read_8
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
736 lowx_corf = scratch1 & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
737 lowy_cmp = scratch2 & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
738 adc lowx_corf lowy_cmp lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
739 if lowy_cmp >=U 0xA
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
740 lowx_corf = 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
741 lowy_cmp = 0x9A
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
742 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
743 lowx_corf = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
744 lowy_cmp = 0xA0
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
745 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
746 adc scratch2 scratch1 res 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
747 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
748 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
749 if cflag
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
750 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
751 res += lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
752 update_flags NV
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
753 else
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
754 if res >=U lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
755 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
756 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
757 res += lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
758 update_flags XCNV
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
759 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
760 if res
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
761 update_flags Z0
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
762 end
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
763 scratch1 = res
2588
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
764 scratch2 = aregs.X
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
765 ocall write_8
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
766 m68k_prefetch
0ea26288d983 Implement abcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2587
diff changeset
767
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
768 1100XXX101000YYY exg_dn_dn
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
769 scratch1 = dregs.X
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
770 dregs.X = dregs.Y
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
771 dregs.Y = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
772 cycles 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
773 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
774
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
775 1100XXX101001YYY exg_an_an
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
776 scratch1 = aregs.X
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
777 aregs.X = aregs.Y
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
778 aregs.Y = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
779 cycles 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
780 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
781
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
782 1100XXX110001YYY exg_dn_an
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
783 scratch1 = dregs.X
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
784 dregs.X = aregs.Y
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
785 aregs.Y = scratch1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
786 cycles 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
787 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
788
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
789 1100DDD011MMMRRR mulu
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
790 local a 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
791 local b 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
792 invalid M 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
793 invalid M 7 R 5
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
794 invalid M 7 R 6
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
795 invalid M 7 R 7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
796
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
797 m68k_fetch_src_ea M R 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
798 #2-cycles per bit x 16, 2 for cleanup
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
799 cycles 34
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
800 #popcnt
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
801 a = src & 0b1010101010101010
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
802 a >>= 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
803 b = src & 0b0101010101010101
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
804 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
805 a = b & 0b1100110011001100
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
806 a >>= 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
807 b &= 0b0011001100110011
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
808 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
809 a = b & 0b1111000011110000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
810 a >>= 4
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
811 b &= 0b0000111100001111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
812 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
813 a = b & 0b1111111100000000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
814 a >>= 8
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
815 b &= 0b0000000011111111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
816 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
817 #2 cycles per set bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
818 b += b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
819 cycles b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
820 dregs.D = src * dregs.D
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
821 update_flags NZV0C0
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
822 m68k_prefetch
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
823
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
824 1100DDD111MMMRRR muls
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
825 local a 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
826 local b 16
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
827 invalid M 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
828 invalid M 7 R 5
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
829 invalid M 7 R 6
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
830 invalid M 7 R 7
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
831
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
832 m68k_fetch_src_ea M R 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
833 #2-cycles per bit x 16, 2 for cleanup
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
834 cycles 34
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
835 #muls timing is essentially the same as muls, but it's based on the number of 0/1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
836 #transitions rather than the number of 1 bits. xoring the value with itself shifted
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
837 #by one effectively sets one bit for every transition
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
838 b = src << 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
839 b ^= src
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
840 #popcnt
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
841 a = b & 0b1010101010101010
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
842 a >>= 1
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
843 b &= 0b0101010101010101
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
844 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
845 a = b & 0b1100110011001100
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
846 a >>= 2
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
847 b &= 0b0011001100110011
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
848 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
849 a = b & 0b1111000011110000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
850 a >>= 4
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
851 b &= 0b0000111100001111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
852 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
853 a = b & 0b1111111100000000
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
854 a >>= 8
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
855 b &= 0b0000000011111111
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
856 b += a
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
857 #2 cycles per set bit
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
858 b += b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
859 cycles b
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
860 dregs.D = src *S dregs.D
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
861 update_flags NZV0C0
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
862 m68k_prefetch
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
863
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
864 1100DDD1ZZMMMRRR and_dn_ea
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
865 invalid M 0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
866 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
867 invalid M 7 R 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
868 invalid M 7 R 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
869 invalid M 7 R 4
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
870 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
871 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
872 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
873 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
874 m68k_fetch_dst_ea M R Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
875
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
876 and dregs.D dst dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
877 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
878 m68k_save_dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
879 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
880
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
881 00000010ZZMMMRRR andi
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
882 local immed 32
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
883 invalid Z 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
884 invalid M 1
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
885 invalid M 7 R 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
886 invalid M 7 R 3
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
887 invalid M 7 R 4
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
888 invalid M 7 R 5
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
889 invalid M 7 R 6
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
890 invalid M 7 R 7
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
891 #fetch immediate operand
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
892 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
893 switch Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
894 case 2
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
895 lsl prefetch 16 immed
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
896 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
897 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
898 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
899 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
900 end
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
901 default
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
902 mov prefetch immed
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
903 end
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
904 #fetch dst EA
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
905 m68k_fetch_dst_ea M R Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
906
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
907 and immed dst dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
908 update_flags NZV0C0
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
909 m68k_save_dst Z
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
910 m68k_prefetch
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
911
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
912 0000001000111100 andi_to_ccr
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
913 #fetch immediate operand
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
914 m68k_prefetch
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
915 ccr &= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
916 cycles 12 #TODO: where do these occur relative to fetches
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
917 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
918
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
919 0000001001111100 andi_to_sr
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
920 #TODO: privilege violation exception if in user mode
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
921 #fetch immediate operand
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
922 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
923 ccr &= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
924 scratch1 = prefetch >> 8
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
925 status &= scratch1
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
926 check_user_mode_swap_ssp_usp
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
927 update_sync
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
928 cycles 12 #TODO: where do these occur relative to fetches
1939
84b32010ef8d Implement 68K and instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1838
diff changeset
929 m68k_prefetch
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
930
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
931 1011DDD1ZZMMMRRR eor_dn_ea
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
932 invalid M 1
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
933 invalid M 7 R 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
934 invalid M 7 R 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
935 invalid M 7 R 4
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
936 invalid M 7 R 5
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
937 invalid M 7 R 6
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
938 invalid M 7 R 7
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
939 invalid Z 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
940 m68k_fetch_dst_ea M R Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
941
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
942 if Z = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
943 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
944 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
945 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
946 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
947
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
948 xor dregs.D dst dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
949 update_flags NZV0C0
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
950 m68k_save_dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
951 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
952
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
953 00001010ZZMMMRRR eori
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
954 local immed 32
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
955 invalid Z 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
956 invalid M 1
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
957 invalid M 7 R 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
958 invalid M 7 R 3
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
959 invalid M 7 R 4
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
960 invalid M 7 R 5
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
961 invalid M 7 R 6
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
962 invalid M 7 R 7
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
963 #fetch immediate operand
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
964 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
965 switch Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
966 case 2
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
967 lsl prefetch 16 immed
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
968 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
969 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
970 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
971 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
972 end
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
973 default
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
974 mov prefetch immed
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
975 end
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
976 #fetch dst EA
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
977 m68k_fetch_dst_ea M R Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
978
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
979 xor immed dst dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
980 update_flags NZV0C0
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
981 m68k_save_dst Z
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
982 m68k_prefetch
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
983
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
984 0000101000111100 eori_to_ccr
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
985 #fetch immediate operand
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
986 m68k_prefetch
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
987 ccr ^= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
988 cycles 12 #TODO: where do these occur relative to fetches
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
989 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
990
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
991 0000101001111100 eori_to_sr
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
992 #TODO: privilege violation exception if in user mode
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
993 #fetch immediate operand
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
994 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
995 ccr ^= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
996 scratch1 = prefetch >> 8
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
997 status ^= scratch1
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
998 check_user_mode_swap_ssp_usp
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
999 update_sync
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1000 cycles 12 #TODO: where do these occur relative to fetches
1940
048442b0cb62 Implement 68K eor instruction in new core
Michael Pavone <pavone@retrodev.com>
parents: 1939
diff changeset
1001 m68k_prefetch
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1002
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1003 1000DDD0ZZMMMRRR or_ea_dn
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1004 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1005 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1006 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1007 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1008 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1009 m68k_fetch_src_ea M R Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1010
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1011 if Z = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1012 switch M
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1013 case 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1014 #dreg
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1015 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1016 case 7
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1017 if R = 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1018 #immediate
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1019 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1020 else
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1021 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1022 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1023 default
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1024 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1025 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1026 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1027
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1028 or src dregs.D dregs.D Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1029 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1030 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1031
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1032 1000DDD1ZZMMMRRR or_dn_ea
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1033 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1034 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1035 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1036 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1037 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1038 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1039 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1040 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1041 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1042 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1043
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1044 or dregs.D dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1045 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1046 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1047 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1048
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1049 00000000ZZMMMRRR ori
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1050 local immed 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1051 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1052 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1053 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1054 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1055 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1056 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1057 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1058 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1059 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1060 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1061 switch Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1062 case 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1063 lsl prefetch 16 immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1064 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1065 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1066 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1067 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1068 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1069 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1070 mov prefetch immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1071 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1072 #fetch dst EA
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1073 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1074
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1075 or immed dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1076 update_flags NZV0C0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1077 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1078 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1079
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1080 0000000000111100 ori_to_ccr
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1081 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1082 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1083 or prefetch ccr ccr
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1084 cycles 12 #TODO: where do these occur relative to fetches
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1085 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1086
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1087 0000000001111100 ori_to_sr
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1088 #TODO: privilege violation exception if in user mode
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1089 #fetch immediate operand
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1090 m68k_prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1091 ccr |= prefetch
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1092 scratch1 = prefetch >> 8
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1093 status |= scratch1
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1094 update_sync
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1095 cycles 12 #TODO: where do these occur relative to fetches
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1096 m68k_prefetch
2587
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1097
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1098 1000YYY100000XXX sbcd_dx_dy
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1099 local lowx_corf 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1100 local lowy 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1101 local res 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1102 lowx_corf = dregs.X & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1103 lowy = dregs.Y & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1104 sbc lowx_corf lowy lowy
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1105 if lowy >=U 0x10
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1106 lowx_corf = 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1107 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1108 lowx_corf = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1109 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1110 sbc dregs.X dregs.Y res 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1111 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1112 if cflag
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1113 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1114 res -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1115 update_flags NV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1116 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1117 res -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1118 update_flags XCNV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1119 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1120 if res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1121 update_flags Z0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1122 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1123 dregs.Y:0 = res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1124 cycles 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1125 m68k_prefetch
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1126
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1127 1000YYY100001XXX sbcd_ax_ay
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1128 local lowx_corf 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1129 local lowy 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1130 if X = 7
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1131 aregs.X -= 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1132 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1133 aregs.X -= 1
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1134 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1135 #predec penalty on src only
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1136 cycles 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1137 scratch1 = aregs.X
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1138 ocall read_8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1139 scratch2 = scratch1
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1140 if Y = 7
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1141 aregs.Y -= 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1142 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1143 aregs.Y -= 1
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1144 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1145 scratch1 = aregs.Y
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1146 ocall read_8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1147 lowy = scratch1 & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1148 lowx_corf = scratch2 & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1149 sbc lowx_corf lowy lowy
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1150 if lowy >=U 0x10
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1151 lowx_corf = 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1152 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1153 lowx_corf = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1154 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1155 sbc scratch2 scratch1 scratch1 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1156 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1157 if cflag
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1158 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1159 scratch1:0 -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1160 update_flags NV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1161 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1162 scratch1:0 -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1163 update_flags XCNV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1164 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1165 scratch1 &= 0xFF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1166 if scratch1
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1167 update_flags Z0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1168 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1169 scratch2 = aregs.Y
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1170 ocall write_8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1171 m68k_prefetch
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1172
2587
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1173 1000DDD011MMMRRR divu
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1174 invalid M 1
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1175 invalid M 7 R 5
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1176 invalid M 7 R 6
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1177 invalid M 7 R 7
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1178 m68k_fetch_src_ea M R 1
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1179
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1180 if src = 0
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1181 cycles 4
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1182 update_flags N0Z0V0
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1183 m68k_trap 5
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1184 else
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1185 ccall divu context D src
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1186 m68k_prefetch
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1187 end
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1188
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1189
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1190 1000DDD111MMMRRR divs
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1191 invalid M 1
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1192 invalid M 7 R 5
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1193 invalid M 7 R 6
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1194 invalid M 7 R 7
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1195 local tmp 32
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1196 m68k_fetch_src_ea M R 1
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1197
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1198 if src = 0
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1199 cycles 4
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1200 update_flags N0Z0V0
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1201 m68k_trap 5
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1202 else
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1203 ccall divs context D src
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1204 m68k_prefetch
e04c7e753bf6 Implement divs and divu in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2586
diff changeset
1205 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1206
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1207 1001DDD0ZZMMMRRR sub_ea_dn
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1208 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1209 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1210 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1211 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1212 m68k_fetch_src_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1213
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1214 sub src dregs.D dregs.D Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1215 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1216 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1217
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1218 1001DDD1ZZMMMRRR sub_dn_ea
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1219 invalid M 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1220 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1221 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1222 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1223 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1224 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1225 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1226 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1227 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1228 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1229
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1230 sub dregs.D dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1231 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1232 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1233 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1234
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1235 1001AAAZ11MMMRRR suba
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1236 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1237 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1238 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1239 local size 16
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1240 local ext_src 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1241 if Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1242 size = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1243 switch M
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1244 case 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1245 #dreg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1246 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1247 case 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1248 #areg src
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1249 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1250 case 7
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1251 if R = 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1252 #immediate
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1253 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1254 else
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1255 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1256 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1257 default
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1258 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1259 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1260 else
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1261 size = 1
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1262 cycles 4
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1263 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1264 m68k_fetch_src_ea M R size
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1265 switch size
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1266 case 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1267 sext 32 src ext_src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1268 meta src ext_src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1269 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1270
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1271 sub src aregs.A aregs.A
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1272 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1273
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1274 00000100ZZMMMRRR subi
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1275 local immed 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1276 invalid Z 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1277 invalid M 1
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1278 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1279 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1280 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1281 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1282 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1283 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1284 #fetch immediate operand
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1285 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1286 switch Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1287 case 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1288 lsl prefetch 16 immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1289 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1290 or prefetch immed immed
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1291 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1292 cycles 4
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1293 end
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1294 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1295 mov prefetch immed
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1296 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1297 #fetch dst EA
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1298 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1299
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1300 sub immed dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1301 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1302 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1303 m68k_prefetch
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1304
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1305 0101III1ZZMMMRRR subq
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1306 invalid Z 3
2647
3c689000e571 Fix addq.w and subq.w with address register destination in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2646
diff changeset
1307 invalid M 1 Z 0
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1308 invalid M 7 R 2
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1309 invalid M 7 R 3
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1310 invalid M 7 R 4
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1311 invalid M 7 R 5
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1312 invalid M 7 R 6
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1313 invalid M 7 R 7
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1314 local src 32
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1315 switch I
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1316 case 0
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1317 mov 8 src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1318 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1319 mov I src
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1320 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1321
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1322 m68k_fetch_dst_ea M R Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1323 switch M
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1324 case 1
2647
3c689000e571 Fix addq.w and subq.w with address register destination in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2646
diff changeset
1325 sub src dst dst 2
1941
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1326 default
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1327 sub src dst dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1328 update_flags XNZVC
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1329 end
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1330 m68k_save_dst Z
9eec86183aae Implement 68K or and sub instructions in new core
Michael Pavone <pavone@retrodev.com>
parents: 1940
diff changeset
1331 m68k_prefetch
2586
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1332
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1333 1001DDD1ZZ000SSS subx_dy_dx
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1334 invalid Z 3
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1335 sbc dregs.S dregs.D dregs.D Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1336 update_flags XNVC
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1337 switch Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1338 case 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1339 local tmp8 8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1340 mov dregs.D tmp8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1341 if tmp8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1342 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1343 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1344 case 1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1345 local tmp16 16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1346 mov dregs.D tmp16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1347 if tmp16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1348 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1349 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1350 case 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1351 cycles 4
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1352 if dregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1353 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1354 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1355 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1356 m68k_prefetch
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1357
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1358 1001DDD1ZZ001SSS subx_ay_ax
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1359 invalid Z 3
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1360 if Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1361 decsize Z aregs.S aregs.S
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1362 else
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1363 switch S
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1364 case 7
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1365 sub 2 aregs.S aregs.S
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1366 default
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1367 decsize Z aregs.S aregs.S
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1368 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1369 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1370 #predec penalty on src only
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1371 cycles 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1372 mov aregs.S scratch1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1373 switch Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1374 case 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1375 ocall read_8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1376 case 1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1377 ocall read_16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1378 case 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1379 m68k_read32
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1380 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1381 mov scratch1 scratch2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1382 if Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1383 decsize Z aregs.D aregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1384 else
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1385 switch D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1386 case 7
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1387 sub 2 aregs.D aregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1388 default
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1389 decsize Z aregs.D aregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1390 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1391 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1392 mov aregs.D scratch1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1393 switch Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1394 case 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1395 ocall read_8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1396 case 1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1397 ocall read_16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1398 case 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1399 m68k_read32
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1400 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1401 sbc scratch2 scratch1 scratch1 Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1402 update_flags XNVC
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1403 switch Z
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1404 case 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1405 local tmp8 8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1406 mov dregs.D tmp8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1407 if tmp8
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1408 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1409 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1410 case 1
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1411 local tmp16 16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1412 mov dregs.D tmp16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1413 if tmp16
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1414 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1415 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1416 case 2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1417 if dregs.D
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1418 update_flags Z0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1419 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1420 end
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1421 mov aregs.D scratch2
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1422 m68k_write_size Z 0
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1423 m68k_prefetch
6c58cadeabe1 Implement subx in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2585
diff changeset
1424
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1425 1110CCC0ZZ001RRR lsri
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1426 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1427 switch C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1428 case 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1429 meta shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1430 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1431 meta shift C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1432 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1433 lsr dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1434 update_flags XNZV0C
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1435 local cyc 32
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1436 cyc = shift + shift
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1437 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1438 case 2
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1439 cyc += 4
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1440 default
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1441 cyc += 2
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1442 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1443 cycles cyc
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1444 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1445 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1446
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1447 1110CCC0ZZ101RRR lsr_dn
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1448 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1449 local shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1450 and dregs.C 63 shift
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1451 switch Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1452 case 2
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1453 if shift >=U 32
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1454 if shift = 32
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1455 lsr dregs.R 31 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1456 lsr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1457 update_flags XN0Z1V0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1458 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1459 dregs.R:Z = 0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1460 update_flags X0N0Z1V0C0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1461 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1462 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1463 lsr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1464 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1465 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1466 xflag = cflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1467 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1468 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1469 case 1
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1470 if shift >=U 16
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1471 if shift = 16
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1472 lsr dregs.R 15 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1473 lsr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1474 update_flags XN0Z1V0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1475 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1476 dregs.R:Z = 0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1477 update_flags X0N0Z1V0C0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1478 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1479 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1480 lsr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1481 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1482 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1483 xflag = cflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1484 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1485 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1486 case 0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1487 if shift >=U 8
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1488 if shift = 8
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1489 lsr dregs.R 7 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1490 lsr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1491 update_flags XN0Z1V0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1492 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1493 dregs.R:Z = 0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1494 update_flags X0N0Z1V0C0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1495 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1496 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1497 lsr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1498 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1499 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1500 xflag = cflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1501 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1502 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1503 end
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1504 add shift shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1505 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1506 case 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1507 add 4 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1508 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1509 add 2 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1510 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1511 cycles shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1512 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1513 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1514
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1515 1110001011MMMRRR lsr_ea
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1516 invalid M 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1517 invalid M 1
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1518 invalid M 7 R 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1519 invalid M 7 R 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1520 invalid M 7 R 4
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1521 invalid M 7 R 5
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1522 invalid M 7 R 6
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1523 invalid M 7 R 7
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1524
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1525 m68k_fetch_dst_ea M R 1
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1526 lsr dst 1 dst 1
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1527 update_flags XNZV0C
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1528 m68k_save_dst 1
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1529 m68k_prefetch
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1530
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1531 1110CCC0ZZ000RRR asri
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1532 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1533 switch C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1534 case 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1535 meta shift 8
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1536 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1537 meta shift C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1538 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1539 asr dregs.R shift dregs.R Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1540 update_flags XNZV0C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1541 local cyc 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1542 cyc = shift + shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1543 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1544 case 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1545 cyc += 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1546 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1547 cyc += 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1548 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1549 cycles cyc
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1550 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1551 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1552
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1553 1110CCC0ZZ100RRR asr_dn
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1554 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1555 local shift 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1556 and dregs.C 63 shift
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1557 switch Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1558 case 2
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1559 if shift >=U 32
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1560 asr dregs.R 31 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1561 asr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1562 update_flags NZV0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1563 cflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1564 xflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1565 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1566 asr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1567 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1568 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1569 xflag = cflag
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1570 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1571 end
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1572 case 1
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1573 if shift >=U 16
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1574 asr dregs.R 15 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1575 asr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1576 update_flags NZV0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1577 cflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1578 xflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1579 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1580 asr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1581 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1582 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1583 xflag = cflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1584 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1585 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1586 case 0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1587 if shift >=U 8
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1588 asr dregs.R 7 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1589 asr dregs.R 1 dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1590 update_flags NZV0
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1591 cflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1592 xflag = nflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1593 else
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1594 asr dregs.R shift dregs.R Z
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1595 update_flags NZV0C
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1596 if shift
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1597 xflag = cflag
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1598 end
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1599 end
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1600 end
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1601 shift += shift
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1602 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1603 case 2
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1604 shift += 4
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1605 default
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1606 shift += 2
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1607 end
2611
9bd90cd94000 Fix asr and lsr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2610
diff changeset
1608 cycles shift
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1609 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1610 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1611
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1612 1110000011MMMRRR asr_ea
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1613 invalid M 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1614 invalid M 1
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1615 invalid M 7 R 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1616 invalid M 7 R 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1617 invalid M 7 R 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1618 invalid M 7 R 5
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1619 invalid M 7 R 6
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1620 invalid M 7 R 7
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1621
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1622 m68k_fetch_dst_ea M R 1
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1623 asr dst 1 dst 1
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1624 update_flags XNZV0C
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1625 m68k_save_dst 1
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1626 m68k_prefetch
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1627
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1628 1110CCC1ZZ001RRR lsli
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1629 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1630 switch C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1631 case 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1632 meta shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1633 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1634 meta shift C
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1635 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1636 lsl dregs.R shift dregs.R Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1637 update_flags XNZV0C
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1638 local cyc 32
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1639 cyc = shift + shift
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1640 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1641 case 2
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1642 cyc += 4
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1643 default
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1644 cyc += 2
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1645 end
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
1646 cycles cyc
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1647 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1648 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1649
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1650 1110CCC1ZZ101RRR lsl_dn
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1651 invalid Z 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1652 local shift 8
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1653 and dregs.C 63 shift
2610
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1654 switch Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1655 case 2
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1656 if shift >=U 32
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1657 if shift = 32
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1658 lsl dregs.R 31 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1659 lsl dregs.R 1 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1660 update_flags XN0Z1V0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1661 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1662 dregs.R:Z = 0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1663 update_flags X0N0Z1V0C0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1664 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1665 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1666 lsl dregs.R shift dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1667 update_flags NZV0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1668 if shift
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1669 xflag = cflag
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1670 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1671 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1672 case 1
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1673 if shift >=U 16
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1674 if shift = 16
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1675 lsl dregs.R 15 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1676 lsl dregs.R 1 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1677 update_flags XN0Z1V0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1678 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1679 dregs.R:Z = 0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1680 update_flags X0N0Z1V0C0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1681 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1682 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1683 lsl dregs.R shift dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1684 update_flags NZV0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1685 if shift
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1686 xflag = cflag
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1687 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1688 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1689 case 0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1690 if shift >=U 8
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1691 if shift = 8
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1692 lsl dregs.R 7 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1693 lsl dregs.R 1 dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1694 update_flags XN0Z1V0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1695 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1696 dregs.R:Z = 0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1697 update_flags X0N0Z1V0C0
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1698 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1699 else
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1700 lsl dregs.R shift dregs.R Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1701 update_flags NZV0C
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1702 if shift
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1703 xflag = cflag
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1704 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1705 end
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1706 end
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1707 add shift shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1708 switch Z
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1709 case 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1710 add 4 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1711 default
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1712 add 2 shift shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1713 end
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1714 cycles shift
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1715 #TODO: should this happen before or after the majority of the shift?
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1716 m68k_prefetch
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1717
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1718 1110001111MMMRRR lsl_ea
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1719 invalid M 0
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1720 invalid M 1
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1721 invalid M 7 R 2
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1722 invalid M 7 R 3
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1723 invalid M 7 R 4
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1724 invalid M 7 R 5
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1725 invalid M 7 R 6
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1726 invalid M 7 R 7
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1727
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1728 m68k_fetch_dst_ea M R 1
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1729 lsl dst 1 dst 1
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1730 update_flags XNZV0C
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1731 m68k_save_dst 1
1991
7d4df6b74263 Somewhat buggy implementations of shift instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 1941
diff changeset
1732 m68k_prefetch
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1733
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1734 1110CCC1ZZ000RRR asli
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1735 invalid Z 3
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1736 local vtmp 8
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1737 local shift 8
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1738 vtmp = 0
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1739 switch C
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1740 case 0
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1741 shift = 8
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1742 default
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1743 shift = C
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1744 end
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1745 shift -= 1
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1746 loop shift
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1747 lsl dregs.R 1 dregs.R Z
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1748 update_flags V
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1749 vtmp |= vflag
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1750 end
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1751 shift += 1
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1752 lsl dregs.R 1 dregs.R Z
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1753 update_flags XNZVC
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1754 vflag |= vtmp
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1755 local cyc 32
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1756 cyc = shift + shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1757 switch Z
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1758 case 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1759 cyc += 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1760 default
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1761 cyc += 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1762 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1763 cycles cyc
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1764 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1765 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1766
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1767 1110CCC1ZZ100RRR asl_dn
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1768 invalid Z 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1769 local shift 8
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1770 local vtmp 8
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1771 and dregs.C 63 shift
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1772 vtmp = 0
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1773 if shift
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1774 shift -= 1
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1775 loop shift
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1776 lsl dregs.R 1 dregs.R Z
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1777 update_flags V
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1778 vtmp |= vflag
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1779 end
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1780 shift += 1
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1781 lsl dregs.R 1 dregs.R Z
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1782 update_flags XNZVC
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1783 vflag |= vtmp
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1784 else
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1785 cmp 0 dregs.R Z
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1786 update_flags NZV0C
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1787 end
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1788 shift += shift
2610
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1789 switch Z
2de52352936c Fix lsl in new CPU core and make asl less broken
Michael Pavone <pavone@retrodev.com>
parents: 2593
diff changeset
1790 case 2
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1791 shift += 4
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1792 default
2621
ce9386a7b21e Fix V flag for asl in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2618
diff changeset
1793 shift += 2
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1794 end
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1795 cycles shift
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1796 #TODO: should this happen before or after the majority of the shift?
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1797 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1798
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1799 1110000111MMMRRR asl_ea
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1800 invalid M 0
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1801 invalid M 1
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1802 invalid M 7 R 2
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1803 invalid M 7 R 3
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1804 invalid M 7 R 4
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1805 invalid M 7 R 5
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1806 invalid M 7 R 6
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1807 invalid M 7 R 7
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1808
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1809 m68k_fetch_dst_ea M R 1
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1810 lsl dst 1 dst 1
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1811 update_flags XNZV0C
2648
e16f567be36c Fix lsl/lsr/asl/asr with memory operand
Michael Pavone <pavone@retrodev.com>
parents: 2647
diff changeset
1812 m68k_save_dst 1
2502
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1813 m68k_prefetch
ad50530a7c27 Partially functional asr/asl implementations in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2501
diff changeset
1814
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1815 00ZZRRRMMMEEESSS move
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1816 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1817 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1818 invalid M 7 #not actually invalid, but will be handled separately due to DSL limitations
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1819 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1820 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1821 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1822 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1823 local memsrc 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1824 #move uses a different size format than most instructions
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1825 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1826 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1827 mov 0 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1828 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1829 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1830 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1831 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1832 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1833 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1834
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1835 if src_is_mem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1836 #avoid clobbering src if we need scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1837 mov src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1838 meta src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1839 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1840
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1841 cmp 0 src size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1842 update_flags NZV0C0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1843
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1844 switch M
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1845 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1846 mov src dregs.R size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1847
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1848 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1849 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1850 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1851 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1852
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1853 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1854 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1855 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1856 switch R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1857 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1858 if size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1859 addsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1860 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1861 addsize 1 aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1862 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1863 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1864 addsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1865 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1866 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1867
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1868 case 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1869 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1870 switch R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1871 case 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1872 if size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1873 decsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1874 else
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1875 decsize 1 aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1876 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1877 default
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1878 decsize size aregs.R aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1879 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1880 mov aregs.R scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1881 m68k_write_size size 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1882
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1883 case 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1884 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1885 sext 32 prefetch scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1886 add aregs.R scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1887 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1888 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1889
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1890 case 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1891 m68k_index_word
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1892 add aregs.R scratch1 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1893 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1894 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1895 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1896 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1897
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1898
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1899 00ZZ00M111EEESSS move_abs
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1900 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1901 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1902 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1903 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1904 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1905 local memsrc 32
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1906 #move uses a different size format than most instructions
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1907 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1908 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1909 mov 0 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1910 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1911 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1912 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1913 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1914 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1915 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1916
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1917 if src_is_mem
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1918 #avoid clobbering src if we need scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1919 mov src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1920 meta src memsrc
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1921 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1922
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1923 cmp 0 src size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1924 update_flags NZV0C0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1925
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1926 switch M
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1927 case 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1928 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1929 sext 32 prefetch scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1930
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1931 case 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1932 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1933 lsl prefetch 16 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1934 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1935 or prefetch scratch2 scratch2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1936 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1937 mov src scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1938 m68k_write_size size 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1939 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1940
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1941 00ZZRRR001EEESSS movea
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1942 local size 8
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1943 invalid Z 0
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1944 invalid Z 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1945 invalid E 7 S 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1946 invalid E 7 S 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1947 invalid E 7 S 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1948 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1949 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1950 mov 2 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1951 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1952 mov 1 size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1953 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1954 m68k_fetch_src_ea E S size
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1955 switch Z
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1956 case 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1957 mov src aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1958 case 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1959 sext 32 src aregs.R
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1960 end
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1961 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1962
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1963 0100010011MMMRRR move_to_ccr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1964 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1965 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1966 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1967 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1968 m68k_fetch_src_ea M R 1
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1969 mov src ccr
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1970 cycles 8
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1971 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1972
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1973 0100011011MMMRRR move_to_sr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1974 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1975 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1976 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1977 invalid M 7 R 7
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
1978 #TODO: privilege violation exception if in user mode
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1979 m68k_fetch_src_ea M R 1
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1980 ccr = src
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
1981 status = src >> 8
2583
0f7609fe03f2 Implement andi/ori/eori to sr, fix eori to ccr in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2580
diff changeset
1982 check_user_mode_swap_ssp_usp
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1983 update_sync
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1984 cycles 8
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1985 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1986
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1987 0100000011MMMRRR move_from_sr
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1988 invalid M 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1989 invalid M 7 R 2
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1990 invalid M 7 R 3
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1991 invalid M 7 R 4
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1992 invalid M 7 R 5
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1993 invalid M 7 R 6
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1994 invalid M 7 R 7
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1995 m68k_fetch_dst_ea M R 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1996 lsl status 8 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1997 or ccr scratch1 scratch1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1998 mov scratch1 dst
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
1999 if M
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2000 cycles 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2001 else
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2002 cycles 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2003 end
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2004 m68k_save_dst 1
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2005 m68k_prefetch
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2006
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2007 01000000ZZMMMRRR negx
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2008 invalid M 1
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2009 invalid M 7 R 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2010 invalid M 7 R 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2011 invalid M 7 R 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2012 invalid M 7 R 5
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2013 invalid M 7 R 6
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2014 invalid M 7 R 7
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2015 m68k_fetch_dst_ea M R Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2016 sbc dst 0 dst Z
2633
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2017 update_flags XNVC
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2018 switch Z
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2019 case 0
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2020 local tmp8 8
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2021 tmp8 = dst
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2022 if tmp8
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2023 update_flags Z0
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2024 end
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2025 case 1
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2026 local tmp16 16
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2027 tmp16 = dst
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2028 if tmp16
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2029 update_flags Z0
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2030 end
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2031 case 2
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2032 local tmp32 32
2464
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2033 if M = 0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2034 cycles 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2035 end
2633
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2036 tmp32 = dst
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2037 if dst
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2038 update_flags Z0
1ef2734ac052 Fix Z flag for negx
Michael Pavone <pavone@retrodev.com>
parents: 2631
diff changeset
2039 end
2464
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2040 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2041 m68k_save_dst Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2042 m68k_prefetch
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2043
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2044 01000010ZZMMMRRR clr
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2045 invalid M 1
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2046 invalid M 7 R 2
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2047 invalid M 7 R 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2048 invalid M 7 R 4
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2049 invalid M 7 R 5
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2050 invalid M 7 R 6
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2051 invalid M 7 R 7
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2052 invalid Z 3
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2053 m68k_fetch_dst_ea M R Z
2450
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2054 if Z = 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2055 if M = 0
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2056 #register clears have 2 cycle penalty for longword size
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2057 cycles 2
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2058 end
6c93869babc1 Fix cycle counts for a number of instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2448
diff changeset
2059 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2060 dst:Z = 0
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2061 update_flags N0Z1V0C0
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2062 m68k_save_dst Z
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2063 m68k_prefetch
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2064
2590
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2065 0100100000MMMRRR nbcd
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2066 local lowx_corf 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2067 local lowy_cmp 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2068 local res 8
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2069 invalid M 1
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2070 invalid M 7 R 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2071 invalid M 7 R 3
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2072 invalid M 7 R 4
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2073 invalid M 7 R 5
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2074 invalid M 7 R 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2075 invalid M 7 R 7
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2076 m68k_fetch_dst_ea M R 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2077 lowx_corf = dst & 0xF
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2078 lowy_cmp = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2079 sbc lowx_corf lowy_cmp lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2080 if lowy_cmp >= 0xA
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2081 lowx_corf = 6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2082 lowy_cmp = 0xA6
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2083 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2084 lowx_corf = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2085 lowy_cmp = 0xA0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2086 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2087 res = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2088 sbc dst res res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2089 update_flags XC
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2090 if cflag
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2091 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2092 res -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2093 update_flags NV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2094 else
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2095 if res >=U lowy_cmp
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2096 lowx_corf |= 0x60
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2097 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2098 res -= lowx_corf
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2099 update_flags XCNV
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2100 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2101 if res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2102 update_flags Z0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2103 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2104 dst:0 = res
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2105 if M = 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2106 cycles 2
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2107 end
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2108 m68k_save_dst 0
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2109 m68k_prefetch
e602dbf776d8 Fix abcd and implement sbcd and nbcd in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2588
diff changeset
2110
2453
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2111 00001100ZZMMMRRR cmpi
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2112 local immed 32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2113 invalid Z 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2114 invalid M 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2115 invalid M 7 R 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2116 invalid M 7 R 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2117 invalid M 7 R 4
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2118 invalid M 7 R 5
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2119 invalid M 7 R 6
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2120 invalid M 7 R 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2121 #fetch immediate operand
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2122 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2123 switch Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2124 case 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2125 immed = prefetch << 16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2126 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2127 immed |= prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2128 if M = 0
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2129 cycles 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2130 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2131 default
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2132 immed = prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2133 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2134 #fetch dst EA
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2135 m68k_fetch_dst_ea M R Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2136
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2137 cmp immed dst Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2138 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2139 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2140
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2141 1011DDD1ZZ001SSS cmpm
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2142 invalid Z 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2143 scratch1 = aregs.S
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2144 switch Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2145 case 0
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2146 ocall read_8
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2147 case 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2148 ocall read_16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2149 case 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2150 m68k_read32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2151 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2152 scratch2 = scratch1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2153 if Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2154 addsize Z aregs.S aregs.S
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2155 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2156 if S = 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2157 aregs.S += 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2158 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2159 aregs.S += 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2160 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2161 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2162 scratch1 = aregs.D
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2163 switch Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2164 case 0
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2165 ocall read_8
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2166 case 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2167 ocall read_16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2168 case 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2169 m68k_read32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2170 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2171 if Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2172 addsize Z aregs.D aregs.D
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2173 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2174 if D = 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2175 aregs.D += 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2176 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2177 aregs.D += 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2178 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2179 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2180 cmp scratch2 scratch1 Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2181 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2182 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2183
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2184 1011DDD0ZZMMMRRR cmp
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2185 invalid M 7 R 5
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2186 invalid M 7 R 6
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2187 invalid M 7 R 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2188 invalid Z 3
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2189 m68k_fetch_src_ea M R Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2190
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2191 if Z = 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2192 cycles 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2193 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2194
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2195 cmp src dregs.D Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2196 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2197 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2198
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2199 1011DDDZ11MMMRRR cmpa
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2200 invalid M 7 R 5
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2201 invalid M 7 R 6
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2202 invalid M 7 R 7
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2203 local size 16
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2204 local ext_src 32
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2205 if Z
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2206 size = 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2207 else
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2208 size = 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2209 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2210 m68k_fetch_src_ea M R size
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2211 cycles 2
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2212 if size = 1
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2213 sext 32 src ext_src
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2214 meta src ext_src
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2215 end
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2216 cmp src aregs.D
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2217 update_flags NZVC
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2218 m68k_prefetch
7d7525769ce2 Implement cmp instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2450
diff changeset
2219
2454
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2220 0000100000MMMRRR btsti
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2221 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2222 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2223 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2224 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2225
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2226 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2227 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2228 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2229 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2230 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2231 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2232 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2233 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2234 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2235 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2236 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2237 m68k_fetch_src_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2238 tmp &= src
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2239 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2240 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2241
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2242 0000100001MMMRRR bchgi
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2243 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2244 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2245 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2246 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2247 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2248 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2249 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2250
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2251 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2252 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2253 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2254 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2255 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2256 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2257 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2258 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2259 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2260 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2261 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2262 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2263 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2264 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2265 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2266 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2267 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2268 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2269 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2270 dst ^= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2271 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2272 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2273
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2274 0000100010MMMRRR bclri
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2275 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2276 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2277 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2278 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2279 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2280 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2281 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2282
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2283 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2284 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2285 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2286 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2287 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2288 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2289 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2290 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2291 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2292 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2293 cycles 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2294 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2295 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2296 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2297 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2298 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2299 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2300 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2301 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2302 tmp = ~tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2303 dst &= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2304 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2305 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2306
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2307 0000100011MMMRRR bseti
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2308 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2309 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2310 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2311 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2312 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2313 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2314 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2315
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2316 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2317 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2318 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2319 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2320 tmp = scratch1 & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2321 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2322 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2323 tmp = scratch1 & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2324 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2325 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2326 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2327 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2328 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2329 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2330 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2331 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2332 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2333 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2334 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2335 dst |= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2336 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2337 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2338
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2339 0000SSS100MMMRRR btst_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2340 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2341 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2342 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2343 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2344
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2345 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2346 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2347 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2348 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2349 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2350 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2351 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2352 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2353 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2354 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2355 m68k_fetch_src_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2356 tmp &= src
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2357 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2358 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2359
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2360 0000SSS101MMMRRR bchg_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2361 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2362 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2363 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2364 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2365 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2366 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2367 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2368
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2369 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2370 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2371 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2372 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2373 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2374 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2375 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2376 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2377 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2378 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2379 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2380 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2381 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2382 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2383 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2384 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2385 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2386 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2387 dst ^= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2388 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2389 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2390
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2391 0000SSS110MMMRRR bclr_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2392 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2393 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2394 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2395 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2396 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2397 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2398 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2399
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2400 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2401 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2402 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2403 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2404 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2405 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2406 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2407 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2408 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2409 cycles 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2410 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2411 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2412 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2413 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2414 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2415 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2416 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2417 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2418 tmp = ~tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2419 dst &= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2420 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2421 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2422
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2423 0000SSS111MMMRRR bset_dn
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2424 invalid M 1
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2425 invalid M 7 R 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2426 invalid M 7 R 3
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2427 invalid M 7 R 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2428 invalid M 7 R 5
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2429 invalid M 7 R 6
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2430 invalid M 7 R 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2431
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2432 local tmp 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2433 local tmp2 32
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2434 if M
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2435 tmp = dregs.S & 7
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2436 meta size 0
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2437 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2438 tmp = dregs.S & 31
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2439 meta size 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2440 if tmp >=U 16
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2441 cycles 4
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2442 else
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2443 cycles 2
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2444 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2445 end
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2446 tmp = 1 << tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2447 m68k_fetch_dst_ea M R size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2448 tmp2 = tmp & dst
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2449 update_flags Z
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2450 dst |= tmp
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2451 m68k_save_dst size
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2452 m68k_prefetch
b1e8e7554f2f Implement bit instructions in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2453
diff changeset
2453
2456
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2454 0000DDD10Z001AAA movep_ay_dx
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2455 local address 32
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2456 m68k_prefetch
2639
0046305e3fa8 Fix movep with negative displacement
Michael Pavone <pavone@retrodev.com>
parents: 2636
diff changeset
2457 sext 32 scratch1 scratch1
2456
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2458 scratch1 += aregs.A
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2459 address = scratch1 + 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2460 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2461 dregs.D:1 = scratch1 << 8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2462 scratch1 = address
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2463 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2464 dregs.D:0 = scratch1
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2465 if Z
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2466 address += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2467 scratch1 = address
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2468 dregs.D <<= 16
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2469 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2470 dregs.D:1 = scratch1 << 8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2471 scratch1 = address + 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2472 ocall read_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2473 dregs.D:0 = scratch1
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2474 end
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2475 m68k_prefetch
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2476
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2477 0000DDD11Z001AAA movep_dx_ay
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2478 m68k_prefetch
2639
0046305e3fa8 Fix movep with negative displacement
Michael Pavone <pavone@retrodev.com>
parents: 2636
diff changeset
2479 sext 32 scratch1 scratch1
2456
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2480 scratch2 = scratch1 + aregs.A
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2481 if Z
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2482 scratch1 = dregs.D >> 24
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2483 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2484 scratch2 += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2485 scratch1 = dregs.D >> 16
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2486 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2487 scratch2 += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2488 end
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2489 scratch1 = dregs.D >> 8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2490 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2491 scratch2 += 2
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2492 scratch1 = dregs.D
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2493 ocall write_8
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2494 m68k_prefetch
72d0eac49507 Implement movep in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2454
diff changeset
2495
2464
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2496 01000100ZZMMMRRR neg
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2497 invalid Z 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2498 invalid M 1
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2499 invalid M 7 R 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2500 invalid M 7 R 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2501 invalid M 7 R 4
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2502 invalid M 7 R 5
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2503 invalid M 7 R 6
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2504 invalid M 7 R 7
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2505
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2506 m68k_fetch_dst_ea M R Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2507 dst:Z = -dst
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2508 update_flags XNZVC
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2509 if Z = 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2510 if M = 0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2511 cycles 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2512 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2513 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2514 m68k_save_dst Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2515 m68k_prefetch
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2516
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2517 01000110ZZMMMRRR not
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2518 invalid Z 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2519 invalid M 1
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2520 invalid M 7 R 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2521 invalid M 7 R 3
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2522 invalid M 7 R 4
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2523 invalid M 7 R 5
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2524 invalid M 7 R 6
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2525 invalid M 7 R 7
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2526
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2527 m68k_fetch_dst_ea M R Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2528 dst:Z = ~dst
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2529 update_flags NZV0C0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2530 if Z = 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2531 if M = 0
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2532 cycles 2
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2533 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2534 end
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2535 m68k_save_dst Z
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2536 m68k_prefetch
f9d5c137c74b Implement neg and not instructions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2456
diff changeset
2537
2468
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2538 01001000ZZ000RRR ext
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2539 invalid Z 0
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2540 invalid Z 1
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2541 if Z = 3
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2542 meta bits 32
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2543 else
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2544 meta bits 16
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2545 end
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2546 sext bits dregs.R dregs.R
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2547 update_flags NZV0C0
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2548 m68k_prefetch
0ca78837e4d2 Implement ext instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2464
diff changeset
2549
2651
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2550 0100101011MMMRRR tas
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2551 invalid M 1
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2552 invalid M 7 R 2
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2553 invalid M 7 R 3
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2554 invalid M 7 R 4
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2555 invalid M 7 R 5
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2556 invalid M 7 R 6
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2557 invalid M 7 R 7
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2558
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2559 m68k_fetch_dst_ea M R 0
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2560 cmp 0 dst 0
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2561 update_flags NZV0C0
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2562 dst |= 0x80
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2563 if M
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2564 cycles 2
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2565 ocall rmw_writeback
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2566 end
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2567 m68k_prefetch
1072cc337822 Implement TAS in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2648
diff changeset
2568
2562
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2569 010011100100VVVV trap
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2570 local vector 32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2571 scratch1 = pc
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2572 vector = V + 32
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2573 m68k_trap vector
595719fe69f2 Implement exg, muls and mulu in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2502
diff changeset
2574
2470
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2575 0100111001010RRR link
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2576 a7 -= 4
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2577 scratch2 = a7
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2578 #TODO: confirm order of fetch and write
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2579 m68k_write32 aregs.R
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2580 m68k_prefetch
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2581 aregs.R = a7
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2582 sext 32 scratch1 scratch1
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2583 a7 += scratch1
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2584 m68k_prefetch
6bec9e66d0db Implement link instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2468
diff changeset
2585
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2586 0100111001011RRR unlk
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2587 a7 = aregs.R
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2588 scratch1 = a7
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2589 m68k_read32
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2590 a7 += 4
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2591 aregs.R = scratch1
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2592 m68k_prefetch
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2593
2472
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2594 0100100001000RRR swap
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2595 ror dregs.R 16 dregs.R
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2596 update_flags NZV0C0
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2597 m68k_prefetch
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2598
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2599 m68k_calc_ea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2600 arg mode 16
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2601 arg reg 16
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2602 arg index_penalty 32
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2603
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2604 switch mode
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2605 case 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2606 #address reg indirect
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2607 meta ea aregs.reg
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2608 case 3
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2609 #postincrement
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2610 meta ea aregs.reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2611 case 4
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2612 #predecrement
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2613 #note: this case is only used when m68k_calc_ea
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2614 #is called from movem_reg_to_mem which does its own decrementing
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2615 meta ea aregs.reg
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2616 case 5
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2617 #displacement
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2618 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2619 sext 32 prefetch scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2620 scratch1 += aregs.reg
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2621 meta ea scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2622 case 6
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2623 #index
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2624 m68k_index_word
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2625 cycles index_penalty
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2626 scratch1 += aregs.reg
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2627 meta ea scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2628 case 7
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2629 switch reg
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2630 case 0
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2631 #absolute short
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2632 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2633 sext 32 prefetch scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2634 case 1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2635 #absoltue long
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2636 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2637 scratch2 = prefetch << 16
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2638 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2639 scratch1 = scratch2 | prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2640 case 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2641 #pc displacement
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2642 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2643 sext 32 prefetch scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2644 scratch1 += pc
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2645 scratch1 -= 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2646 case 3
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2647 #pc indexed
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2648 m68k_index_word
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2649 cycles index_penalty
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2650 scratch1 += pc
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2651 scratch1 -= 2
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2652 end
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2653 meta ea scratch1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2654 end
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2655
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2656 0100100001MMMRRR pea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2657 invalid M 0
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2658 invalid M 1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2659 invalid M 3
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2660 invalid M 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2661 invalid M 7 R 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2662 invalid M 7 R 5
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2663 invalid M 7 R 6
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2664 invalid M 7 R 7
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2665
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2666 m68k_calc_ea M R 4
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2667 scratch2 = a7 - 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2668 m68k_write32_lowfirst ea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2669 a7 -= 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2670
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2671 m68k_prefetch
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2672
2622
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2673 0100DDDZZ0MMMRRR chk
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2674 invalid M 1
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2675 invalid M 7 R 5
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2676 invalid M 7 R 6
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2677 invalid M 7 R 7
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2678 invalid Z 0
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2679 invalid Z 1
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2680 local tmp 8
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2681 local src_alt 32
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2682 switch Z
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2683 case 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2684 meta size 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2685 case 3
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2686 meta size 1
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2687 end
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2688 m68k_fetch_src_ea M R size
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2689 if src_is_mem
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2690 src_alt = src
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2691 meta src src_alt
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2692 end
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2693 m68k_prefetch
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2694 cmp dregs.D src size
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2695 update_flags NZVC
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2696 tmp = vflag
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2697 tmp |= nflag
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2698 cmp 0 dregs.D size
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2699 update_flags NZV0C0
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2700 if tmp
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2701 # D > src (signed)
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2702 pc -= 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2703 m68k_trap 6
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2704 else
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2705 cycles 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2706 if nflag
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2707 # D < 0
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2708 pc -= 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2709 m68k_trap 6
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2710 else
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2711 cycles 2
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2712 end
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2713 end
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2714
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2715 0100DDD111MMMRRR lea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2716 invalid M 0
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2717 invalid M 1
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2718 invalid M 3
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2719 invalid M 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2720 invalid M 7 R 4
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2721 invalid M 7 R 5
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2722 invalid M 7 R 6
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2723 invalid M 7 R 7
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2724
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2725 m68k_calc_ea M R 4
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2726 aregs.D = ea
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2727
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2728 m68k_prefetch
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2729
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2730 01001010ZZMMMRRR tst
2653
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
2731 invalid Z 3
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2732 invalid M 7 R 5
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2733 invalid M 7 R 6
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2734 invalid M 7 R 7
2478
ea37200967c7 Implement lea and pea in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2472
diff changeset
2735
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2736 m68k_fetch_dst_ea M R Z
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2737
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2738 cmp 0 dst Z
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2739 update_flags NZV0C0
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2740 m68k_prefetch
2472
f171a12fc98c Implement swap instruction in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2470
diff changeset
2741
1838
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2742 0100111001110000 reset
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2743 if reset_handler
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2744 pcall reset_handler m68k_reset_handler context
0c1491818f4b WIP new 68K core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
2745 end
2448
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2746 cycles 128
d1eec03dca09 Fix some issues in new 68K core and add implementations of negx and clr instructions
Michael Pavone <pavone@retrodev.com>
parents: 1991
diff changeset
2747 m68k_prefetch
2479
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2748
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2749 0100111001110001 nop
29baf8d5a579 Implement unlk, tst and nop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2478
diff changeset
2750 m68k_prefetch
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2751
2618
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2752 0100111001110010 stop
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2753 if stopped
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2754 else
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2755 mov pc scratch1
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2756 ocall read_16
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2757 pc += 2
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2758 ccr = scratch1
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2759 status = scratch1 >> 8
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2760 check_user_mode_swap_ssp_usp
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2761 update_sync
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2762 stopped = 1
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2763 end
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2764 loop
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2765 cycles 4
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2766 if cycles >=U int_cycle
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2767 break
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2768 end
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2769 if cycles >=U target_cycle
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2770 break
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2771 end
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2772 end
1579b840a1af Implement stop in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2611
diff changeset
2773
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2774 0100111001110011 rte
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2775 #TODO: privilege violation exception if in user mode
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2776 #Read saved SR
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2777 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2778 ocall read_16
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2779 a7 += 2
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2780 ccr = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2781 status = scratch1 >> 8
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2782 #Read saved PC
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2783 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2784 m68k_read32
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2785 a7 += 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2786 pc = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2787
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2788 check_user_mode_swap_ssp_usp
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2789 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2790 update_sync
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2791 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2792
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2793 0100111001110101 m68k_rts
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2794 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2795 m68k_read32
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2796 a7 += 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2797 pc = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2798
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2799 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2800 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2801
2622
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2802 0100111001110110 trapv
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2803 if vflag
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2804 m68k_trap 7
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2805 else
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2806 m68k_prefetch
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2807 end
adff015dc94f Implement chk and trapv in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2621
diff changeset
2808
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2809 0100111001110111 rtr
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2810 #Read saved CCR
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2811 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2812 ocall read_16
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2813 a7 += 2
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2814 ccr = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2815 #Read saved PC
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2816 scratch1 = a7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2817 m68k_read32
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2818 a7 += 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2819 pc = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2820
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2821 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2822 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2823
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2824 0100111010MMMRRR jsr
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2825 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2826 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2827 invalid M 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2828 invalid M 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2829 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2830 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2831 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2832 invalid M 7 R 7
2585
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2833 local tmp 32
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2834
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2835 m68k_calc_ea M R 2
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2836 tmp = ea
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2837
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2838 a7 -= 4
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2839 scratch2 = a7
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2840 m68k_write32 pc
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2841
2585
c730067d5f77 Fix jsr in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2584
diff changeset
2842 pc = tmp
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2843
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2844 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2845 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2846
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
2847 0100111011MMMRRR jmp
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2848 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2849 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2850 invalid M 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2851 invalid M 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2852 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2853 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2854 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2855 invalid M 7 R 7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2856
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2857 m68k_calc_ea M R 2
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2858 pc = ea
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2859
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2860 cycles 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2861 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2862
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2863 m68k_movem_reg_to_mem
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2864 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2865 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2866 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2867 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2868
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2869 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2870 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2871 scratch2 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2872 scratch1 = reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2873 m68k_write_size size 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2874 addsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2875 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2876
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2877 m68k_movem_reg_to_mem_dec
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2878 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2879 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2880 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2881 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2882
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2883 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2884 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2885 decsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2886 scratch2 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2887 scratch1 = reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2888 m68k_write_size size 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2889 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2890
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2891
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2892 010010001ZMMMRRR movem_reg_to_mem
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2893 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2894 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2895 invalid M 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2896 invalid M 7 R 2
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2897 invalid M 7 R 3
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2898 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2899 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2900 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2901 invalid M 7 R 7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2902 local reglist 16
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2903 local address 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2904 local sz 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2905 sz = Z + 1
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2906
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2907 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2908 reglist = scratch1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2909
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2910 m68k_calc_ea M R 2
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2911 address = ea
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2912 meta addr address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2913 if M = 4
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2914 m68k_movem_reg_to_mem_dec reglist 1 a7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2915 m68k_movem_reg_to_mem_dec reglist 2 a6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2916 m68k_movem_reg_to_mem_dec reglist 4 a5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2917 m68k_movem_reg_to_mem_dec reglist 8 a4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2918 m68k_movem_reg_to_mem_dec reglist 16 a3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2919 m68k_movem_reg_to_mem_dec reglist 32 a2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2920 m68k_movem_reg_to_mem_dec reglist 64 a1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2921 m68k_movem_reg_to_mem_dec reglist 128 a0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2922 m68k_movem_reg_to_mem_dec reglist 256 d7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2923 m68k_movem_reg_to_mem_dec reglist 512 d6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2924 m68k_movem_reg_to_mem_dec reglist 1024 d5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2925 m68k_movem_reg_to_mem_dec reglist 2048 d4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2926 m68k_movem_reg_to_mem_dec reglist 4096 d3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2927 m68k_movem_reg_to_mem_dec reglist 8192 d2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2928 m68k_movem_reg_to_mem_dec reglist 16384 d1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2929 m68k_movem_reg_to_mem_dec reglist 32768 d0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2930 ea = address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2931 else
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2932 m68k_movem_reg_to_mem reglist 1 d0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2933 m68k_movem_reg_to_mem reglist 2 d1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2934 m68k_movem_reg_to_mem reglist 4 d2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2935 m68k_movem_reg_to_mem reglist 8 d3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2936 m68k_movem_reg_to_mem reglist 16 d4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2937 m68k_movem_reg_to_mem reglist 32 d5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2938 m68k_movem_reg_to_mem reglist 64 d6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2939 m68k_movem_reg_to_mem reglist 128 d7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2940 m68k_movem_reg_to_mem reglist 256 a0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2941 m68k_movem_reg_to_mem reglist 512 a1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2942 m68k_movem_reg_to_mem reglist 1024 a2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2943 m68k_movem_reg_to_mem reglist 2048 a3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2944 m68k_movem_reg_to_mem reglist 4096 a4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2945 m68k_movem_reg_to_mem reglist 8192 a5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2946 m68k_movem_reg_to_mem reglist 16384 a6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2947 m68k_movem_reg_to_mem reglist 32768 a7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2948 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2949 m68k_prefetch
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2950
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2951 m68k_movem_mem_to_dreg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2952 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2953 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2954 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2955 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2956
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2957 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2958 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2959 scratch1 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2960 if sz = 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2961 ocall read_16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2962 sext 32 scratch1 dregs.reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2963 else
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2964 m68k_read32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2965 dregs.reg = scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2966 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2967 addsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2968 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2969
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2970 m68k_movem_mem_to_areg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2971 arg reglist 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2972 arg mask 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2973 arg reg 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2974 arg size 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2975
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2976 scratch1 = reglist & mask
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2977 if scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2978 scratch1 = addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2979 if sz = 1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2980 ocall read_16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2981 sext 32 scratch1 aregs.reg
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2982 else
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2983 m68k_read32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2984 aregs.reg = scratch1
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2985 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2986 addsize size addr addr
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2987 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2988
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2989 010011001ZMMMRRR movem_mem_to_reg
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2990 invalid M 0
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2991 invalid M 1
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2992 invalid M 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2993 invalid M 7 R 4
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2994 invalid M 7 R 5
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2995 invalid M 7 R 6
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2996 invalid M 7 R 7
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
2997 local reglist 16
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2998 local address 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
2999 local sz 16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3000 sz = Z + 1
2481
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3001
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3002 m68k_prefetch
f0645adddf0d Implement some flow control instructions in new 68K core. WIP implementation of movem in new 68K core.
Michael Pavone <pavone@retrodev.com>
parents: 2479
diff changeset
3003 reglist = scratch1
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3004
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3005 m68k_calc_ea M R 2
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3006 address = ea
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3007 meta addr address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3008
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3009 m68k_movem_mem_to_dreg reglist 1 0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3010 m68k_movem_mem_to_dreg reglist 2 1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3011 m68k_movem_mem_to_dreg reglist 4 2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3012 m68k_movem_mem_to_dreg reglist 8 3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3013 m68k_movem_mem_to_dreg reglist 16 4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3014 m68k_movem_mem_to_dreg reglist 32 5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3015 m68k_movem_mem_to_dreg reglist 64 6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3016 m68k_movem_mem_to_dreg reglist 128 7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3017 m68k_movem_mem_to_areg reglist 256 0 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3018 m68k_movem_mem_to_areg reglist 512 1 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3019 m68k_movem_mem_to_areg reglist 1024 2 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3020 m68k_movem_mem_to_areg reglist 2048 3 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3021 m68k_movem_mem_to_areg reglist 4096 4 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3022 m68k_movem_mem_to_areg reglist 8192 5 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3023 m68k_movem_mem_to_areg reglist 16384 6 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3024 m68k_movem_mem_to_areg reglist 32768 7 sz
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3025 #dummy read
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3026 scratch1 = address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3027 ocall read_16
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3028 if M = 3
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3029 ea = address
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3030 end
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3031
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3032 m68k_prefetch
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3033
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3034 0100111001100RRR move_to_usp
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3035 #TODO: trap if not in supervisor mode
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3036 other_sp = aregs.R
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3037 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3038
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3039 0100111001101RRR move_from_usp
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3040 #TODO: trap if not in supervisor mode
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3041 aregs.R = other_sp
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3042 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3043
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3044 0111RRR0IIIIIIII moveq
2591
563d05355a12 Cut down on code bloat in 68K core a little
Michael Pavone <pavone@retrodev.com>
parents: 2590
diff changeset
3045 nospecialize I
2498
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3046 local tmp 32
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3047 sext 16 I tmp
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3048 sext 32 tmp dregs.R
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3049 cmp 0 dregs.R
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3050 update_flags NZV0C0
dffda054d218 Implement movem and moveq in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2481
diff changeset
3051 m68k_prefetch
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3052
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3053 0110000100000000 bsr_w
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3054 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3055 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3056 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3057 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3058 sext 32 prefetch offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3059
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3060 a7 -= 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3061 scratch2 = a7
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3062 m68k_write32 pc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3063
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3064 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3065 pc -= 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3066
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3067 cycles 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3068 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3069
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3070
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3071 01100001DDDDDDDD bsr
2591
563d05355a12 Cut down on code bloat in 68K core a little
Michael Pavone <pavone@retrodev.com>
parents: 2590
diff changeset
3072 nospecialize D
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3073 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3074 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3075 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3076 sext 16 D offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3077 sext 32 offset offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3078
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3079 a7 -= 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3080 scratch2 = a7
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3081 m68k_write32 pc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3082
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3083 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3084
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3085 cycles 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3086 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3087
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3088 m68k_check_cond
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3089 arg cond 16
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3090 local invert 8
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3091 switch cond
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3092 case 0
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3093 #true
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3094 meta istrue 1
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3095 case 1
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3096 #false
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3097 meta istrue 0
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3098 case 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3099 #high
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3100 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3101 invert = zflag | cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3102 invert = !invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3103 case 3
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3104 #low or same
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3105 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3106 invert = zflag | cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3107 case 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3108 #carry clear
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3109 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3110 invert = !cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3111 case 5
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3112 #carry set
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3113 meta istrue cflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3114 case 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3115 #not equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3116 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3117 invert = !zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3118 case 7
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3119 #equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3120 meta istrue zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3121 case 8
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3122 #overflow clear
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3123 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3124 invert = !vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3125 case 9
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3126 #overflow set
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3127 meta istrue vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3128 case 10
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3129 #plus
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3130 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3131 invert = !nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3132 case 11
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3133 #minus
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3134 meta istrue nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3135 case 12
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3136 #greater or equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3137 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3138 invert = nflag - vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3139 invert = !invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3140 case 13
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3141 #less
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3142 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3143 invert = nflag - vflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3144 case 14
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3145 #greater
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3146 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3147 invert = vflag ^ nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3148 invert |= zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3149 invert = !invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3150 case 15
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3151 #less or equal
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3152 meta istrue invert
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3153 invert = vflag ^ nflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3154 invert |= zflag
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3155 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3156
2584
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3157 0101CCCC11MMMDDD scc
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3158 invalid M 1
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3159 invalid M 7 D 2
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3160 invalid M 7 D 3
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3161 invalid M 7 D 4
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3162 invalid M 7 D 5
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3163 invalid M 7 D 6
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3164 invalid M 7 D 7
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3165 m68k_fetch_dst_ea M D 0
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3166 m68k_check_cond C
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3167 if istrue
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3168 if M = 0
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3169 cycles 2
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3170 end
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3171 dst:0 = 0xFF
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3172 else
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3173 dst:0 = 0
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3174 end
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3175 m68k_save_dst 0
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3176 m68k_prefetch
5851240f71c9 Implement scc in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2583
diff changeset
3177
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3178 0110CCCC00000000 bcc_w
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3179 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3180 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3181 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3182 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3183 m68k_check_cond C
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3184 if istrue
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3185
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3186 sext 32 prefetch offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3187 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3188 pc -= 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3189 cycles 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3190 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3191 cycles 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3192 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3193 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3194
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3195 0110CCCCDDDDDDDD bcc
2591
563d05355a12 Cut down on code bloat in 68K core a little
Michael Pavone <pavone@retrodev.com>
parents: 2590
diff changeset
3196 nospecialize D
2501
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3197 #mid-instruction timing isn't quite right
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3198 #becuase I'm only emulating a 1-word prefetch buffer instead of 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3199 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3200 m68k_check_cond C
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3201 if istrue
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3202 sext 16 D offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3203 sext 32 offset offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3204
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3205 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3206
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3207 cycles 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3208 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3209 cycles 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3210 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3211 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3212
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3213 0101CCCC11001RRR dbcc
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3214 local offset 32
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3215 local tmp 16
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3216 m68k_prefetch
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3217 m68k_check_cond C
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3218 if istrue
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3219 cycles 4
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3220 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3221 dregs.R:1 -= 1
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3222 tmp = dregs.R
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3223 if tmp = 65535
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3224 cycles 6
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3225 else
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3226 sext 32 prefetch offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3227 pc += offset
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3228 pc -= 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3229 cycles 2
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3230 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3231 end
6cd5a1d76e34 Implement some more instructions in new 68K core. First light with some old demos
Michael Pavone <pavone@retrodev.com>
parents: 2500
diff changeset
3232 m68k_prefetch
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3233
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3234 1110CCC0ZZ011RRR rori
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3235 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3236 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3237 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3238 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3239 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3240 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3241 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3242 ror dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3243 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3244 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3245 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3246 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3247 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3248 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3249 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3250 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3251 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3252 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3253 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3254 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3255
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3256 1110CCC0ZZ111RRR ror_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3257 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3258 local shift 8
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3259 shift = dregs.C & 63
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3260 ror dregs.R shift dregs.R Z
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3261 update_flags NZV0C
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3262 shift += shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3263 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3264 case 2
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3265 shift += 4
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3266 default
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3267 shift += 2
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3268 end
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3269 cycles shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3270 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3271 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3272
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3273 1110011011MMMRRR ror_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3274 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3275 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3276 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3277 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3278 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3279 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3280 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3281 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3282
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3283 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3284 ror dst 1 dst 1
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3285 update_flags NZV0C
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3286 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3287 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3288
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3289 1110CCC1ZZ011RRR roli
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3290 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3291 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3292 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3293 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3294 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3295 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3296 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3297 rol dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3298 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3299 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3300 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3301 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3302 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3303 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3304 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3305 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3306 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3307 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3308 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3309 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3310
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3311 1110CCC1ZZ111RRR rol_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3312 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3313 local shift 8
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3314 shift = dregs.C & 63
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3315 rol dregs.R shift dregs.R Z
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3316 update_flags NZV0C
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3317 shift += shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3318 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3319 case 2
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3320 shift += 4
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3321 default
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3322 shift += 2
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3323 end
2578
9b01541cbd60 Fix rol and ror in new CPU core
Michael Pavone <pavone@retrodev.com>
parents: 2577
diff changeset
3324 cycles shift
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3325 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3326 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3327
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3328 1110011111MMMRRR rol_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3329 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3330 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3331 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3332 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3333 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3334 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3335 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3336 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3337
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3338 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3339 rol dst 1 dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3340 update_flags NZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3341 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3342 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3343
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3344 1110CCC0ZZ010RRR roxri
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3345 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3346 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3347 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3348 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3349 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3350 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3351 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3352 rrc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3353 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3354 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3355 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3356 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3357 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3358 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3359 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3360 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3361 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3362 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3363 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3364 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3365
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3366 1110CCC0ZZ110RRR roxr_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3367 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3368 local shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3369 local cycle_shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3370 cycle_shift = dregs.C & 63
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3371 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3372 case 2
2631
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3373 meta max_shift 31
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3374 case 1
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3375 meta max_shift 15
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3376 case 0
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3377 meta max_shift 7
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3378 end
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3379 shift = cycle_shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3380 if shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3381 loop
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3382 if max_shift >=U shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3383 rrc dregs.R shift dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3384 update_flags XNZV0C
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3385 break
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3386 else
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3387 rrc dregs.R max_shift dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3388 update_flags X
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3389 shift -= max_shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3390 end
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3391 end
2631
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3392 else
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3393 cflag = xflag
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3394 cmp 0 dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3395 update_flags NZV0
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3396 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3397 cycle_shift += cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3398 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3399 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3400 cycle_shift += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3401 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3402 cycle_shift += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3403 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3404 cycles cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3405 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3406 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3407
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3408 1110010011MMMRRR roxr_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3409 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3410 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3411 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3412 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3413 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3414 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3415 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3416 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3417
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3418 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3419 rrc dst 1 dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3420 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3421 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3422 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3423
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3424 1110CCC1ZZ010RRR roxli
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3425 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3426 switch C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3427 case 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3428 meta shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3429 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3430 meta shift C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3431 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3432 rlc dregs.R shift dregs.R Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3433 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3434 local cyc 32
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3435 cyc = shift + shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3436 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3437 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3438 cyc += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3439 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3440 cyc += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3441 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3442 cycles cyc
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3443 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3444 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3445
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3446 1110CCC1ZZ110RRR roxl_dn
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3447 invalid Z 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3448 local shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3449 local cycle_shift 8
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3450 cycle_shift = dregs.C & 63
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3451 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3452 case 2
2631
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3453 meta max_shift 31
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3454 case 1
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3455 meta max_shift 15
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3456 case 0
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3457 meta max_shift 7
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3458 end
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3459 shift = cycle_shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3460 if shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3461 loop
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3462 if max_shift >=U shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3463 rlc dregs.R shift dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3464 update_flags XNZV0C
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3465 break
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3466 else
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3467 rlc dregs.R max_shift dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3468 update_flags X
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3469 shift -= max_shift
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3470 end
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3471 end
2631
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3472 else
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3473 cflag = xflag
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3474 cmp 0 dregs.R Z
94c05d4ead51 Fix roxr and roxl in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2622
diff changeset
3475 update_flags NZV0
2577
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3476 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3477 cycle_shift += cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3478 switch Z
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3479 case 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3480 cycle_shift += 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3481 default
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3482 cycle_shift += 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3483 end
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3484 cycles cycle_shift
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3485 #TODO: should this happen before or after the majority of the rotate?
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3486 m68k_prefetch
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3487
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3488 1110010111MMMRRR roxl_ea
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3489 invalid M 0
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3490 invalid M 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3491 invalid M 7 R 2
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3492 invalid M 7 R 3
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3493 invalid M 7 R 4
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3494 invalid M 7 R 5
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3495 invalid M 7 R 6
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3496 invalid M 7 R 7
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3497
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3498 m68k_fetch_dst_ea M R 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3499 rlc dst 1 dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3500 update_flags XNZV0C
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3501 m68k_save_dst 1
5f725429d08f WIP changes to new CPU core for rotate instructions and to get interrupts more functional
Michael Pavone <pavone@retrodev.com>
parents: 2562
diff changeset
3502 m68k_prefetch
2636
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3503
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3504 1010XXXXXXXXXXXX line_a
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3505 nospecialize X
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3506 #TODO cycle counts
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3507 pc -= 2
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3508 m68k_trap 10
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3509
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3510 1111XXXXXXXXXXXX line_f
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3511 nospecialize X
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3512 #TODO cycle counts
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3513 pc -= 2
e8b630a1ea4e Implement line A and line F exceptions in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2633
diff changeset
3514 m68k_trap 11
2646
bde8ec2d0f83 Implement illegal instruction trap in new 68K core
Michael Pavone <pavone@retrodev.com>
parents: 2639
diff changeset
3515
2653
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
3516 XXXXXXXXXXXXXXXX illegal
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
3517 nospecialize X
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
3518 #TODO cycle counts
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
3519 pc -= 2
f85208405ae8 Uncomment illegal instruction implementation in new 68K core and tag an invalid size on tst
Michael Pavone <pavone@retrodev.com>
parents: 2651
diff changeset
3520 m68k_trap 4