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Fix bug in MED mapper protection bit implementation
author Michael Pavone <pavone@retrodev.com>
date Sun, 28 Apr 2024 23:33:11 -0700
parents 8b948cf23557
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1 #include <stdlib.h>
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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parents: 1467
diff changeset
2 #include <string.h>
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da1fae7d5407 Fix embarassing typo
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parents: 2125
diff changeset
3 #include <ctype.h>
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8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
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parents: 2068
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4 #include "cd_graphics.h"
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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parents: 1467
diff changeset
5 #include "genesis.h"
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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parents: 1467
diff changeset
6 #include "util.h"
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ff32a90260c9 Initial support for using debugger on sub CPU
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diff changeset
7 #include "debug.h"
ff32a90260c9 Initial support for using debugger on sub CPU
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parents: 2099
diff changeset
8 #include "gdb_remote.h"
2123
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
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parents: 2122
diff changeset
9 #include "blastem.h"
2280
9ead0fe69d9b Implement savestate support for Sega CD
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parents: 2278
diff changeset
10 #include "cdimage.h"
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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parents: 1467
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11
2054
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parents: 1504
diff changeset
12 #define SCD_MCLKS 50000000
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parents: 1504
diff changeset
13 #define SCD_PERIPH_RESET_CLKS (SCD_MCLKS / 10)
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
14 #define TIMER_TICK_CLKS 1536/*1792*/
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
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parents: 2344
diff changeset
15
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
16 //TODO: do some logic analyzer captuers to get actual values
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
17 #define REFRESH_INTERVAL 259
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
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parents: 2344
diff changeset
18 #define REFRESH_DELAY 2
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parents: 1504
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19
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20 enum {
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21 GA_SUB_CPU_CTRL,
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parents: 1504
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22 GA_MEM_MODE,
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parents: 1504
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23 GA_CDC_CTRL,
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parents: 1504
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24 GA_CDC_REG_DATA,
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parents: 1504
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25 GA_CDC_HOST_DATA,
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parents: 1504
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26 GA_CDC_DMA_ADDR,
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parents: 1504
diff changeset
27 GA_STOP_WATCH,
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parents: 1504
diff changeset
28 GA_COMM_FLAG,
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29 GA_COMM_CMD0,
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parents: 1504
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30 GA_COMM_CMD1,
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parents: 1504
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31 GA_COMM_CMD2,
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32 GA_COMM_CMD3,
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33 GA_COMM_CMD4,
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34 GA_COMM_CMD5,
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parents: 1504
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35 GA_COMM_CMD6,
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parents: 1504
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36 GA_COMM_CMD7,
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parents: 1504
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37 GA_COMM_STATUS0,
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parents: 1504
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38 GA_COMM_STATUS1,
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parents: 1504
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39 GA_COMM_STATUS2,
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parents: 1504
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40 GA_COMM_STATUS3,
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parents: 1504
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41 GA_COMM_STATUS4,
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parents: 1504
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42 GA_COMM_STATUS5,
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parents: 1504
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43 GA_COMM_STATUS6,
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parents: 1504
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44 GA_COMM_STATUS7,
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parents: 1504
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45 GA_TIMER,
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parents: 1504
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46 GA_INT_MASK,
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parents: 1504
diff changeset
47 GA_CDD_FADER,
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parents: 1504
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48 GA_CDD_CTRL,
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49 GA_CDD_STATUS0,
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parents: 2056
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50 GA_CDD_STATUS1,
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parents: 2056
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51 GA_CDD_STATUS2,
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parents: 2056
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52 GA_CDD_STATUS3,
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parents: 2056
diff changeset
53 GA_CDD_STATUS4,
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parents: 2056
diff changeset
54 GA_CDD_CMD0,
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parents: 2056
diff changeset
55 GA_CDD_CMD1,
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parents: 2056
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56 GA_CDD_CMD2,
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parents: 2056
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57 GA_CDD_CMD3,
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58 GA_CDD_CMD4,
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59 GA_FONT_COLOR,
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60 GA_FONT_BITS,
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61 GA_FONT_DATA0,
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62 GA_FONT_DATA1,
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63 GA_FONT_DATA2,
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parents: 2056
diff changeset
64 GA_FONT_DATA3,
2116
cd057d6fe030 Initial stab at subcode emulation
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65 GA_SUBCODE_START = 0x80,
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66 GA_SUBCODE_MIRROR = 0xC0,
2054
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67
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68 GA_HINT_VECTOR = GA_CDC_REG_DATA
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parents: 1504
diff changeset
69 };
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70 //GA_SUB_CPU_CTRL
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parents: 1504
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71 #define BIT_IEN2 0x8000
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diff changeset
72 #define BIT_IFL2 0x0100
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73 #define BIT_LEDG 0x0200
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diff changeset
74 #define BIT_LEDR 0x0100
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75 #define BIT_SBRQ 0x0002
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76 #define BIT_SRES 0x0001
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diff changeset
77 #define BIT_PRES 0x0001
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parents: 1504
diff changeset
78 //GA_MEM_MODE
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parents: 1504
diff changeset
79 #define MASK_PROG_BANK 0x00C0
2057
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diff changeset
80 #define BIT_OVERWRITE 0x0010
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81 #define BIT_UNDERWRITE 0x0008
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82 #define MASK_PRIORITY (BIT_OVERWRITE|BIT_UNDERWRITE)
2054
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parents: 1504
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83 #define BIT_MEM_MODE 0x0004
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84 #define BIT_DMNA 0x0002
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diff changeset
85 #define BIT_RET 0x0001
2057
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parents: 2056
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86
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
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diff changeset
87 //GA_CDC_CTRL
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diff changeset
88 #define BIT_EDT 0x8000
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parents: 2062
diff changeset
89 #define BIT_DSR 0x4000
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90
2080
bafb757e1cd2 Implement CD audio
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parents: 2073
diff changeset
91 //GA_CDD_CTRL
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parents: 2073
diff changeset
92 #define BIT_MUTE 0x0100
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93
2065
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94 enum {
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95 DST_MAIN_CPU = 2,
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96 DST_SUB_CPU,
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97 DST_PCM_RAM,
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98 DST_PROG_RAM,
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99 DST_WORD_RAM = 7
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100 };
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diff changeset
101
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102 //GA_INT_MASK
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diff changeset
103 #define BIT_MASK_IEN1 0x0002
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diff changeset
104 #define BIT_MASK_IEN2 0x0004
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105 #define BIT_MASK_IEN3 0x0008
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106 #define BIT_MASK_IEN4 0x0010
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107 #define BIT_MASK_IEN5 0x0020
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108 #define BIT_MASK_IEN6 0x0040
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109
2061
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parents: 2058
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110 //GA_CDD_CTRL
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111 #define BIT_HOCK 0x0004
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112
1502
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113 static void *prog_ram_wp_write16(uint32_t address, void *vcontext, uint16_t value)
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diff changeset
114 {
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115 m68k_context *m68k = vcontext;
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116 segacd_context *cd = m68k->system;
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diff changeset
117 //if (!(cd->gate_array[GA_MEM_MODE] & (1 << ((address >> 9) + 8)))) {
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parents: 2056
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118 if (address >= ((cd->gate_array[GA_MEM_MODE] & 0xFF00) << 1)) {
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parents: 1504
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119 cd->prog_ram[address >> 1] = value;
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parents: 1504
diff changeset
120 m68k_invalidate_code_range(m68k, address, address + 2);
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121 }
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122 return vcontext;
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123 }
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124
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125 static void *prog_ram_wp_write8(uint32_t address, void *vcontext, uint8_t value)
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126 {
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127 m68k_context *m68k = vcontext;
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128 segacd_context *cd = m68k->system;
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129 if (address >= ((cd->gate_array[GA_MEM_MODE] & 0xFF00) << 1)) {
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130 ((uint8_t *)cd->prog_ram)[address ^ 1] = value;
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131 m68k_invalidate_code_range(m68k, address, address + 1);
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132 }
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133 return vcontext;
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134 }
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135
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136 static uint16_t word_ram_2M_read16(uint32_t address, void *vcontext)
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137 {
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138 m68k_context *m68k = vcontext;
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139 uint16_t* bank = m68k->mem_pointers[1];
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140 if (!bank) {
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141 return 0xFFFF;
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142 }
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143 uint16_t raw = bank[address >> 1 & ~1];
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144 if (address & 2) {
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145 return (raw & 0xF) | (raw << 4 & 0xF00);
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146 } else {
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147 return (raw >> 4 & 0xF00) | (raw >> 8 & 0xF);
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148 }
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149 }
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150
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151 static uint8_t word_ram_2M_read8(uint32_t address, void *vcontext)
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152 {
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153 uint16_t word = word_ram_2M_read16(address, vcontext);
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154 if (address & 1) {
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155 return word;
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156 }
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157 return word >> 8;
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158 }
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159
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160 static void *word_ram_2M_write8(uint32_t address, void *vcontext, uint8_t value)
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161 {
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162 m68k_context *m68k = vcontext;
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163 segacd_context *cd = m68k->system;
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164 if (!(cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE)) {
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165 //TODO: Confirm this first write goes through (seemed like it in initial testing)
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166 if (address & 1) {
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167 address >>= 1;
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168 cd->word_ram[address] &= 0xFF00;
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169 cd->word_ram[address] |= value;
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170 } else {
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171 address >>= 1;
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172 cd->word_ram[address] &= 0x00FF;
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173 cd->word_ram[address] |= value << 8;
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174 }
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175 m68k_invalidate_code_range(cd->genesis->m68k, cd->base + 0x200000 + (address & ~1), cd->base + 0x200000 + (address & ~1) + 1);
2134
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176 cd->sub_paused_wordram = 1;
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177 m68k->sync_cycle = m68k->target_cycle = m68k->current_cycle;
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178 m68k->should_return = 1;
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179 } else {
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180 value &= 0xF;
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181 uint16_t priority = cd->gate_array[GA_MEM_MODE] & MASK_PRIORITY;
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182
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183 if (priority == BIT_OVERWRITE && !value) {
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184 return vcontext;
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185 }
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186 if (priority == BIT_UNDERWRITE) {
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187 if (!value) {
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188 return vcontext;
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189 }
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190 uint8_t old = word_ram_2M_read8(address, vcontext);
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191 if (old) {
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192 return vcontext;
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193 }
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194 }
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195 uint16_t* bank = m68k->mem_pointers[1];
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196 if (!bank) {
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197 return vcontext;
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198 }
2134
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199 uint16_t raw = bank[address >> 1 & ~1];
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200 uint16_t shift = ((address & 3) * 4);
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201 raw &= ~(0xF000 >> shift);
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202 raw |= value << (12 - shift);
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203 bank[address >> 1 & ~1] = raw;
2099
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204 }
1502
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205 return vcontext;
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206 }
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diff changeset
207
2057
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208
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diff changeset
209 static void *word_ram_2M_write16(uint32_t address, void *vcontext, uint16_t value)
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210 {
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diff changeset
211 word_ram_2M_write8(address, vcontext, value >> 8);
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212 return word_ram_2M_write8(address + 1, vcontext, value);
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213 }
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diff changeset
214
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215 static uint16_t word_ram_1M_read16(uint32_t address, void *vcontext)
1502
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diff changeset
216 {
2138
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diff changeset
217 //TODO: check behavior for these on hardware
2054
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218 return 0;
1502
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219 }
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diff changeset
220
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221 static uint8_t word_ram_1M_read8(uint32_t address, void *vcontext)
1502
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222 {
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223 return 0;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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diff changeset
224 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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diff changeset
225
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diff changeset
226 static void *word_ram_1M_write16(uint32_t address, void *vcontext, uint16_t value)
1502
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diff changeset
227 {
2054
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228 return vcontext;
1502
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229 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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diff changeset
230
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diff changeset
231 static void *word_ram_1M_write8(uint32_t address, void *vcontext, uint8_t value)
1502
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diff changeset
232 {
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diff changeset
233 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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diff changeset
234 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
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diff changeset
235
2054
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diff changeset
236
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diff changeset
237 static uint16_t unmapped_prog_read16(uint32_t address, void *vcontext)
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238 {
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diff changeset
239 return 0xFFFF;
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diff changeset
240 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff changeset
241
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff changeset
242 static uint8_t unmapped_prog_read8(uint32_t address, void *vcontext)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
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diff changeset
243 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
244 return 0xFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
245 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
246
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
247 static void *unmapped_prog_write16(uint32_t address, void *vcontext, uint16_t value)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
248 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
249 return vcontext;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
250 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
251
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
252 static void *unmapped_prog_write8(uint32_t address, void *vcontext, uint8_t value)
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
253 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
254 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
255 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
256
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
257 static uint16_t unmapped_word_read16(uint32_t address, void *vcontext)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
258 {
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
259 m68k_context *m68k = vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
260 genesis_context *gen = m68k->system;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
261 segacd_context *cd = gen->expansion;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
262 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
263 return cd->word_ram[address + cd->bank_toggle];
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
264 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
265 return 0xFFFF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
266 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
267 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
268
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
269 static uint8_t unmapped_word_read8(uint32_t address, void *vcontext)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
270 {
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
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parents: 2131
diff changeset
271 m68k_context *m68k = vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
272 genesis_context *gen = m68k->system;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
273 segacd_context *cd = gen->expansion;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
274 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
275 if (address & 1) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
276 return cd->word_ram[(address & ~1) + cd->bank_toggle];
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
277 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
278 return cd->word_ram[address + cd->bank_toggle] >> 8;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
279 }
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
280 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
281 return 0xFF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
282 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
283 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
284
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
285 static void *unmapped_word_write16(uint32_t address, void *vcontext, uint16_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
286 {
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
287 m68k_context *m68k = vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
288 genesis_context *gen = m68k->system;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
289 segacd_context *cd = gen->expansion;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
290 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
291 cd->word_ram[address + cd->bank_toggle] = value;
2137
3ef9456b76cf Fix a crash regression from word RAM interleave changes
Michael Pavone <pavone@retrodev.com>
parents: 2136
diff changeset
292 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + address, cd->base + 0x200000 + address + 1);
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
293 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
294 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
295 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
296
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
297 static void *unmapped_word_write8(uint32_t address, void *vcontext, uint8_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
298 {
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
299 m68k_context *m68k = vcontext;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
300 genesis_context *gen = m68k->system;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
301 segacd_context *cd = gen->expansion;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
302 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
303 if (address & 1) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
304 uint32_t offset = (address & ~1) + cd->bank_toggle;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
305 cd->word_ram[offset] &= 0xFF00;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
306 cd->word_ram[offset] |= value;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
307 } else {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
308 cd->word_ram[address + cd->bank_toggle] &= 0xFF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
309 cd->word_ram[address + cd->bank_toggle] |= value << 8;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
310 }
2138
b6338e18787e Fix some dynarec code invalidation issues
Michael Pavone <pavone@retrodev.com>
parents: 2137
diff changeset
311 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + (address & ~1), cd->base + 0x200000 + (address & ~1) + 1);
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
312 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
313 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
314 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
315
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
316 static uint32_t cell_image_translate_address(uint32_t address)
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
317 {
2087
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
318 uint32_t word_of_cell = address & 2;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
319 if (address < 0x10000) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
320 //64x32 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
321 uint32_t line_of_column = address & 0x3FC;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
322 uint32_t column = address & 0xFC00;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
323 address = (line_of_column << 6) | (column >> 8) | word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
324 } else if (address < 0x18000) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
325 //64x16 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
326 uint32_t line_of_column = address & 0x1FC;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
327 uint32_t column = address & 0x7E00;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
328 address = 0x10000 | (line_of_column << 6) | (column >> 7) | word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
329 } else if (address < 0x1C000) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
330 //64x8 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
331 uint32_t line_of_column = address & 0x00FC;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
332 uint32_t column = address & 0x3F00;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
333 address = 0x18000 | (line_of_column << 6) | (column >> 6) | word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
334 } else {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
335 //64x4 cell view
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
336 uint32_t line_of_column = address & 0x007C;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
337 uint32_t column = address & 0x1F80;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
338 address &= 0x1E000;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
339 address |= (line_of_column << 6) | (column >> 5) | word_of_cell;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
340 }
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
341 return address;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
342 }
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
343
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
344 static uint16_t cell_image_read16(uint32_t address, void *vcontext)
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
345 {
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
346 address = cell_image_translate_address(address);
2087
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
347 m68k_context *m68k = vcontext;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
348 genesis_context *gen = m68k->system;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
349 segacd_context *cd = gen->expansion;
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
350 if (!(cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE)) {
2099
b92c998c6742 Add some missing null checks in the Sega CD code dealing with word RAM switching
Michael Pavone <pavone@retrodev.com>
parents: 2094
diff changeset
351 return 0xFFFF;
b92c998c6742 Add some missing null checks in the Sega CD code dealing with word RAM switching
Michael Pavone <pavone@retrodev.com>
parents: 2094
diff changeset
352 }
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
353 return cd->word_ram[address + cd->bank_toggle];
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
354 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
355
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
356 static uint8_t cell_image_read8(uint32_t address, void *vcontext)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
357 {
2087
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
358 uint16_t word = cell_image_read16(address & 0xFFFFFE, vcontext);
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
359 if (address & 1) {
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
360 return word;
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
361 }
3e0801280bef Implement bitmap to cell mapping feature of 1M mode
Michael Pavone <pavone@retrodev.com>
parents: 2083
diff changeset
362 return word >> 8;
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
363 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
364
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
365 static void *cell_image_write16(uint32_t address, void *vcontext, uint16_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
366 {
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
367 m68k_context *m68k = vcontext;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
368 genesis_context *gen = m68k->system;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
369 segacd_context *cd = gen->expansion;
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
370 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
371 address = cell_image_translate_address(address);
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
372 cd->word_ram[address + cd->bank_toggle] = value;
2138
b6338e18787e Fix some dynarec code invalidation issues
Michael Pavone <pavone@retrodev.com>
parents: 2137
diff changeset
373 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + address, cd->base + 0x200000 + address + 1);
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
374 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
375 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
376 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
377
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
378 static void *cell_image_write8(uint32_t address, void *vcontext, uint8_t value)
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
379 {
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
380 uint32_t byte = address & 1;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
381 address = cell_image_translate_address(address);
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
382 m68k_context *m68k = vcontext;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
383 genesis_context *gen = m68k->system;
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
384 segacd_context *cd = gen->expansion;
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
385 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
386 if (byte) {
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
387 cd->word_ram[address + cd->bank_toggle] &= 0xFF00;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
388 cd->word_ram[address + cd->bank_toggle] |= value;
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
389 } else {
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
390 cd->word_ram[address + cd->bank_toggle] &= 0x00FF;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
391 cd->word_ram[address + cd->bank_toggle] |= value << 8;
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
392 }
2138
b6338e18787e Fix some dynarec code invalidation issues
Michael Pavone <pavone@retrodev.com>
parents: 2137
diff changeset
393 m68k_invalidate_code_range(m68k, cd->base + 0x200000 + address, cd->base + 0x200000 + address + 1);
2121
76ea19e8b1a9 Implement writes to cell image area in 1M mode. Fixes graphics in Stellar Fire
Michael Pavone <pavone@retrodev.com>
parents: 2120
diff changeset
394 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
395 return vcontext;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
396 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
397
2127
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
398 static void cdd_run(segacd_context *cd, uint32_t cycle)
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
399 {
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
400 cdd_mcu_run(&cd->cdd, cycle, cd->gate_array + GA_CDD_CTRL, &cd->cdc, &cd->fader);
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
401 lc8951_run(&cd->cdc, cycle);
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
402 }
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
403
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
404 static uint8_t pcm_read8(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
405 {
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
406 m68k_context *m68k = vcontext;
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
407 segacd_context *cd = m68k->system;
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
408 if (address & 1) {
2127
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
409 //need to run CD drive because there may be a PCM DMA underway
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
410 cdd_run(cd, m68k->current_cycle);
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
411 rf5c164_run(&cd->pcm, m68k->current_cycle);
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
412 return rf5c164_read(&cd->pcm, address >> 1);
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
413 } else {
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
414 return 0xFF;
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
415 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
416 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
417
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
418 static uint16_t pcm_read16(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
419 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
420 return 0xFF00 | pcm_read8(address+1, vcontext);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
421 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
422
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
423 static void *pcm_write8(uint32_t address, void *vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
424 {
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
425 m68k_context *m68k = vcontext;
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
426 segacd_context *cd = m68k->system;
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
427 if (address & 1) {
2127
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
428 //need to run CD drive because there may be a PCM DMA underway
1bf30397dd45 Fix one more test in mcd-verificator CDC DMA1
Michael Pavone <pavone@retrodev.com>
parents: 2126
diff changeset
429 cdd_run(cd, m68k->current_cycle);
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
430 rf5c164_run(&cd->pcm, m68k->current_cycle);
2128
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
431 while ((cd->pcm.flags & 0x81) == 1) {
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
432 //not sounding, but pending write
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
433 //DMA write conflict presumably adds wait states
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
434 m68k->current_cycle += 4;
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
435 rf5c164_run(&cd->pcm, m68k->current_cycle);
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
436 }
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
437 rf5c164_write(&cd->pcm, address >> 1, value);
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
438 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
439 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
440 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
441
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
442 static void *pcm_write16(uint32_t address, void *vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
443 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
444 return pcm_write8(address+1, vcontext, value);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
445 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
446
2281
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
447 static uint16_t cart_area_read16(uint32_t address, void *vcontext)
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
448 {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
449 m68k_context *m68k = vcontext;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
450 genesis_context *gen = m68k->system;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
451 segacd_context *cd = gen->expansion;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
452 uint16_t open_bus = read_word(m68k->last_prefetch_address, (void **)m68k->mem_pointers, &m68k->options->gen, m68k);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
453 if (cd->bram_cart_id > 7) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
454 // No cart, just return open bus
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
455 return open_bus;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
456 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
457 address &= 0x3FFFFF;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
458 if (address < 0x200000) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
459 if (address < 0x100000) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
460 return (open_bus & 0xFF00) | cd->bram_cart_id;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
461 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
462 return open_bus;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
463 } else {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
464 address &= 0x1FFFFF;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
465 uint32_t end = 0x2000 << (1 + cd->bram_cart_id);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
466 if (address >= end) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
467 return open_bus;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
468 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
469 return (open_bus & 0xFF00) | cd->bram_cart[address >> 1];
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
470 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
471 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
472
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
473 static uint8_t cart_area_read8(uint32_t address, void *vcontext)
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
474 {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
475 m68k_context *m68k = vcontext;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
476 genesis_context *gen = m68k->system;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
477 segacd_context *cd = gen->expansion;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
478 if (!(address & 1) || cd->bram_cart_id > 7) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
479 //open bus
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
480 return read_byte(m68k->last_prefetch_address | (address & 1), (void **)m68k->mem_pointers, &m68k->options->gen, m68k);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
481 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
482 address &= 0x3FFFFF;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
483 if (address < 0x200000) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
484 if (address < 0x100000) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
485 return cd->bram_cart_id;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
486 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
487 return read_byte(m68k->last_prefetch_address | 1, (void **)m68k->mem_pointers, &m68k->options->gen, m68k);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
488 } else {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
489 address &= 0x1FFFFF;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
490 uint32_t end = 0x2000 << (1 + cd->bram_cart_id);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
491 if (address >= end) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
492 return read_byte(m68k->last_prefetch_address | 1, (void **)m68k->mem_pointers, &m68k->options->gen, m68k);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
493 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
494 return cd->bram_cart[address >> 1];
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
495 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
496 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
497
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
498 static void *cart_area_write8(uint32_t address, void *vcontext, uint8_t value)
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
499 {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
500 m68k_context *m68k = vcontext;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
501 genesis_context *gen = m68k->system;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
502 segacd_context *cd = gen->expansion;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
503 if (!(address & 1) || cd->bram_cart_id > 7 || address < 0x600000) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
504 return vcontext;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
505 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
506 address &= 0x1FFFFF;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
507 uint32_t end = 0x2000 << (1 + cd->bram_cart_id);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
508 if (address < end && cd->bram_cart_write_enabled) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
509 cd->bram_cart[address >> 1] = value;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
510 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
511 if (address == 0x1FFFFF || (cd->bram_cart_id < 7 && address > 0x100000)) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
512 cd->bram_cart_write_enabled = value & 1;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
513 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
514 return vcontext;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
515 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
516
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
517 static void *cart_area_write16(uint32_t address, void *vcontext, uint16_t value)
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
518 {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
519 return cart_area_write8(address | 1, vcontext, value);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
520 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
521
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
522 static void timers_run(segacd_context *cd, uint32_t cycle)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
523 {
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
524 if (cycle <= cd->stopwatch_cycle) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
525 return;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
526 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
527 uint32_t ticks = (cycle - cd->stopwatch_cycle) / TIMER_TICK_CLKS;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
528 cd->stopwatch_cycle += ticks * TIMER_TICK_CLKS;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
529 cd->gate_array[GA_STOP_WATCH] += ticks;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
530 cd->gate_array[GA_STOP_WATCH] &= 0xFFF;
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
531 if (ticks && !cd->timer_value) {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
532 --ticks;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
533 cd->timer_value = cd->gate_array[GA_TIMER];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
534 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
535 if (ticks && cd->timer_value) {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
536 while (ticks >= (cd->timer_value + 1)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
537 ticks -= cd->timer_value + 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
538 cd->timer_value = cd->gate_array[GA_TIMER];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
539 cd->timer_pending = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
540 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
541 cd->timer_value -= ticks;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
542 if (!cd->timer_value) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
543 cd->timer_pending = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
544 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
545 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
546 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
547
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
548 static uint32_t next_timer_int(segacd_context *cd)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
549 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
550 if (cd->timer_pending) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
551 return cd->stopwatch_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
552 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
553 if (cd->timer_value) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
554 return cd->stopwatch_cycle + TIMER_TICK_CLKS * cd->timer_value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
555 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
556 if (cd->gate_array[GA_TIMER]) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
557 return cd->stopwatch_cycle + TIMER_TICK_CLKS * (cd->gate_array[GA_TIMER] + 1);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
558 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
559 return CYCLE_NEVER;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
560 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
561
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
562 static void calculate_target_cycle(m68k_context * context)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
563 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
564 segacd_context *cd = context->system;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
565 context->int_cycle = CYCLE_NEVER;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
566 uint8_t mask = context->status & 0x7;
2094
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
567 uint32_t cdc_cycle = CYCLE_NEVER;
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
568 if (mask < 6) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
569 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN6) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
570 uint32_t subcode_cycle = cd->cdd.subcode_int_pending ? context->current_cycle : cd->cdd.next_subcode_int_cycle;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
571 if (subcode_cycle != CYCLE_NEVER) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
572 context->int_cycle = subcode_cycle;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
573 context->int_num = 6;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
574 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
575 }
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
576 if (mask < 5) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
577 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN5) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
578 cdc_cycle = lc8951_next_interrupt(&cd->cdc);
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
579 //CDC interrupts only generated on falling edge of !INT signal
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
580 if (cd->cdc_int_ack) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
581 if (cdc_cycle > cd->cdc.cycle) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
582 cd->cdc_int_ack = 0;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
583 } else {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
584 cdc_cycle = CYCLE_NEVER;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
585 }
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
586 }
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
587 if (cdc_cycle < context->int_cycle) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
588 context->int_cycle = cdc_cycle;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
589 context->int_num = 5;
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
590 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
591 }
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
592 if (mask < 4) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
593 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN4) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
594 uint32_t cdd_cycle = cd->cdd.int_pending ? context->current_cycle : cd->cdd.next_int_cycle;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
595 if (cdd_cycle < context->int_cycle) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
596 context->int_cycle = cdd_cycle;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
597 context->int_num = 4;
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
598 }
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
599 }
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
600 if (mask < 3) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
601 uint32_t next_timer;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
602 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN3) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
603 uint32_t next_timer_cycle = next_timer_int(cd);
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
604 if (next_timer_cycle < context->int_cycle) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
605 context->int_cycle = next_timer_cycle;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
606 context->int_num = 3;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
607 }
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
608 }
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
609 if (mask < 2) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
610 if (cd->int2_cycle < context->int_cycle && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2)) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
611 context->int_cycle = cd->int2_cycle;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
612 context->int_num = 2;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
613 }
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
614 if (mask < 1) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
615 if (cd->graphics_int_cycle < context->int_cycle && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN1)) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
616 context->int_cycle = cd->graphics_int_cycle;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
617 context->int_num = 1;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
618 }
2069
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
619 }
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
620 }
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
621 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
622 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
623 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
624 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
625 if (context->int_cycle > context->current_cycle && context->int_pending == INT_PENDING_SR_CHANGE) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
626 context->int_pending = INT_PENDING_NONE;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
627 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
628 if (context->current_cycle >= context->sync_cycle) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
629 context->should_return = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
630 context->target_cycle = context->current_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
631 return;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
632 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
633 if (context->status & M68K_STATUS_TRACE || context->trace_pending) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
634 context->target_cycle = context->current_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
635 return;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
636 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
637 context->target_cycle = context->sync_cycle < context->int_cycle ? context->sync_cycle : context->int_cycle;
2136
01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test
Michael Pavone <pavone@retrodev.com>
parents: 2135
diff changeset
638 if (context->int_cycle == cdc_cycle && context->int_num == 5) {
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
639 uint32_t before = cdc_cycle - cd->m68k->options->gen.clock_divider * 158; //divs worst case
2136
01fcbcba5cf8 Fix regresion on mcd-verificator CDC flags test
Michael Pavone <pavone@retrodev.com>
parents: 2135
diff changeset
640 if (before < context->target_cycle) {
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
641 while (before <= context->current_cycle) {
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
642 before += cd->cdc.clock_step;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
643 }
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
644 if (before < context->target_cycle) {
2131
d90d92ce5cab Improve CDC decode timing accuracy
Michael Pavone <pavone@retrodev.com>
parents: 2129
diff changeset
645 context->target_cycle = context->sync_cycle = before;
d90d92ce5cab Improve CDC decode timing accuracy
Michael Pavone <pavone@retrodev.com>
parents: 2129
diff changeset
646 }
2094
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
647 }
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
648 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
649 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
650
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
651 static uint16_t sub_gate_read16(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
652 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
653 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
654 segacd_context *cd = m68k->system;
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
655 uint32_t before_cycle = m68k->current_cycle - m68k->options->gen.clock_divider * 4;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
656 if (before_cycle >= cd->last_refresh_cycle) {
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
657 uint32_t num_refresh = (before_cycle - cd->last_refresh_cycle) / REFRESH_INTERVAL;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
658 uint32_t num_full = (m68k->current_cycle - cd->last_refresh_cycle) / REFRESH_INTERVAL;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
659 cd->last_refresh_cycle = cd->last_refresh_cycle + num_full * REFRESH_INTERVAL;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
660 m68k->current_cycle += num_refresh * REFRESH_DELAY;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
661 }
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
662
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
663
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
664 uint32_t reg = address >> 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
665 switch (reg)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
666 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
667 case GA_SUB_CPU_CTRL: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
668 uint16_t value = cd->gate_array[reg] & 0xFFFE;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
669 if (cd->periph_reset_cycle == CYCLE_NEVER || (m68k->current_cycle - cd->periph_reset_cycle) > SCD_PERIPH_RESET_CLKS) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
670 value |= BIT_PRES;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
671 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
672 return value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
673 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
674 case GA_MEM_MODE:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
675 return cd->gate_array[reg] & 0xFF1F;
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
676 case GA_CDC_CTRL:
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
677 cdd_run(cd, m68k->current_cycle);
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
678 return cd->gate_array[reg] | cd->cdc.ar;
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
679 case GA_CDC_REG_DATA:
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
680 cdd_run(cd, m68k->current_cycle);
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
681 return lc8951_reg_read(&cd->cdc);
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
682 case GA_CDC_HOST_DATA: {
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
683 cdd_run(cd, m68k->current_cycle);
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
684 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
685 if (dst == DST_SUB_CPU) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
686 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
687 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
688 lc8951_resume_transfer(&cd->cdc);
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
689 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
690 calculate_target_cycle(cd->m68k);
2068
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
691
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
692 }
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
693 return cd->gate_array[reg];
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
694 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
695 case GA_STOP_WATCH:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
696 case GA_TIMER:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
697 timers_run(cd, m68k->current_cycle);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
698 return cd->gate_array[reg];
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
699 case GA_CDD_STATUS0:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
700 case GA_CDD_STATUS1:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
701 case GA_CDD_STATUS2:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
702 case GA_CDD_STATUS3:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
703 case GA_CDD_STATUS4:
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
704 cdd_run(cd, m68k->current_cycle);
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
705 return cd->gate_array[reg];
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
706 break;
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
707 case GA_FONT_DATA0:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
708 case GA_FONT_DATA1:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
709 case GA_FONT_DATA2:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
710 case GA_FONT_DATA3: {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
711 uint16_t shift = 4 * (3 - (reg - GA_FONT_DATA0));
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
712 uint16_t value = 0;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
713 uint16_t fg = cd->gate_array[GA_FONT_COLOR] >> 4;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
714 uint16_t bg = cd->gate_array[GA_FONT_COLOR] & 0xF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
715 for (int i = 0; i < 4; i++) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
716 uint16_t pixel = 0;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
717 if (cd->gate_array[GA_FONT_BITS] & 1 << (shift + i)) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
718 pixel = fg;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
719 } else {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
720 pixel = bg;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
721 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
722 value |= pixel << (i * 4);
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
723 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
724 return value;
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
725 }
2069
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
726 case GA_STAMP_SIZE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
727 case GA_IMAGE_BUFFER_LINES:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
728 //these two have bits that change based on graphics operations
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
729 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
730 return cd->gate_array[reg];
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
731 case GA_TRACE_VECTOR_BASE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
732 //write only
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
733 return 0xFFFF;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
734 default:
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
735 if (reg >= GA_SUBCODE_MIRROR) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
736 return cd->gate_array[GA_SUBCODE_START + (reg & 0x3F)];
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
737 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
738 return cd->gate_array[reg];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
739 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
740 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
741
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
742 static uint8_t sub_gate_read8(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
743 {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
744 uint16_t val = sub_gate_read16(address, vcontext);
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
745 return address & 1 ? val : val >> 8;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
746 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
747
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
748 static void *sub_gate_write16(uint32_t address, void *vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
749 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
750 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
751 segacd_context *cd = m68k->system;
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
752 uint32_t before_cycle = m68k->current_cycle - m68k->options->gen.clock_divider * 4;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
753 if (before_cycle >= cd->last_refresh_cycle) {
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
754 uint32_t num_refresh = (before_cycle - cd->last_refresh_cycle) / REFRESH_INTERVAL;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
755 uint32_t num_full = (m68k->current_cycle - cd->last_refresh_cycle) / REFRESH_INTERVAL;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
756 cd->last_refresh_cycle = cd->last_refresh_cycle + num_full * REFRESH_INTERVAL;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
757 m68k->current_cycle += num_refresh * REFRESH_DELAY;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
758 }
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
759
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
760 uint32_t reg = address >> 1;
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
761 switch (reg)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
762 {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
763 case GA_SUB_CPU_CTRL:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
764 cd->gate_array[reg] &= 0xF0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
765 cd->gate_array[reg] |= value & (BIT_LEDG|BIT_LEDR);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
766 if (value & BIT_PRES) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
767 cd->periph_reset_cycle = m68k->current_cycle;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
768 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
769 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
770 case GA_MEM_MODE: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
771 uint16_t changed = value ^ cd->gate_array[reg];
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
772 uint8_t old_main_has_word2m = cd->main_has_word2m;
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
773 if (value & BIT_RET) {
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
774 cd->main_has_word2m = 1;
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
775 }
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
776 uint8_t old_bank_toggle = cd->bank_toggle;
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
777 cd->bank_toggle = value & BIT_RET;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
778 genesis_context *gen = cd->genesis;
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
779 cd->gate_array[reg] &= 0xFFC0;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
780 if (changed & BIT_MEM_MODE) {
2120
91ed3c4cdfd9 Fix the regression in Stellar Fire while still passing RET/DMNA tests
Michael Pavone <pavone@retrodev.com>
parents: 2119
diff changeset
781 cd->main_swap_request = cd->bank_toggle && !old_bank_toggle;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
782 if (value & BIT_MEM_MODE) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
783 //switch to 1M mode
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
784 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL; //(value & BIT_RET) ? cd->word_ram + 0x10000 : cd->word_ram;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
785 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
786 m68k->mem_pointers[0] = NULL;
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
787 m68k->mem_pointers[1] = cd->bank_toggle ? cd->word_ram : cd->word_ram + 1;
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
788 cd->gate_array[reg] |= value & (MASK_PRIORITY|BIT_RET|BIT_MEM_MODE);
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
789 if (cd->main_swap_request) {
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
790 cd->gate_array[reg] |= BIT_DMNA;
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
791 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
792 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
793 //switch to 2M mode
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
794 if (cd->main_has_word2m) {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
795 //Main CPU will have word ram
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
796 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
797 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
798 m68k->mem_pointers[0] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
799 m68k->mem_pointers[1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
800 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
801 //sub cpu will have word ram
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
802 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
803 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
804 m68k->mem_pointers[0] = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
805 m68k->mem_pointers[1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
806 }
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
807 cd->gate_array[reg] |= value & (MASK_PRIORITY|BIT_MEM_MODE);
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
808 cd->gate_array[reg] |= cd->main_has_word2m ? BIT_RET : BIT_DMNA;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
809 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
810 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
811 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000);
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
812 } else if (value & BIT_MEM_MODE) {
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
813 //1M mode
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
814 if (old_bank_toggle != cd->bank_toggle) {
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
815 m68k->mem_pointers[1] = (value & BIT_RET) ? cd->word_ram : cd->word_ram + 1;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
816 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
817 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000);
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
818 cd->main_swap_request = 0;
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
819 }
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
820 cd->gate_array[reg] |= value & (MASK_PRIORITY|BIT_RET|BIT_MEM_MODE);
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
821 if (cd->main_swap_request) {
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
822 cd->gate_array[reg] |= BIT_DMNA;
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
823 }
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
824 } else {
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
825 //2M mode
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
826 if (old_main_has_word2m != cd->main_has_word2m) {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
827 gen->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
828 gen->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
829 m68k->mem_pointers[0] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
830 m68k_invalidate_code_range(gen->m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
831 m68k_invalidate_code_range(m68k, 0x080000, 0x0E0000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
832 }
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
833 cd->gate_array[reg] |= value & MASK_PRIORITY;
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
834 cd->gate_array[reg] |= cd->main_has_word2m ? BIT_RET : BIT_DMNA;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
835 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
836 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
837 }
2144
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
838 case GA_CDC_CTRL: {
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
839 cdd_run(cd, m68k->current_cycle);
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
840 lc8951_ar_write(&cd->cdc, value);
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
841 //cd->gate_array[reg] &= 0xC000;
2144
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
842 uint16_t old_dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
843 //apparently this clears EDT, should it also clear DSR?
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
844 cd->gate_array[reg] = value & 0x0700;
2144
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
845 uint16_t dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
846 if (dest != old_dest) {
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
847 if (dest == DST_PCM_RAM) {
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
848 lc8951_set_dma_multiple(&cd->cdc, 21);
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
849 } else {
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
850 lc8951_set_dma_multiple(&cd->cdc, 6);
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
851 }
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
852 if ((old_dest < DST_MAIN_CPU || old_dest == 6) && dest >= DST_MAIN_CPU && dest != 6) {
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
853 lc8951_resume_transfer(&cd->cdc);
2144
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
854 }
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
855 calculate_target_cycle(m68k);
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
856 }
2135
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
857 cd->gate_array[GA_CDC_DMA_ADDR] = 0;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
858 cd->cdc_dst_low = 0;
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
859 break;
2144
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
860 }
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
861 case GA_CDC_REG_DATA:
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
862 cdd_run(cd, m68k->current_cycle);
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
863 printf("CDC write %X: %X @ %u\n", cd->cdc.ar, value, m68k->current_cycle);
2426
cde4ea2b4929 Clear DSR in certain gate array writes. Fixes issue in Penn & Teller's Smoke and Mirrors
Michael Pavone <pavone@retrodev.com>
parents: 2384
diff changeset
864 if (cd->cdc.ar == 6) {
cde4ea2b4929 Clear DSR in certain gate array writes. Fixes issue in Penn & Teller's Smoke and Mirrors
Michael Pavone <pavone@retrodev.com>
parents: 2384
diff changeset
865 cd->cdc_dst_low = 0;
cde4ea2b4929 Clear DSR in certain gate array writes. Fixes issue in Penn & Teller's Smoke and Mirrors
Michael Pavone <pavone@retrodev.com>
parents: 2384
diff changeset
866 //TODO: Confirm if DSR is cleared here on hardware
cde4ea2b4929 Clear DSR in certain gate array writes. Fixes issue in Penn & Teller's Smoke and Mirrors
Michael Pavone <pavone@retrodev.com>
parents: 2384
diff changeset
867 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
cde4ea2b4929 Clear DSR in certain gate array writes. Fixes issue in Penn & Teller's Smoke and Mirrors
Michael Pavone <pavone@retrodev.com>
parents: 2384
diff changeset
868 }
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
869 lc8951_reg_write(&cd->cdc, value);
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
870 calculate_target_cycle(m68k);
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
871 break;
2135
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
872 case GA_CDC_HOST_DATA:
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
873 //writes to this register have the same side effects as reads
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
874 sub_gate_read16(address, vcontext);
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
875 break;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
876 case GA_CDC_DMA_ADDR:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
877 cdd_run(cd, m68k->current_cycle);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
878 cd->gate_array[reg] = value;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
879 cd->cdc_dst_low = 0;
2426
cde4ea2b4929 Clear DSR in certain gate array writes. Fixes issue in Penn & Teller's Smoke and Mirrors
Michael Pavone <pavone@retrodev.com>
parents: 2384
diff changeset
880 //TODO: Confirm if DSR is cleared here on hardware
cde4ea2b4929 Clear DSR in certain gate array writes. Fixes issue in Penn & Teller's Smoke and Mirrors
Michael Pavone <pavone@retrodev.com>
parents: 2384
diff changeset
881 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
882 break;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
883 case GA_STOP_WATCH:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
884 //docs say you should only write zero to reset
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
885 //mcd-verificator comments suggest any value will reset
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
886 timers_run(cd, m68k->current_cycle);
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
887 cd->gate_array[reg] = 0;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
888 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
889 case GA_COMM_FLAG:
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
890 cd->gate_array[reg] &= 0xFF00;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
891 cd->gate_array[reg] |= value & 0xFF;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
892 break;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
893 case GA_COMM_STATUS0:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
894 case GA_COMM_STATUS1:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
895 case GA_COMM_STATUS2:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
896 case GA_COMM_STATUS3:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
897 case GA_COMM_STATUS4:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
898 case GA_COMM_STATUS5:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
899 case GA_COMM_STATUS6:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
900 case GA_COMM_STATUS7:
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
901 //no effects for these other than saving the value
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
902 cd->gate_array[reg] = value;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
903 break;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
904 case GA_TIMER:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
905 timers_run(cd, m68k->current_cycle);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
906 cd->gate_array[reg] = value & 0xFF;
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
907 cd->timer_value = 0;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
908 calculate_target_cycle(m68k);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
909 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
910 case GA_INT_MASK:
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
911 if (!(cd->gate_array[reg] & BIT_MASK_IEN6)) {
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
912 //subcode interrupts can't be made pending when they are disabled in this reg
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
913 cd->cdd.subcode_int_pending = 0;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
914 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
915 cd->gate_array[reg] = value & (BIT_MASK_IEN6|BIT_MASK_IEN5|BIT_MASK_IEN4|BIT_MASK_IEN3|BIT_MASK_IEN2|BIT_MASK_IEN1);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
916 calculate_target_cycle(m68k);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
917 break;
2080
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
918 case GA_CDD_FADER:
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
919 cdd_run(cd, m68k->current_cycle);
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
920 value &= 0x7FFF;
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
921 cdd_fader_attenuation_write(&cd->fader, value);
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
922 cd->gate_array[reg] &= 0x8000;
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
923 cd->gate_array[reg] |= value;
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
924 break;
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
925 case GA_CDD_CTRL: {
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
926 cdd_run(cd, m68k->current_cycle);
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
927 uint16_t changed = cd->gate_array[reg] ^ value;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
928 if (changed & BIT_HOCK) {
2073
c69e42444f96 Fix some cycle adjustment stuff and an off-by one on hte TOCT response
Michael Pavone <pavone@retrodev.com>
parents: 2069
diff changeset
929 cd->gate_array[reg] &= ~BIT_HOCK;
c69e42444f96 Fix some cycle adjustment stuff and an off-by one on hte TOCT response
Michael Pavone <pavone@retrodev.com>
parents: 2069
diff changeset
930 cd->gate_array[reg] |= value & BIT_HOCK;
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
931 if (value & BIT_HOCK) {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
932 cdd_hock_enabled(&cd->cdd);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
933 } else {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
934 cdd_hock_disabled(&cd->cdd);
2080
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
935 cd->gate_array[reg] |= BIT_MUTE;
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
936 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
937 calculate_target_cycle(m68k);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
938 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
939 break;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
940 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
941 case GA_CDD_CMD0:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
942 case GA_CDD_CMD1:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
943 case GA_CDD_CMD2:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
944 case GA_CDD_CMD3:
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
945 cdd_run(cd, m68k->current_cycle);
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
946 cd->gate_array[reg] = value & 0x0F0F;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
947 break;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
948 case GA_CDD_CMD4:
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
949 cdd_run(cd, m68k->current_cycle);
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
950 cd->gate_array[reg] = value & 0x0F0F;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
951 cdd_mcu_start_cmd_recv(&cd->cdd, cd->gate_array + GA_CDD_CTRL);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
952 break;
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
953 case GA_FONT_COLOR:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
954 cd->gate_array[reg] = value & 0xFF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
955 break;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
956 case GA_FONT_BITS:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
957 cd->gate_array[reg] = value;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
958 break;
2069
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
959 case GA_STAMP_SIZE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
960 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
961 cd->gate_array[reg] &= BIT_GRON;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
962 cd->gate_array[reg] |= value & (BIT_SMS|BIT_STS|BIT_RPT);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
963 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
964 case GA_STAMP_MAP_BASE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
965 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
966 cd->gate_array[reg] = value & 0xFFE0;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
967 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
968 case GA_IMAGE_BUFFER_VCELLS:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
969 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
970 cd->gate_array[reg] = value & 0x1F;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
971 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
972 case GA_IMAGE_BUFFER_START:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
973 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
974 cd->gate_array[reg] = value & 0xFFF8;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
975 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
976 case GA_IMAGE_BUFFER_OFFSET:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
977 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
978 cd->gate_array[reg] = value & 0x3F;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
979 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
980 case GA_IMAGE_BUFFER_HDOTS:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
981 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
982 cd->gate_array[reg] = value & 0x1FF;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
983 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
984 case GA_IMAGE_BUFFER_LINES:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
985 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
986 cd->gate_array[reg] = value & 0xFF;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
987 break;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
988 case GA_TRACE_VECTOR_BASE:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
989 cd_graphics_run(cd, m68k->current_cycle);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
990 cd->gate_array[reg] = value & 0xFFFE;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
991 cd_graphics_start(cd);
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
992 break;
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
993 default:
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
994 printf("Unhandled gate array write %X:%X\n", address, value);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
995 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
996 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
997 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
998
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
999 static void *sub_gate_write8(uint32_t address, void *vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1000 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1001 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1002 segacd_context *cd = m68k->system;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1003 uint32_t reg = (address & 0x1FF) >> 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1004 uint16_t value16;
2056
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1005 switch (address >> 1)
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1006 {
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
1007 case GA_MEM_MODE:
2056
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1008 case GA_CDC_HOST_DATA:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1009 case GA_CDC_DMA_ADDR:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1010 case GA_STOP_WATCH:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1011 case GA_COMM_FLAG:
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1012 case GA_TIMER:
2056
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1013 case GA_CDD_FADER:
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1014 case GA_FONT_COLOR:
2056
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1015 //these registers treat all writes as word-wide
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1016 value16 = value | (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1017 break;
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
1018 case GA_CDC_CTRL:
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
1019 if (address & 1) {
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
1020 lc8951_ar_write(&cd->cdc, value);
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1021 return vcontext;
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
1022 } else {
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1023 value16 = cd->cdc.ar | (value << 8);
2058
70260f6051dd Initial work on CDC emulation
Michael Pavone <pavone@retrodev.com>
parents: 2057
diff changeset
1024 }
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1025 break;
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1026 case GA_CDD_CMD4:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1027 if (!address) {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1028 //byte write to $FF804A should not trigger transfer
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
1029 cdd_run(cd, m68k->current_cycle);
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1030 cd->gate_array[reg] &= 0x0F;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1031 cd->gate_array[reg] |= (value << 8 & 0x0F00);
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1032 return vcontext;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1033 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1034 //intentional fallthrough for $FF804B
2056
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1035 default:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1036 if (address & 1) {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1037 value16 = cd->gate_array[reg] & 0xFF00 | value;
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1038 } else {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1039 value16 = cd->gate_array[reg] & 0xFF | (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1040 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1041 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1042 return sub_gate_write16(address, vcontext, value16);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1043 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1044
2135
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1045 static uint8_t can_main_access_prog(segacd_context *cd)
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1046 {
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1047 //TODO: use actual busack
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1048 return cd->busreq || !cd->reset;
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1049 }
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1050
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1051 static uint8_t handle_cdc_byte(void *vsys, uint8_t value)
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1052 {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1053 segacd_context *cd = vsys;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1054 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1055 //host reg is already full, pause transfer
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1056 return 0;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1057 }
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1058 if (cd->cdc.cycle == cd->cdc.transfer_end) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1059 cd->gate_array[GA_CDC_CTRL] |= BIT_EDT;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1060 printf("EDT set at %u\n", cd->cdc.cycle);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1061 }
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1062 uint16_t dest = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1063 if (!(cd->cdc_dst_low & 1)) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1064 cd->gate_array[GA_CDC_HOST_DATA] &= 0xFF;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1065 cd->gate_array[GA_CDC_HOST_DATA] |= value << 8;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1066 cd->cdc_dst_low++;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1067 if (dest != DST_PCM_RAM) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1068 //PCM RAM writes a byte at a time
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1069 return 1;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1070 }
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1071 } else {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1072 cd->gate_array[GA_CDC_HOST_DATA] &= 0xFF00;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1073 cd->gate_array[GA_CDC_HOST_DATA] |= value;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1074 }
2068
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1075
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1076 uint32_t dma_addr = cd->gate_array[GA_CDC_DMA_ADDR] << 3;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1077 dma_addr |= cd->cdc_dst_low;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1078 switch (dest)
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1079 {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1080 case DST_MAIN_CPU:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1081 case DST_SUB_CPU:
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1082 cd->cdc_dst_low = 0;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1083 cd->gate_array[GA_CDC_CTRL] |= BIT_DSR;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1084 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1085 case DST_PCM_RAM:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1086 dma_addr &= (1 << 13) - 1;
2094
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
1087 rf5c164_run(&cd->pcm, cd->cdc.cycle);
2128
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
1088 while ((cd->pcm.flags & 0x81) == 1) {
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
1089 //not sounding, but pending write
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
1090 //DMA write conflict with CPU
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
1091 rf5c164_run(&cd->pcm, cd->pcm.cycle + 4);
b0dcf5c9f353 Fix some issues with PCM dma/CPU write conflicts
Michael Pavone <pavone@retrodev.com>
parents: 2127
diff changeset
1092 }
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
1093 rf5c164_write(&cd->pcm, 0x1000 | (dma_addr >> 1), value);
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1094 dma_addr += 2;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1095 cd->cdc_dst_low = dma_addr & 7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1096 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3;
2148
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1097 //TODO: determine actual main CPU penalty
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1098 cd->m68k->current_cycle += 2 * cd->m68k->options->gen.bus_cycles;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1099 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1100 case DST_PROG_RAM:
2135
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1101 if (can_main_access_prog(cd)) {
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1102 return 0;
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1103 }
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1104 cd->prog_ram[dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA];
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1105 m68k_invalidate_code_range(cd->m68k, dma_addr - 1, dma_addr + 1);
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1106 dma_addr++;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1107 cd->cdc_dst_low = dma_addr & 7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1108 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3;
2148
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1109 //TODO: determine actual main CPU penalty
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1110 cd->m68k->current_cycle += 2 * cd->m68k->options->gen.bus_cycles;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1111 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1112 case DST_WORD_RAM:
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1113 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1114 //1M mode, write to bank assigned to Sub CPU
2135
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1115
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1116 uint32_t masked = dma_addr & (1 << 17) - 2;
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1117 cd->m68k->mem_pointers[1][masked] = cd->gate_array[GA_CDC_HOST_DATA];
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1118 m68k_invalidate_code_range(cd->m68k, 0x0C0000 + masked - 1, 0x0C0000 + masked + 1);
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1119 } else {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1120 //2M mode, check if Sub CPU has access
2129
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2128
diff changeset
1121 if (cd->main_has_word2m) {
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2128
diff changeset
1122 return 0;
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2128
diff changeset
1123 } else {
2094
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
1124 cd_graphics_run(cd, cd->cdc.cycle);
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1125 dma_addr &= (1 << 18) - 1;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1126 cd->word_ram[dma_addr >> 1] = cd->gate_array[GA_CDC_HOST_DATA];
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1127 m68k_invalidate_code_range(cd->m68k, 0x080000 + dma_addr, 0x080000 + dma_addr + 1);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1128 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1129 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1130 dma_addr++;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1131 cd->cdc_dst_low = dma_addr & 7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1132 cd->gate_array[GA_CDC_DMA_ADDR] = dma_addr >> 3;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1133 break;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1134 default:
2144
10e4439d8f13 Fix speed of CDC to PCM RAM DMA
Michael Pavone <pavone@retrodev.com>
parents: 2138
diff changeset
1135 return 0;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1136 printf("Invalid CDC transfer destination %d\n", dest);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1137 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1138 return 1;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1139 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1140
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1141 static void scd_peripherals_run(segacd_context *cd, uint32_t cycle)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1142 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1143 timers_run(cd, cycle);
2062
07ed42bd7b4c Some progress on CDC and CDD emulation. Now passes first 3 "CDC INIT" tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2061
diff changeset
1144 cdd_run(cd, cycle);
2069
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1145 cd_graphics_run(cd, cycle);
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
1146 rf5c164_run(&cd->pcm, cycle);
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1147 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1148
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1149 static m68k_context *sync_components(m68k_context * context, uint32_t address)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1150 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1151 segacd_context *cd = context->system;
2148
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1152
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1153 uint32_t num_refresh = (context->current_cycle - cd->last_refresh_cycle) / REFRESH_INTERVAL;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1154 cd->last_refresh_cycle = cd->last_refresh_cycle + num_refresh * REFRESH_INTERVAL;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1155 context->current_cycle += num_refresh * REFRESH_DELAY;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1156
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1157 scd_peripherals_run(cd, context->current_cycle);
2280
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1158 if (address) {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1159 if (cd->enter_debugger) {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1160 genesis_context *gen = cd->genesis;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1161 cd->enter_debugger = 0;
2302
0343f0d5add0 Fix libretro build for real
Michael Pavone <pavone@retrodev.com>
parents: 2282
diff changeset
1162 #ifndef IS_LIB
2280
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1163 if (gen->header.debugger_type == DEBUGGER_NATIVE) {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1164 debugger(context, address);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1165 } else {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1166 gdb_debug_enter(context, address);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1167 }
2302
0343f0d5add0 Fix libretro build for real
Michael Pavone <pavone@retrodev.com>
parents: 2282
diff changeset
1168 #endif
2104
ff32a90260c9 Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents: 2099
diff changeset
1169 }
2280
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1170 cd->m68k_pc = address;
2080
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
1171 }
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1172 calculate_target_cycle(context);
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1173 return context;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1174 }
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1175
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1176 static m68k_context *int_ack(m68k_context *context)
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1177 {
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1178 segacd_context *cd = context->system;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1179 scd_peripherals_run(cd, context->current_cycle);
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1180 switch (context->int_pending)
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1181 {
2069
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1182 case 1:
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1183 cd->graphics_int_cycle = CYCLE_NEVER;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1184 break;
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1185 case 2:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1186 cd->int2_cycle = CYCLE_NEVER;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1187 break;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1188 case 3:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1189 cd->timer_pending = 0;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1190 break;
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1191 case 4:
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1192 cd->cdd.int_pending = 0;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1193 break;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1194 case 5:
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1195 cd->cdc_int_ack = 1;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1196 break;
2116
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
1197 case 6:
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
1198 cd->cdd.subcode_int_pending = 0;
cd057d6fe030 Initial stab at subcode emulation
Michael Pavone <pavone@retrodev.com>
parents: 2111
diff changeset
1199 break;
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1200 }
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1201 //the Sega CD responds to these exclusively with !VPA which means its a slow
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1202 //6800 operation. documentation says these can take between 10 and 19 cycles.
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1203 //actual results measurements seem to suggest it's actually between 9 and 18
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1204 //Base 68K core has added 4 cycles for a normal int ack cycle already
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1205 //We add 5 + the current cycle count (in 68K cycles) mod 10 to simulate the
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1206 //additional variable delay from the use of the 6800 cycle
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1207 uint32_t cycle_count = context->current_cycle / context->options->gen.clock_divider;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1208 context->current_cycle += 5 + (cycle_count % 10);
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1209
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1210 return context;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1211 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1212
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1213 void scd_run(segacd_context *cd, uint32_t cycle)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1214 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1215 uint8_t m68k_run = !can_main_access_prog(cd);
2094
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
1216 while (cycle > cd->m68k->current_cycle) {
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
1217 if (m68k_run && !cd->sub_paused_wordram) {
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1218 uint32_t num_refresh = (cd->m68k->current_cycle - cd->last_refresh_cycle) / REFRESH_INTERVAL;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1219 cd->last_refresh_cycle = cd->last_refresh_cycle + num_refresh * REFRESH_INTERVAL;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1220 cd->m68k->current_cycle += num_refresh * REFRESH_DELAY;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1221
2148
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1222
2104
ff32a90260c9 Initial support for using debugger on sub CPU
Michael Pavone <pavone@retrodev.com>
parents: 2099
diff changeset
1223 cd->m68k->sync_cycle = cd->enter_debugger ? cd->m68k->current_cycle + 1 : cycle;
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1224 if (cd->need_reset) {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1225 cd->need_reset = 0;
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1226 m68k_reset(cd->m68k);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1227 } else {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1228 calculate_target_cycle(cd->m68k);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1229 resume_68k(cd->m68k);
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1230 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1231 } else {
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1232 cd->m68k->current_cycle = cycle;
2148
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1233 cd->last_refresh_cycle = cycle;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1234 }
2094
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
1235 scd_peripherals_run(cd, cd->m68k->current_cycle);
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1236 }
2094
ca6fc8c8dc60 Pass some more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2087
diff changeset
1237
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1238 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1239
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1240 uint32_t gen_cycle_to_scd(uint32_t cycle, genesis_context *gen)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1241 {
2055
c4d066d798c4 Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works
Michael Pavone <pavone@retrodev.com>
parents: 2054
diff changeset
1242 return ((uint64_t)cycle) * ((uint64_t)SCD_MCLKS) / ((uint64_t)gen->normal_clock);
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1243 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1244
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1245 void scd_adjust_cycle(segacd_context *cd, uint32_t deduction)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1246 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1247 deduction = gen_cycle_to_scd(deduction, cd->genesis);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1248 cd->m68k->current_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1249 cd->stopwatch_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1250 if (deduction >= cd->int2_cycle) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1251 cd->int2_cycle = 0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1252 } else if (cd->int2_cycle != CYCLE_NEVER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1253 cd->int2_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1254 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1255 if (deduction >= cd->periph_reset_cycle) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1256 cd->periph_reset_cycle = CYCLE_NEVER;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1257 } else if (cd->periph_reset_cycle != CYCLE_NEVER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1258 cd->periph_reset_cycle -= deduction;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1259 }
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1260 cdd_mcu_adjust_cycle(&cd->cdd, deduction);
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1261 lc8951_adjust_cycles(&cd->cdc, deduction);
2069
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1262 cd->graphics_cycle -= deduction;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1263 if (cd->graphics_int_cycle != CYCLE_NEVER) {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1264 if (cd->graphics_int_cycle > deduction) {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1265 cd->graphics_int_cycle -= deduction;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1266 } else {
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1267 cd->graphics_int_cycle = 0;
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1268 }
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1269 }
2148
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1270 if (deduction >= cd->last_refresh_cycle) {
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1271 cd->last_refresh_cycle -= deduction;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1272 } else {
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1273 cd->last_refresh_cycle = 0;
2da377ea932f Initial stab at CDC DMA cycle stealing and sub CPU refresh delays
Michael Pavone <pavone@retrodev.com>
parents: 2144
diff changeset
1274 }
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
1275 cd->pcm.cycle -= deduction;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1276 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1277
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1278 static uint16_t main_gate_read16(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1279 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1280 m68k_context *m68k = vcontext;
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1281 gen_update_refresh_free_access(m68k);
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1282 genesis_context *gen = m68k->system;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1283 segacd_context *cd = gen->expansion;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1284 uint32_t scd_cycle = gen_cycle_to_scd(m68k->current_cycle, gen);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1285 scd_run(cd, scd_cycle);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1286 uint32_t offset = (address & 0x1FF) >> 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1287 switch (offset)
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1288 {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1289 case GA_SUB_CPU_CTRL: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1290 uint16_t value = 0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1291 if (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1292 value |= BIT_IEN2;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1293 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1294 if (cd->int2_cycle != CYCLE_NEVER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1295 value |= BIT_IFL2;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1296 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1297 if (can_main_access_prog(cd)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1298 value |= BIT_SBRQ;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1299 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1300 if (cd->reset) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1301 value |= BIT_SRES;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1302 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1303 return value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1304 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1305 case GA_MEM_MODE:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1306 //Main CPU can't read priority mode bits
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1307 return cd->gate_array[offset] & 0xFFE7;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1308 case GA_HINT_VECTOR:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1309 return cd->rom_mut[0x72/2];
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1310 case GA_CDC_HOST_DATA: {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1311 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1312 if (dst == DST_MAIN_CPU) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1313 if (cd->gate_array[GA_CDC_CTRL] & BIT_DSR) {
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1314 cd->gate_array[GA_CDC_CTRL] &= ~BIT_DSR;
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1315 lc8951_resume_transfer(&cd->cdc);
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1316 } else {
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1317 printf("Read of CDC host data with DSR clear at %u\n", scd_cycle);
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1318 }
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1319 calculate_target_cycle(cd->m68k);
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1320 }
2066
a61a8a87410c Fix a bunch of CDC/CDD related mcd-verificator failures
Michael Pavone <pavone@retrodev.com>
parents: 2065
diff changeset
1321 return cd->gate_array[offset];
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1322 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1323 case GA_CDC_DMA_ADDR:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1324 //TODO: open bus maybe?
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1325 return 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1326 default:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1327 if (offset < GA_TIMER) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1328 return cd->gate_array[offset];
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1329 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1330 //TODO: open bus maybe?
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1331 return 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1332 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1333 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1334
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1335 static uint8_t main_gate_read8(uint32_t address, void *vcontext)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1336 {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1337 uint16_t val = main_gate_read16(address & 0xFE, vcontext);
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1338 return address & 1 ? val : val >> 8;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1339 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1340
2068
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1341 static void dump_prog_ram(segacd_context *cd)
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1342 {
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1343 static int dump_count;
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1344 char fname[256];
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1345 sprintf(fname, "prog_ram_%d.bin", dump_count++);
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1346 FILE *f = fopen(fname, "wb");
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1347 if (f) {
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1348 uint32_t last = 256*1024-1;
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1349 for(; last > 0; --last)
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1350 {
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1351 if (cd->prog_ram[last]) {
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1352 break;
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1353 }
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1354 }
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1355 for (uint32_t i = 0; i <= last; i++)
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1356 {
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1357 uint8_t pair[2];
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1358 pair[0] = cd->prog_ram[i] >> 8;
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1359 pair[1] = cd->prog_ram[i];
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1360 fwrite(pair, 1, sizeof(pair), f);
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1361 }
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1362
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1363 fclose(f);
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1364 }
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1365 }
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1366
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1367 static void *main_gate_write16(uint32_t address, void *vcontext, uint16_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1368 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1369 m68k_context *m68k = vcontext;
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1370 gen_update_refresh_free_access(m68k);
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1371 genesis_context *gen = m68k->system;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1372 segacd_context *cd = gen->expansion;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1373 uint32_t scd_cycle = gen_cycle_to_scd(m68k->current_cycle, gen);
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1374 uint32_t reg = (address & 0x1FF) >> 1;
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1375 if (reg != GA_SUB_CPU_CTRL) {
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1376 scd_run(cd, scd_cycle);
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1377 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1378 switch (reg)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1379 {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1380 case GA_SUB_CPU_CTRL: {
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1381 if ((value & BIT_IFL2) && (cd->gate_array[GA_INT_MASK] & BIT_MASK_IEN2)) {
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1382 if (cd->int2_cycle != CYCLE_NEVER) {
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1383 scd_run(cd, scd_cycle - 4 * cd->m68k->options->gen.clock_divider);
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1384 while (cd->int2_cycle != CYCLE_NEVER && cd->m68k->current_cycle < scd_cycle) {
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1385 scd_run(cd, cd->m68k->current_cycle + cd->m68k->options->gen.clock_divider);
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1386 }
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1387 }
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1388 cd->int2_cycle = scd_cycle;
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1389
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1390 }
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1391 scd_run(cd, scd_cycle);
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1392 uint8_t old_access = can_main_access_prog(cd);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1393 cd->busreq = value & BIT_SBRQ;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1394 uint8_t old_reset = cd->reset;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1395 cd->reset = value & BIT_SRES;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1396 if (cd->reset && !old_reset) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1397 cd->need_reset = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1398 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1399 /*cd->gate_array[reg] &= 0x7FFF;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1400 cd->gate_array[reg] |= value & 0x8000;*/
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1401 uint8_t new_access = can_main_access_prog(cd);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1402 uint32_t bank = cd->gate_array[GA_MEM_MODE] >> 6 & 0x3;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1403 if (new_access) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1404 if (!old_access) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1405 m68k->mem_pointers[cd->memptr_start_index] = cd->prog_ram + bank * 0x10000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1406 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1407 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1408 } else if (old_access) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1409 m68k->mem_pointers[cd->memptr_start_index] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1410 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1411 m68k_invalidate_code_range(cd->m68k, bank * 0x20000, (bank + 1) * 0x20000);
2135
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1412 dump_prog_ram(cd);
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1413 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1414 if (dst == DST_PROG_RAM) {
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1415 lc8951_resume_transfer(&cd->cdc);
2068
f573f2c31bc9 Dump PROG RAM to file for debugging
Michael Pavone <pavone@retrodev.com>
parents: 2066
diff changeset
1416 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1417 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1418 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1419 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1420 case GA_MEM_MODE: {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1421 uint16_t changed = cd->gate_array[reg] ^ value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1422 //Main CPU can't write priority mode bits, MODE or RET
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1423 cd->gate_array[reg] &= 0x001F;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1424 cd->gate_array[reg] |= value & 0xFFC0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1425 if ((cd->gate_array[reg] & BIT_MEM_MODE)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1426 //1M mode
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1427 if (!(value & BIT_DMNA)) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1428 cd->gate_array[reg] |= BIT_DMNA;
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
1429 cd->main_swap_request = 1;
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
1430 } else {
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
1431 cd->main_has_word2m = 0;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1432 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1433 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1434 //2M mode
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1435 if (changed & value & BIT_DMNA) {
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1436 cd->gate_array[reg] |= BIT_DMNA;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1437 m68k->mem_pointers[cd->memptr_start_index + 1] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1438 m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1439 cd->m68k->mem_pointers[0] = cd->word_ram;
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1440 cd->gate_array[reg] &= ~BIT_RET;
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
1441 cd->main_has_word2m = 0;
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
1442 if (cd->sub_paused_wordram) {
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
1443 cd->sub_paused_wordram = 0;
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
1444 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1445
2129
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2128
diff changeset
1446 uint16_t dst = cd->gate_array[GA_CDC_CTRL] >> 8 & 0x7;
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2128
diff changeset
1447 if (dst == DST_WORD_RAM) {
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1448 lc8951_resume_transfer(&cd->cdc);
2129
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2128
diff changeset
1449 }
4c9e447aa25b Pause word RAM DMA while word RAM is switched to main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2128
diff changeset
1450
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1451 m68k_invalidate_code_range(m68k, cd->base + 0x200000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1452 m68k_invalidate_code_range(cd->m68k, 0x080000, 0x0C0000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1453 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1454 }
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1455 if (changed & MASK_PROG_BANK && can_main_access_prog(cd)) {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1456 uint32_t bank = cd->gate_array[GA_MEM_MODE] >> 6 & 0x3;
2055
c4d066d798c4 Fix prog RAM banking and Genesis to SCD cycle conversion. Arkagis Escape demo now works
Michael Pavone <pavone@retrodev.com>
parents: 2054
diff changeset
1457 m68k->mem_pointers[cd->memptr_start_index] = cd->prog_ram + bank * 0x10000;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1458 m68k_invalidate_code_range(m68k, cd->base + 0x220000, cd->base + 0x240000);
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1459 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1460 break;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1461 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1462 case GA_HINT_VECTOR:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1463 cd->rom_mut[0x72/2] = value;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1464 break;
2135
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1465 case GA_CDC_HOST_DATA:
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1466 //writes to this register have the same side effects as reads
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1467 main_gate_read16(address, vcontext);
95b3752925e0 Can now pass all CDC DMA3 tests in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2134
diff changeset
1468 break;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1469 case GA_COMM_FLAG:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1470 //Main CPU can only write the upper byte;
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1471 cd->gate_array[reg] &= 0xFF;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1472 cd->gate_array[reg] |= value & 0xFF00;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1473 break;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1474 case GA_COMM_CMD0:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1475 case GA_COMM_CMD1:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1476 case GA_COMM_CMD2:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1477 case GA_COMM_CMD3:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1478 case GA_COMM_CMD4:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1479 case GA_COMM_CMD5:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1480 case GA_COMM_CMD6:
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1481 case GA_COMM_CMD7:
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1482 //no effects for these other than saving the value
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1483 cd->gate_array[reg] = value;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1484 break;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1485 default:
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1486 printf("Unhandled gate array write %X:%X\n", address, value);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1487 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1488 return vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1489 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1490
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1491 static void *main_gate_write8(uint32_t address, void *vcontext, uint8_t value)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1492 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1493 m68k_context *m68k = vcontext;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1494 genesis_context *gen = m68k->system;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1495 segacd_context *cd = gen->expansion;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1496 uint32_t reg = (address & 0x1FF) >> 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1497 uint16_t value16;
2108
68d61ba1b762 Fix handling of byte writes to gate array regs from main CPU
Michael Pavone <pavone@retrodev.com>
parents: 2106
diff changeset
1498 switch (reg)
2056
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1499 {
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1500 case GA_SUB_CPU_CTRL:
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1501 if (address & 1) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1502 value16 = value;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1503 } else {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1504 value16 = value << 8;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1505 if (cd->reset) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1506 value16 |= BIT_SRES;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1507 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1508 if (cd->busreq) {
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1509 value16 |= BIT_SBRQ;
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1510 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1511 }
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1512 break;
2056
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1513 case GA_HINT_VECTOR:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1514 case GA_COMM_FLAG:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1515 //writes to these regs are always treated as word wide
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1516 value16 = value | (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1517 break;
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1518 default:
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1519 if (address & 1) {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1520 value16 = cd->gate_array[reg] & 0xFF00 | value;
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1521 } else {
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1522 value16 = cd->gate_array[reg] & 0xFF | (value << 8);
27bbfcb7850a Fix byte write behavior on a few gate array regs to pass the VAR test in mcd-verificator
Michael Pavone <pavone@retrodev.com>
parents: 2055
diff changeset
1523 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1524 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1525 return main_gate_write16(address, vcontext, value16);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1526 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1527
2329
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1528 uint8_t laseractive_regs[256];
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1529
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1530 static uint16_t laseractive_read16(uint32_t address, void *vcontext)
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1531 {
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1532 printf("LaserActive 16-bit register read %X\n", address);
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1533 return 0xFFFF;
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1534 }
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1535
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1536 static uint8_t laseractive_read8(uint32_t address, void *vcontext)
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1537 {
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1538 printf("LaserActive 8-bit register read %X\n", address);
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1539 if (address == 0xFDFE81) {
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1540 return 0x80 | (laseractive_regs[0x41] & 1);
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1541 } else if (address >= 0xFDFE41 && address < 0xFDFE80 && (address & 1)) {
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1542 return laseractive_regs[address & 0xFF];
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1543 }
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1544 return 0xFF;
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1545 }
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1546
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1547 static void *laseractive_write16(uint32_t address, void *vcontext, uint16_t value)
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1548 {
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1549 printf("LaserActive 16-bit register write %X: %X\n", address, value);
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1550 return vcontext;
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1551 }
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1552
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1553 static void *laseractive_write8(uint32_t address, void *vcontext, uint8_t value)
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1554 {
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1555 printf("LaserActive 8-bit register write %X: %X\n", address, value);
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1556 laseractive_regs[address & 0xFF] = value;
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1557 return vcontext;
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1558 }
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1559
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1560 segacd_context *alloc_configure_segacd(system_media *media, uint32_t opts, uint8_t force_region, rom_info *info)
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1561 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1562 static memmap_chunk sub_cpu_map[] = {
2111
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1563 {0x000000, 0x01FF00, 0xFFFFFF, .flags=MMAP_READ | MMAP_CODE, .write_16 = prog_ram_wp_write16, .write_8 = prog_ram_wp_write8},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1564 {0x01FF00, 0x080000, 0xFFFFFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_CODE},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1565 {0x080000, 0x0C0000, 0x03FFFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_CODE | MMAP_PTR_IDX | MMAP_FUNC_NULL, .ptr_index = 0,
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1566 .read_16 = word_ram_2M_read16, .write_16 = word_ram_2M_write16, .read_8 = word_ram_2M_read8, .write_8 = word_ram_2M_write8},
2111
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1567 {0x0C0000, 0x0E0000, 0x01FFFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_CODE | MMAP_PTR_IDX | MMAP_FUNC_NULL, .ptr_index = 1,
2134
9caebcfeac72 Implement word RAM interleaving in 1M mode, now passes mcd-verificator word RAM tests
Michael Pavone <pavone@retrodev.com>
parents: 2131
diff changeset
1568 .read_16 = word_ram_1M_read16, .write_16 = word_ram_1M_write16, .read_8 = word_ram_1M_read8, .write_8 = word_ram_1M_write8, .shift = 1},
2111
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1569 {0xFE0000, 0xFF0000, 0x003FFF, .flags=MMAP_READ | MMAP_WRITE | MMAP_ONLY_ODD},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1570 {0xFF0000, 0xFF8000, 0x003FFF, .read_16 = pcm_read16, .write_16 = pcm_write16, .read_8 = pcm_read8, .write_8 = pcm_write8},
2329
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1571 {0xFF8000, 0xFF8200, 0x0001FF, .read_16 = sub_gate_read16, .write_16 = sub_gate_write16, .read_8 = sub_gate_read8, .write_8 = sub_gate_write8},
06d5e9b08bdb Add NTSC composite shader by Sik
Michael Pavone <pavone@retrodev.com>
parents: 2302
diff changeset
1572 {0xFD0000, 0xFE0000, 0xFFFFFF, .read_16 = laseractive_read16, .write_16 = laseractive_write16, .read_8 = laseractive_read8, .write_8 = laseractive_write8}
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1573 };
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1574
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1575 segacd_context *cd = calloc(sizeof(segacd_context), 1);
2384
03e6ac327ba0 Handle changes to sample rate while content is running
Michael Pavone <pavone@retrodev.com>
parents: 2350
diff changeset
1576 cd->speed_percent = 100;
2083
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents: 2081
diff changeset
1577 uint32_t firmware_size;
2123
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1578 uint8_t region = force_region;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1579 if (!region) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1580 char * def_region = tern_find_path_default(config, "system\0default_region\0", (tern_val){.ptrval = "U"}, TVAL_PTR).ptrval;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1581 if (!info->regions || (info->regions & translate_region_char(toupper(*def_region)))) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1582 region = translate_region_char(toupper(*def_region));
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1583 } else {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1584 region = info->regions;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1585 }
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1586 }
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1587 const char *key;
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1588 if (region & REGION_E) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1589 key = "system\0scd_bios_eu\0";
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1590 } else if (region & REGION_J) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1591 key = "system\0scd_bios_jp\0";
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1592 } else {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1593 key = "system\0scd_bios_us\0";
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1594 }
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1595 char *bios_path = tern_find_path_default(config, key, (tern_val){.ptrval = "cdbios.bin"}, TVAL_PTR).ptrval;
2160
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1596 if (is_absolute_path(bios_path)) {
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1597 FILE *f = fopen(bios_path, "rb");
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1598 if (f) {
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1599 long to_read = file_size(f);
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1600 cd->rom = malloc(to_read);
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1601 firmware_size = fread(cd->rom, 1, to_read, f);
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1602 if (!firmware_size) {
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1603 free(cd->rom);
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1604 cd->rom = NULL;
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1605 }
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1606 fclose(f);
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1607 }
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1608 } else {
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1609 cd->rom = (uint16_t *)read_bundled_file(bios_path, &firmware_size);
3f09312685e3 Fix loading CD bios from absolute path
Michael Pavone <pavone@retrodev.com>
parents: 2148
diff changeset
1610 }
2123
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1611 if (!cd->rom) {
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1612 fatal_error("Failed to load Sega CD BIOS from %s\n", bios_path);
50385ae2617b Attempt to select an appropriate Sega/Mega CD BIOS file based on region and config
Michael Pavone <pavone@retrodev.com>
parents: 2122
diff changeset
1613 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1614 uint32_t adjusted_size = nearest_pow2(firmware_size);
2083
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents: 2081
diff changeset
1615 if (adjusted_size != firmware_size) {
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents: 2081
diff changeset
1616 cd->rom = realloc(cd->rom, adjusted_size);
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1617 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1618 cd->rom_mut = malloc(adjusted_size);
1503
a763523dadf4 Added code for initializing a combined Genesis + Sega CD system when a Sega CD ISO is loaded
Michael Pavone <pavone@retrodev.com>
parents: 1502
diff changeset
1619 byteswap_rom(adjusted_size, cd->rom);
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1620 memcpy(cd->rom_mut, cd->rom, adjusted_size);
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1621 cd->rom_mut[0x72/2] = 0xFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1622
2083
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents: 2081
diff changeset
1623 cd->prog_ram = calloc(512*1024, 1);
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents: 2081
diff changeset
1624 cd->word_ram = calloc(256*1024, 1);
372625dd9590 Persist BRAM to file. Load BIOS relative to blastem directory
Michael Pavone <pavone@retrodev.com>
parents: 2081
diff changeset
1625 cd->bram = calloc(8*1024, 1);
2281
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1626 char *bram_size_id = tern_find_path_default(config, "system\0bram_cart_size_id\0", (tern_val){.ptrval = "4"}, TVAL_PTR).ptrval;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1627 cd->bram_cart_id = 0xFF;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1628 cd->bram_cart = NULL;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1629 if (strcmp(bram_size_id, "none")) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1630 char *end;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1631 long id = strtol(bram_size_id, &end, 10);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1632 if (end != bram_size_id && id < 8) {
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1633 cd->bram_cart_id = id;
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1634 cd->bram_cart = calloc(0x2000 << id, 1);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1635 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1636 }
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1637
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1638 sub_cpu_map[0].buffer = sub_cpu_map[1].buffer = cd->prog_ram;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1639 sub_cpu_map[4].buffer = cd->bram;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1640 m68k_options *mopts = malloc(sizeof(m68k_options));
2350
f8b5142c06aa Allow 68K to return mid-instruction. Adjust how 68K interrupt ack works so int2 busy flag timing is more correct. Fix some other SCD timing issues
Michael Pavone <pavone@retrodev.com>
parents: 2344
diff changeset
1641 init_m68k_opts(mopts, sub_cpu_map, sizeof(sub_cpu_map) / sizeof(*sub_cpu_map), 4, sync_components, int_ack);
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1642 cd->m68k = init_68k_context(mopts, NULL);
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1643 cd->m68k->system = cd;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1644 cd->int2_cycle = CYCLE_NEVER;
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1645 cd->busreq = 1;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1646 cd->busack = 1;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1647 cd->need_reset = 1;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1648 cd->reset = 1; //active low, so reset is not active on start
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1649 cd->memptr_start_index = 0;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1650 cd->gate_array[1] = 1;
2080
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
1651 cd->gate_array[GA_CDD_CTRL] = BIT_MUTE; //Data/mute flag is set on start
2119
5ec2f97365a2 More accurate RET/DMNA implementation
Michael Pavone <pavone@retrodev.com>
parents: 2116
diff changeset
1652 cd->main_has_word2m = 1;
2065
02a9846668d1 Implement transfer of data from CDC to elsewhere. Other miscellaneous CDD/CDC improvements
Michael Pavone <pavone@retrodev.com>
parents: 2062
diff changeset
1653 lc8951_init(&cd->cdc, handle_cdc_byte, cd);
2061
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1654 if (media->chain && media->type != MEDIA_CDROM) {
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1655 media = media->chain;
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1656 }
7c1760b5b3e5 Implemented basic TOC functionality of CDD MCU
Michael Pavone <pavone@retrodev.com>
parents: 2058
diff changeset
1657 cdd_mcu_init(&cd->cdd, media);
2069
8e51c0c3f2e3 Initial attempt at implementing the Sega CD graphics hardware
Michael Pavone <pavone@retrodev.com>
parents: 2068
diff changeset
1658 cd_graphics_init(cd);
2080
bafb757e1cd2 Implement CD audio
Michael Pavone <pavone@retrodev.com>
parents: 2073
diff changeset
1659 cdd_fader_init(&cd->fader);
2081
cfd53c94fffb Initial stab at RF5C164 emulation
Michael Pavone <pavone@retrodev.com>
parents: 2080
diff changeset
1660 rf5c164_init(&cd->pcm, SCD_MCLKS, 4);
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1661 return cd;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1662 }
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1663
2164
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1664 void free_segacd(segacd_context *cd)
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1665 {
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1666 cdd_fader_deinit(&cd->fader);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1667 rf5c164_deinit(&cd->pcm);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1668 m68k_options_free(cd->m68k->options);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1669 free(cd->m68k);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1670 free(cd->bram);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1671 free(cd->word_ram);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1672 free(cd->prog_ram);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1673 free(cd->rom_mut);
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1674 }
4fbe1e7c4a73 Don't leak all Sega CD resources when freeing a Genesis instance
Michael Pavone <pavone@retrodev.com>
parents: 2160
diff changeset
1675
2280
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1676 void segacd_serialize(segacd_context *cd, serialize_buffer *buf, uint8_t all)
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1677 {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1678 if (all) {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1679 start_section(buf, SECTION_SUB_68000);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1680 m68k_serialize(cd->m68k, cd->m68k_pc, buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1681 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1682
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1683 start_section(buf, SECTION_GATE_ARRAY);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1684 save_buffer16(buf, cd->gate_array, sizeof(cd->gate_array)/sizeof(*cd->gate_array));
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1685 save_buffer16(buf, cd->prog_ram, 256*1024);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1686 save_buffer16(buf, cd->word_ram, 128*1024);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1687 save_int16(buf, cd->rom_mut[0x72/2]);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1688 save_int32(buf, cd->stopwatch_cycle);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1689 save_int32(buf, cd->int2_cycle);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1690 save_int32(buf, cd->graphics_int_cycle);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1691 save_int32(buf, cd->periph_reset_cycle);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1692 save_int32(buf, cd->last_refresh_cycle);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1693 save_int32(buf, cd->graphics_cycle);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1694 save_int32(buf, cd->base);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1695 save_int32(buf, cd->graphics_x);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1696 save_int32(buf, cd->graphics_y);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1697 save_int32(buf, cd->graphics_dx);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1698 save_int32(buf, cd->graphics_dy);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1699 save_int32(buf, cd->graphics_dst_x);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1700 save_buffer8(buf, cd->graphics_pixels, sizeof(cd->graphics_pixels));
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1701 save_int8(buf, cd->timer_pending);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1702 save_int8(buf, cd->timer_value);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1703 save_int8(buf, cd->busreq);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1704 save_int8(buf, cd->reset);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1705 save_int8(buf, cd->need_reset);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1706 save_int8(buf, cd->cdc_dst_low);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1707 save_int8(buf, cd->cdc_int_ack);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1708 save_int8(buf, cd->graphics_step);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1709 save_int8(buf, cd->graphics_dst_y);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1710 save_int8(buf, cd->main_has_word2m);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1711 save_int8(buf, cd->main_swap_request);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1712 save_int8(buf, cd->bank_toggle);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1713 save_int8(buf, cd->sub_paused_wordram);
2281
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1714 save_int8(buf, cd->bram_cart_write_enabled);
2280
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1715 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1716
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1717 start_section(buf, SECTION_CDD_MCU);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1718 cdd_mcu_serialize(&cd->cdd, buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1719 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1720
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1721 start_section(buf, SECTION_LC8951);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1722 lc8951_serialize(&cd->cdc, buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1723 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1724
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1725 start_section(buf, SECTION_CDROM);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1726 cdimage_serialize(cd->cdd.media, buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1727 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1728 }
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1729 start_section(buf, SECTION_RF5C164);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1730 rf5c164_serialize(&cd->pcm, buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1731 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1732
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1733 start_section(buf, SECTION_CDD_FADER);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1734 cdd_fader_serialize(&cd->fader, buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1735 end_section(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1736 }
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1737
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1738 static void gate_array_deserialize(deserialize_buffer *buf, void *vcd)
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1739 {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1740 segacd_context *cd = vcd;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1741 load_buffer16(buf, cd->gate_array, sizeof(cd->gate_array)/sizeof(*cd->gate_array));
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1742 load_buffer16(buf, cd->prog_ram, 256*1024);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1743 load_buffer16(buf, cd->word_ram, 128*1024);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1744 cd->rom_mut[0x72/2] = load_int16(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1745 cd->stopwatch_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1746 cd->int2_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1747 cd->graphics_int_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1748 cd->periph_reset_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1749 cd->last_refresh_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1750 cd->graphics_cycle = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1751 cd->base = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1752 cd->graphics_x = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1753 cd->graphics_y = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1754 cd->graphics_dx = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1755 cd->graphics_dy = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1756 cd->graphics_dst_x = load_int32(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1757 load_buffer8(buf, cd->graphics_pixels, sizeof(cd->graphics_pixels));
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1758 cd->timer_pending = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1759 cd->timer_value = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1760 cd->busreq = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1761 cd->reset = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1762 cd->need_reset = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1763 cd->cdc_dst_low = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1764 cd->cdc_int_ack = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1765 cd->graphics_step = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1766 cd->graphics_dst_y = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1767 cd->main_has_word2m = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1768 cd->main_swap_request = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1769 cd->bank_toggle = load_int8(buf);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1770 cd->sub_paused_wordram = load_int8(buf);
2281
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1771 cd->bram_cart_write_enabled = load_int8(buf);
2280
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1772
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1773 if (cd->gate_array[GA_MEM_MODE] & BIT_MEM_MODE) {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1774 //1M mode
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1775 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1776 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1777 cd->m68k->mem_pointers[0] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1778 cd->m68k->mem_pointers[1] = cd->bank_toggle ? cd->word_ram : cd->word_ram + 1;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1779 } else {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1780 //2M mode
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1781 if (cd->main_has_word2m) {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1782 //main CPU has word ram
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1783 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 1] = cd->word_ram;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1784 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 2] = cd->word_ram + 0x10000;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1785 cd->m68k->mem_pointers[0] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1786 cd->m68k->mem_pointers[1] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1787 } else {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1788 //sub cpu has word ram
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1789 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 1] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1790 cd->genesis->m68k->mem_pointers[cd->memptr_start_index + 2] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1791 cd->m68k->mem_pointers[0] = cd->word_ram;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1792 cd->m68k->mem_pointers[1] = NULL;
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1793 }
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1794 }
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1795
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1796 m68k_invalidate_code_range(cd->m68k, 0, 0x0E0000);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1797 m68k_invalidate_code_range(cd->genesis->m68k, cd->base + 0x200000, cd->base + 0x240000);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1798 }
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1799
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1800 void segacd_register_section_handlers(segacd_context *cd, deserialize_buffer *buf)
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1801 {
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1802 register_section_handler(buf, (section_handler){.fun = m68k_deserialize, .data = cd->m68k}, SECTION_SUB_68000);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1803 register_section_handler(buf, (section_handler){.fun = gate_array_deserialize, .data = cd}, SECTION_GATE_ARRAY);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1804 register_section_handler(buf, (section_handler){.fun = cdd_mcu_deserialize, .data = &cd->cdd}, SECTION_CDD_MCU);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1805 register_section_handler(buf, (section_handler){.fun = lc8951_deserialize, .data = &cd->cdc}, SECTION_LC8951);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1806 register_section_handler(buf, (section_handler){.fun = rf5c164_deserialize, .data = &cd->pcm}, SECTION_RF5C164);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1807 register_section_handler(buf, (section_handler){.fun = cdd_fader_deserialize, .data = &cd->fader}, SECTION_CDD_FADER);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1808 register_section_handler(buf, (section_handler){.fun = cdimage_deserialize, .data = cd->cdd.media}, SECTION_CDROM);
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1809 }
9ead0fe69d9b Implement savestate support for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2278
diff changeset
1810
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1811 memmap_chunk *segacd_main_cpu_map(segacd_context *cd, uint8_t cart_boot, uint32_t *num_chunks)
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1812 {
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1813 static memmap_chunk main_cpu_map[] = {
2111
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1814 {0x000000, 0x020000, 0x01FFFF, .flags=MMAP_READ},
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1815 {0x020000, 0x040000, 0x01FFFF, .flags=MMAP_READ|MMAP_WRITE|MMAP_PTR_IDX|MMAP_FUNC_NULL|MMAP_CODE, .ptr_index = 0,
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1816 .read_16 = unmapped_prog_read16, .write_16 = unmapped_prog_write16, .read_8 = unmapped_prog_read8, .write_8 = unmapped_prog_write8},
2111
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1817 {0x040000, 0x060000, 0x01FFFF, .flags=MMAP_READ}, //first ROM alias
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1818 //TODO: additional ROM/prog RAM aliases
2111
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1819 {0x200000, 0x220000, 0x01FFFF, .flags=MMAP_READ|MMAP_WRITE|MMAP_PTR_IDX|MMAP_FUNC_NULL|MMAP_CODE, .ptr_index = 1,
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1820 .read_16 = unmapped_word_read16, .write_16 = unmapped_word_write16, .read_8 = unmapped_word_read8, .write_8 = unmapped_word_write8},
2111
4be496489eda Fix some off-by-ones in the address map definition for Sega CD hardware
Michael Pavone <pavone@retrodev.com>
parents: 2108
diff changeset
1821 {0x220000, 0x240000, 0x01FFFF, .flags=MMAP_READ|MMAP_WRITE|MMAP_PTR_IDX|MMAP_FUNC_NULL|MMAP_CODE, .ptr_index = 2,
2057
88deea42caf0 Fix a bunch of stuff to pass more mcd-verificator tests
Michael Pavone <pavone@retrodev.com>
parents: 2056
diff changeset
1822 .read_16 = cell_image_read16, .write_16 = cell_image_write16, .read_8 = cell_image_read8, .write_8 = cell_image_write8},
2281
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1823 {0xA12000, 0xA13000, 0xFFFFFF, .read_16 = main_gate_read16, .write_16 = main_gate_write16, .read_8 = main_gate_read8, .write_8 = main_gate_write8},
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1824 {0x400000, 0x800000, 0xFFFFFF, .read_16 = cart_area_read16, .write_16 = cart_area_write16, .read_8 = cart_area_read8, .write_8 = cart_area_write8}
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1825 };
2281
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1826 *num_chunks = sizeof(main_cpu_map) / sizeof(*main_cpu_map);
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1827 if (cart_boot) {
2282
a6a68c33cce7 Fix regression in Mode 1 boot
Michael Pavone <pavone@retrodev.com>
parents: 2281
diff changeset
1828 (*num_chunks)--;
2281
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1829 }
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1830 for (int i = 0; i < *num_chunks; i++)
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1831 {
2281
b9fed07f19e4 Implement BRAM cart support
Michael Pavone <pavone@retrodev.com>
parents: 2280
diff changeset
1832 if (main_cpu_map[i].start < 0x400000) {
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1833 if (cart_boot) {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1834 main_cpu_map[i].start |= 0x400000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1835 main_cpu_map[i].end |= 0x400000;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1836 } else {
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1837 main_cpu_map[i].start &= 0x3FFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1838 main_cpu_map[i].end &= 0x3FFFFF;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1839 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1840 }
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1841 }
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1842 main_cpu_map[0].buffer = cd->rom_mut;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1843 main_cpu_map[2].buffer = cd->rom;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1844 main_cpu_map[1].buffer = cd->prog_ram;
2054
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1845 main_cpu_map[3].buffer = cd->word_ram;
8ee7ecbf3f21 Implement enough of Sega CD gate array and Sub CPU to pass Sik's Mode 1 test ROM
Michael Pavone <pavone@retrodev.com>
parents: 1504
diff changeset
1846 main_cpu_map[4].buffer = cd->word_ram + 0x10000;
1502
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1847 return main_cpu_map;
2564b6ba2e12 Initial skeleton of Sega CD memory handlers
Michael Pavone <pavone@retrodev.com>
parents: 1467
diff changeset
1848 }
2278
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1849
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1850 void segacd_set_speed_percent(segacd_context *cd, uint32_t percent)
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1851 {
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1852 uint32_t scd_cycle = gen_cycle_to_scd(cd->genesis->ym->current_cycle, cd->genesis);
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1853 scd_run(cd, scd_cycle);
2384
03e6ac327ba0 Handle changes to sample rate while content is running
Michael Pavone <pavone@retrodev.com>
parents: 2350
diff changeset
1854 cd->speed_percent = percent;
03e6ac327ba0 Handle changes to sample rate while content is running
Michael Pavone <pavone@retrodev.com>
parents: 2350
diff changeset
1855 uint32_t new_clock = ((uint64_t)SCD_MCLKS * (uint64_t)cd->speed_percent) / 100;
2278
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1856 rf5c164_adjust_master_clock(&cd->pcm, new_clock);
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1857 cdd_fader_set_speed_percent(&cd->fader, percent);
5a21bc0ec583 Implement turbo/slo mo for Sega CD
Michael Pavone <pavone@retrodev.com>
parents: 2233
diff changeset
1858 }
2335
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1859
2384
03e6ac327ba0 Handle changes to sample rate while content is running
Michael Pavone <pavone@retrodev.com>
parents: 2350
diff changeset
1860 void segacd_config_updated(segacd_context *cd)
03e6ac327ba0 Handle changes to sample rate while content is running
Michael Pavone <pavone@retrodev.com>
parents: 2350
diff changeset
1861 {
03e6ac327ba0 Handle changes to sample rate while content is running
Michael Pavone <pavone@retrodev.com>
parents: 2350
diff changeset
1862 //sample rate may have changed
03e6ac327ba0 Handle changes to sample rate while content is running
Michael Pavone <pavone@retrodev.com>
parents: 2350
diff changeset
1863 uint32_t new_clock = ((uint64_t)SCD_MCLKS * (uint64_t)cd->speed_percent) / 100;
03e6ac327ba0 Handle changes to sample rate while content is running
Michael Pavone <pavone@retrodev.com>
parents: 2350
diff changeset
1864 rf5c164_adjust_master_clock(&cd->pcm, new_clock);
03e6ac327ba0 Handle changes to sample rate while content is running
Michael Pavone <pavone@retrodev.com>
parents: 2350
diff changeset
1865 cdd_fader_set_speed_percent(&cd->fader, cd->speed_percent);
03e6ac327ba0 Handle changes to sample rate while content is running
Michael Pavone <pavone@retrodev.com>
parents: 2350
diff changeset
1866 }
03e6ac327ba0 Handle changes to sample rate while content is running
Michael Pavone <pavone@retrodev.com>
parents: 2350
diff changeset
1867
2335
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1868 static uint8_t *copy_chars(uint8_t *dst, uint8_t *str)
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1869 {
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1870 size_t len = strlen(str);
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1871 memcpy(dst, str, len);
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1872 return dst + len;
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1873 }
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1874
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1875 void segacd_format_bram(uint8_t *buffer, size_t size)
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1876 {
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1877 memset(buffer, 0, size);
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1878 uint16_t free_blocks = (size / 64) - 3;
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1879 uint8_t *cur = buffer + size - 0x40;
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1880 cur = copy_chars(cur, "___________");
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1881 cur += 4;
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1882 *(cur++) = 0x40;
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1883 for (int i = 0; i < 4; i++)
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1884 {
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1885 *(cur++) = free_blocks >> 8;
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1886 *(cur++) = free_blocks;
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1887 }
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1888 cur += 8;
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1889 cur = copy_chars(cur, "SEGA_CD_ROM");
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1890 ++cur;
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1891 *(cur++) = 1;
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1892 cur += 3;
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1893 copy_chars(cur, "RAM_CARTRIDGE___");
c05b7c5e6f11 Automatically format Sega CD backup RAM
Michael Pavone <pavone@retrodev.com>
parents: 2329
diff changeset
1894 }