repos/blastem: ym2612.c annotate

annotate ym2612.c @ 1955:1c7af12efe8b

Fix awful playback latencin in new netplay implementation

author	Michael Pavone <pavone@retrodev.com>
date	Fri, 01 May 2020 21:17:21 -0700
parents	c3c62dbf1ceb
children	3ce38692a3f2

rev	line source
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 451 diff changeset	1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 451 diff changeset	2 Copyright 2013 Michael Pavone
483 3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	3 This file is part of BlastEm.
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 451 diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 451 diff changeset	5 */
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	6 #include <string.h>
359 cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	7 #include <math.h>
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	8 #include <stdio.h>
364 62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request Mike Pavone <pavone@retrodev.com> parents: 362 diff changeset	9 #include <stdlib.h>
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	10 #include "ym2612.h"
364 62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request Mike Pavone <pavone@retrodev.com> parents: 362 diff changeset	11 #include "render.h"
407 c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	12 #include "wave.h"
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 483 diff changeset	13 #include "blastem.h"
1946 c3c62dbf1ceb WIP netplay support Michael Pavone <pavone@retrodev.com> parents: 1912 diff changeset	14 #include "event_log.h"
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	15
370 5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	16 //#define DO_DEBUG_PRINT
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	17 #ifdef DO_DEBUG_PRINT
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	18 #define dfprintf fprintf
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	19 #define dfopen(var, fname, mode) var=fopen(fname, mode)
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	20 #else
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	21 #define dfprintf
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	22 #define dfopen(var, fname, mode)
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	23 #endif
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	24
1902 32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	25 #define BUSY_CYCLES 32
364 62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request Mike Pavone <pavone@retrodev.com> parents: 362 diff changeset	26 #define OP_UPDATE_PERIOD 144
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	27
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	28 #define BIT_TIMERA_ENABLE 0x1
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	29 #define BIT_TIMERB_ENABLE 0x2
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	30 #define BIT_TIMERA_OVEREN 0x4
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	31 #define BIT_TIMERB_OVEREN 0x8
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	32 #define BIT_TIMERA_RESET 0x10
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	33 #define BIT_TIMERB_RESET 0x20
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	34
845 3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track. Michael Pavone <pavone@retrodev.com> parents: 740 diff changeset	35 #define BIT_TIMERA_LOAD 0x40
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track. Michael Pavone <pavone@retrodev.com> parents: 740 diff changeset	36 #define BIT_TIMERB_LOAD 0x80
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track. Michael Pavone <pavone@retrodev.com> parents: 740 diff changeset	37
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	38 #define BIT_STATUS_TIMERA 0x1
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	39 #define BIT_STATUS_TIMERB 0x2
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	40
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1002 diff changeset	41 static uint32_t ym_calc_phase_inc(ym2612_context * context, ym_operator * operator, uint32_t op);
935 01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation Michael Pavone <pavone@retrodev.com> parents: 930 diff changeset	42
359 cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	43 enum {
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	44 PHASE_ATTACK,
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	45 PHASE_DECAY,
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	46 PHASE_SUSTAIN,
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	47 PHASE_RELEASE
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	48 };
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	49
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	50 uint8_t did_tbl_init = 0;
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	51 //According to Nemesis, real hardware only uses a 256 entry quarter sine table; however,
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	52 //memory is cheap so using a half sine table will probably save some cycles
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	53 //a full sine table would be nice, but negative numbers don't get along with log2
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	54 #define SINE_TABLE_SIZE 512
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1002 diff changeset	55 static uint16_t sine_table[SINE_TABLE_SIZE];
359 cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	56 //Similar deal here with the power table for log -> linear conversion
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	57 //According to Nemesis, real hardware only uses a 256 entry table for the fractional part
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	58 //and uses the whole part as a shift amount.
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	59 #define POW_TABLE_SIZE (1 << 13)
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1002 diff changeset	60 static uint16_t pow_table[POW_TABLE_SIZE];
359 cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	61
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1002 diff changeset	62 static uint16_t rate_table_base[] = {
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	63 //main portion
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	64 0,1,0,1,0,1,0,1,
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	65 0,1,0,1,1,1,0,1,
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	66 0,1,1,1,0,1,1,1,
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	67 0,1,1,1,1,1,1,1,
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	68 //top end
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	69 1,1,1,1,1,1,1,1,
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	70 1,1,1,2,1,1,1,2,
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	71 1,2,1,2,1,2,1,2,
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	72 1,2,2,2,1,2,2,2,
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	73 };
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	74
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1002 diff changeset	75 static uint16_t rate_table[64*8];
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	76
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1002 diff changeset	77 static uint8_t lfo_timer_values[] = {108, 77, 71, 67, 62, 44, 8, 5};
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1002 diff changeset	78 static uint8_t lfo_pm_base[][8] = {
411 baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	79 {0, 0, 0, 0, 0, 0, 0, 0},
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	80 {0, 0, 0, 0, 4, 4, 4, 4},
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	81 {0, 0, 0, 4, 4, 4, 8, 8},
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	82 {0, 0, 4, 4, 8, 8, 0xc, 0xc},
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	83 {0, 0, 4, 8, 8, 8, 0xc,0x10},
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	84 {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	85 {0, 0,0x10,0x18,0x20,0x20,0x28,0x30},
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	86 {0, 0,0x20,0x30,0x40,0x40,0x50,0x60}
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	87 };
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1002 diff changeset	88 static int16_t lfo_pm_table[128 * 32 * 8];
411 baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	89
930 f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	90 int16_t ams_shift[] = {8, 1, -1, -2};
740 25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation Michael Pavone <pavone@retrodev.com> parents: 739 diff changeset	91
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	92 #define MAX_ENVELOPE 0xFFC
364 62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request Mike Pavone <pavone@retrodev.com> parents: 362 diff changeset	93 #define YM_DIVIDER 2
374 d42a8a3e4894 Fix YM2612 busy flag Mike Pavone <pavone@retrodev.com> parents: 371 diff changeset	94 #define CYCLE_NEVER 0xFFFFFFFF
359 cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	95
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1002 diff changeset	96 static uint16_t round_fixed_point(double value, int dec_bits)
359 cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	97 {
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	98 return value * (1 << dec_bits) + 0.5;
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	99 }
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	100
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1002 diff changeset	101 static FILE * debug_file = NULL;
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1002 diff changeset	102 static uint32_t first_key_on=0;
370 5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	103
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1002 diff changeset	104 static ym2612_context * log_context = NULL;
407 c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	105
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1002 diff changeset	106 static void ym_finalize_log()
407 c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	107 {
884 252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	108 if (!log_context) {
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	109 return;
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	110 }
407 c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	111 for (int i = 0; i < NUM_CHANNELS; i++) {
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	112 if (log_context->channels[i].logfile) {
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	113 wave_finalize(log_context->channels[i].logfile);
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	114 }
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	115 }
884 252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	116 log_context = NULL;
407 c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	117 }
483 3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	118
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	119 void ym_adjust_master_clock(ym2612_context * context, uint32_t master_clock)
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	120 {
1555 6ce36c3f250b More audio refactoring in preparation for allowing proper sync to video with dynamic audio rate control Michael Pavone <pavone@retrodev.com> parents: 1551 diff changeset	121 render_audio_adjust_clock(context->audio, master_clock, context->clock_inc * NUM_OPERATORS);
483 3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button Mike Pavone <pavone@retrodev.com> parents: 467 diff changeset	122 }
407 c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	123
1902 32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	124 void ym_adjust_cycles(ym2612_context *context, uint32_t deduction)
32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	125 {
32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	126 context->current_cycle -= deduction;
32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	127 if (context->write_cycle != CYCLE_NEVER && context->write_cycle >= deduction) {
32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	128 context->write_cycle -= deduction;
32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	129 } else {
32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	130 context->write_cycle = CYCLE_NEVER;
32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	131 }
32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	132 if (context->busy_start != CYCLE_NEVER && context->busy_start >= deduction) {
32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	133 context->busy_start -= deduction;
32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	134 } else {
32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	135 context->busy_start = CYCLE_NEVER;
32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	136 }
1904 8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	137 if (context->last_status_cycle != CYCLE_NEVER && context->last_status_cycle >= deduction) {
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	138 context->last_status_cycle -= deduction;
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	139 } else {
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	140 context->last_status = 0;
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	141 context->last_status_cycle = CYCLE_NEVER;
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	142 }
1902 32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	143 }
32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	144
859 46bb673eed4e Load config file and rom.db from appropriate locations on Android Michael Pavone <pavone@retrodev.com> parents: 853 diff changeset	145 #ifdef __ANDROID__
46bb673eed4e Load config file and rom.db from appropriate locations on Android Michael Pavone <pavone@retrodev.com> parents: 853 diff changeset	146 #define log2(x) (log(x)/log(2))
46bb673eed4e Load config file and rom.db from appropriate locations on Android Michael Pavone <pavone@retrodev.com> parents: 853 diff changeset	147 #endif
46bb673eed4e Load config file and rom.db from appropriate locations on Android Michael Pavone <pavone@retrodev.com> parents: 853 diff changeset	148
1308 1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	149
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	150 #define TIMER_A_MAX 1023
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	151 #define TIMER_B_MAX 255
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	152
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	153 void ym_reset(ym2612_context *context)
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	154 {
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	155 memset(context->part1_regs, 0, sizeof(context->part1_regs));
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	156 memset(context->part2_regs, 0, sizeof(context->part2_regs));
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	157 memset(context->operators, 0, sizeof(context->operators));
1654 4637ab86be8c Preserve WAVE logging FILE * across YM2612 device reset Michael Pavone <pavone@retrodev.com> parents: 1555 diff changeset	158 FILE* savedlogs[NUM_CHANNELS];
4637ab86be8c Preserve WAVE logging FILE * across YM2612 device reset Michael Pavone <pavone@retrodev.com> parents: 1555 diff changeset	159 for (int i = 0; i < NUM_CHANNELS; i++)
4637ab86be8c Preserve WAVE logging FILE * across YM2612 device reset Michael Pavone <pavone@retrodev.com> parents: 1555 diff changeset	160 {
4637ab86be8c Preserve WAVE logging FILE * across YM2612 device reset Michael Pavone <pavone@retrodev.com> parents: 1555 diff changeset	161 savedlogs[i] = context->channels[i].logfile;
4637ab86be8c Preserve WAVE logging FILE * across YM2612 device reset Michael Pavone <pavone@retrodev.com> parents: 1555 diff changeset	162 }
1308 1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	163 memset(context->channels, 0, sizeof(context->channels));
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	164 memset(context->ch3_supp, 0, sizeof(context->ch3_supp));
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	165 context->selected_reg = 0;
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	166 context->csm_keyon = 0;
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	167 context->ch3_mode = 0;
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	168 context->dac_enable = 0;
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	169 context->status = 0;
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	170 context->timer_a_load = 0;
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	171 context->timer_b_load = 0;
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	172 //TODO: Confirm these on hardware
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	173 context->timer_a = TIMER_A_MAX;
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	174 context->timer_b = TIMER_B_MAX;
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	175
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	176 //TODO: Reset LFO state
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	177
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	178 //some games seem to expect that the LR flags start out as 1
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	179 for (int i = 0; i < NUM_CHANNELS; i++) {
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	180 context->channels[i].lr = 0xC0;
1654 4637ab86be8c Preserve WAVE logging FILE * across YM2612 device reset Michael Pavone <pavone@retrodev.com> parents: 1555 diff changeset	181 context->channels[i].logfile = savedlogs[i];
1308 1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	182 }
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	183 context->write_cycle = CYCLE_NEVER;
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	184 for (int i = 0; i < NUM_OPERATORS; i++) {
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	185 context->operators[i].envelope = MAX_ENVELOPE;
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	186 context->operators[i].env_phase = PHASE_RELEASE;
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	187 }
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	188 }
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	189
1555 6ce36c3f250b More audio refactoring in preparation for allowing proper sync to video with dynamic audio rate control Michael Pavone <pavone@retrodev.com> parents: 1551 diff changeset	190 void ym_init(ym2612_context * context, uint32_t master_clock, uint32_t clock_div, uint32_t options)
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	191 {
884 252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	192 static uint8_t registered_finalize;
370 5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	193 dfopen(debug_file, "ym_debug.txt", "w");
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	194 memset(context, 0, sizeof(*context));
380 1c8d74f2ab0b Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run. Mike Pavone <pavone@retrodev.com> parents: 379 diff changeset	195 context->clock_inc = clock_div * 6;
1902 32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	196 context->busy_cycles = BUSY_CYCLES * context->clock_inc;
1555 6ce36c3f250b More audio refactoring in preparation for allowing proper sync to video with dynamic audio rate control Michael Pavone <pavone@retrodev.com> parents: 1551 diff changeset	197 context->audio = render_audio_source(master_clock, context->clock_inc * NUM_OPERATORS, 2);
1904 8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	198 //TODO: pick a randomish high initial value and lower it over time
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	199 context->invalid_status_decay = 225000 * context->clock_inc;
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	200 context->status_address_mask = (options & YM_OPT_3834) ? 0 : 3;
1308 1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	201
369 fc820ab1394b Fix left/right enable default value Mike Pavone <pavone@retrodev.com> parents: 365 diff changeset	202 //some games seem to expect that the LR flags start out as 1
fc820ab1394b Fix left/right enable default value Mike Pavone <pavone@retrodev.com> parents: 365 diff changeset	203 for (int i = 0; i < NUM_CHANNELS; i++) {
407 c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	204 if (options & YM_OPT_WAVE_LOG) {
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	205 char fname[64];
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	206 sprintf(fname, "ym_channel_%d.wav", i);
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	207 FILE * f = context->channels[i].logfile = fopen(fname, "wb");
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	208 if (!f) {
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	209 fprintf(stderr, "Failed to open WAVE log file %s for writing\n", fname);
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	210 continue;
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	211 }
1555 6ce36c3f250b More audio refactoring in preparation for allowing proper sync to video with dynamic audio rate control Michael Pavone <pavone@retrodev.com> parents: 1551 diff changeset	212 if (!wave_init(f, master_clock / (context->clock_inc * NUM_OPERATORS), 16, 1)) {
407 c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	213 fclose(f);
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	214 context->channels[i].logfile = NULL;
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	215 }
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	216 }
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	217 }
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	218 if (options & YM_OPT_WAVE_LOG) {
c3abc4ada43d Add support for logging YM2612 channels to WAVE files Mike Pavone <pavone@retrodev.com> parents: 406 diff changeset	219 log_context = context;
884 252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	220 if (!registered_finalize) {
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	221 atexit(ym_finalize_log);
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	222 registered_finalize = 1;
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	223 }
369 fc820ab1394b Fix left/right enable default value Mike Pavone <pavone@retrodev.com> parents: 365 diff changeset	224 }
359 cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	225 if (!did_tbl_init) {
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	226 //populate sine table
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	227 for (int32_t i = 0; i < 512; i++) {
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	228 double sine = sin( ((double)(i2+1) / SINE_TABLE_SIZE) M_PI_2 );
448 e85a107e6ec0 Fix handling of key on in YM2612 core Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	229
359 cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	230 //table stores 4.8 fixed pointed representation of the base 2 log
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	231 sine_table[i] = round_fixed_point(-log2(sine), 8);
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	232 }
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	233 //populate power table
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	234 for (int32_t i = 0; i < POW_TABLE_SIZE; i++) {
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	235 double linear = pow(2, -((double)((i & 0xFF)+1) / 256.0));
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	236 int32_t tmp = round_fixed_point(linear, 11);
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	237 int32_t shift = (i >> 8) - 2;
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	238 if (shift < 0) {
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	239 tmp <<= 0-shift;
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	240 } else {
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	241 tmp >>= shift;
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	242 }
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	243 pow_table[i] = tmp;
cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	244 }
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	245 //populate envelope generator rate table, from small base table
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	246 for (int rate = 0; rate < 64; rate++) {
370 5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	247 for (int cycle = 0; cycle < 8; cycle++) {
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	248 uint16_t value;
370 5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	249 if (rate < 2) {
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	250 value = 0;
365 3ba3b6656fff Actually save the shifted phase inc after applying the block shift Mike Pavone <pavone@retrodev.com> parents: 364 diff changeset	251 } else if (rate >= 60) {
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	252 value = 8;
365 3ba3b6656fff Actually save the shifted phase inc after applying the block shift Mike Pavone <pavone@retrodev.com> parents: 364 diff changeset	253 } else if (rate < 8) {
370 5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	254 value = rate_table_base[((rate & 6) == 6 ? 16 : 0) + cycle];
365 3ba3b6656fff Actually save the shifted phase inc after applying the block shift Mike Pavone <pavone@retrodev.com> parents: 364 diff changeset	255 } else if (rate < 48) {
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	256 value = rate_table_base[(rate & 0x3) * 8 + cycle];
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	257 } else {
370 5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	258 value = rate_table_base[32 + (rate & 0x3) * 8 + cycle] << ((rate - 48) >> 2);
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	259 }
365 3ba3b6656fff Actually save the shifted phase inc after applying the block shift Mike Pavone <pavone@retrodev.com> parents: 364 diff changeset	260 rate_table[rate * 8 + cycle] = value;
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	261 }
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	262 }
411 baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	263 //populate LFO PM table from small base table
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	264 //seems like there must be a better way to derive this
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	265 for (int freq = 0; freq < 128; freq++) {
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	266 for (int pms = 0; pms < 8; pms++) {
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	267 for (int step = 0; step < 32; step++) {
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	268 int16_t value = 0;
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	269 for (int bit = 0x40, shift = 0; bit > 0; bit >>= 1, shift++) {
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	270 if (freq & bit) {
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	271 value += lfo_pm_base[pms][(step & 0x8) ? 7-step & 7 : step & 7] >> shift;
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	272 }
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	273 }
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	274 if (step & 0x10) {
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	275 value = -value;
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	276 }
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	277 lfo_pm_table[freq * 256 + pms * 32 + step] = value;
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	278 }
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	279 }
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	280 }
359 cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	281 }
1308 1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon Michael Pavone <pavone@retrodev.com> parents: 1301 diff changeset	282 ym_reset(context);
1798 5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612 Michael Pavone <pavone@retrodev.com> parents: 1656 diff changeset	283 ym_enable_zero_offset(context, 1);
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	284 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	285
884 252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	286 void ym_free(ym2612_context *context)
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	287 {
1551 ce1f93be0104 Small cleanup to audio interface between emulation code and renderer backend Michael Pavone <pavone@retrodev.com> parents: 1450 diff changeset	288 render_free_source(context->audio);
884 252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	289 if (context == log_context) {
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	290 ym_finalize_log();
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	291 }
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	292 free(context);
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	293 }
252dfd29831d Selecting a second game from the menu now works Michael Pavone <pavone@retrodev.com> parents: 859 diff changeset	294
1798 5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612 Michael Pavone <pavone@retrodev.com> parents: 1656 diff changeset	295 void ym_enable_zero_offset(ym2612_context *context, uint8_t enabled)
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612 Michael Pavone <pavone@retrodev.com> parents: 1656 diff changeset	296 {
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612 Michael Pavone <pavone@retrodev.com> parents: 1656 diff changeset	297 if (enabled) {
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612 Michael Pavone <pavone@retrodev.com> parents: 1656 diff changeset	298 context->zero_offset = 0x70;
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612 Michael Pavone <pavone@retrodev.com> parents: 1656 diff changeset	299 context->volume_mult = 79;
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612 Michael Pavone <pavone@retrodev.com> parents: 1656 diff changeset	300 context->volume_div = 120;
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612 Michael Pavone <pavone@retrodev.com> parents: 1656 diff changeset	301 } else {
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612 Michael Pavone <pavone@retrodev.com> parents: 1656 diff changeset	302 context->zero_offset = 0;
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612 Michael Pavone <pavone@retrodev.com> parents: 1656 diff changeset	303 context->volume_mult = 2;
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612 Michael Pavone <pavone@retrodev.com> parents: 1656 diff changeset	304 context->volume_div = 3;
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612 Michael Pavone <pavone@retrodev.com> parents: 1656 diff changeset	305 }
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612 Michael Pavone <pavone@retrodev.com> parents: 1656 diff changeset	306 }
381 7815ebbbd705 Fix modulation shift value Mike Pavone <pavone@retrodev.com> parents: 380 diff changeset	307 #define YM_MOD_SHIFT 1
370 5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	308
1300 4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	309 #define CSM_MODE 0x80
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	310
1301 babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	311 #define SSG_ENABLE 8
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	312 #define SSG_INVERT 4
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	313 #define SSG_ALTERNATE 2
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	314 #define SSG_HOLD 1
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	315
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	316 #define SSG_CENTER 0x800
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	317
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	318 static void start_envelope(ym_operator op, ym_channel channel)
1300 4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	319 {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	320 //Deal with "infinite" attack rates
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	321 uint8_t rate = op->rates[PHASE_ATTACK];
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	322 if (rate) {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	323 uint8_t ks = channel->keycode >> op->key_scaling;;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	324 rate = rate*2 + ks;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	325 }
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	326 if (rate >= 62) {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	327 op->env_phase = PHASE_DECAY;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	328 op->envelope = 0;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	329 } else {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	330 op->env_phase = PHASE_ATTACK;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	331 }
1301 babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	332 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	333
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	334 static void keyon(ym_operator op, ym_channel channel)
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	335 {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	336 start_envelope(op, channel);
1300 4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	337 op->phase_counter = 0;
1301 babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	338 op->inverted = op->ssg & SSG_INVERT;
1300 4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	339 }
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	340
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	341 static const uint8_t keyon_bits[] = {0x10, 0x40, 0x20, 0x80};
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	342
1301 babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	343 static void keyoff(ym_operator *op)
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	344 {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	345 op->env_phase = PHASE_RELEASE;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	346 if (op->inverted) {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	347 //Nemesis says the inversion state doesn't change here, but I don't see how that is observable either way
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	348 op->inverted = 0;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	349 op->envelope = (SSG_CENTER - op->envelope) & MAX_ENVELOPE;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	350 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	351 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	352
1300 4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	353 static void csm_keyoff(ym2612_context *context)
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	354 {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	355 context->csm_keyon = 0;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	356 uint8_t changes = 0xF0 ^ context->channels[2].keyon;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	357 for (uint8_t op = 24, bit = 0; op < 34; op++, bit++)
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	358 {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	359 if (changes & keyon_bits[bit]) {
1301 babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	360 keyoff(context->operators + op);
1300 4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	361 }
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	362 }
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	363 }
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	364
1879 43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	365 void ym_run_timers(ym2612_context *context)
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	366 {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	367 if (context->timer_control & BIT_TIMERA_ENABLE) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	368 if (context->timer_a != TIMER_A_MAX) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	369 context->timer_a++;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	370 if (context->csm_keyon) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	371 csm_keyoff(context);
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	372 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	373 } else {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	374 if (context->timer_control & BIT_TIMERA_LOAD) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	375 context->timer_control &= ~BIT_TIMERA_LOAD;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	376 } else if (context->timer_control & BIT_TIMERA_OVEREN) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	377 context->status \|= BIT_STATUS_TIMERA;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	378 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	379 context->timer_a = context->timer_a_load;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	380 if (!context->csm_keyon && context->ch3_mode == CSM_MODE) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	381 context->csm_keyon = 0xF0;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	382 uint8_t changes = 0xF0 ^ context->channels[2].keyon;;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	383 for (uint8_t op = 24, bit = 0; op < 34; op++, bit++)
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	384 {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	385 if (changes & keyon_bits[bit]) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	386 keyon(context->operators + op, context->channels + 2);
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	387 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	388 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	389 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	390 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	391 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	392 if (!context->sub_timer_b) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	393 if (context->timer_control & BIT_TIMERB_ENABLE) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	394 if (context->timer_b != TIMER_B_MAX) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	395 context->timer_b++;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	396 } else {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	397 if (context->timer_control & BIT_TIMERB_LOAD) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	398 context->timer_control &= ~BIT_TIMERB_LOAD;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	399 } else if (context->timer_control & BIT_TIMERB_OVEREN) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	400 context->status \|= BIT_STATUS_TIMERB;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	401 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	402 context->timer_b = context->timer_b_load;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	403 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	404 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	405 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	406 context->sub_timer_b += 0x10;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	407 //Update LFO
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	408 if (context->lfo_enable) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	409 if (context->lfo_counter) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	410 context->lfo_counter--;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	411 } else {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	412 context->lfo_counter = lfo_timer_values[context->lfo_freq];
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	413 context->lfo_am_step += 2;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	414 context->lfo_am_step &= 0xFE;
1880 e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	415 uint8_t old_pm_step = context->lfo_pm_step;
1879 43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	416 context->lfo_pm_step = context->lfo_am_step / 8;
1880 e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	417 if (context->lfo_pm_step != old_pm_step) {
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	418 for (int chan = 0; chan < NUM_CHANNELS; chan++)
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	419 {
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	420 if (context->channels[chan].pms) {
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	421 for (int op = chan * 4; op < (chan + 1) * 4; op++)
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	422 {
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	423 context->operators[op].phase_inc = ym_calc_phase_inc(context, context->operators + op, op);
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	424 }
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	425 }
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	426 }
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	427 }
1879 43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	428 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	429 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	430 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	431
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	432 void ym_run_envelope(ym2612_context context, ym_channel channel, ym_operator *operator)
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	433 {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	434 uint32_t env_cyc = context->env_counter;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	435 uint8_t rate;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	436 if (operator->env_phase == PHASE_DECAY && operator->envelope >= operator->sustain_level) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	437 //operator->envelope = operator->sustain_level;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	438 operator->env_phase = PHASE_SUSTAIN;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	439 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	440 rate = operator->rates[operator->env_phase];
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	441 if (rate) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	442 uint8_t ks = channel->keycode >> operator->key_scaling;;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	443 rate = rate*2 + ks;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	444 if (rate > 63) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	445 rate = 63;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	446 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	447 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	448 uint32_t cycle_shift = rate < 0x30 ? ((0x2F - rate) >> 2) : 0;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	449 if (!(env_cyc & ((1 << cycle_shift) - 1))) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	450 uint32_t update_cycle = env_cyc >> cycle_shift & 0x7;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	451 uint16_t envelope_inc = rate_table[rate * 8 + update_cycle];
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	452 if (operator->env_phase == PHASE_ATTACK) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	453 //this can probably be optimized to a single shift rather than a multiply + shift
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	454 uint16_t old_env = operator->envelope;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	455 operator->envelope += ((~operator->envelope * envelope_inc) >> 4) & 0xFFFFFFFC;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	456 if (operator->envelope > old_env) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	457 //Handle overflow
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	458 operator->envelope = 0;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	459 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	460 if (!operator->envelope) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	461 operator->env_phase = PHASE_DECAY;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	462 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	463 } else {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	464 if (operator->ssg) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	465 if (operator->envelope < SSG_CENTER) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	466 envelope_inc *= 4;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	467 } else {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	468 envelope_inc = 0;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	469 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	470 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	471 //envelope value is 10-bits, but it will be used as a 4.8 value
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	472 operator->envelope += envelope_inc << 2;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	473 //clamp to max attenuation value
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	474 if (
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	475 operator->envelope > MAX_ENVELOPE
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	476 \|\| (operator->env_phase == PHASE_RELEASE && operator->envelope >= SSG_CENTER)
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	477 ) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	478 operator->envelope = MAX_ENVELOPE;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	479 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	480 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	481 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	482 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	483
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	484 void ym_run_phase(ym2612_context *context, uint32_t channel, uint32_t op)
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	485 {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	486 if (channel != 5 \|\| !context->dac_enable) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	487 //printf("updating operator %d of channel %d\n", op, channel);
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	488 ym_operator * operator = context->operators + op;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	489 ym_channel * chan = context->channels + channel;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	490 uint16_t phase = operator->phase_counter >> 10 & 0x3FF;
1880 e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	491 operator->phase_counter += operator->phase_inc;//ym_calc_phase_inc(context, operator, op);
1879 43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	492 int16_t mod = 0;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	493 if (op & 3) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	494 if (operator->mod_src[0]) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	495 mod = *operator->mod_src[0];
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	496 if (operator->mod_src[1]) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	497 mod += *operator->mod_src[1];
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	498 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	499 mod >>= YM_MOD_SHIFT;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	500 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	501 } else {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	502 if (chan->feedback) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	503 mod = (chan->op1_old + operator->output) >> (10-chan->feedback);
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	504 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	505 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	506 uint16_t env = operator->envelope;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	507 if (operator->ssg) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	508 if (env >= SSG_CENTER) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	509 if (operator->ssg & SSG_ALTERNATE) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	510 if (operator->env_phase != PHASE_RELEASE && (
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	511 !(operator->ssg & SSG_HOLD) \|\| ((operator->ssg ^ operator->inverted) & SSG_INVERT) == 0
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	512 )) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	513 operator->inverted ^= SSG_INVERT;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	514 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	515 } else if (!(operator->ssg & SSG_HOLD)) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	516 phase = operator->phase_counter = 0;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	517 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	518 if (
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	519 (operator->env_phase == PHASE_DECAY \|\| operator->env_phase == PHASE_SUSTAIN)
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	520 && !(operator->ssg & SSG_HOLD)
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	521 ) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	522 start_envelope(operator, chan);
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	523 env = operator->envelope;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	524 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	525 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	526 if (operator->inverted) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	527 env = (SSG_CENTER - env) & MAX_ENVELOPE;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	528 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	529 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	530 env += operator->total_level;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	531 if (operator->am) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	532 uint16_t base_am = (context->lfo_am_step & 0x80 ? context->lfo_am_step : ~context->lfo_am_step) & 0x7E;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	533 if (ams_shift[chan->ams] >= 0) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	534 env += (base_am >> ams_shift[chan->ams]) & MAX_ENVELOPE;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	535 } else {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	536 env += base_am << (-ams_shift[chan->ams]);
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	537 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	538 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	539 if (env > MAX_ENVELOPE) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	540 env = MAX_ENVELOPE;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	541 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	542 if (first_key_on) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	543 dfprintf(debug_file, "op %d, base phase: %d, mod: %d, sine: %d, out: %d\n", op, phase, mod, sine_table[(phase+mod) & 0x1FF], pow_table[sine_table[phase & 0x1FF] + env]);
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	544 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	545 //if ((channel != 0 && channel != 4) \|\| chan->algorithm != 5) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	546 phase += mod;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	547 //}
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	548
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	549 int16_t output = pow_table[sine_table[phase & 0x1FF] + env];
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	550 if (phase & 0x200) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	551 output = -output;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	552 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	553 if (op % 4 == 0) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	554 chan->op1_old = operator->output;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	555 } else if (op % 4 == 2) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	556 chan->op2_old = operator->output;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	557 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	558 operator->output = output;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	559 //Update the channel output if we've updated all operators
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	560 if (op % 4 == 3) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	561 if (chan->algorithm < 4) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	562 chan->output = operator->output;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	563 } else if(chan->algorithm == 4) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	564 chan->output = operator->output + context->operators[channel * 4 + 2].output;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	565 } else {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	566 output = 0;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	567 for (uint32_t op = ((chan->algorithm == 7) ? 0 : 1) + channel4; op < (channel+1)4; op++) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	568 output += context->operators[op].output;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	569 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	570 chan->output = output;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	571 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	572 if (first_key_on) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	573 int16_t value = context->channels[channel].output & 0x3FE0;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	574 if (value & 0x2000) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	575 value \|= 0xC000;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	576 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	577 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	578 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	579 //puts("operator update done");
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	580 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	581 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	582
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	583 void ym_output_sample(ym2612_context *context)
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	584 {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	585 int16_t left = 0, right = 0;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	586 for (int i = 0; i < NUM_CHANNELS; i++) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	587 int16_t value = context->channels[i].output;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	588 if (value > 0x1FE0) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	589 value = 0x1FE0;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	590 } else if (value < -0x1FF0) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	591 value = -0x1FF0;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	592 } else {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	593 value &= 0x3FE0;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	594 if (value & 0x2000) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	595 value \|= 0xC000;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	596 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	597 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	598 if (value >= 0) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	599 value += context->zero_offset;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	600 } else {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	601 value -= context->zero_offset;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	602 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	603 if (context->channels[i].logfile) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	604 fwrite(&value, sizeof(value), 1, context->channels[i].logfile);
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	605 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	606 if (context->channels[i].lr & 0x80) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	607 left += (value * context->volume_mult) / context->volume_div;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	608 } else if (context->zero_offset) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	609 if (value >= 0) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	610 left += (context->zero_offset * context->volume_mult) / context->volume_div;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	611 } else {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	612 left -= (context->zero_offset * context->volume_mult) / context->volume_div;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	613 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	614 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	615 if (context->channels[i].lr & 0x40) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	616 right += (value * context->volume_mult) / context->volume_div;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	617 } else if (context->zero_offset) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	618 if (value >= 0) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	619 right += (context->zero_offset * context->volume_mult) / context->volume_div;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	620 } else {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	621 right -= (context->zero_offset * context->volume_mult) / context->volume_div;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	622 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	623 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	624 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	625 render_put_stereo_sample(context->audio, left, right);
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	626 }
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	627
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	628 void ym_run(ym2612_context * context, uint32_t to_cycle)
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	629 {
1879 43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	630 if (context->current_cycle >= to_cycle) {
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	631 return;
43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	632 }
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	633 //printf("Running YM2612 from cycle %d to cycle %d\n", context->current_cycle, to_cycle);
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	634 //TODO: Fix channel update order OR remap channels in register write
380 1c8d74f2ab0b Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run. Mike Pavone <pavone@retrodev.com> parents: 379 diff changeset	635 for (; context->current_cycle < to_cycle; context->current_cycle += context->clock_inc) {
359 cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	636 //Update timers at beginning of 144 cycle period
403 f0a3f86595ae Fix YM2612 timers Mike Pavone <pavone@retrodev.com> parents: 396 diff changeset	637 if (!context->current_op) {
1879 43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	638 ym_run_timers(context);
411 baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	639 }
359 cc39629e8d06 YM2612 WIP snapshot before register refactor Mike Pavone <pavone@retrodev.com> parents: 288 diff changeset	640 //Update Envelope Generator
364 62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request Mike Pavone <pavone@retrodev.com> parents: 362 diff changeset	641 if (!(context->current_op % 3)) {
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request Mike Pavone <pavone@retrodev.com> parents: 362 diff changeset	642 uint32_t op = context->current_env_op;
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	643 ym_operator * operator = context->operators + op;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	644 ym_channel * channel = context->channels + op/4;
1879 43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	645 ym_run_envelope(context, channel, operator);
364 62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request Mike Pavone <pavone@retrodev.com> parents: 362 diff changeset	646 context->current_env_op++;
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request Mike Pavone <pavone@retrodev.com> parents: 362 diff changeset	647 if (context->current_env_op == NUM_OPERATORS) {
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request Mike Pavone <pavone@retrodev.com> parents: 362 diff changeset	648 context->current_env_op = 0;
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request Mike Pavone <pavone@retrodev.com> parents: 362 diff changeset	649 context->env_counter++;
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	650 }
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	651 }
448 e85a107e6ec0 Fix handling of key on in YM2612 core Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	652
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	653 //Update Phase Generator
1879 43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	654 ym_run_phase(context, context->current_op / 4, context->current_op);
364 62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request Mike Pavone <pavone@retrodev.com> parents: 362 diff changeset	655 context->current_op++;
396 09328dbe6700 Fix output of algorithm 4 and make some other minor YM2612 core improvements Mike Pavone <pavone@retrodev.com> parents: 386 diff changeset	656 if (context->current_op == NUM_OPERATORS) {
09328dbe6700 Fix output of algorithm 4 and make some other minor YM2612 core improvements Mike Pavone <pavone@retrodev.com> parents: 386 diff changeset	657 context->current_op = 0;
1879 43a6cee4fd00 Split ym_run into a few different functions to enhance clarity Michael Pavone <pavone@retrodev.com> parents: 1808 diff changeset	658 ym_output_sample(context);
364 62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request Mike Pavone <pavone@retrodev.com> parents: 362 diff changeset	659 }
965 5257e85364ed Implemented linear resampling and low pass filter for the YM2612 Michael Pavone <pavone@retrodev.com> parents: 936 diff changeset	660
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	661 }
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	662 //printf("Done running YM2612 at cycle %d\n", context->current_cycle, to_cycle);
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	663 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	664
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	665 void ym_address_write_part1(ym2612_context * context, uint8_t address)
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	666 {
364 62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request Mike Pavone <pavone@retrodev.com> parents: 362 diff changeset	667 //printf("address_write_part1: %X\n", address);
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	668 context->selected_reg = address;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	669 context->selected_part = 0;
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	670 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	671
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	672 void ym_address_write_part2(ym2612_context * context, uint8_t address)
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	673 {
364 62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request Mike Pavone <pavone@retrodev.com> parents: 362 diff changeset	674 //printf("address_write_part2: %X\n", address);
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	675 context->selected_reg = address;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	676 context->selected_part = 1;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	677 }
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	678
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1002 diff changeset	679 static uint8_t fnum_to_keycode[] = {
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	680 //F11 = 0
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	681 0,0,0,0,0,0,0,1,
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	682 //F11 = 1
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	683 2,3,3,3,3,3,3,3
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	684 };
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	685
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	686 //table courtesy of Nemesis
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1002 diff changeset	687 static uint32_t detune_table[][4] = {
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	688 {0, 0, 1, 2}, //0 (0x00)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	689 {0, 0, 1, 2}, //1 (0x01)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	690 {0, 0, 1, 2}, //2 (0x02)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	691 {0, 0, 1, 2}, //3 (0x03)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	692 {0, 1, 2, 2}, //4 (0x04)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	693 {0, 1, 2, 3}, //5 (0x05)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	694 {0, 1, 2, 3}, //6 (0x06)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	695 {0, 1, 2, 3}, //7 (0x07)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	696 {0, 1, 2, 4}, //8 (0x08)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	697 {0, 1, 3, 4}, //9 (0x09)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	698 {0, 1, 3, 4}, //10 (0x0A)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	699 {0, 1, 3, 5}, //11 (0x0B)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	700 {0, 2, 4, 5}, //12 (0x0C)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	701 {0, 2, 4, 6}, //13 (0x0D)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	702 {0, 2, 4, 6}, //14 (0x0E)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	703 {0, 2, 5, 7}, //15 (0x0F)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	704 {0, 2, 5, 8}, //16 (0x10)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	705 {0, 3, 6, 8}, //17 (0x11)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	706 {0, 3, 6, 9}, //18 (0x12)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	707 {0, 3, 7,10}, //19 (0x13)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	708 {0, 4, 8,11}, //20 (0x14)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	709 {0, 4, 8,12}, //21 (0x15)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	710 {0, 4, 9,13}, //22 (0x16)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	711 {0, 5,10,14}, //23 (0x17)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	712 {0, 5,11,16}, //24 (0x18)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	713 {0, 6,12,17}, //25 (0x19)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	714 {0, 6,13,19}, //26 (0x1A)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	715 {0, 7,14,20}, //27 (0x1B)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	716 {0, 8,16,22}, //28 (0x1C)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	717 {0, 8,16,22}, //29 (0x1D)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	718 {0, 8,16,22}, //30 (0x1E)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	719 {0, 8,16,22}
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	720 }; //31 (0x1F)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	721
1102 c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code Michael Pavone <pavone@retrodev.com> parents: 1002 diff changeset	722 static uint32_t ym_calc_phase_inc(ym2612_context * context, ym_operator * operator, uint32_t op)
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	723 {
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	724 uint32_t chan_num = op / 4;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	725 //printf("ym_update_phase_inc \| channel: %d, op: %d\n", chan_num, op);
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	726 //base frequency
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	727 ym_channel * channel = context->channels + chan_num;
383 72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	728 uint32_t inc, detune;
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	729 if (chan_num == 2 && context->ch3_mode && (op < (2*4 + 3))) {
738 8972378e314f Fix register to operator mapping for channel 3 special mode Michael Pavone <pavone@retrodev.com> parents: 650 diff changeset	730 //supplemental fnum registers are in a different order than normal slot paramters
936 f1a8124ad881 Fix register to operator mapping for channel 3 special mode and actually get it right this time Michael Pavone <pavone@retrodev.com> parents: 935 diff changeset	731 int index = op-2*4;
f1a8124ad881 Fix register to operator mapping for channel 3 special mode and actually get it right this time Michael Pavone <pavone@retrodev.com> parents: 935 diff changeset	732 if (index < 2) {
f1a8124ad881 Fix register to operator mapping for channel 3 special mode and actually get it right this time Michael Pavone <pavone@retrodev.com> parents: 935 diff changeset	733 index ^= 1;
f1a8124ad881 Fix register to operator mapping for channel 3 special mode and actually get it right this time Michael Pavone <pavone@retrodev.com> parents: 935 diff changeset	734 }
738 8972378e314f Fix register to operator mapping for channel 3 special mode Michael Pavone <pavone@retrodev.com> parents: 650 diff changeset	735 inc = context->ch3_supp[index].fnum;
935 01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation Michael Pavone <pavone@retrodev.com> parents: 930 diff changeset	736 if (channel->pms) {
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation Michael Pavone <pavone@retrodev.com> parents: 930 diff changeset	737 inc = inc * 2 + lfo_pm_table[(inc & 0x7F0) * 16 + channel->pms + context->lfo_pm_step];
1802 1d1198f16279 Fix a couple of minor cases of extra precision in LFO implementation Michael Pavone <pavone@retrodev.com> parents: 1798 diff changeset	738 inc &= 0xFFF;
935 01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation Michael Pavone <pavone@retrodev.com> parents: 930 diff changeset	739 }
738 8972378e314f Fix register to operator mapping for channel 3 special mode Michael Pavone <pavone@retrodev.com> parents: 650 diff changeset	740 if (!context->ch3_supp[index].block) {
383 72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	741 inc >>= 1;
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	742 } else {
738 8972378e314f Fix register to operator mapping for channel 3 special mode Michael Pavone <pavone@retrodev.com> parents: 650 diff changeset	743 inc <<= (context->ch3_supp[index].block-1);
383 72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	744 }
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	745 //detune
738 8972378e314f Fix register to operator mapping for channel 3 special mode Michael Pavone <pavone@retrodev.com> parents: 650 diff changeset	746 detune = detune_table[context->ch3_supp[index].keycode][operator->detune & 0x3];
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	747 } else {
383 72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	748 inc = channel->fnum;
935 01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation Michael Pavone <pavone@retrodev.com> parents: 930 diff changeset	749 if (channel->pms) {
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation Michael Pavone <pavone@retrodev.com> parents: 930 diff changeset	750 inc = inc * 2 + lfo_pm_table[(inc & 0x7F0) * 16 + channel->pms + context->lfo_pm_step];
1808 ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	751 inc &= 0xFFF;
935 01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation Michael Pavone <pavone@retrodev.com> parents: 930 diff changeset	752 }
383 72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	753 if (!channel->block) {
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	754 inc >>= 1;
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	755 } else {
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	756 inc <<= (channel->block-1);
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	757 }
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	758 //detune
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	759 detune = detune_table[channel->keycode][operator->detune & 0x3];
448 e85a107e6ec0 Fix handling of key on in YM2612 core Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	760 }
935 01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation Michael Pavone <pavone@retrodev.com> parents: 930 diff changeset	761 if (channel->pms) {
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation Michael Pavone <pavone@retrodev.com> parents: 930 diff changeset	762 inc >>= 1;
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation Michael Pavone <pavone@retrodev.com> parents: 930 diff changeset	763 }
739 2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	764 if (operator->detune & 0x4) {
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	765 inc -= detune;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	766 //this can underflow, mask to 17-bit result
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	767 inc &= 0x1FFFF;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	768 } else {
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	769 inc += detune;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	770 }
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	771 //multiple
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	772 if (operator->multiple) {
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	773 inc *= operator->multiple;
739 2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	774 inc &= 0xFFFFF;
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	775 } else {
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	776 //0.5
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	777 inc >>= 1;
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	778 }
365 3ba3b6656fff Actually save the shifted phase inc after applying the block shift Mike Pavone <pavone@retrodev.com> parents: 364 diff changeset	779 //printf("phase_inc for operator %d: %d, block: %d, fnum: %d, detune: %d, multiple: %d\n", op, inc, channel->block, channel->fnum, detune, operator->multiple);
935 01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation Michael Pavone <pavone@retrodev.com> parents: 930 diff changeset	780 return inc;
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	781 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	782
1909 508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	783 void ym_vgm_log(ym2612_context context, uint32_t master_clock, vgm_writer vgm)
508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	784 {
508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	785 vgm_ym2612_init(vgm, 6 * master_clock / context->clock_inc);
508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	786 context->vgm = vgm;
508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	787 for (uint8_t reg = YM_PART1_START; reg < YM_REG_END; reg++) {
1912 00fb99805445 Skip invalid registers when dumping initial YM2612 state to VGM log Michael Pavone <pavone@retrodev.com> parents: 1909 diff changeset	788 if ((reg >= REG_DETUNE_MULT && (reg & 3) == 3) \|\| (reg >= 0x2D && reg < REG_DETUNE_MULT) \|\| reg == 0x23 \|\| reg == 0x29) {
00fb99805445 Skip invalid registers when dumping initial YM2612 state to VGM log Michael Pavone <pavone@retrodev.com> parents: 1909 diff changeset	789 //skip invalid registers
00fb99805445 Skip invalid registers when dumping initial YM2612 state to VGM log Michael Pavone <pavone@retrodev.com> parents: 1909 diff changeset	790 continue;
00fb99805445 Skip invalid registers when dumping initial YM2612 state to VGM log Michael Pavone <pavone@retrodev.com> parents: 1909 diff changeset	791 }
1909 508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	792 vgm_ym2612_part1_write(context->vgm, context->current_cycle, reg, context->part1_regs[reg - YM_PART1_START]);
508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	793 }
508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	794
508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	795 for (uint8_t reg = YM_PART2_START; reg < YM_REG_END; reg++) {
1912 00fb99805445 Skip invalid registers when dumping initial YM2612 state to VGM log Michael Pavone <pavone@retrodev.com> parents: 1909 diff changeset	796 if ((reg & 3) == 3 \|\| (reg >= REG_FNUM_LOW_CH3 && reg < REG_ALG_FEEDBACK)) {
00fb99805445 Skip invalid registers when dumping initial YM2612 state to VGM log Michael Pavone <pavone@retrodev.com> parents: 1909 diff changeset	797 //skip invalid registers
00fb99805445 Skip invalid registers when dumping initial YM2612 state to VGM log Michael Pavone <pavone@retrodev.com> parents: 1909 diff changeset	798 continue;
00fb99805445 Skip invalid registers when dumping initial YM2612 state to VGM log Michael Pavone <pavone@retrodev.com> parents: 1909 diff changeset	799 }
1909 508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	800 vgm_ym2612_part2_write(context->vgm, context->current_cycle, reg, context->part2_regs[reg - YM_PART2_START]);
508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	801 }
508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	802 }
508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	803
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	804 void ym_data_write(ym2612_context * context, uint8_t value)
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	805 {
1902 32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	806 context->write_cycle = context->current_cycle;
32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	807 context->busy_start = context->current_cycle + context->clock_inc;
32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	808
451 b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness Mike Pavone <pavone@retrodev.com> parents: 448 diff changeset	809 if (context->selected_reg >= YM_REG_END) {
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	810 return;
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	811 }
451 b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness Mike Pavone <pavone@retrodev.com> parents: 448 diff changeset	812 if (context->selected_part) {
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness Mike Pavone <pavone@retrodev.com> parents: 448 diff changeset	813 if (context->selected_reg < YM_PART2_START) {
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness Mike Pavone <pavone@retrodev.com> parents: 448 diff changeset	814 return;
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness Mike Pavone <pavone@retrodev.com> parents: 448 diff changeset	815 }
1909 508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	816 if (context->vgm) {
508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	817 vgm_ym2612_part2_write(context->vgm, context->current_cycle, context->selected_reg, value);
508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	818 }
451 b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness Mike Pavone <pavone@retrodev.com> parents: 448 diff changeset	819 context->part2_regs[context->selected_reg - YM_PART2_START] = value;
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness Mike Pavone <pavone@retrodev.com> parents: 448 diff changeset	820 } else {
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness Mike Pavone <pavone@retrodev.com> parents: 448 diff changeset	821 if (context->selected_reg < YM_PART1_START) {
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness Mike Pavone <pavone@retrodev.com> parents: 448 diff changeset	822 return;
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness Mike Pavone <pavone@retrodev.com> parents: 448 diff changeset	823 }
1909 508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	824 if (context->vgm) {
508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	825 vgm_ym2612_part1_write(context->vgm, context->current_cycle, context->selected_reg, value);
508522f08e4d Initial stab at VGM logging support Michael Pavone <pavone@retrodev.com> parents: 1904 diff changeset	826 }
451 b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness Mike Pavone <pavone@retrodev.com> parents: 448 diff changeset	827 context->part1_regs[context->selected_reg - YM_PART1_START] = value;
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness Mike Pavone <pavone@retrodev.com> parents: 448 diff changeset	828 }
1946 c3c62dbf1ceb WIP netplay support Michael Pavone <pavone@retrodev.com> parents: 1912 diff changeset	829 uint8_t buffer[3] = {context->selected_part, context->selected_reg, value};
c3c62dbf1ceb WIP netplay support Michael Pavone <pavone@retrodev.com> parents: 1912 diff changeset	830 event_log(EVENT_YM_REG, context->current_cycle, sizeof(buffer), buffer);
370 5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	831 dfprintf(debug_file, "write of %X to reg %X in part %d\n", value, context->selected_reg, context->selected_part+1);
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	832 if (context->selected_reg < 0x30) {
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	833 //Shared regs
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	834 switch (context->selected_reg)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	835 {
411 baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	836 //TODO: Test reg
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	837 case REG_LFO:
532 666210adf87b Comment out LFO debug printf Mike Pavone <pavone@retrodev.com> parents: 527 diff changeset	838 /*if ((value & 0x8) && !context->lfo_enable) {
411 baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	839 printf("LFO Enabled, Freq: %d\n", value & 0x7);
532 666210adf87b Comment out LFO debug printf Mike Pavone <pavone@retrodev.com> parents: 527 diff changeset	840 }*/
411 baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	841 context->lfo_enable = value & 0x8;
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	842 if (!context->lfo_enable) {
1880 e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	843 uint8_t old_pm_step = context->lfo_pm_step;
411 baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	844 context->lfo_am_step = context->lfo_pm_step = 0;
1880 e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	845 if (old_pm_step) {
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	846 for (int chan = 0; chan < NUM_CHANNELS; chan++)
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	847 {
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	848 if (context->channels[chan].pms) {
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	849 for (int op = chan * 4; op < (chan + 1) * 4; op++)
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	850 {
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	851 context->operators[op].phase_inc = ym_calc_phase_inc(context, context->operators + op, op);
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	852 }
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	853 }
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	854 }
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	855 }
411 baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	856 }
baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	857 context->lfo_freq = value & 0x7;
448 e85a107e6ec0 Fix handling of key on in YM2612 core Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	858
411 baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	859 break;
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	860 case REG_TIMERA_HIGH:
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	861 context->timer_a_load &= 0x3;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	862 context->timer_a_load \|= value << 2;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	863 break;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	864 case REG_TIMERA_LOW:
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	865 context->timer_a_load &= 0xFFFC;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	866 context->timer_a_load \|= value & 0x3;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	867 break;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	868 case REG_TIMERB:
845 3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track. Michael Pavone <pavone@retrodev.com> parents: 740 diff changeset	869 context->timer_b_load = value;
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	870 break;
383 72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	871 case REG_TIME_CTRL: {
403 f0a3f86595ae Fix YM2612 timers Mike Pavone <pavone@retrodev.com> parents: 396 diff changeset	872 if (value & BIT_TIMERA_ENABLE && !(context->timer_control & BIT_TIMERA_ENABLE)) {
845 3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track. Michael Pavone <pavone@retrodev.com> parents: 740 diff changeset	873 context->timer_a = TIMER_A_MAX;
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track. Michael Pavone <pavone@retrodev.com> parents: 740 diff changeset	874 context->timer_control \|= BIT_TIMERA_LOAD;
403 f0a3f86595ae Fix YM2612 timers Mike Pavone <pavone@retrodev.com> parents: 396 diff changeset	875 }
f0a3f86595ae Fix YM2612 timers Mike Pavone <pavone@retrodev.com> parents: 396 diff changeset	876 if (value & BIT_TIMERB_ENABLE && !(context->timer_control & BIT_TIMERB_ENABLE)) {
845 3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track. Michael Pavone <pavone@retrodev.com> parents: 740 diff changeset	877 context->timer_b = TIMER_B_MAX;
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track. Michael Pavone <pavone@retrodev.com> parents: 740 diff changeset	878 context->timer_control \|= BIT_TIMERB_LOAD;
403 f0a3f86595ae Fix YM2612 timers Mike Pavone <pavone@retrodev.com> parents: 396 diff changeset	879 }
845 3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track. Michael Pavone <pavone@retrodev.com> parents: 740 diff changeset	880 context->timer_control &= (BIT_TIMERA_LOAD \| BIT_TIMERB_LOAD);
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track. Michael Pavone <pavone@retrodev.com> parents: 740 diff changeset	881 context->timer_control \|= value & 0xF;
403 f0a3f86595ae Fix YM2612 timers Mike Pavone <pavone@retrodev.com> parents: 396 diff changeset	882 if (value & BIT_TIMERA_RESET) {
f0a3f86595ae Fix YM2612 timers Mike Pavone <pavone@retrodev.com> parents: 396 diff changeset	883 context->status &= ~BIT_STATUS_TIMERA;
f0a3f86595ae Fix YM2612 timers Mike Pavone <pavone@retrodev.com> parents: 396 diff changeset	884 }
f0a3f86595ae Fix YM2612 timers Mike Pavone <pavone@retrodev.com> parents: 396 diff changeset	885 if (value & BIT_TIMERB_RESET) {
f0a3f86595ae Fix YM2612 timers Mike Pavone <pavone@retrodev.com> parents: 396 diff changeset	886 context->status &= ~BIT_STATUS_TIMERB;
f0a3f86595ae Fix YM2612 timers Mike Pavone <pavone@retrodev.com> parents: 396 diff changeset	887 }
1300 4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	888 if (context->ch3_mode == CSM_MODE && (value & 0xC0) != CSM_MODE && context->csm_keyon) {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	889 csm_keyoff(context);
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	890 }
1880 e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	891 uint8_t old_mode = context->ch3_mode;
383 72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	892 context->ch3_mode = value & 0xC0;
1880 e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	893 if (context->ch3_mode != old_mode) {
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	894 for (int op = 2 * 4; op < 3*4; op++)
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	895 {
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	896 context->operators[op].phase_inc = ym_calc_phase_inc(context, context->operators + op, op);
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	897 }
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	898 }
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	899 break;
383 72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	900 }
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	901 case REG_KEY_ONOFF: {
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	902 uint8_t channel = value & 0x7;
386 6e5c4f3ab0e2 Fix channel mapping in key on/off register Mike Pavone <pavone@retrodev.com> parents: 383 diff changeset	903 if (channel != 3 && channel != 7) {
6e5c4f3ab0e2 Fix channel mapping in key on/off register Mike Pavone <pavone@retrodev.com> parents: 383 diff changeset	904 if (channel > 2) {
6e5c4f3ab0e2 Fix channel mapping in key on/off register Mike Pavone <pavone@retrodev.com> parents: 383 diff changeset	905 channel--;
6e5c4f3ab0e2 Fix channel mapping in key on/off register Mike Pavone <pavone@retrodev.com> parents: 383 diff changeset	906 }
1300 4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	907 uint8_t changes = channel == 2
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	908 ? (value \| context->csm_keyon) ^ (context->channels[channel].keyon \| context->csm_keyon)
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	909 : value ^ context->channels[channel].keyon;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	910 context->channels[channel].keyon = value & 0xF0;
851 b10cf2c921ad Fix mapping of key on/off reg bits to operators Michael Pavone <pavone@retrodev.com> parents: 848 diff changeset	911 for (uint8_t op = channel * 4, bit = 0; op < (channel + 1) * 4; op++, bit++) {
1300 4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	912 if (changes & keyon_bits[bit]) {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	913 if (value & keyon_bits[bit]) {
448 e85a107e6ec0 Fix handling of key on in YM2612 core Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	914 first_key_on = 1;
e85a107e6ec0 Fix handling of key on in YM2612 core Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	915 //printf("Key On for operator %d in channel %d\n", op, channel);
1300 4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	916 keyon(context->operators + op, context->channels + channel);
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	917 } else {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though Michael Pavone <pavone@retrodev.com> parents: 1102 diff changeset	918 //printf("Key Off for operator %d in channel %d\n", op, channel);
1301 babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	919 keyoff(context->operators + op);
448 e85a107e6ec0 Fix handling of key on in YM2612 core Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	920 }
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	921 }
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	922 }
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	923 }
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	924 break;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	925 }
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	926 case REG_DAC:
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	927 if (context->dac_enable) {
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	928 context->channels[5].output = (((int16_t)value) - 0x80) << 6;
396 09328dbe6700 Fix output of algorithm 4 and make some other minor YM2612 core improvements Mike Pavone <pavone@retrodev.com> parents: 386 diff changeset	929 //printf("DAC Write %X(%d) @ %d\n", value, context->channels[5].output, context->current_cycle);
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	930 }
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	931 break;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	932 case REG_DAC_ENABLE:
364 62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request Mike Pavone <pavone@retrodev.com> parents: 362 diff changeset	933 //printf("DAC Enable: %X\n", value);
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	934 context->dac_enable = value & 0x80;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	935 break;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	936 }
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	937 } else if (context->selected_reg < 0xA0) {
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	938 //part
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	939 uint8_t op = context->selected_part ? (NUM_OPERATORS/2) : 0;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	940 //channel in part
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	941 if ((context->selected_reg & 0x3) != 0x3) {
370 5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase. Mike Pavone <pavone@retrodev.com> parents: 369 diff changeset	942 op += 4 * (context->selected_reg & 0x3) + ((context->selected_reg & 0xC) / 4);
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	943 //printf("write targets operator %d (%d of channel %d)\n", op, op % 4, op / 4);
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	944 ym_operator * operator = context->operators + op;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	945 switch (context->selected_reg & 0xF0)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	946 {
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	947 case REG_DETUNE_MULT:
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	948 operator->detune = value >> 4 & 0x7;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	949 operator->multiple = value & 0xF;
1880 e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	950 operator->phase_inc = ym_calc_phase_inc(context, operator, op);
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	951 break;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	952 case REG_TOTAL_LEVEL:
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	953 operator->total_level = (value & 0x7F) << 5;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	954 break;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	955 case REG_ATTACK_KS:
376 f6def5cdf1b4 Fix key scaling Mike Pavone <pavone@retrodev.com> parents: 374 diff changeset	956 operator->key_scaling = 3 - (value >> 6);
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	957 operator->rates[PHASE_ATTACK] = value & 0x1F;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	958 break;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	959 case REG_DECAY_AM:
739 2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	960 operator->am = value & 0x80;
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	961 operator->rates[PHASE_DECAY] = value & 0x1F;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	962 break;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	963 case REG_SUSTAIN_RATE:
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	964 operator->rates[PHASE_SUSTAIN] = value & 0x1F;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	965 break;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	966 case REG_S_LVL_R_RATE:
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	967 operator->rates[PHASE_RELEASE] = (value & 0xF) << 1 \| 1;
852 5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator Michael Pavone <pavone@retrodev.com> parents: 851 diff changeset	968 operator->sustain_level = (value & 0xF0) << 3;
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator Michael Pavone <pavone@retrodev.com> parents: 851 diff changeset	969 if (operator->sustain_level == 0x780) {
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator Michael Pavone <pavone@retrodev.com> parents: 851 diff changeset	970 operator->sustain_level = MAX_ENVELOPE;
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator Michael Pavone <pavone@retrodev.com> parents: 851 diff changeset	971 }
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	972 break;
1301 babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	973 case REG_SSG_EG:
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	974 if (!(value & SSG_ENABLE)) {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	975 value = 0;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	976 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	977 if ((value ^ operator->ssg) & SSG_INVERT) {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	978 operator->inverted ^= SSG_INVERT;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	979 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	980 operator->ssg = value;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode Michael Pavone <pavone@retrodev.com> parents: 1300 diff changeset	981 break;
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	982 }
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	983 }
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	984 } else {
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	985 uint8_t channel = context->selected_reg & 0x3;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	986 if (channel != 3) {
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	987 if (context->selected_part) {
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	988 channel += 3;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	989 }
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	990 //printf("write targets channel %d\n", channel);
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	991 switch (context->selected_reg & 0xFC)
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	992 {
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	993 case REG_FNUM_LOW:
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	994 context->channels[channel].block = context->channels[channel].block_fnum_latch >> 3 & 0x7;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	995 context->channels[channel].fnum = (context->channels[channel].block_fnum_latch & 0x7) << 8 \| value;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	996 context->channels[channel].keycode = context->channels[channel].block << 2 \| fnum_to_keycode[context->channels[channel].fnum >> 7];
1880 e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	997 for (int op = channel * 4; op < (channel + 1) * 4; op++)
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	998 {
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	999 context->operators[op].phase_inc = ym_calc_phase_inc(context, context->operators + op, op);
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	1000 }
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	1001 break;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	1002 case REG_BLOCK_FNUM_H:{
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	1003 context->channels[channel].block_fnum_latch = value;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	1004 break;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	1005 }
383 72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	1006 case REG_FNUM_LOW_CH3:
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	1007 if (channel < 3) {
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	1008 context->ch3_supp[channel].block = context->ch3_supp[channel].block_fnum_latch >> 3 & 0x7;
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	1009 context->ch3_supp[channel].fnum = (context->ch3_supp[channel].block_fnum_latch & 0x7) << 8 \| value;
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	1010 context->ch3_supp[channel].keycode = context->ch3_supp[channel].block << 2 \| fnum_to_keycode[context->ch3_supp[channel].fnum >> 7];
1880 e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	1011 if (context->ch3_mode) {
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	1012 int op = 2 * 4 + (channel < 2 ? (channel ^ 1) : channel);
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	1013 context->operators[op].phase_inc = ym_calc_phase_inc(context, context->operators + op, op);
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	1014 }
383 72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	1015 }
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	1016 break;
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	1017 case REG_BLOCK_FN_CH3:
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	1018 if (channel < 3) {
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	1019 context->ch3_supp[channel].block_fnum_latch = value;
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	1020 }
72933100c55c Initial implementation of channel 3 special mode Mike Pavone <pavone@retrodev.com> parents: 382 diff changeset	1021 break;
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	1022 case REG_ALG_FEEDBACK:
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	1023 context->channels[channel].algorithm = value & 0x7;
1656 804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1024 switch (context->channels[channel].algorithm)
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1025 {
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1026 case 0:
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1027 //operator 3 modulated by operator 2
1808 ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1028 //this uses a special op2 result reg on HW, but that reg will have the most recent
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1029 //result from op2 when op3 starts executing
1656 804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1030 context->operators[channel4+1].mod_src[0] = &context->operators[channel4+2].output;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1031 context->operators[channel*4+1].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1032
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1033 //operator 2 modulated by operator 1
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1034 context->operators[channel4+2].mod_src[0] = &context->operators[channel4+0].output;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1035
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1036 //operator 4 modulated by operator 3
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1037 context->operators[channel4+3].mod_src[0] = &context->operators[channel4+1].output;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1038 context->operators[channel*4+3].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1039 break;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1040 case 1:
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1041 //operator 3 modulated by operator 1+2
1808 ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1042 //op1 starts executing before this, but due to pipeline length the most current result is
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1043 //not available and instead the previous result is used
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1044 context->operators[channel*4+1].mod_src[0] = &context->channels[channel].op1_old;
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1045 //this uses a special op2 result reg on HW, but that reg will have the most recent
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1046 //result from op2 when op3 starts executing
1656 804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1047 context->operators[channel4+1].mod_src[1] = &context->operators[channel4+2].output;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1048
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1049 //operator 2 unmodulated
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1050 context->operators[channel*4+2].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1051
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1052 //operator 4 modulated by operator 3
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1053 context->operators[channel4+3].mod_src[0] = &context->operators[channel4+1].output;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1054 context->operators[channel*4+3].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1055 break;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1056 case 2:
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1057 //operator 3 modulated by operator 2
1808 ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1058 //this uses a special op2 result reg on HW, but that reg will have the most recent
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1059 //result from op2 when op3 starts executing
1656 804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1060 context->operators[channel4+1].mod_src[0] = &context->operators[channel4+2].output;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1061 context->operators[channel*4+1].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1062
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1063 //operator 2 unmodulated
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1064 context->operators[channel*4+2].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1065
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1066 //operator 4 modulated by operator 1+3
1808 ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1067 //this uses a special op1 result reg on HW, but that reg will have the most recent
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1068 //result from op1 when op4 starts executing
1656 804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1069 context->operators[channel4+3].mod_src[0] = &context->operators[channel4+0].output;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1070 context->operators[channel4+3].mod_src[1] = &context->operators[channel4+1].output;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1071 break;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1072 case 3:
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1073 //operator 3 unmodulated
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1074 context->operators[channel*4+1].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1075 context->operators[channel*4+1].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1076
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1077 //operator 2 modulated by operator 1
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1078 context->operators[channel4+2].mod_src[0] = &context->operators[channel4+0].output;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1079
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1080 //operator 4 modulated by operator 2+3
1808 ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1081 //op2 starts executing before this, but due to pipeline length the most current result is
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1082 //not available and instead the previous result is used
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1083 context->operators[channel*4+3].mod_src[0] = &context->channels[channel].op2_old;
1656 804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1084 context->operators[channel4+3].mod_src[1] = &context->operators[channel4+1].output;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1085 break;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1086 case 4:
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1087 //operator 3 unmodulated
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1088 context->operators[channel*4+1].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1089 context->operators[channel*4+1].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1090
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1091 //operator 2 modulated by operator 1
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1092 context->operators[channel4+2].mod_src[0] = &context->operators[channel4+0].output;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1093
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1094 //operator 4 modulated by operator 3
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1095 context->operators[channel4+3].mod_src[0] = &context->operators[channel4+1].output;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1096 context->operators[channel*4+3].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1097 break;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1098 case 5:
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1099 //operator 3 modulated by operator 1
1808 ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1100 //op1 starts executing before this, but due to pipeline length the most current result is
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1101 //not available and instead the previous result is used
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1102 context->operators[channel*4+1].mod_src[0] = &context->channels[channel].op1_old;
1656 804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1103 context->operators[channel*4+1].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1104
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1105 //operator 2 modulated by operator 1
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1106 context->operators[channel4+2].mod_src[0] = &context->operators[channel4+0].output;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1107
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1108 //operator 4 modulated by operator 1
1808 ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1109 //this uses a special op1 result reg on HW, but that reg will have the most recent
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length Michael Pavone <pavone@retrodev.com> parents: 1803 diff changeset	1110 //result from op1 when op4 starts executing
1656 804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1111 context->operators[channel4+3].mod_src[0] = &context->operators[channel4+0].output;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1112 context->operators[channel*4+3].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1113 break;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1114 case 6:
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1115 //operator 3 unmodulated
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1116 context->operators[channel*4+1].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1117 context->operators[channel*4+1].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1118
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1119 //operator 2 modulated by operator 1
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1120 context->operators[channel4+2].mod_src[0] = &context->operators[channel4+0].output;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1121
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1122 //operator 4 unmodulated
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1123 context->operators[channel*4+3].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1124 context->operators[channel*4+3].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1125 break;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1126 case 7:
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1127 //everything is an output so no modulation (except for op 1 feedback)
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1128 context->operators[channel*4+1].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1129 context->operators[channel*4+1].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1130
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1131 context->operators[channel*4+2].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1132
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1133 context->operators[channel*4+3].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1134 context->operators[channel*4+3].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1135 break;
804f13c090b4 Optimize YM operator modulation Mike Pavone <pavone@retrodev.com> parents: 1654 diff changeset	1136 }
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	1137 context->channels[channel].feedback = value >> 3 & 0x7;
527 7df7f493b3b6 Fix operator 1 self-feedback Michael Pavone <pavone@retrodev.com> parents: 522 diff changeset	1138 //printf("Algorithm %d, feedback %d for channel %d\n", value & 0x7, value >> 3 & 0x7, channel);
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	1139 break;
1880 e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	1140 case REG_LR_AMS_PMS: {
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	1141 uint8_t old_pms = context->channels[channel].pms;
411 baf4688901f2 Initial stab at LFO phase modulation Mike Pavone <pavone@retrodev.com> parents: 407 diff changeset	1142 context->channels[channel].pms = (value & 0x7) * 32;
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	1143 context->channels[channel].ams = value >> 4 & 0x3;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	1144 context->channels[channel].lr = value & 0xC0;
1880 e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	1145 if (old_pms != context->channels[channel].pms) {
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	1146 for (int op = channel * 4; op < (channel + 1) * 4; op++)
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	1147 {
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	1148 context->operators[op].phase_inc = ym_calc_phase_inc(context, context->operators + op, op);
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	1149 }
e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	1150 }
369 fc820ab1394b Fix left/right enable default value Mike Pavone <pavone@retrodev.com> parents: 365 diff changeset	1151 //printf("Write of %X to LR_AMS_PMS reg for channel %d\n", value, channel);
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	1152 break;
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	1153 }
1880 e77f7a7c79a5 Cache operator phase increment for a small perf improvement Michael Pavone <pavone@retrodev.com> parents: 1879 diff changeset	1154 }
362 b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	1155 }
b7c3facee762 YM2612 WIP update Mike Pavone <pavone@retrodev.com> parents: 359 diff changeset	1156 }
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1157 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1158
1904 8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1159 uint8_t ym_read_status(ym2612_context * context, uint32_t cycle, uint32_t port)
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1160 {
1904 8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1161 uint8_t status;
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1162 port &= context->status_address_mask;
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1163 if (port) {
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1164 if (context->last_status_cycle != CYCLE_NEVER && cycle - context->last_status_cycle > context->invalid_status_decay) {
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1165 context->last_status = 0;
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1166 }
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1167 status = context->last_status;
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1168 } else {
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1169 status = context->status;
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1170 if (cycle >= context->busy_start && cycle < context->busy_start + context->busy_cycles) {
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1171 status \|= 0x80;
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1172 }
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1173 context->last_status = status;
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1174 context->last_status_cycle = cycle;
1902 32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	1175 }
32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	1176 return status;
1904 8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1177
288 a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1178 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1179
739 2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1180 void ym_print_channel_info(ym2612_context *context, int channel)
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1181 {
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1182 ym_channel *chan = context->channels + channel;
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1183 printf("\n*Channel %d*\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1184 "Algorithm: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1185 "Feedback: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1186 "Pan: %s\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1187 "AMS: %d\n"
845 3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track. Michael Pavone <pavone@retrodev.com> parents: 740 diff changeset	1188 "PMS: %d\n",
739 2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1189 channel+1, chan->algorithm, chan->feedback,
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1190 chan->lr == 0xC0 ? "LR" : chan->lr == 0x80 ? "L" : chan->lr == 0x40 ? "R" : "",
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1191 chan->ams, chan->pms);
930 f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1192 if (channel == 2) {
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1193 printf(
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1194 "Mode: %X: %s\n",
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1195 context->ch3_mode, context->ch3_mode ? "special" : "normal");
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1196 }
739 2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1197 for (int operator = channel * 4; operator < channel * 4+4; operator++)
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1198 {
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1199 int dispnum = operator - channel * 4 + 1;
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1200 if (dispnum == 2) {
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1201 dispnum = 3;
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1202 } else if (dispnum == 3) {
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1203 dispnum = 2;
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1204 }
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1205 ym_operator *op = context->operators + operator;
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1206 printf("\nOperator %d:\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1207 " Multiple: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1208 " Detune: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1209 " Total Level: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1210 " Attack Rate: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1211 " Key Scaling: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1212 " Decay Rate: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1213 " Sustain Level: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1214 " Sustain Rate: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1215 " Release Rate: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1216 " Amplitude Modulation %s\n",
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1217 dispnum, op->multiple, op->detune, op->total_level,
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1218 op->rates[PHASE_ATTACK], op->key_scaling, op->rates[PHASE_DECAY],
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1219 op->sustain_level, op->rates[PHASE_SUSTAIN], op->rates[PHASE_RELEASE],
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1220 op->am ? "On" : "Off");
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1221 }
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1222 }
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation Michael Pavone <pavone@retrodev.com> parents: 738 diff changeset	1223
930 f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1224 void ym_print_timer_info(ym2612_context *context)
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1225 {
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1226 printf("*Timer A*\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1227 "Current Value: %d\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1228 "Load Value: %d\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1229 "Triggered: %s\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1230 "Enabled: %s\n\n",
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1231 context->timer_a,
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1232 context->timer_a_load,
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1233 context->status & BIT_STATUS_TIMERA ? "yes" : "no",
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1234 context->timer_control & BIT_TIMERA_ENABLE ? "yes" : "no");
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1235 printf("*Timer B*\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1236 "Current Value: %d\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1237 "Load Value: %d\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1238 "Triggered: %s\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1239 "Enabled: %s\n\n",
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1240 context->timer_b,
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1241 context->timer_b_load,
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1242 context->status & BIT_STATUS_TIMERB ? "yes" : "no",
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1243 context->timer_control & BIT_TIMERB_ENABLE ? "yes" : "no");
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1244 }
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values. Michael Pavone <pavone@retrodev.com> parents: 929 diff changeset	1245
1427 4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1246 void ym_serialize(ym2612_context context, serialize_buffer buf)
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1247 {
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1248 save_buffer8(buf, context->part1_regs, YM_PART1_REGS);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1249 save_buffer8(buf, context->part2_regs, YM_PART2_REGS);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1250 for (int i = 0; i < NUM_OPERATORS; i++)
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1251 {
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1252 save_int32(buf, context->operators[i].phase_counter);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1253 save_int16(buf, context->operators[i].envelope);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1254 save_int16(buf, context->operators[i].output);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1255 save_int8(buf, context->operators[i].env_phase);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1256 save_int8(buf, context->operators[i].inverted);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1257 }
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1258 for (int i = 0; i < NUM_CHANNELS; i++)
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1259 {
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1260 save_int16(buf, context->channels[i].output);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1261 save_int16(buf, context->channels[i].op1_old);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1262 //Due to the latching behavior, these need to be saved
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1263 //even though duplicate info is probably in the regs array
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1264 save_int8(buf, context->channels[i].block);
1450 08bc099a622f Save entirety of fnum register, not just the low 8 bits Michael Pavone <pavone@retrodev.com> parents: 1447 diff changeset	1265 save_int16(buf, context->channels[i].fnum);
1447 a094815b1168 Save and restore YM2612 timer control and keyon/off state in native save states Michael Pavone <pavone@retrodev.com> parents: 1427 diff changeset	1266 save_int8(buf, context->channels[i].keyon);
1427 4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1267 }
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1268 for (int i = 0; i < 3; i++)
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1269 {
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1270 //Due to the latching behavior, these need to be saved
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1271 //even though duplicate info is probably in the regs array
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1272 save_int8(buf, context->ch3_supp[i].block);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1273 save_int8(buf, context->ch3_supp[i].fnum);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1274 }
1447 a094815b1168 Save and restore YM2612 timer control and keyon/off state in native save states Michael Pavone <pavone@retrodev.com> parents: 1427 diff changeset	1275 save_int8(buf, context->timer_control);
1427 4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1276 save_int16(buf, context->timer_a);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1277 save_int8(buf, context->timer_b);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1278 save_int8(buf, context->sub_timer_b);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1279 save_int16(buf, context->env_counter);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1280 save_int8(buf, context->current_op);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1281 save_int8(buf, context->current_env_op);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1282 save_int8(buf, context->lfo_counter);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1283 save_int8(buf, context->csm_keyon);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1284 save_int8(buf, context->status);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1285 save_int8(buf, context->selected_reg);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1286 save_int8(buf, context->selected_part);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1287 save_int32(buf, context->current_cycle);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1288 save_int32(buf, context->write_cycle);
1902 32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	1289 save_int32(buf, context->busy_start);
1904 8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1290 save_int32(buf, context->last_status_cycle);
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1291 save_int32(buf, context->invalid_status_decay);
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1292 save_int8(buf, context->last_status);
1427 4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1293 }
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1294
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1295 void ym_deserialize(deserialize_buffer buf, void vcontext)
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1296 {
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1297 ym2612_context *context = vcontext;
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1298 uint8_t temp_regs[YM_PART1_REGS];
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1299 load_buffer8(buf, temp_regs, YM_PART1_REGS);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1300 context->selected_part = 0;
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1301 for (int i = 0; i < YM_PART1_REGS; i++)
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1302 {
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1303 uint8_t reg = YM_PART1_START + i;
1447 a094815b1168 Save and restore YM2612 timer control and keyon/off state in native save states Michael Pavone <pavone@retrodev.com> parents: 1427 diff changeset	1304 if (reg == REG_TIME_CTRL) {
a094815b1168 Save and restore YM2612 timer control and keyon/off state in native save states Michael Pavone <pavone@retrodev.com> parents: 1427 diff changeset	1305 context->ch3_mode = temp_regs[i] & 0xC0;
a094815b1168 Save and restore YM2612 timer control and keyon/off state in native save states Michael Pavone <pavone@retrodev.com> parents: 1427 diff changeset	1306 } else if (reg != REG_FNUM_LOW && reg != REG_KEY_ONOFF) {
1427 4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1307 context->selected_reg = reg;
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1308 ym_data_write(context, temp_regs[i]);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1309 }
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1310 }
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1311 load_buffer8(buf, temp_regs, YM_PART2_REGS);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1312 context->selected_part = 1;
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1313 for (int i = 0; i < YM_PART2_REGS; i++)
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1314 {
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1315 uint8_t reg = YM_PART2_START + i;
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1316 if (reg != REG_FNUM_LOW) {
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1317 context->selected_reg = reg;
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1318 ym_data_write(context, temp_regs[i]);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1319 }
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1320 }
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1321 for (int i = 0; i < NUM_OPERATORS; i++)
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1322 {
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1323 context->operators[i].phase_counter = load_int32(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1324 context->operators[i].envelope = load_int16(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1325 context->operators[i].output = load_int16(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1326 context->operators[i].env_phase = load_int8(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1327 if (context->operators[i].env_phase > PHASE_RELEASE) {
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1328 context->operators[i].env_phase = PHASE_RELEASE;
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1329 }
1450 08bc099a622f Save entirety of fnum register, not just the low 8 bits Michael Pavone <pavone@retrodev.com> parents: 1447 diff changeset	1330 context->operators[i].inverted = load_int8(buf) != 0 ? SSG_INVERT : 0;
1427 4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1331 }
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1332 for (int i = 0; i < NUM_CHANNELS; i++)
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1333 {
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1334 context->channels[i].output = load_int16(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1335 context->channels[i].op1_old = load_int16(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1336 context->channels[i].block = load_int8(buf);
1450 08bc099a622f Save entirety of fnum register, not just the low 8 bits Michael Pavone <pavone@retrodev.com> parents: 1447 diff changeset	1337 context->channels[i].fnum = load_int16(buf);
1427 4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1338 context->channels[i].keycode = context->channels[i].block << 2 \| fnum_to_keycode[context->channels[i].fnum >> 7];
1447 a094815b1168 Save and restore YM2612 timer control and keyon/off state in native save states Michael Pavone <pavone@retrodev.com> parents: 1427 diff changeset	1339 context->channels[i].keyon = load_int8(buf);
1427 4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1340 }
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1341 for (int i = 0; i < 3; i++)
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1342 {
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1343 context->ch3_supp[i].block = load_int8(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1344 context->ch3_supp[i].fnum = load_int8(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1345 context->ch3_supp[i].keycode = context->ch3_supp[i].block << 2 \| fnum_to_keycode[context->ch3_supp[i].fnum >> 7];
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1346 }
1447 a094815b1168 Save and restore YM2612 timer control and keyon/off state in native save states Michael Pavone <pavone@retrodev.com> parents: 1427 diff changeset	1347 context->timer_control = load_int8(buf);
1427 4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1348 context->timer_a = load_int16(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1349 context->timer_b = load_int8(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1350 context->sub_timer_b = load_int8(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1351 context->env_counter = load_int16(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1352 context->current_op = load_int8(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1353 if (context->current_op >= NUM_OPERATORS) {
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1354 context->current_op = 0;
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1355 }
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1356 context->current_env_op = load_int8(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1357 if (context->current_env_op >= NUM_OPERATORS) {
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1358 context->current_env_op = 0;
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1359 }
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1360 context->lfo_counter = load_int8(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1361 context->csm_keyon = load_int8(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1362 context->status = load_int8(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1363 context->selected_reg = load_int8(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1364 context->selected_part = load_int8(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1365 context->current_cycle = load_int32(buf);
4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1366 context->write_cycle = load_int32(buf);
1902 32a3aa7b4a45 Fix YM2612 busy flag timing Michael Pavone <pavone@retrodev.com> parents: 1880 diff changeset	1367 context->busy_start = load_int32(buf);
1904 8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1368 if (buf->size > buf->cur_pos) {
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1369 context->last_status_cycle = load_int32(buf);
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1370 context->invalid_status_decay = load_int32(buf);
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1371 context->last_status = load_int8(buf);
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1372 } else {
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1373 context->last_status = context->status;
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1374 context->last_status_cycle = context->write_cycle;
8312e574100a Implement selectable YM2612/YM3834 invalid status port behavior Michael Pavone <pavone@retrodev.com> parents: 1902 diff changeset	1375 }
1427 4e5797b3935a WIP - New savestate format Michael Pavone <pavone@retrodev.com> parents: 1356 diff changeset	1376 }

Mercurial > repos > blastem

annotate ym2612.c @ 1955:1c7af12efe8b