repos/blastem: cpu_dsl.py annotate

annotate cpu_dsl.py @ 1715:4fd84c3efc72

Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right

author	Michael Pavone <pavone@retrodev.com>
date	Tue, 29 Jan 2019 23:56:48 -0800
parents	0264d8b288e2
children	04cafe626118

rev	line source
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1 #!/usr/bin/env python3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	4 class Block:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	5 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	6 pass
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	8 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	9 if parts[0] == 'switch':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	10 o = Switch(self, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	11 self.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	12 return o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	13 elif parts[0] == 'if':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	14 o = If(self, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	15 self.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	16 return o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	17 elif parts[0] == 'end':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	18 raise Exception('end is only allowed inside a switch or if block')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	19 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	20 self.addOp(NormalOp(parts))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	21 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	22
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	23 def processOps(self, prog, fieldVals, output, otype, oplist):
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	24 for i in range(0, len(oplist)):
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	25 if i + 1 < len(oplist) and oplist[i+1].op == 'update_flags':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	26 flagUpdates, _ = prog.flags.parseFlagUpdate(oplist[i+1].params[0])
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	27 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	28 flagUpdates = None
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	29 oplist[i].generate(prog, self, fieldVals, output, otype, flagUpdates)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	30
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	31 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	32 return None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	33
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	34 class ChildBlock(Block):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	35 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	36 if parts[0] == 'end':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	37 return self.parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	38 return super().processLine(parts)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	39
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	40 #Represents an instruction of the emulated CPU
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	41 class Instruction(Block):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	42 def __init__(self, value, fields, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	43 self.value = value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	44 self.fields = fields
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	45 self.name = name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	46 self.implementation = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	47 self.locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	48 self.regValues = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	49 self.varyingBits = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	50 self.invalidFieldValues = {}
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	51 self.newLocals = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	52 for field in fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	53 self.varyingBits += fields[field][1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	54
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	55 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	56 if op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	57 name = op.params[0]
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	58 size = int(op.params[1])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	59 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	60 elif op.op == 'invalid':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	61 name = op.params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	62 value = int(op.params[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	63 self.invalidFieldValues.setdefault(name, set()).add(value)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	64 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	65 self.implementation.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	66
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	67 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	68 if name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	69 return name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	70 return None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	71
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	72 def addLocal(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	73 self.locals[name] = size
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	74 self.newLocals.append(name)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	75
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	76 def localSize(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	77 return self.locals.get(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	78
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	79 def __lt__(self, other):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	80 if isinstance(other, Instruction):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	81 if self.varyingBits != other.varyingBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	82 return self.varyingBits < other.varyingBits
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	83 return self.value < other.value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	84 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	85 return NotImplemented
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	86
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	87 def allValues(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	88 values = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	89 for i in range(0, 1 << self.varyingBits):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	90 iword = self.value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	91 doIt = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	92 for field in self.fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	93 shift,bits = self.fields[field]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	94 val = i & ((1 << bits) - 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	95 if field in self.invalidFieldValues and val in self.invalidFieldValues[field]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	96 doIt = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	97 break
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	98 i >>= bits
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	99 iword \|= val << shift
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	100 if doIt:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	101 values.append(iword)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	102 return values
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	103
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	104 def getFieldVals(self, value):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	105 fieldVals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	106 fieldBits = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	107 for field in self.fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	108 shift,bits = self.fields[field]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	109 val = (value >> shift) & ((1 << bits) - 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	110 fieldVals[field] = val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	111 fieldBits[field] = bits
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	112 return (fieldVals, fieldBits)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	113
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	114 def generateName(self, value):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	115 fieldVals,fieldBits = self.getFieldVals(value)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	116 names = list(fieldVals.keys())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	117 names.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	118 funName = self.name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	119 for name in names:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	120 funName += '_{0}_{1:0>{2}}'.format(name, bin(fieldVals[name])[2:], fieldBits[name])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	121 return funName
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	122
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	123 def generateBody(self, value, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	124 output = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	125 prog.meta = {}
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	126 prog.pushScope(self)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	127 self.regValues = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	128 for var in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	129 output.append('\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	130 self.newLocals = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	131 fieldVals,_ = self.getFieldVals(value)
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	132 self.processOps(prog, fieldVals, output, otype, self.implementation)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	133 begin = '\nvoid ' + self.generateName(value) + '(' + prog.context_type + ' *context)\n{'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	134 if prog.needFlagCoalesce:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	135 begin += prog.flags.coalesceFlags(prog, otype)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	136 if prog.needFlagDisperse:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	137 output.append(prog.flags.disperseFlags(prog, otype))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	138 for var in self.newLocals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	139 begin += '\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var)
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	140 prog.popScope()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	141 return begin + ''.join(output) + '\n}'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	142
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	143 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	144 pieces = [self.name + ' ' + hex(self.value) + ' ' + str(self.fields)]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	145 for name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	146 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	147 for op in self.implementation:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	148 pieces.append(str(op))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	149 return ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	150
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	151 #Represents the definition of a helper function
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	152 class SubRoutine(Block):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	153 def __init__(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	154 self.name = name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	155 self.implementation = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	156 self.args = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	157 self.arg_map = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	158 self.locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	159 self.regValues = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	160
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	161 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	162 if op.op == 'arg':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	163 name = op.params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	164 size = op.params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	165 self.arg_map[name] = len(self.args)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	166 self.args.append((name, size))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	167 elif op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	168 name = op.params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	169 size = op.params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	170 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	171 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	172 self.implementation.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	173
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	174 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	175 if name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	176 return self.name + '_' + name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	177 return None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	178
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	179 def addLocal(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	180 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	181
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	182 def localSize(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	183 return self.locals.get(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	184
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	185 def inline(self, prog, params, output, otype, parent):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	186 if len(params) != len(self.args):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	187 raise Exception('{0} expects {1} arguments, but was called with {2}'.format(self.name, len(self.args), len(params)))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	188 argValues = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	189 if parent:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	190 self.regValues = parent.regValues
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	191 prog.pushScope(self)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	192 i = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	193 for name,size in self.args:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	194 argValues[name] = params[i]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	195 i += 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	196 for name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	197 size = self.locals[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	198 output.append('\n\tuint{size}_t {sub}_{local};'.format(size=size, sub=self.name, local=name))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	199 self.processOps(prog, argValues, output, otype, self.implementation)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	200 prog.popScope()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	201
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	202 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	203 pieces = [self.name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	204 for name,size in self.args:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	205 pieces.append('\n\targ {0} {1}'.format(name, size))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	206 for name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	207 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	208 for op in self.implementation:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	209 pieces.append(str(op))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	210 return ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	211
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	212 class Op:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	213 def __init__(self, evalFun = None):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	214 self.evalFun = evalFun
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	215 self.impls = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	216 self.outOp = ()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	217 def cBinaryOperator(self, op):
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	218 def _impl(prog, params, rawParams, flagUpdates):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	219 if op == '-':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	220 a = params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	221 b = params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	222 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	223 a = params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	224 b = params[1]
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	225 needsCarry = needsOflow = needsHalf = False
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	226 if flagUpdates:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	227 for flag in flagUpdates:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	228 calc = prog.flags.flagCalc[flag]
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	229 if calc == 'carry':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	230 needsCarry = True
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	231 elif calc == 'half-carry':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	232 needsHalf = True
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	233 elif calc == 'overflow':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	234 needsOflow = True
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	235 decl = ''
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	236 if needsCarry or needsOflow or needsHalf:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	237 size = prog.paramSize(rawParams[2])
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	238 if needsCarry:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	239 size *= 2
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	240 decl,name = prog.getTemp(size)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	241 dst = prog.carryFlowDst = name
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	242 prog.lastA = a
1708 5bfed2eedc9d Fixed flag calculation for sub instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1707 diff changeset	243 prog.lastB = b
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	244 prog.lastBFlow = b if op == '-' else '(~{b})'.format(b=b)
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	245 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	246 dst = params[2]
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	247 return decl + '\n\t{dst} = {a} {op} {b};'.format(
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	248 dst = dst, a = a, b = b, op = op
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	249 )
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	250 self.impls['c'] = _impl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	251 self.outOp = (2,)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	252 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	253 def cUnaryOperator(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	254 def _impl(prog, params):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	255 return '\n\t{dst} = {op}{a};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	256 dst = params[1], a = params[0], op = op
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	257 )
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	258 self.impls['c'] = _impl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	259 self.outOp = (1,)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	260 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	261 def addImplementation(self, lang, outOp, impl):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	262 self.impls[lang] = impl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	263 if not outOp is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	264 if type(outOp) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	265 self.outOp = outOp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	266 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	267 self.outOp = (outOp,)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	268 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	269 def evaluate(self, params):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	270 return self.evalFun(*params)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	271 def canEval(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	272 return not self.evalFun is None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	273 def numArgs(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	274 return self.evalFun.__code__.co_argcount
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	275 def generate(self, otype, prog, params, rawParams, flagUpdates):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	276 if self.impls[otype].__code__.co_argcount == 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	277 return self.impls[otype](prog, params)
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	278 elif self.impls[otype].__code__.co_argcount == 3:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	279 return self.impls[otype](prog, params, rawParams)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	280 else:
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	281 return self.impls[otype](prog, params, rawParams, flagUpdates)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	282
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	283
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	284 def _xchgCImpl(prog, params, rawParams):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	285 size = prog.paramSize(rawParams[0])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	286 decl,name = prog.getTemp(size)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	287 return decl + '\n\t{tmp} = {a};\n\t{a} = {b};\n\t{b} = {tmp};'.format(a = params[0], b = params[1], tmp = name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	288
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	289 def _dispatchCImpl(prog, params):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	290 if len(params) == 1:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	291 table = 'main'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	292 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	293 table = params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	294 return '\n\timpl_{tbl}[{op}](context);'.format(tbl = table, op = params[0])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	295
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	296 def _updateFlagsCImpl(prog, params, rawParams):
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	297 autoUpdate, explicit = prog.flags.parseFlagUpdate(params[0])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	298 output = []
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	299 parity = None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	300 for flag in autoUpdate:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	301 calc = prog.flags.flagCalc[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	302 calc,_,resultBit = calc.partition('-')
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	303 if prog.carryFlowDst:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	304 lastDst = prog.carryFlowDst
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	305 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	306 lastDst = prog.resolveParam(prog.lastDst, None, {})
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	307 storage = prog.flags.getStorage(flag)
1705 9ab64ef5cba0 Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction Michael Pavone <pavone@retrodev.com> parents: 1704 diff changeset	308 if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half' or calc == 'overflow':
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	309 myRes = lastDst
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	310 if calc == 'sign':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	311 resultBit = prog.paramSize(prog.lastDst) - 1
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	312 elif calc == 'carry':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	313 resultBit = prog.paramSize(prog.lastDst)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	314 elif calc == 'half':
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	315 resultBit = prog.paramSize(prog.lastDst) - 4
1708 5bfed2eedc9d Fixed flag calculation for sub instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1707 diff changeset	316 myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst)
1705 9ab64ef5cba0 Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction Michael Pavone <pavone@retrodev.com> parents: 1704 diff changeset	317 elif calc == 'overflow':
9ab64ef5cba0 Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction Michael Pavone <pavone@retrodev.com> parents: 1704 diff changeset	318 resultBit = prog.paramSize(prog.lastDst) - 1
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	319 myRes = '((({a} ^ {b})) & ({a} ^ {res}))'.format(a = prog.lastA, b = prog.lastBFlow, res = lastDst)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	320 else:
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	321 #Note: offsetting this by the operation size - 8 makes sense for the Z80
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	322 #but might not for other CPUs with this kind of fixed bit flag behavior
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	323 resultBit = int(resultBit) + prog.paramSize(prog.lastDst) - 8
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	324 if type(storage) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	325 reg,storageBit = storage
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	326 reg = prog.resolveParam(reg, None, {})
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	327 if storageBit == resultBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	328 #TODO: optimize this case
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	329 output.append('\n\t{reg} = ({reg} & ~{mask}U) \| ({res} & {mask}U);'.format(
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	330 reg = reg, mask = 1 << resultBit, res = myRes
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	331 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	332 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	333 if resultBit > storageBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	334 op = '>>'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	335 shift = resultBit - storageBit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	336 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	337 op = '<<'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	338 shift = storageBit - resultBit
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	339 output.append('\n\t{reg} = ({reg} & ~{mask}U) \| ({res} {op} {shift}U & {mask}U);'.format(
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	340 reg = reg, mask = 1 << storageBit, res = myRes, op = op, shift = shift
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	341 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	342 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	343 reg = prog.resolveParam(storage, None, {})
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	344 maxBit = prog.paramSize(storage) - 1
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	345 if resultBit > maxBit:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	346 output.append('\n\t{reg} = {res} >> {shift} & {mask}U;'.format(reg=reg, res=myRes, shift = resultBit - maxBit, mask = 1 << maxBit))
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	347 else:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	348 output.append('\n\t{reg} = {res} & {mask}U;'.format(reg=reg, res=myRes, mask = 1 << resultBit))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	349 elif calc == 'zero':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	350 if type(storage) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	351 reg,storageBit = storage
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	352 reg = prog.resolveParam(reg, None, {})
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	353 output.append('\n\t{reg} = {res} ? ({reg} & {mask}U) : ({reg} \| {bit}U);'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	354 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	355 ))
1703 49a52c737bf0 Fix zero flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1702 diff changeset	356 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	357 reg = prog.resolveParam(storage, None, {})
1703 49a52c737bf0 Fix zero flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1702 diff changeset	358 output.append('\n\t{reg} = {res} == 0;'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	359 reg = reg, res = lastDst
1705 9ab64ef5cba0 Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction Michael Pavone <pavone@retrodev.com> parents: 1704 diff changeset	360 ))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	361 elif calc == 'parity':
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	362 parity = storage
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	363 paritySize = prog.paramSize(prog.lastDst)
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	364 if prog.carryFlowDst:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	365 parityDst = paritySrc = prog.carryFlowDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	366 else:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	367 paritySrc = lastDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	368 decl,name = prog.getTemp(paritySize)
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	369 output.append(decl)
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	370 parityDst = name
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	371 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	372 raise Exception('Unknown flag calc type: ' + calc)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	373 if prog.carryFlowDst:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	374 output.append('\n\t{dst} = {tmpdst};'.format(dst = prog.resolveParam(prog.lastDst, None, {}), tmpdst = prog.carryFlowDst))
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	375 prog.carryFlowDst = None
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	376 if parity:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	377 if paritySize > 8:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	378 if paritySize > 16:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	379 output.append('\n\t{dst} = {src} ^ ({src} >> 16);'.format(dst=parityDst, src=paritySrc))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	380 paritySrc = parityDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	381 output.append('\n\t{dst} = {src} ^ ({src} >> 8);'.format(dst=parityDst, src=paritySrc))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	382 paritySrc = parityDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	383 output.append('\n\t{dst} = ({src} ^ ({src} >> 4)) & 0xF;'.format(dst=parityDst, src=paritySrc))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	384 if type(parity) is tuple:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	385 reg,bit = parity
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	386 reg = prog.resolveParam(reg, None, {})
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	387 output.append('\n\t{flag} = ({flag} & ~{mask}U) \| ((0x6996 >> {parity}) << {bit} & {mask}U);'.format(
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	388 flag=reg, mask = 1 << bit, bit = bit, parity = parityDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	389 ))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	390 else:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	391 reg = prog.resolveParam(parity, None, {})
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	392 output.append('\n\t{flag} = 0x9669 >> {parity} & 1;'.format(flag=reg, parity=parityDst))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	393
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	394 #TODO: combine explicit flags targeting the same storage location
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	395 for flag in explicit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	396 location = prog.flags.getStorage(flag)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	397 if type(location) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	398 reg,bit = location
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	399 reg = prog.resolveReg(reg, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	400 value = str(1 << bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	401 if explicit[flag]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	402 operator = '\|='
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	403 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	404 operator = '&='
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	405 value = '~' + value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	406 output.append('\n\t{reg} {op} {val};'.format(reg=reg, op=operator, val=value))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	407 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	408 reg = prog.resolveReg(location, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	409 output.append('\n\t{reg} = {val};'.format(reg=reg, val=explicit[flag]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	410 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	411
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	412 def _cmpCImpl(prog, params):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	413 size = prog.paramSize(params[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	414 tmpvar = 'cmp_tmp{sz}__'.format(sz=size)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	415 typename = ''
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	416 scope = prog.getRootScope()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	417 if not scope.resolveLocal(tmpvar):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	418 scope.addLocal(tmpvar, size)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	419 prog.lastDst = tmpvar
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	420 return '\n\t{var} = {b} - {a};'.format(var = tmpvar, a = params[0], b = params[1])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	421
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	422 def _asrCImpl(prog, params, rawParams):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	423 shiftSize = prog.paramSize(rawParams[0])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	424 mask = 1 << (shiftSize - 1)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	425 return '\n\t{dst} = ({a} >> {b}) \| ({a} & {mask});'.format(a = params[0], b = params[1], dst = params[2], mask = mask)
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	426
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	427 def _sext(size, src):
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	428 if size == 16:
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	429 return src \| 0xFF00 if src & 0x80 else src
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	430 else:
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	431 return src \| 0xFFFF0000 if src & 0x8000 else src
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	432
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	433 def _sextCImpl(prog, params, rawParms):
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	434 if params[0] == 16:
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	435 fmt = '\n\t{dst} = {src} & 0x80 ? {src} \| 0xFF00 : {src};'
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	436 else:
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	437 fmt = '\n\t{dst} = {src} & 0x8000 ? {src} \| 0xFFFF0000 : {src};'
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	438 return fmt.format(src=params[1], dst=params[2])
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	439
73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	440 def _getCarryCheck(prog):
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	441 carryFlag = None
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	442 for flag in prog.flags.flagCalc:
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	443 if prog.flags.flagCalc[flag] == 'carry':
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	444 carryFlag = flag
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	445 if carryFlag is None:
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	446 raise Exception('adc requires a defined carry flag')
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	447 carryStorage = prog.flags.getStorage(carryFlag)
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	448 if type(carryStorage) is tuple:
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	449 reg,bit = carryStorage
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	450 reg = prog.resolveReg(reg, None, (), False)
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	451 return '({reg} & 1 << {bit})'.format(reg=reg, bit=bit)
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	452 else:
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	453 return prog.resolveReg(carryStorage, None, (), False)
73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	454
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	455 def _adcCImpl(prog, params, rawParams, flagUpdates):
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	456 needsCarry = needsOflow = needsHalf = False
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	457 if flagUpdates:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	458 for flag in flagUpdates:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	459 calc = prog.flags.flagCalc[flag]
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	460 if calc == 'carry':
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	461 needsCarry = True
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	462 elif calc == 'half-carry':
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	463 needsHalf = True
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	464 elif calc == 'overflow':
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	465 needsOflow = True
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	466 decl = ''
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	467 carryCheck = _getCarryCheck(prog)
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	468 if needsCarry or needsOflow or needsHalf:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	469 size = prog.paramSize(rawParams[2])
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	470 if needsCarry:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	471 size *= 2
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	472 decl,name = prog.getTemp(size)
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	473 dst = prog.carryFlowDst = name
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	474 prog.lastA = params[0]
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	475 prog.lastB = '({b} + ({check} ? 1 : 0))'.format(b = params[1], check = carryCheck)
87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	476 prog.lastBFlow = '(~{b})'.format(b=params[1])
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	477 else:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	478 dst = params[2]
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	479 return decl + '\n\t{dst} = {a} + {b} + ({check} ? 1 : 0);'.format(dst = dst,
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	480 a = params[0], b = params[1], check = carryCheck
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	481 )
73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	482
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	483 def _sbcCImpl(prog, params, rawParams, flagUpdates):
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	484 needsCarry = needsOflow = needsHalf = False
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	485 if flagUpdates:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	486 for flag in flagUpdates:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	487 calc = prog.flags.flagCalc[flag]
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	488 if calc == 'carry':
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	489 needsCarry = True
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	490 elif calc == 'half-carry':
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	491 needsHalf = True
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	492 elif calc == 'overflow':
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	493 needsOflow = True
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	494 decl = ''
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	495 carryCheck = _getCarryCheck(prog)
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	496 if needsCarry or needsOflow or needsHalf:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	497 size = prog.paramSize(rawParams[2])
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	498 if needsCarry:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	499 size *= 2
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	500 decl,name = prog.getTemp(size)
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	501 dst = prog.carryFlowDst = name
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	502 prog.lastA = params[1]
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	503 prog.lastB = '({b} ^ ({check} ? 1 : 0))'.format(b = params[0], check = carryCheck)
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	504 prog.lastBFlow = params[0]
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	505 else:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	506 dst = params[2]
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	507 return decl + '\n\t{dst} = {b} - {a} - ({check} ? 1 : 0);'.format(dst = dst,
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	508 a = params[0], b = params[1], check=_getCarryCheck(prog)
73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	509 )
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	510
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	511 _opMap = {
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	512 'mov': Op(lambda val: val).cUnaryOperator(''),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	513 'not': Op(lambda val: ~val).cUnaryOperator('~'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	514 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	515 'neg': Op(lambda val: -val).cUnaryOperator('-'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	516 'add': Op(lambda a, b: a + b).cBinaryOperator('+'),
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	517 'adc': Op().addImplementation('c', 2, _adcCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	518 'sub': Op(lambda a, b: b - a).cBinaryOperator('-'),
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	519 'sbc': Op().addImplementation('c', 2, _sbcCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	520 'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	521 'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	522 'asr': Op(lambda a, b: a >> b).addImplementation('c', 2, _asrCImpl),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	523 'and': Op(lambda a, b: a & b).cBinaryOperator('&'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	524 'or': Op(lambda a, b: a \| b).cBinaryOperator('\|'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	525 'xor': Op(lambda a, b: a ^ b).cBinaryOperator('^'),
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	526 'abs': Op(lambda val: abs(val)).addImplementation(
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	527 'c', 1, lambda prog, params: '\n\t{dst} = abs({src});'.format(dst=params[1], src=params[0])
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	528 ),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	529 'cmp': Op().addImplementation('c', None, _cmpCImpl),
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	530 'sext': Op(_sext).addImplementation('c', 2, _sextCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	531 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	532 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	533 )),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	534 'cycles': Op().addImplementation('c', None,
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	535 lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	536 params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	537 )
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	538 ),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	539 'addsize': Op(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	540 lambda a, b: b + (2 * a if a else 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	541 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} + {sz} ? {sz} * 2 : 1;'.format(
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	542 dst = params[2], sz = params[0], val = params[1]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	543 )),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	544 'decsize': Op(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	545 lambda a, b: b - (2 * a if a else 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	546 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} - {sz} ? {sz} * 2 : 1;'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	547 dst = params[2], sz = params[0], val = params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	548 )),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	549 'xchg': Op().addImplementation('c', (0,1), _xchgCImpl),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	550 'dispatch': Op().addImplementation('c', None, _dispatchCImpl),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	551 'update_flags': Op().addImplementation('c', None, _updateFlagsCImpl)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	552 }
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	553
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	554 #represents a simple DSL instruction
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	555 class NormalOp:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	556 def __init__(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	557 self.op = parts[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	558 self.params = parts[1:]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	559
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	560 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	561 procParams = []
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	562 allParamsConst = flagUpdates is None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	563 opDef = _opMap.get(self.op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	564 for param in self.params:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	565 allowConst = (self.op in prog.subroutines or len(procParams) != len(self.params) - 1) and param in parent.regValues
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	566 isDst = (not opDef is None) and len(procParams) in opDef.outOp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	567 param = prog.resolveParam(param, parent, fieldVals, allowConst, isDst)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	568
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	569 if (not type(param) is int) and len(procParams) != len(self.params) - 1:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	570 allParamsConst = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	571 procParams.append(param)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	572
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	573 if self.op == 'meta':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	574 param,_,index = self.params[1].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	575 if index:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	576 index = (parent.resolveLocal(index) or index)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	577 if index in fieldVals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	578 index = str(fieldVals[index])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	579 param = param + '.' + index
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	580 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	581 param = parent.resolveLocal(param) or param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	582 if param in fieldVals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	583 param = fieldVals[index]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	584 prog.meta[self.params[0]] = param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	585 elif self.op == 'dis':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	586 #TODO: Disassembler
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	587 pass
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	588 elif not opDef is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	589 if opDef.canEval() and allParamsConst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	590 #do constant folding
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	591 if opDef.numArgs() >= len(procParams):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	592 raise Exception('Insufficient args for ' + self.op + ' (' + ', '.join(self.params) + ')')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	593 dst = self.params[opDef.numArgs()]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	594 result = opDef.evaluate(procParams[:opDef.numArgs()])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	595 while dst in prog.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	596 dst = prog.meta[dst]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	597 maybeLocal = parent.resolveLocal(dst)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	598 if maybeLocal:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	599 dst = maybeLocal
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	600 parent.regValues[dst] = result
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	601 if prog.isReg(dst):
1699 93103ad9d7f7 Fix constant propagation to a non-ephemeral destination in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1698 diff changeset	602 shortProc = (procParams[0], procParams[-1])
93103ad9d7f7 Fix constant propagation to a non-ephemeral destination in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1698 diff changeset	603 shortParams = (self.params[0], self.params[-1])
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	604 output.append(_opMap['mov'].generate(otype, prog, shortProc, shortParams, None))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	605 else:
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	606 output.append(opDef.generate(otype, prog, procParams, self.params, flagUpdates))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	607 elif self.op in prog.subroutines:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	608 prog.subroutines[self.op].inline(prog, procParams, output, otype, parent)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	609 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	610 output.append('\n\t' + self.op + '(' + ', '.join([str(p) for p in procParams]) + ');')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	611 prog.lastOp = self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	612
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	613 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	614 return '\n\t' + self.op + ' ' + ' '.join(self.params)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	615
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	616 #represents a DSL switch construct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	617 class Switch(ChildBlock):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	618 def __init__(self, parent, param):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	619 self.op = 'switch'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	620 self.parent = parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	621 self.param = param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	622 self.cases = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	623 self.regValues = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	624 self.current_locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	625 self.case_locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	626 self.current_case = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	627 self.default = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	628 self.default_locals = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	629
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	630 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	631 if op.op == 'case':
1619 0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	632 val = int(op.params[0], 16) if op.params[0].startswith('0x') else int(op.params[0])
0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	633 self.cases[val] = self.current_case = []
0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	634 self.case_locals[val] = self.current_locals = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	635 elif op.op == 'default':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	636 self.default = self.current_case = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	637 self.default_locals = self.current_locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	638 elif self.current_case == None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	639 raise ion('Orphan instruction in switch')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	640 elif op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	641 name = op.params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	642 size = op.params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	643 self.current_locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	644 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	645 self.current_case.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	646
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	647 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	648 if name in self.current_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	649 return name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	650 return self.parent.resolveLocal(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	651
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	652 def addLocal(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	653 self.current_locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	654
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	655 def localSize(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	656 if name in self.current_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	657 return self.current_locals[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	658 return self.parent.localSize(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	659
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	660 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates):
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	661 prog.pushScope(self)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	662 param = prog.resolveParam(self.param, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	663 if type(param) is int:
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	664 self.regValues = self.parent.regValues
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	665 if param in self.cases:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	666 self.current_locals = self.case_locals[param]
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	667 output.append('\n\t{')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	668 for local in self.case_locals[param]:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	669 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[param][local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	670 self.processOps(prog, fieldVals, output, otype, self.cases[param])
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	671 output.append('\n\t}')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	672 elif self.default:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	673 self.current_locals = self.default_locals
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	674 output.append('\n\t{')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	675 for local in self.default_locals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	676 output.append('\n\tuint{0}_t {1};'.format(self.default[local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	677 self.processOps(prog, fieldVals, output, otype, self.default)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	678 output.append('\n\t}')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	679 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	680 output.append('\n\tswitch(' + param + ')')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	681 output.append('\n\t{')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	682 for case in self.cases:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	683 self.current_locals = self.case_locals[case]
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	684 self.regValues = dict(self.parent.regValues)
1619 0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	685 output.append('\n\tcase {0}U: '.format(case) + '{')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	686 for local in self.case_locals[case]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	687 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[case][local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	688 self.processOps(prog, fieldVals, output, otype, self.cases[case])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	689 output.append('\n\tbreak;')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	690 output.append('\n\t}')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	691 if self.default:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	692 self.current_locals = self.default_locals
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	693 self.regValues = dict(self.parent.regValues)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	694 output.append('\n\tdefault: {')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	695 for local in self.default_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	696 output.append('\n\tuint{0}_t {1};'.format(self.default_locals[local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	697 self.processOps(prog, fieldVals, output, otype, self.default)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	698 output.append('\n\t}')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	699 prog.popScope()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	700
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	701 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	702 keys = self.cases.keys()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	703 keys.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	704 lines = ['\n\tswitch']
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	705 for case in keys:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	706 lines.append('\n\tcase {0}'.format(case))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	707 lines.append(''.join([str(op) for op in self.cases[case]]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	708 lines.append('\n\tend')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	709 return ''.join(lines)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	710
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	711
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	712 def _geuCImpl(prog, parent, fieldVals, output):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	713 if prog.lastOp.op == 'cmp':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	714 output.pop()
1616 8c78543c4783 Fix implementation cmp+condition version of if in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1615 diff changeset	715 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params]
8c78543c4783 Fix implementation cmp+condition version of if in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1615 diff changeset	716 return '\n\tif ({a} >= {b}) '.format(a=params[1], b = params[0]) + '{'
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	717 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	718 raise ion(">=U not implemented in the general case yet")
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	719
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	720 _ifCmpImpl = {
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	721 'c': {
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	722 '>=U': _geuCImpl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	723 }
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	724 }
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	725 #represents a DSL conditional construct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	726 class If(ChildBlock):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	727 def __init__(self, parent, cond):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	728 self.op = 'if'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	729 self.parent = parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	730 self.cond = cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	731 self.body = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	732 self.elseBody = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	733 self.curBody = self.body
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	734 self.locals = {}
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	735 self.elseLocals = {}
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	736 self.curLocals = self.locals
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	737 self.regValues = None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	738
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	739 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	740 if op.op in ('case', 'arg'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	741 raise Exception(self.op + ' is not allows inside an if block')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	742 if op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	743 name = op.params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	744 size = op.params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	745 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	746 elif op.op == 'else':
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	747 self.curLocals = self.elseLocals
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	748 self.curBody = self.elseBody
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	749 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	750 self.curBody.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	751
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	752 def localSize(self, name):
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	753 return self.curLocals.get(name)
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	754
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	755 def resolveLocal(self, name):
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	756 if name in self.locals:
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	757 return name
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	758 return self.parent.resolveLocal(name)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	759
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	760 def _genTrueBody(self, prog, fieldVals, output, otype):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	761 self.curLocals = self.locals
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	762 for local in self.locals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	763 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.locals[local], nm=local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	764 self.processOps(prog, fieldVals, output, otype, self.body)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	765
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	766 def _genFalseBody(self, prog, fieldVals, output, otype):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	767 self.curLocals = self.elseLocals
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	768 for local in self.elseLocals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	769 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.elseLocals[local], nm=local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	770 self.processOps(prog, fieldVals, output, otype, self.elsebody)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	771
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	772 def _genConstParam(self, param, prog, fieldVals, output, otype):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	773 if param:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	774 self._genTrueBody(prog, fieldVals, output, otype)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	775 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	776 self._genFalseBody(prog, fieldVals, output, otype)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	777
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	778 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	779 self.regValues = parent.regValues
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	780 try:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	781 self._genConstParam(prog.checkBool(self.cond), prog, fieldVals, output, otype)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	782 except Exception:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	783 if self.cond in _ifCmpImpl[otype]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	784 output.append(_ifCmpImpl[otype][self.cond](prog, parent, fieldVals, output))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	785 self._genTrueBody(prog, fieldVals, output, otype)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	786 if self.elseBody:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	787 output.append('\n\t} else {')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	788 self._genFalseBody(prog, fieldVals, output, otype)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	789 output.append('\n\t}')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	790 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	791 cond = prog.resolveParam(self.cond, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	792 if type(cond) is int:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	793 self._genConstParam(cond, prog, fieldVals, output, otype)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	794 else:
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	795 output.append('\n\tif ({cond}) '.format(cond=cond) + '{')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	796 self._genTrueBody(prog, fieldVals, output, otype)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	797 if self.elseBody:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	798 output.append('\n\t} else {')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	799 self._genFalseBody(prog, fieldVals, output, otype)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	800 output.append('\n\t}')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	801
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	802
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	803 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	804 lines = ['\n\tif']
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	805 for op in self.body:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	806 lines.append(str(op))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	807 lines.append('\n\tend')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	808 return ''.join(lines)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	809
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	810 class Registers:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	811 def __init__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	812 self.regs = {}
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	813 self.pointers = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	814 self.regArrays = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	815 self.regToArray = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	816
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	817 def addReg(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	818 self.regs[name] = size
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	819
ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	820 def addPointer(self, name, size):
ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	821 self.pointers[name] = size
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	822
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	823 def addRegArray(self, name, size, regs):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	824 self.regArrays[name] = (size, regs)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	825 idx = 0
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	826 if not type(regs) is int:
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	827 for reg in regs:
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	828 self.regs[reg] = size
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	829 self.regToArray[reg] = (name, idx)
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	830 idx += 1
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	831
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	832 def isReg(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	833 return name in self.regs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	834
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	835 def isRegArray(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	836 return name in self.regArrays
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	837
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	838 def isRegArrayMember(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	839 return name in self.regToArray
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	840
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	841 def arrayMemberParent(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	842 return self.regToArray[name][0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	843
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	844 def arrayMemberIndex(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	845 return self.regToArray[name][1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	846
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	847 def arrayMemberName(self, array, index):
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	848 if type(index) is int and not type(self.regArrays[array][1]) is int:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	849 return self.regArrays[array][1][index]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	850 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	851 return None
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	852
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	853 def isNamedArray(self, array):
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	854 return array in self.regArrays and type(self.regArrays[array][1]) is int
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	855
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	856 def processLine(self, parts):
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	857 if len(parts) == 3:
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	858 self.addRegArray(parts[0], int(parts[1]), int(parts[2]))
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	859 elif len(parts) > 2:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	860 self.addRegArray(parts[0], int(parts[1]), parts[2:])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	861 else:
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	862 if parts[1].startswith('ptr'):
ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	863 self.addPointer(parts[0], int(parts[1][3:]))
ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	864 else:
ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	865 self.addReg(parts[0], int(parts[1]))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	866 return self
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	867
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	868 def writeHeader(self, otype, hFile):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	869 fieldList = []
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	870 for pointer in self.pointers:
ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	871 hFile.write('\n\tuint{sz}_t *{nm};'.format(nm=pointer, sz=self.pointers[pointer]))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	872 for reg in self.regs:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	873 if not self.isRegArrayMember(reg):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	874 fieldList.append((self.regs[reg], 1, reg))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	875 for arr in self.regArrays:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	876 size,regs = self.regArrays[arr]
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	877 if not type(regs) is int:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	878 regs = len(regs)
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	879 fieldList.append((size, regs, arr))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	880 fieldList.sort()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	881 fieldList.reverse()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	882 for size, count, name in fieldList:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	883 if count > 1:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	884 hFile.write('\n\tuint{sz}_t {nm}[{ct}];'.format(sz=size, nm=name, ct=count))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	885 else:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	886 hFile.write('\n\tuint{sz}_t {nm};'.format(sz=size, nm=name))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	887
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	888 class Flags:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	889 def __init__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	890 self.flagBits = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	891 self.flagCalc = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	892 self.flagStorage = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	893 self.flagReg = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	894 self.maxBit = -1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	895
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	896 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	897 if parts[0] == 'register':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	898 self.flagReg = parts[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	899 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	900 flag,bit,calc,storage = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	901 bit,_,top = bit.partition('-')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	902 bit = int(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	903 if top:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	904 top = int(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	905 if top > self.maxBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	906 self.maxBit = top
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	907 self.flagBits[flag] = (bit,top)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	908 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	909 if bit > self.maxBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	910 self.maxBit = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	911 self.flagBits[flag] = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	912 self.flagCalc[flag] = calc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	913 self.flagStorage[flag] = storage
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	914 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	915
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	916 def getStorage(self, flag):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	917 if not flag in self.flagStorage:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	918 raise Exception('Undefined flag ' + flag)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	919 loc,_,bit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	920 if bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	921 return (loc, int(bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	922 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	923 return loc
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	924
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	925 def parseFlagUpdate(self, flagString):
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	926 last = ''
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	927 autoUpdate = set()
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	928 explicit = {}
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	929 for c in flagString:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	930 if c.isdigit():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	931 if last.isalpha():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	932 num = int(c)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	933 if num > 1:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	934 raise Exception(c + ' is not a valid digit for update_flags')
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	935 explicit[last] = num
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	936 last = c
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	937 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	938 raise Exception('Digit must follow flag letter in update_flags')
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	939 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	940 if last.isalpha():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	941 autoUpdate.add(last)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	942 last = c
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	943 if last.isalpha():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	944 autoUpdate.add(last)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	945 return (autoUpdate, explicit)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	946
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	947 def disperseFlags(self, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	948 bitToFlag = [None] * (self.maxBit+1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	949 src = prog.resolveReg(self.flagReg, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	950 output = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	951 for flag in self.flagBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	952 bit = self.flagBits[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	953 if type(bit) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	954 bot,top = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	955 mask = ((1 << (top + 1 - bot)) - 1) << bot
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	956 output.append('\n\t{dst} = {src} & mask;'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	957 dst=prog.resolveReg(self.flagStorage[flag], None, {}), src=src, mask=mask
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	958 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	959 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	960 bitToFlag[self.flagBits[flag]] = flag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	961 multi = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	962 for bit in range(len(bitToFlag)-1,-1,-1):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	963 flag = bitToFlag[bit]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	964 if not flag is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	965 field,_,dstbit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	966 dst = prog.resolveReg(field, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	967 if dstbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	968 dstbit = int(dstbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	969 multi.setdefault(dst, []).append((dstbit, bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	970 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	971 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=(1 << bit)))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	972 for dst in multi:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	973 didClear = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	974 direct = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	975 for dstbit, bit in multi[dst]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	976 if dstbit == bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	977 direct.append(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	978 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	979 if not didClear:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	980 output.append('\n\t{dst} = 0;'.format(dst=dst))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	981 didClear = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	982 if dstbit > bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	983 shift = '<<'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	984 diff = dstbit - bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	985 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	986 shift = '>>'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	987 diff = bit - dstbit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	988 output.append('\n\t{dst} \|= {src} {shift} {diff} & {mask};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	989 src=src, dst=dst, shift=shift, diff=diff, mask=(1 << dstbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	990 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	991 if direct:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	992 if len(direct) == len(multi[dst]):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	993 output.append('\n\t{dst} = {src};'.format(dst=dst, src=src))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	994 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	995 mask = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	996 for bit in direct:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	997 mask = mask \| (1 << bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	998 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=mask))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	999 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1000
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1001 def coalesceFlags(self, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1002 dst = prog.resolveReg(self.flagReg, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1003 output = ['\n\t{dst} = 0;'.format(dst=dst)]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1004 bitToFlag = [None] * (self.maxBit+1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1005 for flag in self.flagBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1006 bit = self.flagBits[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1007 if type(bit) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1008 bot,_ = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1009 src = prog.resolveReg(self.flagStorage[flag], None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1010 if bot:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1011 output.append('\n\t{dst} \|= {src} << {shift};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1012 dst=dst, src = src, shift = bot
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1013 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1014 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1015 output.append('\n\t{dst} \|= {src};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1016 dst=dst, src = src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1017 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1018 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1019 bitToFlag[bit] = flag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1020 multi = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1021 for bit in range(len(bitToFlag)-1,-1,-1):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1022 flag = bitToFlag[bit]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1023 if not flag is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1024 field,_,srcbit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1025 src = prog.resolveReg(field, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1026 if srcbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1027 srcbit = int(srcbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1028 multi.setdefault(src, []).append((srcbit,bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1029 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1030 output.append('\n\tif ({src}) {{\n\t\t{dst} \|= 1 << {bit};\n\t}}'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1031 dst=dst, src=src, bit=bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1032 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1033 for src in multi:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1034 direct = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1035 for srcbit, dstbit in multi[src]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1036 if srcbit == dstbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1037 direct = direct \| (1 << srcbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1038 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1039 output.append('\n\tif ({src} & (1 << {srcbit})) {{\n\t\t{dst} \|= 1 << {dstbit};\n\t}}'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1040 src=src, dst=dst, srcbit=srcbit, dstbit=dstbit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1041 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1042 if direct:
1698 90272218469c Fixed missing semicolon in coalesceFlags Michael Pavone <pavone@retrodev.com> parents: 1697 diff changeset	1043 output.append('\n\t{dst} \|= {src} & {mask};'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1044 dst=dst, src=src, mask=direct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1045 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1046 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1047
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1048
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1049 class Program:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1050 def __init__(self, regs, instructions, subs, info, flags):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1051 self.regs = regs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1052 self.instructions = instructions
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1053 self.subroutines = subs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1054 self.meta = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1055 self.booleans = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1056 self.prefix = info.get('prefix', [''])[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1057 self.opsize = int(info.get('opcode_size', ['8'])[0])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1058 self.extra_tables = info.get('extra_tables', [])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1059 self.context_type = self.prefix + 'context'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1060 self.body = info.get('body', [None])[0]
1620 a172f97d873f Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16 Michael Pavone <pavone@retrodev.com> parents: 1619 diff changeset	1061 self.includes = info.get('include', [])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1062 self.flags = flags
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1063 self.lastDst = None
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1064 self.scopes = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1065 self.currentScope = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1066 self.lastOp = None
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1067 self.carryFlowDst = None
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1068 self.lastA = None
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1069 self.lastB = None
1708 5bfed2eedc9d Fixed flag calculation for sub instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1707 diff changeset	1070 self.lastBFlow = None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1071
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1072 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1073 pieces = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1074 for reg in self.regs:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1075 pieces.append(str(self.regs[reg]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1076 for name in self.subroutines:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1077 pieces.append('\n'+str(self.subroutines[name]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1078 for instruction in self.instructions:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1079 pieces.append('\n'+str(instruction))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1080 return ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1081
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1082 def writeHeader(self, otype, header):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1083 hFile = open(header, 'w')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1084 macro = header.upper().replace('.', '_')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1085 hFile.write('#ifndef {0}_'.format(macro))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1086 hFile.write('\n#define {0}_'.format(macro))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1087 hFile.write('\n#include "backend.h"')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1088 hFile.write('\n\ntypedef struct {')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1089 hFile.write('\n\tcpu_options gen;')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1090 hFile.write('\n}} {0}options;'.format(self.prefix))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1091 hFile.write('\n\ntypedef struct {')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1092 hFile.write('\n\t{0}options *opts;'.format(self.prefix))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1093 hFile.write('\n\tuint32_t cycles;')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1094 self.regs.writeHeader(otype, hFile)
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1095 hFile.write('\n}} {0}context;'.format(self.prefix))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1096 hFile.write('\n')
1703 49a52c737bf0 Fix zero flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1702 diff changeset	1097 hFile.write('\nvoid {pre}execute({type} *context, uint32_t target_cycle);'.format(pre = self.prefix, type = self.context_type))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1098 hFile.write('\n#endif //{0}_'.format(macro))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1099 hFile.write('\n')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1100 hFile.close()
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1101
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1102 def _buildTable(self, otype, table, body):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1103 pieces = []
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1104 opmap = [None] * (1 << self.opsize)
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1105 bodymap = {}
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1106 if table in self.instructions:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1107 instructions = self.instructions[table]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1108 instructions.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1109 for inst in instructions:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1110 for val in inst.allValues():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1111 if opmap[val] is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1112 self.meta = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1113 self.temp = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1114 self.needFlagCoalesce = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1115 self.needFlagDisperse = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1116 self.lastOp = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1117 opmap[val] = inst.generateName(val)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1118 bodymap[val] = inst.generateBody(val, self, otype)
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1119
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1120 pieces.append('\ntypedef void (impl_fun)({pre}context context);'.format(pre=self.prefix))
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1121 pieces.append('\nstatic impl_fun impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap)))
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1122 for inst in range(0, len(opmap)):
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1123 op = opmap[inst]
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1124 if op is None:
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1125 pieces.append('\n\tunimplemented,')
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1126 else:
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1127 pieces.append('\n\t' + op + ',')
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1128 body.append(bodymap[inst])
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1129 pieces.append('\n};')
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1130 body.extend(pieces)
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1131
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1132 def build(self, otype):
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1133 body = []
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1134 pieces = []
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1135 for include in self.includes:
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1136 body.append('#include "{0}"\n'.format(include))
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1137 body.append('\nstatic void unimplemented({pre}context *context)'.format(pre = self.prefix))
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1138 body.append('\n{')
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1139 body.append('\n\tfatal_error("Unimplemented instruction");')
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1140 body.append('\n}\n')
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1141 for table in self.extra_tables:
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1142 self._buildTable(otype, table, body)
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1143 self._buildTable(otype, 'main', body)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1144 if self.body in self.subroutines:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1145 pieces.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1146 pieces.append('\n{')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1147 pieces.append('\n\twhile (context->cycles < target_cycle)')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1148 pieces.append('\n\t{')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1149 self.meta = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1150 self.temp = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1151 self.subroutines[self.body].inline(self, [], pieces, otype, None)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1152 pieces.append('\n\t}')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1153 pieces.append('\n}')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1154 return ''.join(body) + ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1155
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1156 def checkBool(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1157 if not name in self.booleans:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1158 raise Exception(name + ' is not a defined boolean flag')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1159 return self.booleans[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1160
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1161 def getTemp(self, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1162 if size in self.temp:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1163 return ('', self.temp[size])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1164 self.temp[size] = 'tmp{sz}'.format(sz=size);
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1165 return ('\n\tuint{sz}_t tmp{sz};'.format(sz=size), self.temp[size])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1166
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1167 def resolveParam(self, param, parent, fieldVals, allowConstant=True, isdst=False):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1168 keepGoing = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1169 while keepGoing:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1170 keepGoing = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1171 try:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1172 if type(param) is int:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1173 pass
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1174 elif param.startswith('0x'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1175 param = int(param, 16)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1176 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1177 param = int(param)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1178 except ValueError:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1179
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1180 if parent:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1181 if param in parent.regValues and allowConstant:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1182 return parent.regValues[param]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1183 maybeLocal = parent.resolveLocal(param)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1184 if maybeLocal:
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1185 if isdst:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1186 self.lastDst = param
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1187 return maybeLocal
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1188 if param in fieldVals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1189 param = fieldVals[param]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1190 elif param in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1191 param = self.meta[param]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1192 keepGoing = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1193 elif self.isReg(param):
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1194 return self.resolveReg(param, parent, fieldVals, isdst)
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1195 if isdst:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1196 self.lastDst = param
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1197 return param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1198
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1199 def isReg(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1200 if not type(name) is str:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1201 return False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1202 begin,sep,_ = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1203 if sep:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1204 if begin in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1205 begin = self.meta[begin]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1206 return self.regs.isRegArray(begin)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1207 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1208 return self.regs.isReg(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1209
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1210 def resolveReg(self, name, parent, fieldVals, isDst=False):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1211 begin,sep,end = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1212 if sep:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1213 if begin in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1214 begin = self.meta[begin]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1215 if not self.regs.isRegArrayMember(end):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1216 end = self.resolveParam(end, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1217 if not type(end) is int and self.regs.isRegArrayMember(end):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1218 arrayName = self.regs.arrayMemberParent(end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1219 end = self.regs.arrayMemberIndex(end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1220 if arrayName != begin:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1221 end = 'context->{0}[{1}]'.format(arrayName, end)
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1222 if self.regs.isNamedArray(begin):
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1223 regName = self.regs.arrayMemberName(begin, end)
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1224 else:
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1225 regName = '{0}.{1}'.format(begin, end)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1226 ret = 'context->{0}[{1}]'.format(begin, end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1227 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1228 regName = name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1229 if self.regs.isRegArrayMember(name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1230 arr,idx = self.regs.regToArray[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1231 ret = 'context->{0}[{1}]'.format(arr, idx)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1232 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1233 ret = 'context->' + name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1234 if regName == self.flags.flagReg:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1235 if isDst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1236 self.needFlagDisperse = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1237 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1238 self.needFlagCoalesce = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1239 if isDst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1240 self.lastDst = regName
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1241 return ret
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1242
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1243
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1244
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1245 def paramSize(self, name):
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1246 if name in self.meta:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1247 return self.paramSize(self.meta[name])
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1248 for i in range(len(self.scopes) -1, -1, -1):
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1249 size = self.scopes[i].localSize(name)
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1250 if size:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1251 return size
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1252 begin,sep,_ = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1253 if sep and self.regs.isRegArray(begin):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1254 return self.regs.regArrays[begin][0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1255 if self.regs.isReg(name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1256 return self.regs.regs[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1257 return 32
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1258
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1259 def pushScope(self, scope):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1260 self.scopes.append(scope)
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1261 self.currentScope = scope
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1262
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1263 def popScope(self):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1264 ret = self.scopes.pop()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1265 self.currentScope = self.scopes[-1] if self.scopes else None
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1266 return ret
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1267
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1268 def getRootScope(self):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1269 return self.scopes[0]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1270
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1271 def parse(f):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1272 instructions = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1273 subroutines = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1274 registers = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1275 flags = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1276 errors = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1277 info = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1278 line_num = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1279 cur_object = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1280 for line in f:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1281 line_num += 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1282 line,_,comment = line.partition('#')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1283 if not line.strip():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1284 continue
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1285 if line[0].isspace():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1286 if not cur_object is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1287 parts = [el.strip() for el in line.split(' ')]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1288 if type(cur_object) is dict:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1289 cur_object[parts[0]] = parts[1:]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1290 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1291 cur_object = cur_object.processLine(parts)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1292
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1293 # if type(cur_object) is Registers:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1294 # if len(parts) > 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1295 # cur_object.addRegArray(parts[0], int(parts[1]), parts[2:])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1296 # else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1297 # cur_object.addReg(parts[0], int(parts[1]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1298 # elif type(cur_object) is dict:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1299 # cur_object[parts[0]] = parts[1:]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1300 # elif parts[0] == 'switch':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1301 # o = Switch(cur_object, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1302 # cur_object.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1303 # cur_object = o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1304 # elif parts[0] == 'if':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1305 # o = If(cur_object, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1306 # cur_object.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1307 # cur_object = o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1308 # elif parts[0] == 'end':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1309 # cur_object = cur_object.parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1310 # else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1311 # cur_object.addOp(NormalOp(parts))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1312 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1313 errors.append("Orphan instruction on line {0}".format(line_num))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1314 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1315 parts = line.split(' ')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1316 if len(parts) > 1:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1317 if len(parts) > 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1318 table,bitpattern,name = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1319 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1320 bitpattern,name = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1321 table = 'main'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1322 value = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1323 fields = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1324 curbit = len(bitpattern) - 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1325 for char in bitpattern:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1326 value <<= 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1327 if char in ('0', '1'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1328 value \|= int(char)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1329 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1330 if char in fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1331 fields[char] = (curbit, fields[char][1] + 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1332 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1333 fields[char] = (curbit, 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1334 curbit -= 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1335 cur_object = Instruction(value, fields, name.strip())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1336 instructions.setdefault(table, []).append(cur_object)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1337 elif line.strip() == 'regs':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1338 if registers is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1339 registers = Registers()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1340 cur_object = registers
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1341 elif line.strip() == 'info':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1342 cur_object = info
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1343 elif line.strip() == 'flags':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1344 if flags is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1345 flags = Flags()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1346 cur_object = flags
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1347 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1348 cur_object = SubRoutine(line.strip())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1349 subroutines[cur_object.name] = cur_object
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1350 if errors:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1351 print(errors)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1352 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1353 p = Program(registers, instructions, subroutines, info, flags)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1354 p.booleans['dynarec'] = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1355 p.booleans['interp'] = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1356
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1357 if 'header' in info:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1358 print('#include "{0}"'.format(info['header'][0]))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1359 p.writeHeader('c', info['header'][0])
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1360 print('#include "util.h"')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1361 print('#include <stdlib.h>')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1362 print(p.build('c'))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1363
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1364 def main(argv):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1365 f = open(argv[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1366 parse(f)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1367
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1368 if __name__ == '__main__':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1369 from sys import argv
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1370 main(argv)

Mercurial > repos > blastem

annotate cpu_dsl.py @ 1715:4fd84c3efc72