Mercurial > repos > blastem
annotate vdp.c @ 330:57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
| author | Mike Pavone <pavone@retrodev.com> |
|---|---|
| date | Mon, 13 May 2013 23:42:52 -0700 |
| parents | fd5f6577db9b |
| children | de17e0352f27 |
| rev | line source |
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1 #include "vdp.h" |
| 75 | 2 #include "blastem.h" |
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3 #include <stdlib.h> |
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4 #include <string.h> |
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5 |
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6 #define NTSC_ACTIVE 225 |
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7 #define PAL_ACTIVE 241 |
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8 #define BUF_BIT_PRIORITY 0x40 |
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9 #define MAP_BIT_PRIORITY 0x8000 |
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10 #define MAP_BIT_H_FLIP 0x800 |
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11 #define MAP_BIT_V_FLIP 0x1000 |
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12 |
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13 //Mode reg 1 |
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14 #define BIT_HINT_EN 0x10 |
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15 #define BIT_PAL_SEL 0x04 |
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16 #define BIT_HVC_LATCH 0x02 |
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17 #define BIT_DISP_DIS 0x01 |
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18 |
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19 //Mode reg 2 |
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20 #define BIT_DISP_EN 0x40 |
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21 #define BIT_VINT_EN 0x20 |
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22 #define BIT_DMA_ENABLE 0x10 |
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23 #define BIT_PAL 0x08 |
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24 #define BIT_MODE_5 0x04 |
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25 |
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26 //Mode reg 3 |
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27 #define BIT_EINT_EN 0x10 |
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28 #define BIT_VSCROLL 0x04 |
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29 |
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30 //Mode reg 4 |
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31 #define BIT_H40 0x01 |
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32 #define BIT_HILIGHT 0x8 |
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33 |
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34 #define SCROLL_BUFFER_SIZE 32 |
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35 #define SCROLL_BUFFER_DRAW 16 |
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36 |
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37 #define FIFO_SIZE 4 |
| 40 | 38 |
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39 #define VINT_SLOTS_H40 (21+16+10) //21 slots before HSYNC, 16 during, 10 after TODO: deal with clock switching during HSYNC |
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40 #define VINT_SLOTS_H32 (33+20+7) //33 slots before HSYNC, 20 during, 7 after TODO: confirm final number |
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41 #define MCLKS_SLOT_H40 16 |
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42 #define MCLKS_SLOT_H32 20 |
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43 #define HSYNC_SLOT_H40 21 |
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44 #define MCLK_WEIRD_END (HSYNC_SLOT_H40*MCLKS_SLOT_H40 + 332) |
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45 #define SLOT_WEIRD_END (HSYNC_SLOT_H40+17) |
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46 |
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47 void init_vdp_context(vdp_context * context) |
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48 { |
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49 memset(context, 0, sizeof(*context)); |
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50 context->vdpmem = malloc(VRAM_SIZE); |
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51 memset(context->vdpmem, 0, VRAM_SIZE); |
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52 context->framebuf = malloc(FRAMEBUF_SIZE); |
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53 memset(context->framebuf, 0, FRAMEBUF_SIZE); |
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54 context->linebuf = malloc(LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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55 memset(context->linebuf, 0, LINEBUF_SIZE + SCROLL_BUFFER_SIZE*2); |
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56 context->tmp_buf_a = context->linebuf + LINEBUF_SIZE; |
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57 context->tmp_buf_b = context->tmp_buf_a + SCROLL_BUFFER_SIZE; |
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58 context->sprite_draws = MAX_DRAWS; |
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59 context->fifo_cur = malloc(sizeof(fifo_entry) * FIFO_SIZE); |
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60 context->fifo_end = context->fifo_cur + FIFO_SIZE; |
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61 } |
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62 |
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63 void render_sprite_cells(vdp_context * context) |
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64 { |
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65 if (context->cur_slot >= context->sprite_draws) { |
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66 sprite_draw * d = context->sprite_draw_list + context->cur_slot; |
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67 |
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68 uint16_t dir; |
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69 int16_t x; |
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70 if (d->h_flip) { |
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71 x = d->x_pos + 7; |
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72 dir = -1; |
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73 } else { |
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74 x = d->x_pos; |
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75 dir = 1; |
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76 } |
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77 //printf("Draw Slot %d of %d, Rendering sprite cell from %X to x: %d\n", context->cur_slot, context->sprite_draws, d->address, x); |
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78 context->cur_slot--; |
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79 for (uint16_t address = d->address; address != ((d->address+4) & 0xFFFF); address++) { |
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80 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
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81 context->linebuf[x] = (context->vdpmem[address] >> 4) | d->pal_priority; |
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82 } |
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83 x += dir; |
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84 if (x >= 0 && x < 320 && !(context->linebuf[x] & 0xF)) { |
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85 context->linebuf[x] = (context->vdpmem[address] & 0xF) | d->pal_priority; |
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86 } |
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87 x += dir; |
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88 } |
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89 } |
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90 } |
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91 |
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92 void vdp_print_sprite_table(vdp_context * context) |
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93 { |
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94 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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95 uint16_t current_index = 0; |
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96 uint8_t count = 0; |
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97 do { |
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98 uint16_t address = current_index * 8 + sat_address; |
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99 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * 8; |
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100 uint8_t width = (((context->vdpmem[address+2] >> 2) & 0x3) + 1) * 8; |
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101 int16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & 0x1FF; |
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102 int16_t x = ((context->vdpmem[address+ 6] & 0x3) << 8 | context->vdpmem[address + 7]) & 0x1FF; |
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103 uint16_t link = context->vdpmem[address+3] & 0x7F; |
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104 uint8_t pal = context->vdpmem[address + 4] >> 5 & 0x3; |
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105 uint8_t pri = context->vdpmem[address + 4] >> 7; |
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106 uint16_t pattern = ((context->vdpmem[address + 4] << 8 | context->vdpmem[address + 5]) & 0x7FF) << 5; |
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107 //printf("Sprite %d: X=%d(%d), Y=%d(%d), Width=%u, Height=%u, Link=%u, Pal=%u, Pri=%u, Pat=%X\n", current_index, x, x-128, y, y-128, width, height, link, pal, pri, pattern); |
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108 current_index = link; |
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109 count++; |
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110 } while (current_index != 0 && count < 80); |
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111 } |
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112 |
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113 void vdp_print_reg_explain(vdp_context * context) |
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114 { |
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115 char * hscroll[] = {"full", "7-line", "cell", "line"}; |
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116 printf("**Mode Group**\n" |
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117 "00: %.2X | H-ints %s, Pal Select %d, HVC latch %s, Display gen %s\n" |
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118 "01: %.2X | Display %s, V-ints %s, Height: %d, Mode %d\n" |
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119 "0B: %.2X | E-ints %s, V-Scroll: %s, H-Scroll: %s\n" |
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120 "0C: %.2X | Width: %d, Shadow/Highlight: %s\n", |
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121 context->regs[REG_MODE_1], context->regs[REG_MODE_1] & BIT_HINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_PAL_SEL != 0, |
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122 context->regs[REG_MODE_1] & BIT_HVC_LATCH ? "enabled" : "disabled", context->regs[REG_MODE_1] & BIT_DISP_DIS ? "disabled" : "enabled", |
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123 context->regs[REG_MODE_2], context->regs[REG_MODE_2] & BIT_DISP_EN ? "enabled" : "disabled", context->regs[REG_MODE_2] & BIT_VINT_EN ? "enabled" : "disabled", |
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124 context->regs[REG_MODE_2] & BIT_PAL ? 30 : 28, context->regs[REG_MODE_2] & BIT_MODE_5 ? 5 : 4, |
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125 context->regs[REG_MODE_3], context->regs[REG_MODE_3] & BIT_EINT_EN ? "enabled" : "disabled", context->regs[REG_MODE_3] & BIT_VSCROLL ? "2 cell" : "full", |
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126 hscroll[context->regs[REG_MODE_3] & 0x3], |
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127 context->regs[REG_MODE_4], context->regs[REG_MODE_4] & BIT_H40 ? 40 : 32, context->regs[REG_MODE_4] & BIT_HILIGHT ? "enabled" : "disabled"); |
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128 printf("\n**Table Group**\n" |
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129 "02: %.2X | Scroll A Name Table: $%.4X\n" |
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130 "03: %.2X | Window Name Table: $%.4X\n" |
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131 "04: %.2X | Scroll B Name Table: $%.4X\n" |
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132 "05: %.2X | Sprite Attribute Table: $%.4X\n" |
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133 "0D: %.2X | HScroll Data Table: $%.4X\n", |
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134 context->regs[REG_SCROLL_A], (context->regs[REG_SCROLL_A] & 0x38) << 10, |
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135 context->regs[REG_WINDOW], (context->regs[REG_WINDOW] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3C : 0x3E)) << 10, |
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136 context->regs[REG_SCROLL_B], (context->regs[REG_SCROLL_B] & 0x7) << 13, |
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137 context->regs[REG_SAT], (context->regs[REG_SAT] & (context->regs[REG_MODE_4] & BIT_H40 ? 0x3E : 0x3F)) << 9, |
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138 context->regs[REG_HSCROLL], (context->regs[REG_HSCROLL] & 0x1F) << 10); |
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139 char * sizes[] = {"32", "64", "invalid", "128"}; |
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140 printf("\n**Misc Group**\n" |
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141 "07: %.2X | Backdrop Color: $%X\n" |
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142 "0A: %.2X | H-Int Counter: %u\n" |
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143 "0F: %.2X | Auto-increment: $%X\n" |
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144 "10: %.2X | Scroll A/B Size: %sx%s\n", |
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145 context->regs[REG_BG_COLOR], context->regs[REG_BG_COLOR] & 0x3F, |
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146 context->regs[REG_HINT], context->regs[REG_HINT], |
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147 context->regs[REG_AUTOINC], context->regs[REG_AUTOINC], |
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148 context->regs[REG_SCROLL], sizes[context->regs[REG_SCROLL] & 0x3], sizes[context->regs[REG_SCROLL] >> 4 & 0x3]); |
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149 |
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150 //TODO: Window Group, DMA Group |
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151 } |
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152 |
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153 void scan_sprite_table(uint32_t line, vdp_context * context) |
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154 { |
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155 if (context->sprite_index && context->slot_counter) { |
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156 line += 1; |
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157 line &= 0xFF; |
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158 context->sprite_index &= 0x7F; |
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159 if (context->latched_mode & BIT_H40) { |
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160 if (context->sprite_index >= MAX_SPRITES_FRAME) { |
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161 context->sprite_index = 0; |
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162 return; |
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163 } |
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164 } else if(context->sprite_index >= MAX_SPRITES_FRAME_H32) { |
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165 context->sprite_index = 0; |
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166 return; |
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167 } |
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168 //TODO: Read from SAT cache rather than from VRAM |
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169 uint16_t sat_address = (context->regs[REG_SAT] & 0x7F) << 9; |
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170 uint16_t address = context->sprite_index * 8 + sat_address; |
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180
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171 line += 128; |
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172 uint16_t y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & 0x1FF; |
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173 uint8_t height = ((context->vdpmem[address+2] & 0x3) + 1) * 8; |
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174 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
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175 if (y <= line && line < (y + height)) { |
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176 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
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177 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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178 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
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180
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179 context->sprite_info_list[context->slot_counter].y = y-128; |
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180 } |
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181 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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182 if (context->sprite_index && context->slot_counter) |
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183 { |
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184 address = context->sprite_index * 8 + sat_address; |
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185 y = ((context->vdpmem[address] & 0x3) << 8 | context->vdpmem[address+1]) & 0x1FF; |
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186 height = ((context->vdpmem[address+2] & 0x3) + 1) * 8; |
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187 //printf("Sprite %d | y: %d, height: %d\n", context->sprite_index, y, height); |
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188 if (y <= line && line < (y + height)) { |
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189 //printf("Sprite %d at y: %d with height %d is on line %d\n", context->sprite_index, y, height, line); |
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190 context->sprite_info_list[--(context->slot_counter)].size = context->vdpmem[address+2]; |
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191 context->sprite_info_list[context->slot_counter].index = context->sprite_index; |
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180
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192 context->sprite_info_list[context->slot_counter].y = y-128; |
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193 } |
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194 context->sprite_index = context->vdpmem[address+3] & 0x7F; |
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195 } |
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196 } |
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197 } |
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198 |
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199 void read_sprite_x(uint32_t line, vdp_context * context) |
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200 { |
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34
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201 if (context->cur_slot >= context->slot_counter) { |
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202 if (context->sprite_draws) { |
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203 line += 1; |
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204 line &= 0xFF; |
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205 //in tiles |
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206 uint8_t width = ((context->sprite_info_list[context->cur_slot].size >> 2) & 0x3) + 1; |
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207 //in pixels |
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208 uint8_t height = ((context->sprite_info_list[context->cur_slot].size & 0x3) + 1) * 8; |
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209 uint16_t att_addr = ((context->regs[REG_SAT] & 0x7F) << 9) + context->sprite_info_list[context->cur_slot].index * 8 + 4; |
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210 uint16_t tileinfo = (context->vdpmem[att_addr] << 8) | context->vdpmem[att_addr+1]; |
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211 uint8_t pal_priority = (tileinfo >> 9) & 0x70; |
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212 uint8_t row; |
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213 if (tileinfo & MAP_BIT_V_FLIP) { |
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214 row = (context->sprite_info_list[context->cur_slot].y + height - 1) - line; |
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215 } else { |
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216 row = line-context->sprite_info_list[context->cur_slot].y; |
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217 } |
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218 uint16_t address = ((tileinfo & 0x7FF) << 5) + row * 4; |
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219 int16_t x = ((context->vdpmem[att_addr+ 2] & 0x3) << 8 | context->vdpmem[att_addr + 3]) & 0x1FF; |
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220 if (x) { |
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221 context->flags |= FLAG_CAN_MASK; |
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222 } else if(context->flags & (FLAG_CAN_MASK | FLAG_DOT_OFLOW)) { |
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223 context->flags |= FLAG_MASKED; |
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224 } |
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225 |
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226 context->flags &= ~FLAG_DOT_OFLOW; |
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227 int16_t i; |
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228 if (context->flags & FLAG_MASKED) { |
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229 for (i=0; i < width && context->sprite_draws; i++) { |
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230 --context->sprite_draws; |
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231 context->sprite_draw_list[context->sprite_draws].x_pos = -128; |
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232 } |
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233 } else { |
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234 x -= 128; |
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235 int16_t base_x = x; |
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236 int16_t dir; |
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237 if (tileinfo & MAP_BIT_H_FLIP) { |
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238 x += (width-1) * 8; |
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239 dir = -8; |
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240 } else { |
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241 dir = 8; |
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242 } |
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243 //printf("Sprite %d | x: %d, y: %d, width: %d, height: %d, pal_priority: %X, row: %d, tile addr: %X\n", context->sprite_info_list[context->cur_slot].index, x, context->sprite_info_list[context->cur_slot].y, width, height, pal_priority, row, address); |
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244 for (i=0; i < width && context->sprite_draws; i++, x += dir) { |
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245 --context->sprite_draws; |
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246 context->sprite_draw_list[context->sprite_draws].address = address + i * height * 4; |
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247 context->sprite_draw_list[context->sprite_draws].x_pos = x; |
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248 context->sprite_draw_list[context->sprite_draws].pal_priority = pal_priority; |
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249 context->sprite_draw_list[context->sprite_draws].h_flip = (tileinfo & MAP_BIT_H_FLIP) ? 1 : 0; |
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250 } |
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251 } |
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252 if (i < width) { |
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253 context->flags |= FLAG_DOT_OFLOW; |
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254 } |
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255 context->cur_slot--; |
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256 } else { |
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257 context->flags |= FLAG_DOT_OFLOW; |
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258 } |
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259 } |
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260 } |
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261 |
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262 #define VRAM_READ 0 |
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263 #define VRAM_WRITE 1 |
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264 #define CRAM_READ 8 |
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265 #define CRAM_WRITE 3 |
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266 #define VSRAM_READ 4 |
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267 #define VSRAM_WRITE 5 |
| 75 | 268 #define DMA_START 0x20 |
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269 |
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270 void external_slot(vdp_context * context) |
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271 { |
| 75 | 272 //TODO: Figure out what happens if CD bit 4 is not set in DMA copy mode |
| 273 //TODO: Figure out what happens when CD:0-3 is not set to a write mode in DMA operations | |
| 274 //TODO: Figure out what happens if DMA gets disabled part way through a DMA fill or DMA copy | |
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275 if(context->flags & FLAG_DMA_RUN) { |
| 75 | 276 uint16_t dma_len; |
| 277 switch(context->regs[REG_DMASRC_H] & 0xC0) | |
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278 { |
| 75 | 279 //68K -> VDP |
| 280 case 0: | |
| 281 case 0x40: | |
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282 switch(context->dma_cd & 0xF) |
| 75 | 283 { |
| 284 case VRAM_WRITE: | |
| 285 if (context->flags & FLAG_DMA_PROG) { | |
| 286 context->vdpmem[context->address ^ 1] = context->dma_val; | |
| 287 context->flags &= ~FLAG_DMA_PROG; | |
| 288 } else { | |
| 289 context->dma_val = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | |
| 290 context->vdpmem[context->address] = context->dma_val >> 8; | |
| 291 context->flags |= FLAG_DMA_PROG; | |
| 292 } | |
| 293 break; | |
| 294 case CRAM_WRITE: | |
| 295 context->cram[(context->address/2) & (CRAM_SIZE-1)] = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | |
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296 //printf("CRAM DMA | %X set to %X from %X at %d\n", (context->address/2) & (CRAM_SIZE-1), context->cram[(context->address/2) & (CRAM_SIZE-1)], (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->cycles); |
| 75 | 297 break; |
| 298 case VSRAM_WRITE: | |
| 299 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 300 context->vsram[(context->address/2) & 63] = read_dma_value((context->regs[REG_DMASRC_H] << 16) | (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); | |
| 301 } | |
| 302 break; | |
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303 } |
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304 break; |
| 75 | 305 //Fill |
| 306 case 0x80: | |
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307 switch(context->dma_cd & 0xF) |
| 75 | 308 { |
| 309 case VRAM_WRITE: | |
| 310 //Charles MacDonald's VDP doc says that the low byte gets written first | |
| 142 | 311 context->vdpmem[context->address] = context->dma_val; |
| 312 context->dma_val = (context->dma_val << 8) | ((context->dma_val >> 8) & 0xFF); | |
| 75 | 313 break; |
| 314 case CRAM_WRITE: | |
| 315 context->cram[(context->address/2) & (CRAM_SIZE-1)] = context->dma_val; | |
| 316 break; | |
| 317 case VSRAM_WRITE: | |
| 318 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 319 context->vsram[(context->address/2) & 63] = context->dma_val; | |
| 320 } | |
| 321 break; | |
| 322 } | |
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323 break; |
| 75 | 324 //Copy |
| 325 case 0xC0: | |
| 326 if (context->flags & FLAG_DMA_PROG) { | |
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327 switch(context->dma_cd & 0xF) |
| 75 | 328 { |
| 329 case VRAM_WRITE: | |
| 330 context->vdpmem[context->address] = context->dma_val; | |
| 331 break; | |
| 332 case CRAM_WRITE: | |
| 333 context->cram[(context->address/2) & (CRAM_SIZE-1)] = context->dma_val; | |
| 334 break; | |
| 335 case VSRAM_WRITE: | |
| 336 if (((context->address/2) & 63) < VSRAM_SIZE) { | |
| 337 context->vsram[(context->address/2) & 63] = context->dma_val; | |
| 338 } | |
| 339 break; | |
| 340 } | |
| 341 context->flags &= ~FLAG_DMA_PROG; | |
| 342 } else { | |
| 343 //I assume, that DMA copy copies from the same RAM as the destination | |
| 344 //but it's possible I'm mistaken | |
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345 switch(context->dma_cd & 0xF) |
| 75 | 346 { |
| 347 case VRAM_WRITE: | |
| 348 context->dma_val = context->vdpmem[(context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]]; | |
| 349 break; | |
| 350 case CRAM_WRITE: | |
| 351 context->dma_val = context->cram[context->regs[REG_DMASRC_L] & (CRAM_SIZE-1)]; | |
| 352 break; | |
| 353 case VSRAM_WRITE: | |
| 354 if ((context->regs[REG_DMASRC_L] & 63) < VSRAM_SIZE) { | |
| 355 context->dma_val = context->vsram[context->regs[REG_DMASRC_L] & 63]; | |
| 356 } else { | |
| 357 context->dma_val = 0; | |
| 358 } | |
| 359 break; | |
| 360 } | |
| 361 context->flags |= FLAG_DMA_PROG; | |
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362 } |
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363 break; |
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364 } |
| 75 | 365 if (!(context->flags & FLAG_DMA_PROG)) { |
| 366 context->address += context->regs[REG_AUTOINC]; | |
| 367 context->regs[REG_DMASRC_L] += 1; | |
| 135 | 368 if (!context->regs[REG_DMASRC_L]) { |
| 369 context->regs[REG_DMASRC_M] += 1; | |
| 370 } | |
| 75 | 371 dma_len = ((context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]) - 1; |
| 372 context->regs[REG_DMALEN_H] = dma_len >> 8; | |
| 373 context->regs[REG_DMALEN_L] = dma_len; | |
| 374 if (!dma_len) { | |
| 375 context->flags &= ~FLAG_DMA_RUN; | |
| 376 } | |
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377 } |
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378 } else { |
| 75 | 379 fifo_entry * start = (context->fifo_end - FIFO_SIZE); |
| 380 if (context->fifo_cur != start && start->cycle <= context->cycles) { | |
| 381 if ((context->regs[REG_MODE_2] & BIT_DMA_ENABLE) && (context->cd & DMA_START)) { | |
| 382 context->flags |= FLAG_DMA_RUN; | |
| 383 context->dma_val = start->value; | |
| 138 | 384 context->address = start->address; //undo auto-increment |
|
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385 context->dma_cd = context->cd; |
| 75 | 386 } else { |
| 138 | 387 switch (start->cd & 0xF) |
| 75 | 388 { |
| 389 case VRAM_WRITE: | |
| 390 if (start->partial) { | |
| 391 //printf("VRAM Write: %X to %X\n", start->value, context->address ^ 1); | |
| 138 | 392 context->vdpmem[start->address ^ 1] = start->value; |
| 75 | 393 } else { |
| 394 //printf("VRAM Write High: %X to %X\n", start->value >> 8, context->address); | |
| 138 | 395 context->vdpmem[start->address] = start->value >> 8; |
| 75 | 396 start->partial = 1; |
| 397 //skip auto-increment and removal of entry from fifo | |
| 398 return; | |
| 399 } | |
| 400 break; | |
| 401 case CRAM_WRITE: | |
|
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402 //printf("CRAM Write | %X to %X\n", start->value, (start->address/2) & (CRAM_SIZE-1)); |
| 138 | 403 context->cram[(start->address/2) & (CRAM_SIZE-1)] = start->value; |
| 75 | 404 break; |
| 405 case VSRAM_WRITE: | |
| 138 | 406 if (((start->address/2) & 63) < VSRAM_SIZE) { |
| 75 | 407 //printf("VSRAM Write: %X to %X\n", start->value, context->address); |
| 138 | 408 context->vsram[(start->address/2) & 63] = start->value; |
| 75 | 409 } |
| 410 break; | |
| 411 } | |
| 138 | 412 //context->address += context->regs[REG_AUTOINC]; |
| 75 | 413 } |
| 414 fifo_entry * cur = start+1; | |
| 415 if (cur < context->fifo_cur) { | |
| 416 memmove(start, cur, sizeof(fifo_entry) * (context->fifo_cur - cur)); | |
| 417 } | |
| 418 context->fifo_cur -= 1; | |
| 419 } else { | |
| 420 context->flags |= FLAG_UNUSED_SLOT; | |
| 421 } | |
|
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422 } |
|
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423 } |
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424 |
| 40 | 425 #define WINDOW_RIGHT 0x80 |
| 426 #define WINDOW_DOWN 0x80 | |
| 427 | |
|
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428 void read_map_scroll(uint16_t column, uint16_t vsram_off, uint32_t line, uint16_t address, uint16_t hscroll_val, vdp_context * context) |
|
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429 { |
| 40 | 430 if (!vsram_off) { |
| 431 uint16_t left_col, right_col; | |
| 432 if (context->regs[REG_WINDOW_H] & WINDOW_RIGHT) { | |
|
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433 left_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; |
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434 right_col = 42; |
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435 } else { |
| 40 | 436 left_col = 0; |
| 437 right_col = (context->regs[REG_WINDOW_H] & 0x1F) * 2; | |
| 438 if (right_col) { | |
| 439 right_col += 2; | |
| 440 } | |
| 441 } | |
|
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442 uint16_t top_line, bottom_line; |
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443 if (context->regs[REG_WINDOW_V] & WINDOW_DOWN) { |
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444 top_line = (context->regs[REG_WINDOW_V] & 0x1F) * 8; |
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445 bottom_line = 241; |
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446 } else { |
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447 top_line = 0; |
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448 bottom_line = (context->regs[REG_WINDOW_V] & 0x1F) * 8; |
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449 } |
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450 if ((column >= left_col && column < right_col) || (line >= top_line && line < bottom_line)) { |
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451 uint16_t address = context->regs[REG_WINDOW] << 10; |
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452 uint16_t line_offset, offset, mask; |
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453 if (context->latched_mode & BIT_H40) { |
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454 address &= 0xF000; |
|
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455 line_offset = (((line) / 8) * 64 * 2) & 0xFFF; |
|
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456 mask = 0x7F; |
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457 |
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458 } else { |
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459 address &= 0xF800; |
|
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460 line_offset = (((line) / 8) * 32 * 2) & 0xFFF; |
|
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461 mask = 0x3F; |
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462 } |
|
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463 offset = address + line_offset + (((column - 2) * 2) & mask); |
|
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464 context->col_1 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
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465 //printf("Window | top: %d, bot: %d, left: %d, right: %d, base: %X, line: %X offset: %X, tile: %X, reg: %X\n", top_line, bottom_line, left_col, right_col, address, line_offset, offset, ((context->col_1 & 0x3FF) << 5), context->regs[REG_WINDOW]); |
|
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466 offset = address + line_offset + (((column - 1) * 2) & mask); |
|
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467 context->col_2 = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
|
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468 context->v_offset = (line) & 0x7; |
|
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469 context->flags |= FLAG_WINDOW; |
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470 return; |
| 40 | 471 } |
| 472 context->flags &= ~FLAG_WINDOW; | |
| 473 } | |
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474 uint16_t vscroll; |
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475 switch(context->regs[REG_SCROLL] & 0x30) |
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476 { |
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477 case 0: |
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478 vscroll = 0xFF; |
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479 break; |
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480 case 0x10: |
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481 vscroll = 0x1FF; |
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482 break; |
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483 case 0x20: |
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484 //TODO: Verify this behavior |
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485 vscroll = 0; |
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486 break; |
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487 case 0x30: |
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488 vscroll = 0x3FF; |
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489 break; |
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490 } |
|
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491 vscroll &= (context->vsram[(context->regs[REG_MODE_3] & BIT_VSCROLL ? column : 0) + vsram_off] + line); |
|
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492 context->v_offset = vscroll & 0x7; |
|
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diff
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493 //printf("%s | line %d, vsram: %d, vscroll: %d, v_offset: %d\n",(vsram_off ? "B" : "A"), line, context->vsram[context->regs[REG_MODE_3] & 0x4 ? column : 0], vscroll, context->v_offset); |
|
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494 vscroll /= 8; |
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495 uint16_t hscroll_mask; |
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496 uint16_t v_mul; |
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497 switch(context->regs[REG_SCROLL] & 0x3) |
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498 { |
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499 case 0: |
|
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diff
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|
500 hscroll_mask = 0x1F; |
|
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501 v_mul = 64; |
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502 break; |
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503 case 0x1: |
|
39
3c69319269ef
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38
diff
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|
504 hscroll_mask = 0x3F; |
|
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505 v_mul = 128; |
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506 break; |
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507 case 0x2: |
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508 //TODO: Verify this behavior |
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509 hscroll_mask = 0; |
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510 v_mul = 0; |
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511 break; |
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512 case 0x3: |
|
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|
513 hscroll_mask = 0x7F; |
|
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514 v_mul = 256; |
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515 break; |
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516 } |
| 28 | 517 uint16_t hscroll, offset; |
| 518 for (int i = 0; i < 2; i++) { | |
|
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diff
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519 hscroll = (column - 2 + i - ((hscroll_val/8) & 0xFFFE)) & hscroll_mask; |
|
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diff
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|
520 offset = address + ((vscroll * v_mul + hscroll*2) & 0x1FFF); |
|
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521 //printf("%s | line: %d, col: %d, x: %d, hs_mask %X, scr reg: %X, tbl addr: %X\n", (vsram_off ? "B" : "A"), line, (column-2+i), hscroll, hscroll_mask, context->regs[REG_SCROLL], offset); |
| 28 | 522 uint16_t col_val = (context->vdpmem[offset] << 8) | context->vdpmem[offset+1]; |
| 523 if (i) { | |
| 524 context->col_2 = col_val; | |
| 525 } else { | |
| 526 context->col_1 = col_val; | |
| 527 } | |
| 528 } | |
|
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529 } |
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530 |
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531 void read_map_scroll_a(uint16_t column, uint32_t line, vdp_context * context) |
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532 { |
|
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|
533 read_map_scroll(column, 0, line, (context->regs[REG_SCROLL_A] & 0x38) << 10, context->hscroll_a, context); |
|
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534 } |
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535 |
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536 void read_map_scroll_b(uint16_t column, uint32_t line, vdp_context * context) |
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|
537 { |
|
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|
538 read_map_scroll(column, 1, line, (context->regs[REG_SCROLL_B] & 0x7) << 13, context->hscroll_b, context); |
|
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539 } |
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|
540 |
|
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541 void render_map(uint16_t col, uint8_t * tmp_buf, vdp_context * context) |
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|
542 { |
|
42
6653e67a6811
Fix bug in tile address masking. Remove some debug code from window plane.
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41
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543 uint16_t address = ((col & 0x7FF) << 5); |
|
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544 if (col & MAP_BIT_V_FLIP) { |
|
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42
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545 address += 28 - 4 * context->v_offset; |
|
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|
546 } else { |
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547 address += 4 * context->v_offset; |
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|
548 } |
|
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549 uint16_t pal_priority = (col >> 9) & 0x70; |
|
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|
550 int32_t dir; |
|
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diff
changeset
|
551 if (col & MAP_BIT_H_FLIP) { |
|
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552 tmp_buf += 7; |
|
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|
553 dir = -1; |
|
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diff
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|
554 } else { |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
555 dir = 1; |
|
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Mike Pavone <pavone@retrodev.com>
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|
556 } |
|
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parents:
diff
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|
557 for (uint32_t i=0; i < 4; i++, address++) |
|
f664eeb55cb4
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|
558 { |
|
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diff
changeset
|
559 *tmp_buf = pal_priority | (context->vdpmem[address] >> 4); |
|
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|
560 tmp_buf += dir; |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
561 *tmp_buf = pal_priority | (context->vdpmem[address] & 0xF); |
|
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changeset
|
562 tmp_buf += dir; |
|
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|
563 } |
|
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|
564 } |
|
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
565 |
|
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Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
566 void render_map_1(vdp_context * context) |
|
f664eeb55cb4
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parents:
diff
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|
567 { |
|
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
568 render_map(context->col_1, context->tmp_buf_a+SCROLL_BUFFER_DRAW, context); |
|
20
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diff
changeset
|
569 } |
|
f664eeb55cb4
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diff
changeset
|
570 |
|
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parents:
diff
changeset
|
571 void render_map_2(vdp_context * context) |
|
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Mike Pavone <pavone@retrodev.com>
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diff
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|
572 { |
|
39
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Mike Pavone <pavone@retrodev.com>
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38
diff
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|
573 render_map(context->col_2, context->tmp_buf_a+SCROLL_BUFFER_DRAW+8, context); |
|
20
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|
574 } |
|
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changeset
|
575 |
|
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diff
changeset
|
576 void render_map_3(vdp_context * context) |
|
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|
577 { |
|
39
3c69319269ef
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38
diff
changeset
|
578 render_map(context->col_1, context->tmp_buf_b+SCROLL_BUFFER_DRAW, context); |
|
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Mike Pavone <pavone@retrodev.com>
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|
579 } |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
580 |
|
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parents:
diff
changeset
|
581 void render_map_output(uint32_t line, int32_t col, vdp_context * context) |
|
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parents:
diff
changeset
|
582 { |
|
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parents:
diff
changeset
|
583 if (line >= 240) { |
|
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
584 return; |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
585 } |
|
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
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38
diff
changeset
|
586 render_map(context->col_2, context->tmp_buf_b+SCROLL_BUFFER_DRAW+8, context); |
|
20
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parents:
diff
changeset
|
587 uint16_t *dst, *end; |
|
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parents:
diff
changeset
|
588 uint8_t *sprite_buf, *plane_a, *plane_b; |
|
f664eeb55cb4
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parents:
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changeset
|
589 if (col) |
|
f664eeb55cb4
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
590 { |
|
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Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
591 col-=2; |
|
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parents:
diff
changeset
|
592 dst = context->framebuf + line * 320 + col * 8; |
|
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parents:
diff
changeset
|
593 sprite_buf = context->linebuf + col * 8; |
|
43
3fc57e1a2c56
Add debug render mode and fix vertical flip bit for bg tiles
Mike Pavone <pavone@retrodev.com>
parents:
42
diff
changeset
|
594 uint16_t a_src; |
| 40 | 595 if (context->flags & FLAG_WINDOW) { |
| 596 plane_a = context->tmp_buf_a + SCROLL_BUFFER_DRAW; | |
|
43
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Add debug render mode and fix vertical flip bit for bg tiles
Mike Pavone <pavone@retrodev.com>
parents:
42
diff
changeset
|
597 a_src = FBUF_SRC_W; |
| 40 | 598 } else { |
| 599 plane_a = context->tmp_buf_a + SCROLL_BUFFER_DRAW - (context->hscroll_a & 0xF); | |
|
43
3fc57e1a2c56
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Mike Pavone <pavone@retrodev.com>
parents:
42
diff
changeset
|
600 a_src = FBUF_SRC_A; |
| 40 | 601 } |
|
39
3c69319269ef
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Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
602 plane_b = context->tmp_buf_b + SCROLL_BUFFER_DRAW - (context->hscroll_b & 0xF); |
| 30 | 603 end = dst + 16; |
|
43
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Add debug render mode and fix vertical flip bit for bg tiles
Mike Pavone <pavone@retrodev.com>
parents:
42
diff
changeset
|
604 uint16_t src; |
| 30 | 605 //printf("A | tmp_buf offset: %d\n", 8 - (context->hscroll_a & 0x7)); |
|
230
d3266cee02c9
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parents:
191
diff
changeset
|
606 |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
607 if (context->regs[REG_MODE_4] & BIT_HILIGHT) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
608 for (; dst < end; ++plane_a, ++plane_b, ++sprite_buf, ++dst) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
609 uint8_t pixel; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
610 |
|
d3266cee02c9
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191
diff
changeset
|
611 src = 0; |
|
d3266cee02c9
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191
diff
changeset
|
612 uint8_t sprite_color = *sprite_buf & 0x3F; |
|
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parents:
191
diff
changeset
|
613 if (sprite_color == 0x3E || sprite_color == 0x3F) { |
|
232
54873acb982e
Shadow and higlight operators were switched
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parents:
230
diff
changeset
|
614 if (sprite_color == 0x3F) { |
|
54873acb982e
Shadow and higlight operators were switched
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230
diff
changeset
|
615 src = FBUF_SHADOW; |
|
230
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191
diff
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|
616 } else { |
|
232
54873acb982e
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230
diff
changeset
|
617 src = FBUF_HILIGHT; |
|
230
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Implemented shadow hilight mode.
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191
diff
changeset
|
618 } |
|
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Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
619 if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
620 pixel = *plane_a; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
621 src |= a_src; |
|
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Implemented shadow hilight mode.
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191
diff
changeset
|
622 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
623 pixel = *plane_b; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
624 src |= FBUF_SRC_B; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
625 } else if (*plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
626 pixel = *plane_a; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
627 src |= a_src; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
628 } else if (*plane_b & 0xF){ |
|
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191
diff
changeset
|
629 pixel = *plane_b; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
630 src |= FBUF_SRC_B; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
631 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
632 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
633 src |= FBUF_SRC_BG; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
634 } |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
635 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
636 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
637 pixel = *sprite_buf; |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
638 src = FBUF_SRC_S; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
639 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
640 pixel = *plane_a; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
641 src = a_src; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
642 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
643 pixel = *plane_b; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
644 src = FBUF_SRC_B; |
|
233
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232
diff
changeset
|
645 } else { |
|
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232
diff
changeset
|
646 if (!(*plane_a & BUF_BIT_PRIORITY || *plane_a & BUF_BIT_PRIORITY)) { |
|
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232
diff
changeset
|
647 src = FBUF_SHADOW; |
|
230
d3266cee02c9
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191
diff
changeset
|
648 } |
|
233
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232
diff
changeset
|
649 if (*sprite_buf & 0xF) { |
|
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232
diff
changeset
|
650 pixel = *sprite_buf; |
|
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232
diff
changeset
|
651 if (*sprite_buf & 0xF == 0xE) { |
|
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232
diff
changeset
|
652 src = FBUF_SRC_S; |
|
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232
diff
changeset
|
653 } else { |
|
9d10669f2579
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232
diff
changeset
|
654 src |= FBUF_SRC_S; |
|
9d10669f2579
Less broken implementation of shadow/highlight
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parents:
232
diff
changeset
|
655 } |
|
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232
diff
changeset
|
656 } else if (*plane_a & 0xF) { |
|
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232
diff
changeset
|
657 pixel = *plane_a; |
|
9d10669f2579
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232
diff
changeset
|
658 src |= a_src; |
|
9d10669f2579
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232
diff
changeset
|
659 } else if (*plane_b & 0xF){ |
|
9d10669f2579
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232
diff
changeset
|
660 pixel = *plane_b; |
|
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|
661 src |= FBUF_SRC_B; |
|
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232
diff
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|
662 } else { |
|
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232
diff
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|
663 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
9d10669f2579
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232
diff
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|
664 src |= FBUF_SRC_BG; |
|
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232
diff
changeset
|
665 } |
|
230
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
666 } |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
667 } |
|
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
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|
668 *dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
|
20
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diff
changeset
|
669 } |
|
230
d3266cee02c9
Implemented shadow hilight mode.
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191
diff
changeset
|
670 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
671 for (; dst < end; ++plane_a, ++plane_b, ++sprite_buf, ++dst) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
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191
diff
changeset
|
672 uint8_t pixel; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
673 if (*sprite_buf & BUF_BIT_PRIORITY && *sprite_buf & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
674 pixel = *sprite_buf; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
675 src = FBUF_SRC_S; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
676 } else if (*plane_a & BUF_BIT_PRIORITY && *plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
677 pixel = *plane_a; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
678 src = a_src; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
679 } else if (*plane_b & BUF_BIT_PRIORITY && *plane_b & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
680 pixel = *plane_b; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
681 src = FBUF_SRC_B; |
|
d3266cee02c9
Implemented shadow hilight mode.
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parents:
191
diff
changeset
|
682 } else if (*sprite_buf & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
683 pixel = *sprite_buf; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
684 src = FBUF_SRC_S; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
685 } else if (*plane_a & 0xF) { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
686 pixel = *plane_a; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
687 src = a_src; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
688 } else if (*plane_b & 0xF){ |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
689 pixel = *plane_b; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
690 src = FBUF_SRC_B; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
691 } else { |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
692 pixel = context->regs[REG_BG_COLOR] & 0x3F; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
693 src = FBUF_SRC_BG; |
|
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
694 } |
|
291
eea3b118940d
Make sure all rendering operations mask CRAM with 0xEEE before using it
Mike Pavone <pavone@retrodev.com>
parents:
233
diff
changeset
|
695 *dst = (context->cram[pixel & 0x3F] & 0xEEE) | ((pixel & BUF_BIT_PRIORITY) ? FBUF_BIT_PRIORITY : 0) | src; |
|
230
d3266cee02c9
Implemented shadow hilight mode.
Mike Pavone <pavone@retrodev.com>
parents:
191
diff
changeset
|
696 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
697 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
698 } else { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
699 //dst = context->framebuf + line * 320; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
700 //sprite_buf = context->linebuf + col * 8; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
701 //plane_a = context->tmp_buf_a + 16 - (context->hscroll_a & 0x7); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
702 //plane_b = context->tmp_buf_b + 16 - (context->hscroll_b & 0x7); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
703 //end = dst + 8; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
704 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
705 |
| 40 | 706 uint16_t remaining; |
| 707 if (!(context->flags & FLAG_WINDOW)) { | |
| 708 remaining = context->hscroll_a & 0xF; | |
| 709 memcpy(context->tmp_buf_a + SCROLL_BUFFER_DRAW - remaining, context->tmp_buf_a + SCROLL_BUFFER_SIZE - remaining, remaining); | |
| 710 } | |
|
39
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
711 remaining = context->hscroll_b & 0xF; |
|
3c69319269ef
Horizontal scroll works correctly now. In particular, the SEGA logo in Vectorman has a nice smooth wave like it should
Mike Pavone <pavone@retrodev.com>
parents:
38
diff
changeset
|
712 memcpy(context->tmp_buf_b + SCROLL_BUFFER_DRAW - remaining, context->tmp_buf_b + SCROLL_BUFFER_SIZE - remaining, remaining); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
713 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
714 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
715 #define COLUMN_RENDER_BLOCK(column, startcyc) \ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
716 case startcyc:\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
717 read_map_scroll_a(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
718 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
719 case (startcyc+1):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
720 external_slot(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
721 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
722 case (startcyc+2):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
723 render_map_1(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
724 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
725 case (startcyc+3):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
726 render_map_2(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
727 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
728 case (startcyc+4):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
729 read_map_scroll_b(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
730 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
731 case (startcyc+5):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
732 read_sprite_x(line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
733 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
734 case (startcyc+6):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
735 render_map_3(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
736 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
737 case (startcyc+7):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
738 render_map_output(line, column, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
739 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
740 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
741 #define COLUMN_RENDER_BLOCK_REFRESH(column, startcyc) \ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
742 case startcyc:\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
743 read_map_scroll_a(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
744 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
745 case (startcyc+1):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
746 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
747 case (startcyc+2):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
748 render_map_1(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
749 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
750 case (startcyc+3):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
751 render_map_2(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
752 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
753 case (startcyc+4):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
754 read_map_scroll_b(column, line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
755 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
756 case (startcyc+5):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
757 read_sprite_x(line, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
758 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
759 case (startcyc+6):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
760 render_map_3(context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
761 break;\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
762 case (startcyc+7):\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
763 render_map_output(line, column, context);\ |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
764 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
765 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
766 void vdp_h40(uint32_t line, uint32_t linecyc, vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
767 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
768 uint16_t address; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
769 uint32_t mask; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
770 switch(linecyc) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
771 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
772 //sprite render to line buffer starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
773 case 0: |
|
26
a7c2b92d8056
Fix management of context->sprite_draws so the sprite layer only draws when it should
Mike Pavone <pavone@retrodev.com>
parents:
25
diff
changeset
|
774 context->cur_slot = MAX_DRAWS-1; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
775 memset(context->linebuf, 0, LINEBUF_SIZE); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
776 case 1: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
777 case 2: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
778 case 3: |
|
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
779 if (line == 0xFF) { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
780 external_slot(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
781 } else { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
782 render_sprite_cells(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
783 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
784 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
785 //sprite attribute table scan starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
786 case 4: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
787 render_sprite_cells( context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
788 context->sprite_index = 0x80; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
789 context->slot_counter = MAX_SPRITES_LINE; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
790 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
791 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
792 case 5: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
793 case 6: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
794 case 7: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
795 case 8: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
796 case 9: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
797 case 10: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
798 case 11: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
799 case 12: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
800 case 13: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
801 case 14: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
802 case 15: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
803 case 16: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
804 case 17: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
805 case 18: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
806 case 19: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
807 case 20: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
808 //!HSYNC asserted |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
809 case 21: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
810 case 22: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
811 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
812 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
813 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
814 case 23: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
815 external_slot(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
816 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
817 case 24: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
818 case 25: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
819 case 26: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
820 case 27: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
821 case 28: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
822 case 29: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
823 case 30: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
824 case 31: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
825 case 32: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
826 case 33: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
827 case 34: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
828 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
829 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
830 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
831 case 35: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
832 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
833 mask = 0; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
834 if (context->regs[REG_MODE_3] & 0x2) { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
835 mask |= 0xF8; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
836 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
837 if (context->regs[REG_MODE_3] & 0x1) { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
838 mask |= 0x7; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
839 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
840 line &= mask; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
841 address += line * 4; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
842 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
843 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
844 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
845 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
846 case 36: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
847 //!HSYNC high |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
848 case 37: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
849 case 38: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
850 case 39: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
851 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
852 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
853 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
854 case 40: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
855 read_map_scroll_a(0, line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
856 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
857 case 41: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
858 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
859 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
860 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
861 case 42: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
862 render_map_1(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
863 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
864 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
865 case 43: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
866 render_map_2(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
867 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
868 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
869 case 44: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
870 read_map_scroll_b(0, line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
871 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
872 case 45: |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
873 render_sprite_cells(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
874 scan_sprite_table(line, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
875 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
876 case 46: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
877 render_map_3(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
878 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
879 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
880 case 47: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
881 render_map_output(line, 0, context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
882 scan_sprite_table(line, context);//Just a guess |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
883 //reverse context slot counter so it counts the number of sprite slots |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
884 //filled rather than the number of available slots |
|
21
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
885 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; |
|
72ce60cb1711
Sprites somewhat less broken
Mike Pavone <pavone@retrodev.com>
parents:
20
diff
changeset
|
886 context->cur_slot = MAX_SPRITES_LINE-1; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
887 context->sprite_draws = MAX_DRAWS; |
|
36
04672c060062
Pass all sprite masking tests
Mike Pavone <pavone@retrodev.com>
parents:
35
diff
changeset
|
888 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
889 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
890 COLUMN_RENDER_BLOCK(2, 48) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
891 COLUMN_RENDER_BLOCK(4, 56) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
892 COLUMN_RENDER_BLOCK(6, 64) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
893 COLUMN_RENDER_BLOCK_REFRESH(8, 72) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
894 COLUMN_RENDER_BLOCK(10, 80) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
895 COLUMN_RENDER_BLOCK(12, 88) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
896 COLUMN_RENDER_BLOCK(14, 96) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
897 COLUMN_RENDER_BLOCK_REFRESH(16, 104) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
898 COLUMN_RENDER_BLOCK(18, 112) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
899 COLUMN_RENDER_BLOCK(20, 120) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
900 COLUMN_RENDER_BLOCK(22, 128) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
901 COLUMN_RENDER_BLOCK_REFRESH(24, 136) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
902 COLUMN_RENDER_BLOCK(26, 144) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
903 COLUMN_RENDER_BLOCK(28, 152) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
904 COLUMN_RENDER_BLOCK(30, 160) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
905 COLUMN_RENDER_BLOCK_REFRESH(32, 168) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
906 COLUMN_RENDER_BLOCK(34, 176) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
907 COLUMN_RENDER_BLOCK(36, 184) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
908 COLUMN_RENDER_BLOCK(38, 192) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
909 COLUMN_RENDER_BLOCK_REFRESH(40, 200) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
910 case 208: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
911 case 209: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
912 external_slot(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
913 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
914 default: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
915 //leftovers from HSYNC clock change nonsense |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
916 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
917 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
918 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
919 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
920 void vdp_h32(uint32_t line, uint32_t linecyc, vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
921 { |
| 37 | 922 uint16_t address; |
| 923 uint32_t mask; | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
924 switch(linecyc) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
925 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
926 //sprite render to line buffer starts |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
927 case 0: |
| 37 | 928 context->cur_slot = MAX_DRAWS_H32-1; |
| 929 memset(context->linebuf, 0, LINEBUF_SIZE); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
930 case 1: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
931 case 2: |
| 37 | 932 case 3: |
|
329
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
933 if (line == 0xFF) { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
934 external_slot(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
935 } else { |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
936 render_sprite_cells(context); |
|
fd5f6577db9b
Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
parents:
328
diff
changeset
|
937 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
938 break; |
| 37 | 939 //sprite attribute table scan starts |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
940 case 4: |
| 37 | 941 render_sprite_cells( context); |
| 942 context->sprite_index = 0x80; | |
| 943 context->slot_counter = MAX_SPRITES_LINE_H32; | |
| 944 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
945 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
946 case 5: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
947 case 6: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
948 case 7: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
949 case 8: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
950 case 9: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
951 case 10: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
952 case 11: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
953 case 12: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
954 case 13: |
| 37 | 955 render_sprite_cells(context); |
| 956 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
957 case 14: |
| 37 | 958 external_slot(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
959 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
960 case 15: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
961 case 16: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
962 case 17: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
963 case 18: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
964 case 19: |
| 37 | 965 //HSYNC start |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
966 case 20: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
967 case 21: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
968 case 22: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
969 case 23: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
970 case 24: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
971 case 25: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
972 case 26: |
| 37 | 973 render_sprite_cells(context); |
| 974 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
975 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
976 case 27: |
| 37 | 977 external_slot(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
978 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
979 case 28: |
| 37 | 980 address = (context->regs[REG_HSCROLL] & 0x3F) << 10; |
| 981 mask = 0; | |
| 982 if (context->regs[REG_MODE_3] & 0x2) { | |
| 983 mask |= 0xF8; | |
| 984 } | |
| 985 if (context->regs[REG_MODE_3] & 0x1) { | |
| 986 mask |= 0x7; | |
| 987 } | |
| 988 line &= mask; | |
| 989 address += line * 4; | |
| 990 context->hscroll_a = context->vdpmem[address] << 8 | context->vdpmem[address+1]; | |
| 991 context->hscroll_b = context->vdpmem[address+2] << 8 | context->vdpmem[address+3]; | |
| 992 //printf("%d: HScroll A: %d, HScroll B: %d\n", line, context->hscroll_a, context->hscroll_b); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
993 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
994 case 29: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
995 case 30: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
996 case 31: |
| 37 | 997 case 32: |
| 998 render_sprite_cells(context); | |
| 999 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1000 break; |
| 37 | 1001 //!HSYNC high |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1002 case 33: |
| 37 | 1003 read_map_scroll_a(0, line, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1004 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1005 case 34: |
| 37 | 1006 render_sprite_cells(context); |
| 1007 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1008 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1009 case 35: |
| 37 | 1010 render_map_1(context); |
| 1011 scan_sprite_table(line, context);//Just a guess | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1012 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1013 case 36: |
| 37 | 1014 render_map_2(context); |
| 1015 scan_sprite_table(line, context);//Just a guess | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1016 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1017 case 37: |
| 37 | 1018 read_map_scroll_b(0, line, context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1019 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1020 case 38: |
| 37 | 1021 render_sprite_cells(context); |
| 1022 scan_sprite_table(line, context); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1023 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1024 case 39: |
| 37 | 1025 render_map_3(context); |
| 1026 scan_sprite_table(line, context);//Just a guess | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1027 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1028 case 40: |
| 37 | 1029 render_map_output(line, 0, context); |
| 1030 scan_sprite_table(line, context);//Just a guess | |
| 1031 //reverse context slot counter so it counts the number of sprite slots | |
| 1032 //filled rather than the number of available slots | |
| 1033 //context->slot_counter = MAX_SPRITES_LINE - context->slot_counter; | |
| 1034 context->cur_slot = MAX_SPRITES_LINE_H32-1; | |
| 1035 context->sprite_draws = MAX_DRAWS_H32; | |
| 1036 context->flags &= (~FLAG_CAN_MASK & ~FLAG_MASKED); | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1037 break; |
| 37 | 1038 COLUMN_RENDER_BLOCK(2, 41) |
| 1039 COLUMN_RENDER_BLOCK(4, 49) | |
| 1040 COLUMN_RENDER_BLOCK(6, 57) | |
| 1041 COLUMN_RENDER_BLOCK_REFRESH(8, 65) | |
| 1042 COLUMN_RENDER_BLOCK(10, 73) | |
| 1043 COLUMN_RENDER_BLOCK(12, 81) | |
| 1044 COLUMN_RENDER_BLOCK(14, 89) | |
| 1045 COLUMN_RENDER_BLOCK_REFRESH(16, 97) | |
| 1046 COLUMN_RENDER_BLOCK(18, 105) | |
| 1047 COLUMN_RENDER_BLOCK(20, 113) | |
| 1048 COLUMN_RENDER_BLOCK(22, 121) | |
| 1049 COLUMN_RENDER_BLOCK_REFRESH(24, 129) | |
| 1050 COLUMN_RENDER_BLOCK(26, 137) | |
| 1051 COLUMN_RENDER_BLOCK(28, 145) | |
| 1052 COLUMN_RENDER_BLOCK(30, 153) | |
| 1053 COLUMN_RENDER_BLOCK_REFRESH(32, 161) | |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1054 case 169: |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1055 case 170: |
| 37 | 1056 external_slot(context); |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1057 break; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1058 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1059 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1060 void latch_mode(vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1061 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1062 context->latched_mode = (context->regs[REG_MODE_4] & 0x81) | (context->regs[REG_MODE_2] & BIT_PAL); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1063 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1064 |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1065 int is_refresh(vdp_context * context, uint32_t slot) |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1066 { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1067 if (context->latched_mode & BIT_H40) { |
|
189
806c3b7a6f2a
Fix background rendering when display is off and improve refresh cycle emulation so that direct color DMA demos work
Mike Pavone <pavone@retrodev.com>
parents:
180
diff
changeset
|
1068 //TODO: Figure out the exact behavior that reduces DMA slots for direct color DMA demos |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1069 return (slot == 37 || slot == 69 || slot == 102 || slot == 133 || slot == 165 || slot == 197 || slot >= 210 || (slot < 6 && (context->flags & FLAG_DMA_RUN) && ((context->dma_cd & 0xF) == CRAM_WRITE))); |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1070 } else { |
|
189
806c3b7a6f2a
Fix background rendering when display is off and improve refresh cycle emulation so that direct color DMA demos work
Mike Pavone <pavone@retrodev.com>
parents:
180
diff
changeset
|
1071 //TODO: Figure out which slots are refresh when display is off in 32-cell mode |
|
191
1b4d856b067a
Fixes for direct color dma stuff
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1072 //These numbers are guesses based on H40 numbers |
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1073 return (slot == 24 || slot == 56 || slot == 88 || slot == 120 || slot == 152 || (slot < 5 && (context->flags & FLAG_DMA_RUN) && ((context->dma_cd & 0xF) == CRAM_WRITE))); |
|
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1074 //The numbers below are the refresh slots during active display |
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1075 //return (slot == 66 || slot == 98 || slot == 130 || slot == 162); |
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1076 } |
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1077 } |
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1078 |
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1079 void check_render_bg(vdp_context * context, int32_t line, uint32_t slot) |
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1080 { |
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1081 if (line > 0) { |
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1082 line -= 1; |
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1083 uint16_t * start = NULL, *end = NULL; |
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1084 if (context->latched_mode & BIT_H40) { |
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1085 if (slot >= 50 && slot < 210) { |
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1086 uint32_t x = (slot-50)*2; |
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1087 start = context->framebuf + line * 320 + x; |
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1088 end = start + 2; |
|
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1089 } |
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1090 } else { |
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1091 if (slot >= 43 && slot < 171) { |
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1092 uint32_t x = (slot-43)*2; |
|
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1093 start = context->framebuf + line * 320 + x; |
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1094 end = start + 2; |
|
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1095 } |
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1096 } |
|
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1097 uint16_t color = (context->cram[context->regs[REG_BG_COLOR] & 0x3F] & 0xEEE); |
|
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1098 while (start != end) { |
|
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1099 *start = color; |
|
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1100 ++start; |
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1101 } |
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1102 } |
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1103 } |
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1104 |
|
20
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|
1105 void vdp_run_context(vdp_context * context, uint32_t target_cycles) |
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1106 { |
|
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1107 while(context->cycles < target_cycles) |
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1108 { |
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1109 uint32_t line = context->cycles / MCLKS_LINE; |
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|
1110 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
|
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1111 if (!line) { |
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|
1112 latch_mode(context); |
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1113 } |
|
317
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1114 uint32_t linecyc = context->cycles % MCLKS_LINE; |
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1115 if (linecyc == 0) { |
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1116 if (line <= 1 || line >= active_lines) { |
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1117 context->hint_counter = context->regs[REG_HINT]; |
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1118 } else if (context->hint_counter) { |
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|
1119 context->hint_counter--; |
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|
1120 } else { |
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|
1121 context->flags2 |= FLAG2_HINT_PENDING; |
|
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|
1122 context->hint_counter = context->regs[REG_HINT]; |
|
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1123 } |
|
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|
1124 } else if(line == active_lines) { |
|
328
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|
1125 uint32_t intcyc = context->latched_mode & BIT_H40 ? VINT_SLOTS_H40 * MCLKS_SLOT_H40 : VINT_SLOTS_H32 * MCLKS_SLOT_H32; |
|
317
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|
1126 if (linecyc == intcyc) { |
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|
1127 context->flags2 |= FLAG2_VINT_PENDING; |
|
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|
1128 } |
|
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|
1129 } |
|
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|
1130 uint32_t inccycles, slot; |
|
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1131 if (context->latched_mode & BIT_H40){ |
|
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1132 if (linecyc < MCLKS_SLOT_H40*HSYNC_SLOT_H40) { |
|
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1133 slot = linecyc/MCLKS_SLOT_H40; |
|
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1134 inccycles = MCLKS_SLOT_H40; |
|
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1135 } else if(linecyc < MCLK_WEIRD_END) { |
|
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1136 switch(linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)) |
|
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|
1137 { |
|
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|
1138 case 0: |
|
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|
1139 inccycles = 19; |
|
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|
1140 slot = 0; |
|
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|
1141 break; |
|
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|
1142 case 19: |
|
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|
1143 slot = 1; |
|
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|
1144 inccycles = 20; |
|
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|
1145 break; |
|
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|
1146 case 39: |
|
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|
1147 slot = 2; |
|
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|
1148 inccycles = 20; |
|
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|
1149 break; |
|
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|
1150 case 59: |
|
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|
1151 slot = 2; |
|
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|
1152 inccycles = 20; |
|
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|
1153 break; |
|
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|
1154 case 79: |
|
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|
1155 slot = 3; |
|
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|
1156 inccycles = 18; |
|
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|
1157 break; |
|
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|
1158 case 97: |
|
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|
1159 slot = 4; |
|
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|
1160 inccycles = 20; |
|
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|
1161 break; |
|
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|
1162 case 117: |
|
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|
1163 slot = 5; |
|
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|
1164 inccycles = 20; |
|
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|
1165 break; |
|
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|
1166 case 137: |
|
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|
1167 slot = 6; |
|
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|
1168 inccycles = 20; |
|
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|
1169 break; |
|
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|
1170 case 157: |
|
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|
1171 slot = 7; |
|
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|
1172 inccycles = 18; |
|
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|
1173 break; |
|
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|
1174 case 175: |
|
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|
1175 slot = 8; |
|
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|
1176 inccycles = 20; |
|
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1177 break; |
|
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1178 case 195: |
|
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1179 slot = 9; |
|
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1180 inccycles = 20; |
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|
1181 break; |
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|
1182 case 215: |
|
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1183 slot = 11; |
|
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1184 inccycles = 20; |
|
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|
1185 break; |
|
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|
1186 case 235: |
|
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|
1187 slot = 12; |
|
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1188 inccycles = 18; |
|
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|
1189 break; |
|
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1190 case 253: |
|
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1191 slot = 13; |
|
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1192 inccycles = 20; |
|
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|
1193 break; |
|
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|
1194 case 273: |
|
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1195 slot = 14; |
|
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1196 inccycles = 20; |
|
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|
1197 break; |
|
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|
1198 case 293: |
|
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|
1199 slot = 15; |
|
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|
1200 inccycles = 20; |
|
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|
1201 break; |
|
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|
1202 case 313: |
|
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|
1203 slot = 16; |
|
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|
1204 inccycles = 19; |
|
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|
1205 break; |
|
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|
1206 default: |
|
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|
1207 fprintf(stderr, "cycles after weirdness %d\n", linecyc-(MCLKS_SLOT_H40*HSYNC_SLOT_H40)); |
|
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|
1208 exit(1); |
|
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|
1209 } |
|
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|
1210 slot += HSYNC_SLOT_H40; |
|
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|
1211 } else { |
|
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329
diff
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|
1212 slot = (linecyc-MCLK_WEIRD_END)/MCLKS_SLOT_H40 + SLOT_WEIRD_END; |
|
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|
1213 inccycles = MCLKS_SLOT_H40; |
|
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|
1214 } |
|
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|
1215 } else { |
|
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|
1216 inccycles = MCLKS_SLOT_H32; |
|
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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|
1217 slot = linecyc/MCLKS_SLOT_H32; |
|
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diff
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|
1218 } |
|
329
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Implement first line/last line weirdness in VDP
Mike Pavone <pavone@retrodev.com>
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328
diff
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|
1219 if ((line < active_lines || (line == active_lines && linecyc < (context->latched_mode & BIT_H40 ? 64 : 80))) && context->regs[REG_MODE_2] & DISPLAY_ENABLE) { |
|
20
f664eeb55cb4
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diff
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|
1220 //first sort-of active line is treated as 255 internally |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1221 //it's used for gathering sprite info for line |
|
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Mostly broken VDP core and savestate viewer
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parents:
diff
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|
1222 line = (line - 1) & 0xFF; |
|
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diff
changeset
|
1223 |
|
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|
1224 //Convert to slot number |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
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|
1225 if (context->latched_mode & BIT_H40){ |
|
330
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diff
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|
1226 vdp_h40(line, slot, context); |
|
20
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diff
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|
1227 } else { |
|
330
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diff
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|
1228 vdp_h32(line, slot, context); |
|
20
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Mostly broken VDP core and savestate viewer
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diff
changeset
|
1229 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
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diff
changeset
|
1230 } else { |
|
330
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|
1231 if (!is_refresh(context, slot)) { |
|
54
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diff
changeset
|
1232 external_slot(context); |
|
3b79cbcf6846
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43
diff
changeset
|
1233 } |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
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|
1234 if (line < active_lines) { |
|
330
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Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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diff
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|
1235 check_render_bg(context, line, slot); |
|
54
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43
diff
changeset
|
1236 } |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1237 } |
|
330
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diff
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|
1238 context->cycles += inccycles; |
|
20
f664eeb55cb4
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parents:
diff
changeset
|
1239 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1240 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1241 |
|
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Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1242 uint32_t vdp_run_to_vblank(vdp_context * context) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1243 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1244 uint32_t target_cycles = ((context->latched_mode & BIT_PAL) ? PAL_ACTIVE : NTSC_ACTIVE) * MCLKS_LINE; |
|
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Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1245 vdp_run_context(context, target_cycles); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1246 return context->cycles; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1247 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
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parents:
diff
changeset
|
1248 |
| 75 | 1249 void vdp_run_dma_done(vdp_context * context, uint32_t target_cycles) |
| 1250 { | |
| 1251 for(;;) { | |
| 1252 uint32_t dmalen = (context->regs[REG_DMALEN_H] << 8) | context->regs[REG_DMALEN_L]; | |
| 1253 if (!dmalen) { | |
| 1254 dmalen = 0x10000; | |
| 1255 } | |
| 1256 uint32_t min_dma_complete = dmalen * (context->latched_mode & BIT_H40 ? 16 : 20); | |
| 1257 if ((context->regs[REG_DMASRC_H] & 0xC0) == 0xC0 || (context->cd & 0xF) == VRAM_WRITE) { | |
| 1258 //DMA copies take twice as long to complete since they require a read and a write | |
| 1259 //DMA Fills and transfers to VRAM also take twice as long as it requires 2 writes for a single word | |
| 1260 min_dma_complete *= 2; | |
| 1261 } | |
| 1262 min_dma_complete += context->cycles; | |
| 1263 if (target_cycles < min_dma_complete) { | |
| 1264 vdp_run_context(context, target_cycles); | |
| 1265 return; | |
| 1266 } else { | |
| 1267 vdp_run_context(context, min_dma_complete); | |
| 1268 if (!(context->flags & FLAG_DMA_RUN)) { | |
| 1269 return; | |
| 1270 } | |
| 1271 } | |
| 1272 } | |
| 1273 } | |
| 1274 | |
| 1275 int vdp_control_port_write(vdp_context * context, uint16_t value) | |
|
54
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diff
changeset
|
1276 { |
|
58
a6a19c45d358
Properly zero-init all VDP buffers. Comment out some debug printfs.
Mike Pavone <pavone@retrodev.com>
parents:
56
diff
changeset
|
1277 //printf("control port write: %X\n", value); |
|
149
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
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143
diff
changeset
|
1278 if (context->flags & FLAG_DMA_RUN) { |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
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143
diff
changeset
|
1279 return -1; |
|
139e5dcd6aa3
Make writes to control and data port block when DMA is in progress
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143
diff
changeset
|
1280 } |
|
54
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43
diff
changeset
|
1281 if (context->flags & FLAG_PENDING) { |
|
3b79cbcf6846
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43
diff
changeset
|
1282 context->address = (context->address & 0x3FFF) | (value << 14); |
|
3b79cbcf6846
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43
diff
changeset
|
1283 context->cd = (context->cd & 0x3) | ((value >> 2) & 0x3C); |
| 75 | 1284 context->flags &= ~FLAG_PENDING; |
|
87
60b5c9e2f4e0
vertical interrupts now work
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84
diff
changeset
|
1285 //printf("New Address: %X, New CD: %X\n", context->address, context->cd); |
|
327
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Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1286 if (context->cd & 0x20 && (context->regs[REG_MODE_2] & BIT_DMA_ENABLE)) { |
|
1b00258b1f29
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Mike Pavone <pavone@retrodev.com>
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323
diff
changeset
|
1287 // |
| 75 | 1288 if((context->regs[REG_DMASRC_H] & 0xC0) != 0x80) { |
| 1289 //DMA copy or 68K -> VDP, transfer starts immediately | |
| 1290 context->flags |= FLAG_DMA_RUN; | |
|
131
8fc8e46be691
Fix bug that was causing DMA fills to lock up under certain circumstances
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parents:
109
diff
changeset
|
1291 context->dma_cd = context->cd; |
| 75 | 1292 if (!(context->regs[REG_DMASRC_H] & 0x80)) { |
|
327
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Mike Pavone <pavone@retrodev.com>
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323
diff
changeset
|
1293 //printf("DMA Address: %X, New CD: %X, Source: %X, Length: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_H] << 17) | (context->regs[REG_DMASRC_M] << 9) | (context->regs[REG_DMASRC_L] << 1), context->regs[REG_DMALEN_H] << 8 | context->regs[REG_DMALEN_L]); |
| 75 | 1294 return 1; |
|
327
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parents:
323
diff
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|
1295 } else { |
|
1b00258b1f29
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parents:
323
diff
changeset
|
1296 //printf("DMA Copy Address: %X, New CD: %X, Source: %X\n", context->address, context->cd, (context->regs[REG_DMASRC_M] << 8) | context->regs[REG_DMASRC_L]); |
| 75 | 1297 } |
|
327
1b00258b1f29
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Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1298 } else { |
|
1b00258b1f29
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Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1299 //printf("DMA Fill Address: %X, New CD: %X\n", context->address, context->cd); |
| 75 | 1300 } |
|
63
a6dd5b7a971b
Add FPS counter to console output
Mike Pavone <pavone@retrodev.com>
parents:
58
diff
changeset
|
1301 } |
|
54
3b79cbcf6846
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43
diff
changeset
|
1302 } else { |
|
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1303 if ((value & 0xC000) == 0x8000) { |
|
3b79cbcf6846
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43
diff
changeset
|
1304 //Register write |
|
3b79cbcf6846
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parents:
43
diff
changeset
|
1305 uint8_t reg = (value >> 8) & 0x1F; |
|
3b79cbcf6846
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Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1306 if (reg < VDP_REGS) { |
|
87
60b5c9e2f4e0
vertical interrupts now work
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parents:
84
diff
changeset
|
1307 //printf("register %d set to %X\n", reg, value & 0xFF); |
|
54
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43
diff
changeset
|
1308 context->regs[reg] = value; |
|
151
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
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149
diff
changeset
|
1309 if (reg == REG_MODE_2) { |
|
6b593ea0ed90
Implement MULU/MULS and DIVU/DIVS
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|
1310 //printf("Display is now %s\n", (context->regs[REG_MODE_2] & DISPLAY_ENABLE) ? "enabled" : "disabled"); |
|
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Implement MULU/MULS and DIVU/DIVS
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diff
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|
1311 } |
|
54
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43
diff
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|
1312 } |
|
3b79cbcf6846
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diff
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|
1313 } else { |
|
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
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43
diff
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|
1314 context->flags |= FLAG_PENDING; |
|
3b79cbcf6846
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diff
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|
1315 context->address = (context->address &0xC000) | (value & 0x3FFF); |
|
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Get Flavio's color bar demo kind of sort of working
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diff
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|
1316 context->cd = (context->cd &0x3C) | (value >> 14); |
|
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Get Flavio's color bar demo kind of sort of working
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43
diff
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|
1317 } |
|
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Get Flavio's color bar demo kind of sort of working
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diff
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|
1318 } |
| 75 | 1319 return 0; |
|
54
3b79cbcf6846
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diff
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|
1320 } |
|
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|
1321 |
|
149
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diff
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|
1322 int vdp_data_port_write(vdp_context * context, uint16_t value) |
|
54
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Get Flavio's color bar demo kind of sort of working
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43
diff
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|
1323 { |
|
58
a6a19c45d358
Properly zero-init all VDP buffers. Comment out some debug printfs.
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56
diff
changeset
|
1324 //printf("data port write: %X\n", value); |
|
149
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|
1325 if (context->flags & FLAG_DMA_RUN) { |
|
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diff
changeset
|
1326 return -1; |
|
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diff
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|
1327 } |
|
139e5dcd6aa3
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diff
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|
1328 if (!(context->cd & 1)) { |
|
139e5dcd6aa3
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143
diff
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|
1329 //ignore writes when cd is configured for read |
|
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diff
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|
1330 return 0; |
|
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|
1331 } |
|
54
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diff
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|
1332 context->flags &= ~FLAG_PENDING; |
|
109
004dd46e0a97
COmment out fifo full debug printf
Mike Pavone <pavone@retrodev.com>
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108
diff
changeset
|
1333 /*if (context->fifo_cur == context->fifo_end) { |
|
54
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diff
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|
1334 printf("FIFO full, waiting for space before next write at cycle %X\n", context->cycles); |
|
109
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diff
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|
1335 }*/ |
|
54
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diff
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|
1336 while (context->fifo_cur == context->fifo_end) { |
|
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diff
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|
1337 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
|
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diff
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|
1338 } |
|
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43
diff
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|
1339 context->fifo_cur->cycle = context->cycles; |
| 138 | 1340 context->fifo_cur->address = context->address; |
|
54
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diff
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|
1341 context->fifo_cur->value = value; |
| 138 | 1342 context->fifo_cur->cd = context->cd; |
|
54
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43
diff
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|
1343 context->fifo_cur->partial = 0; |
|
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diff
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|
1344 context->fifo_cur++; |
| 138 | 1345 context->address += context->regs[REG_AUTOINC]; |
|
149
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|
1346 return 0; |
|
54
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diff
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|
1347 } |
|
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diff
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|
1348 |
|
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diff
changeset
|
1349 uint16_t vdp_control_port_read(vdp_context * context) |
|
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diff
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|
1350 { |
|
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|
1351 context->flags &= ~FLAG_PENDING; |
|
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diff
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|
1352 uint16_t value = 0x3400; |
|
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|
1353 if (context->fifo_cur == (context->fifo_end - FIFO_SIZE)) { |
|
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diff
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|
1354 value |= 0x200; |
|
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diff
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|
1355 } |
|
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diff
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|
1356 if (context->fifo_cur == context->fifo_end) { |
|
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diff
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|
1357 value |= 0x100; |
|
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diff
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|
1358 } |
|
317
e5e8b48ad157
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diff
changeset
|
1359 if (context->flags2 & FLAG2_VINT_PENDING) { |
|
e5e8b48ad157
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diff
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|
1360 value |- 0x80; |
|
e5e8b48ad157
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diff
changeset
|
1361 } |
|
318
789f2f5f2277
Implement hblank flag in status register
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317
diff
changeset
|
1362 uint32_t line= context->cycles / MCLKS_LINE; |
|
789f2f5f2277
Implement hblank flag in status register
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diff
changeset
|
1363 uint32_t linecyc = context->cycles % MCLKS_LINE; |
|
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diff
changeset
|
1364 if (line >= (context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE)) { |
|
789f2f5f2277
Implement hblank flag in status register
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diff
changeset
|
1365 value |= 0x8; |
|
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diff
changeset
|
1366 } |
|
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diff
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|
1367 if (linecyc < (context->latched_mode & BIT_H40 ? (148 + 61) * 4 : ( + 46) * 5)) { |
|
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diff
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|
1368 value |= 0x4; |
|
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diff
changeset
|
1369 } |
|
149
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changeset
|
1370 if (context->flags & FLAG_DMA_RUN) { |
|
141
576f55711d8d
Fix DMA in progress flag in VDP status register
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138
diff
changeset
|
1371 value |= 0x2; |
| 75 | 1372 } |
|
317
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diff
changeset
|
1373 if (context->latched_mode & BIT_PAL) {//Not sure about this, need to verify |
|
e5e8b48ad157
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diff
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|
1374 value |= 0x1; |
|
e5e8b48ad157
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diff
changeset
|
1375 } |
|
318
789f2f5f2277
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317
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changeset
|
1376 //TODO: Sprite overflow, sprite collision, odd frame flag |
|
54
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|
1377 return value; |
|
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diff
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|
1378 } |
|
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|
1379 |
|
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|
1380 uint16_t vdp_data_port_read(vdp_context * context) |
|
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|
1381 { |
|
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|
1382 context->flags &= ~FLAG_PENDING; |
| 138 | 1383 if (context->cd & 1) { |
|
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|
1384 return 0; |
|
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|
1385 } |
|
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|
1386 //Not sure if the FIFO should be drained before processing a read or not, but it would make sense |
|
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|
1387 context->flags &= ~FLAG_UNUSED_SLOT; |
|
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|
1388 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
|
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|
1389 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
|
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|
1390 } |
|
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|
1391 uint16_t value = 0; |
| 138 | 1392 switch (context->cd & 0xF) |
|
54
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|
1393 { |
|
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|
1394 case VRAM_READ: |
|
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|
1395 value = context->vdpmem[context->address] << 8; |
|
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|
1396 context->flags &= ~FLAG_UNUSED_SLOT; |
|
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|
1397 while (!(context->flags & FLAG_UNUSED_SLOT)) { |
|
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|
1398 vdp_run_context(context, context->cycles + ((context->latched_mode & BIT_H40) ? 16 : 20)); |
|
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|
1399 } |
|
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|
1400 value |= context->vdpmem[context->address ^ 1]; |
|
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|
1401 break; |
|
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|
1402 case CRAM_READ: |
|
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|
1403 value = context->cram[(context->address/2) & (CRAM_SIZE-1)]; |
|
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|
1404 break; |
|
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|
1405 case VSRAM_READ: |
|
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|
1406 if (((context->address / 2) & 63) < VSRAM_SIZE) { |
|
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|
1407 value = context->vsram[context->address & 63]; |
|
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|
1408 } |
|
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changeset
|
1409 break; |
|
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|
1410 } |
|
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changeset
|
1411 context->address += context->regs[REG_AUTOINC]; |
|
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|
1412 return value; |
|
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|
1413 } |
|
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|
1414 |
| 137 | 1415 uint16_t vdp_hv_counter_read(vdp_context * context) |
| 1416 { | |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
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329
diff
changeset
|
1417 //TODO: deal with clock adjustemnts handled in vdp_run_context |
| 137 | 1418 uint32_t line= context->cycles / MCLKS_LINE; |
| 1419 if (!line) { | |
| 1420 line = 0xFF; | |
| 1421 } else { | |
| 1422 line--; | |
| 1423 if (line > 0xEA) { | |
| 1424 line = (line + 0xFA) & 0xFF; | |
| 1425 } | |
| 1426 } | |
| 1427 uint32_t linecyc = context->cycles % MCLKS_LINE; | |
| 1428 if (context->latched_mode & BIT_H40) { | |
| 1429 linecyc /= 8; | |
| 1430 if (linecyc >= 86) { | |
| 1431 linecyc -= 86; | |
| 1432 } else { | |
| 1433 linecyc += 334; | |
| 1434 } | |
| 1435 if (linecyc > 0x16C) { | |
| 1436 linecyc += 92; | |
| 1437 } | |
| 1438 } else { | |
| 1439 linecyc /= 10; | |
| 1440 if (linecyc >= 74) { | |
| 1441 linecyc -= 74; | |
| 1442 } else { | |
| 1443 linecyc += 268; | |
| 1444 } | |
| 1445 if (linecyc > 0x127) { | |
| 1446 linecyc += 170; | |
| 1447 } | |
| 1448 } | |
| 1449 linecyc &= 0xFF; | |
| 1450 return (line << 8) | linecyc; | |
| 1451 } | |
| 1452 | |
|
65
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1453 void vdp_adjust_cycles(vdp_context * context, uint32_t deduction) |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1454 { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1455 context->cycles -= deduction; |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1456 for(fifo_entry * start = (context->fifo_end - FIFO_SIZE); start < context->fifo_cur; start++) { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1457 if (start->cycle >= deduction) { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1458 start->cycle -= deduction; |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1459 } else { |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1460 start->cycle = 0; |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1461 } |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1462 } |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1463 } |
|
aef6302770c2
Fix issue in which VDP would have trouble emptying FIFO because the VDP cycle count got reset at end of frame.
Mike Pavone <pavone@retrodev.com>
parents:
63
diff
changeset
|
1464 |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1465 uint32_t vdp_next_hint(vdp_context * context) |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1466 { |
|
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1467 if (!(context->regs[REG_MODE_1] & BIT_HINT_EN)) { |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1468 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1469 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1470 if (context->flags2 & FLAG2_HINT_PENDING) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1471 return context->cycles; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1472 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1473 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1474 uint32_t line = context->cycles / MCLKS_LINE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1475 if (line >= active_lines) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1476 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1477 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1478 uint32_t linecyc = context->cycles % MCLKS_LINE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1479 uint32_t hcycle = context->cycles + context->hint_counter * MCLKS_LINE + MCLKS_LINE - linecyc; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1480 if (!line) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1481 hcycle += MCLKS_LINE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1482 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1483 return hcycle; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1484 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1485 |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1486 uint32_t vdp_next_vint(vdp_context * context) |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1487 { |
|
330
57453d3d8be4
Initial stab at implementing funky clock adjustments during HSYNC for H40 mode
Mike Pavone <pavone@retrodev.com>
parents:
329
diff
changeset
|
1488 //TODO: deal with clock adjustemnts handled in vdp_run_context |
|
327
1b00258b1f29
Added some basic VDP debugging features to debugger. Fixed DMA enable bug
Mike Pavone <pavone@retrodev.com>
parents:
323
diff
changeset
|
1489 if (!(context->regs[REG_MODE_2] & BIT_VINT_EN)) { |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1490 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1491 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1492 if (context->flags2 & FLAG2_VINT_PENDING) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1493 return context->cycles; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1494 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1495 uint32_t active_lines = context->latched_mode & BIT_PAL ? PAL_ACTIVE : NTSC_ACTIVE; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1496 uint32_t vcycle = MCLKS_LINE * active_lines; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1497 if (context->latched_mode & BIT_H40) { |
|
328
bf7ed23efa40
Fewer magic numbers in the VDP core for the win
Mike Pavone <pavone@retrodev.com>
parents:
327
diff
changeset
|
1498 vcycle += VINT_SLOTS_H40 * MCLKS_SLOT_H40; |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1499 } else { |
|
328
bf7ed23efa40
Fewer magic numbers in the VDP core for the win
Mike Pavone <pavone@retrodev.com>
parents:
327
diff
changeset
|
1500 vcycle += VINT_SLOTS_H32 * MCLKS_SLOT_H32; |
|
317
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1501 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1502 if (vcycle < context->cycles) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1503 return 0xFFFFFFFF; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1504 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1505 return vcycle; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1506 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1507 |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1508 void vdp_int_ack(vdp_context * context, uint16_t int_num) |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1509 { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1510 if (int_num == 6) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1511 context->flags2 &= ~FLAG2_VINT_PENDING; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1512 } else if(int_num ==4) { |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1513 context->flags2 &= ~FLAG2_HINT_PENDING; |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1514 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1515 } |
|
e5e8b48ad157
Initial stab at horizontal interrupts and improving accuracy of vertical interrupts. Also added the VINT pending flag to status port.
Mike Pavone <pavone@retrodev.com>
parents:
291
diff
changeset
|
1516 |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1517 #define GST_VDP_REGS 0xFA |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1518 #define GST_VDP_MEM 0x12478 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1519 |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1520 void vdp_load_savestate(vdp_context * context, FILE * state_file) |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1521 { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1522 uint8_t tmp_buf[CRAM_SIZE*2]; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1523 fseek(state_file, GST_VDP_REGS, SEEK_SET); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1524 fread(context->regs, 1, VDP_REGS, state_file); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1525 latch_mode(context); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1526 fread(tmp_buf, 1, sizeof(tmp_buf), state_file); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1527 for (int i = 0; i < CRAM_SIZE; i++) { |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1528 context->cram[i] = (tmp_buf[i*2+1] << 8) | tmp_buf[i*2]; |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1529 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1530 fread(tmp_buf, 2, VSRAM_SIZE, state_file); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1531 for (int i = 0; i < VSRAM_SIZE; i++) { |
|
23
3e924bb56560
Fix endianness of VSRAM when read from Genecyst save state
Mike Pavone <pavone@retrodev.com>
parents:
22
diff
changeset
|
1532 context->vsram[i] = (tmp_buf[i*2+1] << 8) | tmp_buf[i*2]; |
|
20
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1533 } |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1534 fseek(state_file, GST_VDP_MEM, SEEK_SET); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1535 fread(context->vdpmem, 1, VRAM_SIZE, state_file); |
|
f664eeb55cb4
Mostly broken VDP core and savestate viewer
Mike Pavone <pavone@retrodev.com>
parents:
diff
changeset
|
1536 } |
|
54
3b79cbcf6846
Get Flavio's color bar demo kind of sort of working
Mike Pavone <pavone@retrodev.com>
parents:
43
diff
changeset
|
1537 |
|
56
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1538 void vdp_save_state(vdp_context * context, FILE * outfile) |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1539 { |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1540 uint8_t tmp_buf[CRAM_SIZE*2]; |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1541 fseek(outfile, GST_VDP_REGS, SEEK_SET); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1542 fwrite(context->regs, 1, VDP_REGS, outfile); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1543 for (int i = 0; i < CRAM_SIZE; i++) { |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1544 tmp_buf[i*2] = context->cram[i]; |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1545 tmp_buf[i*2+1] = context->cram[i] >> 8; |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1546 } |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1547 fwrite(tmp_buf, 1, sizeof(tmp_buf), outfile); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1548 for (int i = 0; i < VSRAM_SIZE; i++) { |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1549 tmp_buf[i*2] = context->vsram[i]; |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1550 tmp_buf[i*2+1] = context->vsram[i] >> 8; |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1551 } |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1552 fwrite(tmp_buf, 2, VSRAM_SIZE, outfile); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1553 fseek(outfile, GST_VDP_MEM, SEEK_SET); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1554 fwrite(context->vdpmem, 1, VRAM_SIZE, outfile); |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1555 } |
|
a28b1dfe1af2
Fix CRAM and possibly VSRAM writes
Mike Pavone <pavone@retrodev.com>
parents:
54
diff
changeset
|
1556 |