annotate ym2612.c @ 989:d70000fdff0b

Implemented IR and undefined bits of info word for address error exception frames
author Michael Pavone <pavone@retrodev.com>
date Wed, 27 Apr 2016 21:39:17 -0700
parents 5257e85364ed
children 8d032a368dd5
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1 /*
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2 Copyright 2013 Michael Pavone
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3 This file is part of BlastEm.
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
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5 */
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6 #include <string.h>
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7 #include <math.h>
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8 #include <stdio.h>
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9 #include <stdlib.h>
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10 #include "ym2612.h"
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11 #include "render.h"
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12 #include "wave.h"
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13 #include "blastem.h"
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14
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15 //#define DO_DEBUG_PRINT
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16 #ifdef DO_DEBUG_PRINT
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17 #define dfprintf fprintf
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18 #define dfopen(var, fname, mode) var=fopen(fname, mode)
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19 #else
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20 #define dfprintf
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21 #define dfopen(var, fname, mode)
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22 #endif
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23
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24 #define BUSY_CYCLES_ADDRESS 17
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25 #define BUSY_CYCLES_DATA_LOW 83
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26 #define BUSY_CYCLES_DATA_HIGH 47
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27 #define OP_UPDATE_PERIOD 144
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29 #define BIT_TIMERA_ENABLE 0x1
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30 #define BIT_TIMERB_ENABLE 0x2
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31 #define BIT_TIMERA_OVEREN 0x4
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32 #define BIT_TIMERB_OVEREN 0x8
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33 #define BIT_TIMERA_RESET 0x10
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34 #define BIT_TIMERB_RESET 0x20
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35
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36 #define BIT_TIMERA_LOAD 0x40
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37 #define BIT_TIMERB_LOAD 0x80
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39 #define BIT_STATUS_TIMERA 0x1
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40 #define BIT_STATUS_TIMERB 0x2
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41
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42 uint32_t ym_calc_phase_inc(ym2612_context * context, ym_operator * operator, uint32_t op);
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43
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44 enum {
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45 PHASE_ATTACK,
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46 PHASE_DECAY,
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47 PHASE_SUSTAIN,
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48 PHASE_RELEASE
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49 };
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50
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51 uint8_t did_tbl_init = 0;
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52 //According to Nemesis, real hardware only uses a 256 entry quarter sine table; however,
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53 //memory is cheap so using a half sine table will probably save some cycles
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54 //a full sine table would be nice, but negative numbers don't get along with log2
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55 #define SINE_TABLE_SIZE 512
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56 uint16_t sine_table[SINE_TABLE_SIZE];
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57 //Similar deal here with the power table for log -> linear conversion
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58 //According to Nemesis, real hardware only uses a 256 entry table for the fractional part
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59 //and uses the whole part as a shift amount.
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60 #define POW_TABLE_SIZE (1 << 13)
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61 uint16_t pow_table[POW_TABLE_SIZE];
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62
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63 uint16_t rate_table_base[] = {
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64 //main portion
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65 0,1,0,1,0,1,0,1,
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66 0,1,0,1,1,1,0,1,
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67 0,1,1,1,0,1,1,1,
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68 0,1,1,1,1,1,1,1,
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69 //top end
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70 1,1,1,1,1,1,1,1,
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71 1,1,1,2,1,1,1,2,
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72 1,2,1,2,1,2,1,2,
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73 1,2,2,2,1,2,2,2,
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74 };
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75
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76 uint16_t rate_table[64*8];
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77
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78 uint8_t lfo_timer_values[] = {108, 77, 71, 67, 62, 44, 8, 5};
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79 uint8_t lfo_pm_base[][8] = {
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80 {0, 0, 0, 0, 0, 0, 0, 0},
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81 {0, 0, 0, 0, 4, 4, 4, 4},
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82 {0, 0, 0, 4, 4, 4, 8, 8},
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83 {0, 0, 4, 4, 8, 8, 0xc, 0xc},
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84 {0, 0, 4, 8, 8, 8, 0xc,0x10},
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85 {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
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86 {0, 0,0x10,0x18,0x20,0x20,0x28,0x30},
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87 {0, 0,0x20,0x30,0x40,0x40,0x50,0x60}
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88 };
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89 int16_t lfo_pm_table[128 * 32 * 8];
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90
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91 int16_t ams_shift[] = {8, 1, -1, -2};
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92
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93 #define MAX_ENVELOPE 0xFFC
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94 #define YM_DIVIDER 2
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95 #define CYCLE_NEVER 0xFFFFFFFF
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96
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97 uint16_t round_fixed_point(double value, int dec_bits)
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98 {
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99 return value * (1 << dec_bits) + 0.5;
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100 }
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101
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102 FILE * debug_file = NULL;
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103 uint32_t first_key_on=0;
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104
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105 ym2612_context * log_context = NULL;
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106
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107 void ym_finalize_log()
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108 {
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109 if (!log_context) {
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110 return;
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111 }
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112 for (int i = 0; i < NUM_CHANNELS; i++) {
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113 if (log_context->channels[i].logfile) {
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114 wave_finalize(log_context->channels[i].logfile);
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115 }
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116 }
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117 log_context = NULL;
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118 }
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119 #define BUFFER_INC_RES 0x40000000UL
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120
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121 void ym_adjust_master_clock(ym2612_context * context, uint32_t master_clock)
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122 {
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123 uint64_t old_inc = context->buffer_inc;
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124 context->buffer_inc = ((BUFFER_INC_RES * (uint64_t)context->sample_rate) / (uint64_t)master_clock) * (uint64_t)context->clock_inc * NUM_OPERATORS;
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parents: 467
diff changeset
125 }
407
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents: 406
diff changeset
126
859
46bb673eed4e Load config file and rom.db from appropriate locations on Android
Michael Pavone <pavone@retrodev.com>
parents: 853
diff changeset
127 #ifdef __ANDROID__
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parents: 853
diff changeset
128 #define log2(x) (log(x)/log(2))
46bb673eed4e Load config file and rom.db from appropriate locations on Android
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parents: 853
diff changeset
129 #endif
46bb673eed4e Load config file and rom.db from appropriate locations on Android
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parents: 853
diff changeset
130
965
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parents: 936
diff changeset
131 #define LOWPASS_CUTOFF 3390
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
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parents: 936
diff changeset
132
407
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parents: 406
diff changeset
133 void ym_init(ym2612_context * context, uint32_t sample_rate, uint32_t master_clock, uint32_t clock_div, uint32_t sample_limit, uint32_t options)
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
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parents:
diff changeset
134 {
884
252dfd29831d Selecting a second game from the menu now works
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parents: 859
diff changeset
135 static uint8_t registered_finalize;
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
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parents: 369
diff changeset
136 dfopen(debug_file, "ym_debug.txt", "w");
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
137 memset(context, 0, sizeof(*context));
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
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parents: 362
diff changeset
138 context->audio_buffer = malloc(sizeof(*context->audio_buffer) * sample_limit*2);
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
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parents: 362
diff changeset
139 context->back_buffer = malloc(sizeof(*context->audio_buffer) * sample_limit*2);
483
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
140 context->sample_rate = sample_rate;
380
1c8d74f2ab0b Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run.
Mike Pavone <pavone@retrodev.com>
parents: 379
diff changeset
141 context->clock_inc = clock_div * 6;
483
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
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parents: 467
diff changeset
142 ym_adjust_master_clock(context, master_clock);
965
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
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parents: 936
diff changeset
143
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
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parents: 936
diff changeset
144 double rc = (1.0 / (double)LOWPASS_CUTOFF) / (2.0 * M_PI);
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
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parents: 936
diff changeset
145 double dt = 1.0 / ((double)master_clock / (double)(context->clock_inc * NUM_OPERATORS));
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
146 double alpha = dt / (dt + rc);
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
147 context->lowpass_alpha = (int32_t)(((double)0x10000) * alpha);
483
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
148
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
149 context->sample_limit = sample_limit*2;
374
d42a8a3e4894 Fix YM2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 371
diff changeset
150 context->write_cycle = CYCLE_NEVER;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
151 for (int i = 0; i < NUM_OPERATORS; i++) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
152 context->operators[i].envelope = MAX_ENVELOPE;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
153 context->operators[i].env_phase = PHASE_RELEASE;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
154 }
369
fc820ab1394b Fix left/right enable default value
Mike Pavone <pavone@retrodev.com>
parents: 365
diff changeset
155 //some games seem to expect that the LR flags start out as 1
fc820ab1394b Fix left/right enable default value
Mike Pavone <pavone@retrodev.com>
parents: 365
diff changeset
156 for (int i = 0; i < NUM_CHANNELS; i++) {
fc820ab1394b Fix left/right enable default value
Mike Pavone <pavone@retrodev.com>
parents: 365
diff changeset
157 context->channels[i].lr = 0xC0;
407
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents: 406
diff changeset
158 if (options & YM_OPT_WAVE_LOG) {
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents: 406
diff changeset
159 char fname[64];
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents: 406
diff changeset
160 sprintf(fname, "ym_channel_%d.wav", i);
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents: 406
diff changeset
161 FILE * f = context->channels[i].logfile = fopen(fname, "wb");
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents: 406
diff changeset
162 if (!f) {
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents: 406
diff changeset
163 fprintf(stderr, "Failed to open WAVE log file %s for writing\n", fname);
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
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parents: 406
diff changeset
164 continue;
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents: 406
diff changeset
165 }
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents: 406
diff changeset
166 if (!wave_init(f, sample_rate, 16, 1)) {
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents: 406
diff changeset
167 fclose(f);
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents: 406
diff changeset
168 context->channels[i].logfile = NULL;
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents: 406
diff changeset
169 }
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents: 406
diff changeset
170 }
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents: 406
diff changeset
171 }
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents: 406
diff changeset
172 if (options & YM_OPT_WAVE_LOG) {
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
Mike Pavone <pavone@retrodev.com>
parents: 406
diff changeset
173 log_context = context;
884
252dfd29831d Selecting a second game from the menu now works
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parents: 859
diff changeset
174 if (!registered_finalize) {
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Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
175 atexit(ym_finalize_log);
252dfd29831d Selecting a second game from the menu now works
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parents: 859
diff changeset
176 registered_finalize = 1;
252dfd29831d Selecting a second game from the menu now works
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parents: 859
diff changeset
177 }
369
fc820ab1394b Fix left/right enable default value
Mike Pavone <pavone@retrodev.com>
parents: 365
diff changeset
178 }
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
179 if (!did_tbl_init) {
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
180 //populate sine table
cc39629e8d06 YM2612 WIP snapshot before register refactor
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parents: 288
diff changeset
181 for (int32_t i = 0; i < 512; i++) {
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
182 double sine = sin( ((double)(i*2+1) / SINE_TABLE_SIZE) * M_PI_2 );
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
183
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
184 //table stores 4.8 fixed pointed representation of the base 2 log
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
185 sine_table[i] = round_fixed_point(-log2(sine), 8);
cc39629e8d06 YM2612 WIP snapshot before register refactor
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parents: 288
diff changeset
186 }
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
187 //populate power table
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
188 for (int32_t i = 0; i < POW_TABLE_SIZE; i++) {
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
189 double linear = pow(2, -((double)((i & 0xFF)+1) / 256.0));
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
190 int32_t tmp = round_fixed_point(linear, 11);
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
191 int32_t shift = (i >> 8) - 2;
cc39629e8d06 YM2612 WIP snapshot before register refactor
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parents: 288
diff changeset
192 if (shift < 0) {
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
193 tmp <<= 0-shift;
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
194 } else {
cc39629e8d06 YM2612 WIP snapshot before register refactor
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parents: 288
diff changeset
195 tmp >>= shift;
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
196 }
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
197 pow_table[i] = tmp;
cc39629e8d06 YM2612 WIP snapshot before register refactor
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parents: 288
diff changeset
198 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
199 //populate envelope generator rate table, from small base table
b7c3facee762 YM2612 WIP update
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parents: 359
diff changeset
200 for (int rate = 0; rate < 64; rate++) {
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
201 for (int cycle = 0; cycle < 8; cycle++) {
362
b7c3facee762 YM2612 WIP update
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parents: 359
diff changeset
202 uint16_t value;
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
203 if (rate < 2) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
204 value = 0;
365
3ba3b6656fff Actually save the shifted phase inc after applying the block shift
Mike Pavone <pavone@retrodev.com>
parents: 364
diff changeset
205 } else if (rate >= 60) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
206 value = 8;
365
3ba3b6656fff Actually save the shifted phase inc after applying the block shift
Mike Pavone <pavone@retrodev.com>
parents: 364
diff changeset
207 } else if (rate < 8) {
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
208 value = rate_table_base[((rate & 6) == 6 ? 16 : 0) + cycle];
365
3ba3b6656fff Actually save the shifted phase inc after applying the block shift
Mike Pavone <pavone@retrodev.com>
parents: 364
diff changeset
209 } else if (rate < 48) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
210 value = rate_table_base[(rate & 0x3) * 8 + cycle];
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
211 } else {
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
212 value = rate_table_base[32 + (rate & 0x3) * 8 + cycle] << ((rate - 48) >> 2);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
213 }
365
3ba3b6656fff Actually save the shifted phase inc after applying the block shift
Mike Pavone <pavone@retrodev.com>
parents: 364
diff changeset
214 rate_table[rate * 8 + cycle] = value;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
215 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
216 }
411
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
217 //populate LFO PM table from small base table
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
218 //seems like there must be a better way to derive this
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
219 for (int freq = 0; freq < 128; freq++) {
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
220 for (int pms = 0; pms < 8; pms++) {
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
221 for (int step = 0; step < 32; step++) {
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
222 int16_t value = 0;
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
223 for (int bit = 0x40, shift = 0; bit > 0; bit >>= 1, shift++) {
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
224 if (freq & bit) {
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
225 value += lfo_pm_base[pms][(step & 0x8) ? 7-step & 7 : step & 7] >> shift;
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
226 }
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
227 }
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
228 if (step & 0x10) {
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
229 value = -value;
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
230 }
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
231 lfo_pm_table[freq * 256 + pms * 32 + step] = value;
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
232 }
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
233 }
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
234 }
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
235 }
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
236 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
237
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
238 void ym_free(ym2612_context *context)
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
239 {
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
240 if (context == log_context) {
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
241 ym_finalize_log();
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
242 }
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
243 free(context->audio_buffer);
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
244 //TODO: Figure out how to make this 100% safe
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
245 //audio thread could still be using this
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
246 free(context->back_buffer);
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
247 free(context);
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
248 }
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
249
522
6a14c5a95648 Adjust PSG and YM-2612 volume to be closer to the real console
Michael Pavone <pavone@retrodev.com>
parents: 521
diff changeset
250 #define YM_VOLUME_MULTIPLIER 2
6a14c5a95648 Adjust PSG and YM-2612 volume to be closer to the real console
Michael Pavone <pavone@retrodev.com>
parents: 521
diff changeset
251 #define YM_VOLUME_DIVIDER 3
381
7815ebbbd705 Fix modulation shift value
Mike Pavone <pavone@retrodev.com>
parents: 380
diff changeset
252 #define YM_MOD_SHIFT 1
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
253
403
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
254 #define TIMER_A_MAX 1023
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
255 #define TIMER_B_MAX 255
403
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
256
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
257 void ym_run(ym2612_context * context, uint32_t to_cycle)
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
258 {
362
b7c3facee762 YM2612 WIP update
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parents: 359
diff changeset
259 //printf("Running YM2612 from cycle %d to cycle %d\n", context->current_cycle, to_cycle);
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
260 //TODO: Fix channel update order OR remap channels in register write
380
1c8d74f2ab0b Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run.
Mike Pavone <pavone@retrodev.com>
parents: 379
diff changeset
261 for (; context->current_cycle < to_cycle; context->current_cycle += context->clock_inc) {
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
262 //Update timers at beginning of 144 cycle period
403
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
263 if (!context->current_op) {
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
264 if (context->timer_control & BIT_TIMERA_ENABLE) {
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
265 if (context->timer_a != TIMER_A_MAX) {
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
266 context->timer_a++;
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
267 } else {
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
268 if (context->timer_control & BIT_TIMERA_LOAD) {
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
269 context->timer_control &= ~BIT_TIMERA_LOAD;
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
270 } else if (context->timer_control & BIT_TIMERA_OVEREN) {
403
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
271 context->status |= BIT_STATUS_TIMERA;
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
272 }
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
273 context->timer_a = context->timer_a_load;
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
274 }
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
275 }
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
276 if (!context->sub_timer_b) {
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
277 if (context->timer_control & BIT_TIMERB_ENABLE) {
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
278 if (context->timer_b != TIMER_B_MAX) {
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
279 context->timer_b++;
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
280 } else {
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
281 if (context->timer_control & BIT_TIMERB_LOAD) {
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
282 context->timer_control &= ~BIT_TIMERB_LOAD;
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
283 } else if (context->timer_control & BIT_TIMERB_OVEREN) {
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
284 context->status |= BIT_STATUS_TIMERB;
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
285 }
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
286 context->timer_b = context->timer_b_load;
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
287 }
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
288 }
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
289 }
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
290 context->sub_timer_b += 0x10;
740
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
291 //Update LFO
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
292 if (context->lfo_enable) {
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
293 if (context->lfo_counter) {
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
294 context->lfo_counter--;
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
295 } else {
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
296 context->lfo_counter = lfo_timer_values[context->lfo_freq];
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
297 context->lfo_am_step += 2;
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
298 context->lfo_am_step &= 0xFE;
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
299 context->lfo_pm_step = context->lfo_am_step / 8;
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
300 }
411
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
301 }
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
302 }
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
303 //Update Envelope Generator
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
304 if (!(context->current_op % 3)) {
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
305 uint32_t env_cyc = context->env_counter;
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
306 uint32_t op = context->current_env_op;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
307 ym_operator * operator = context->operators + op;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
308 ym_channel * channel = context->channels + op/4;
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
309 uint8_t rate;
929
0ee8cfcc06d1 Change where decay to sustain transition happens to match hardware when decay rate is slow or 0
Michael Pavone <pavone@retrodev.com>
parents: 884
diff changeset
310 if (operator->env_phase == PHASE_DECAY && operator->envelope >= operator->sustain_level) {
0ee8cfcc06d1 Change where decay to sustain transition happens to match hardware when decay rate is slow or 0
Michael Pavone <pavone@retrodev.com>
parents: 884
diff changeset
311 //operator->envelope = operator->sustain_level;
0ee8cfcc06d1 Change where decay to sustain transition happens to match hardware when decay rate is slow or 0
Michael Pavone <pavone@retrodev.com>
parents: 884
diff changeset
312 operator->env_phase = PHASE_SUSTAIN;
0ee8cfcc06d1 Change where decay to sustain transition happens to match hardware when decay rate is slow or 0
Michael Pavone <pavone@retrodev.com>
parents: 884
diff changeset
313 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
314 for(;;) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
315 rate = operator->rates[operator->env_phase];
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
316 if (rate) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
317 uint8_t ks = channel->keycode >> operator->key_scaling;;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
318 rate = rate*2 + ks;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
319 if (rate > 63) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
320 rate = 63;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
321 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
322 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
323 //Deal with "infinite" rates
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
324 //According to Nemesis this should be handled in key-on instead
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
325 if (rate >= 62 && operator->env_phase == PHASE_ATTACK) {
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
326 operator->env_phase = PHASE_DECAY;
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
327 operator->envelope = 0;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
328 } else {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
329 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
330 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
331 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
332 uint32_t cycle_shift = rate < 0x30 ? ((0x2F - rate) >> 2) : 0;
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
333 if (first_key_on) {
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
334 dfprintf(debug_file, "Operator: %d, env rate: %d (2*%d+%d), env_cyc: %d, cycle_shift: %d, env_cyc & ((1 << cycle_shift) - 1): %d\n", op, rate, operator->rates[operator->env_phase], channel->keycode >> operator->key_scaling,env_cyc, cycle_shift, env_cyc & ((1 << cycle_shift) - 1));
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
335 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
336 if (!(env_cyc & ((1 << cycle_shift) - 1))) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
337 uint32_t update_cycle = env_cyc >> cycle_shift & 0x7;
852
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator
Michael Pavone <pavone@retrodev.com>
parents: 851
diff changeset
338 uint16_t envelope_inc = rate_table[rate * 8 + update_cycle];
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
339 if (operator->env_phase == PHASE_ATTACK) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
340 //this can probably be optimized to a single shift rather than a multiply + shift
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
341 if (first_key_on) {
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
342 dfprintf(debug_file, "Changing op %d envelope %d by %d(%d * %d) in attack phase\n", op, operator->envelope, (~operator->envelope * envelope_inc) >> 4, ~operator->envelope, envelope_inc);
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
343 }
513
24ebabd89162 Properly clamp envelope value to zero when it overflows during the attack phase. This fixes a number of instruments that sounded rather wrong as well as the missing melody line from Mushroom Hill Zone in Sonic and Knuckles
Michael Pavone <pavone@retrodev.com>
parents: 505
diff changeset
344 uint16_t old_env = operator->envelope;
852
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator
Michael Pavone <pavone@retrodev.com>
parents: 851
diff changeset
345 operator->envelope += ((~operator->envelope * envelope_inc) >> 4) & 0xFFFFFFFC;
513
24ebabd89162 Properly clamp envelope value to zero when it overflows during the attack phase. This fixes a number of instruments that sounded rather wrong as well as the missing melody line from Mushroom Hill Zone in Sonic and Knuckles
Michael Pavone <pavone@retrodev.com>
parents: 505
diff changeset
346 if (operator->envelope > old_env) {
24ebabd89162 Properly clamp envelope value to zero when it overflows during the attack phase. This fixes a number of instruments that sounded rather wrong as well as the missing melody line from Mushroom Hill Zone in Sonic and Knuckles
Michael Pavone <pavone@retrodev.com>
parents: 505
diff changeset
347 //Handle overflow
24ebabd89162 Properly clamp envelope value to zero when it overflows during the attack phase. This fixes a number of instruments that sounded rather wrong as well as the missing melody line from Mushroom Hill Zone in Sonic and Knuckles
Michael Pavone <pavone@retrodev.com>
parents: 505
diff changeset
348 operator->envelope = 0;
24ebabd89162 Properly clamp envelope value to zero when it overflows during the attack phase. This fixes a number of instruments that sounded rather wrong as well as the missing melody line from Mushroom Hill Zone in Sonic and Knuckles
Michael Pavone <pavone@retrodev.com>
parents: 505
diff changeset
349 }
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
350 if (!operator->envelope) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
351 operator->env_phase = PHASE_DECAY;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
352 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
353 } else {
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
354 if (first_key_on) {
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
355 dfprintf(debug_file, "Changing op %d envelope %d by %d in %s phase\n", op, operator->envelope, envelope_inc,
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
356 operator->env_phase == PHASE_SUSTAIN ? "sustain" : (operator->env_phase == PHASE_DECAY ? "decay": "release"));
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
357 }
852
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator
Michael Pavone <pavone@retrodev.com>
parents: 851
diff changeset
358 //envelope value is 10-bits, but it will be used as a 4.8 value
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator
Michael Pavone <pavone@retrodev.com>
parents: 851
diff changeset
359 operator->envelope += envelope_inc << 2;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
360 //clamp to max attenuation value
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
361 if (operator->envelope > MAX_ENVELOPE) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
362 operator->envelope = MAX_ENVELOPE;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
363 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
364 }
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
365 }
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
366 context->current_env_op++;
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
367 if (context->current_env_op == NUM_OPERATORS) {
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
368 context->current_env_op = 0;
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
369 context->env_counter++;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
370 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
371 }
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
372
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
373 //Update Phase Generator
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
374 uint32_t channel = context->current_op / 4;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
375 if (channel != 5 || !context->dac_enable) {
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
376 uint32_t op = context->current_op;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
377 //printf("updating operator %d of channel %d\n", op, channel);
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
378 ym_operator * operator = context->operators + op;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
379 ym_channel * chan = context->channels + channel;
396
09328dbe6700 Fix output of algorithm 4 and make some other minor YM2612 core improvements
Mike Pavone <pavone@retrodev.com>
parents: 386
diff changeset
380 uint16_t phase = operator->phase_counter >> 10 & 0x3FF;
935
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
381 operator->phase_counter += ym_calc_phase_inc(context, operator, context->current_op);
371
0f8a759f1ff4 Use signed ints for things that represent signed values in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 370
diff changeset
382 int16_t mod = 0;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
383 switch (op % 4)
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
384 {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
385 case 0://Operator 1
377
da8d53dc914b Initial stab at feedback
Mike Pavone <pavone@retrodev.com>
parents: 376
diff changeset
386 if (chan->feedback) {
527
7df7f493b3b6 Fix operator 1 self-feedback
Michael Pavone <pavone@retrodev.com>
parents: 522
diff changeset
387 mod = (chan->op1_old + operator->output) >> (10-chan->feedback);
377
da8d53dc914b Initial stab at feedback
Mike Pavone <pavone@retrodev.com>
parents: 376
diff changeset
388 }
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
389 break;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
390 case 1://Operator 3
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
391 switch(chan->algorithm)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
392 {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
393 case 0:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
394 case 2:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
395 //modulate by operator 2
379
3218e2f8d685 Make shift value of operator output to modulation input a define
Mike Pavone <pavone@retrodev.com>
parents: 378
diff changeset
396 mod = context->operators[op+1].output >> YM_MOD_SHIFT;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
397 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
398 case 1:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
399 //modulate by operator 1+2
379
3218e2f8d685 Make shift value of operator output to modulation input a define
Mike Pavone <pavone@retrodev.com>
parents: 378
diff changeset
400 mod = (context->operators[op-1].output + context->operators[op+1].output) >> YM_MOD_SHIFT;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
401 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
402 case 5:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
403 //modulate by operator 1
379
3218e2f8d685 Make shift value of operator output to modulation input a define
Mike Pavone <pavone@retrodev.com>
parents: 378
diff changeset
404 mod = context->operators[op-1].output >> YM_MOD_SHIFT;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
405 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
406 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
407 case 2://Operator 2
406
b1bc1947d949 Fix modulation condition for operator 2
Mike Pavone <pavone@retrodev.com>
parents: 403
diff changeset
408 if (chan->algorithm != 1 && chan->algorithm != 2 && chan->algorithm != 7) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
409 //modulate by Operator 1
379
3218e2f8d685 Make shift value of operator output to modulation input a define
Mike Pavone <pavone@retrodev.com>
parents: 378
diff changeset
410 mod = context->operators[op-2].output >> YM_MOD_SHIFT;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
411 }
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
412 break;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
413 case 3://Operator 4
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
414 switch(chan->algorithm)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
415 {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
416 case 0:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
417 case 1:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
418 case 4:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
419 //modulate by operator 3
379
3218e2f8d685 Make shift value of operator output to modulation input a define
Mike Pavone <pavone@retrodev.com>
parents: 378
diff changeset
420 mod = context->operators[op-2].output >> YM_MOD_SHIFT;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
421 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
422 case 2:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
423 //modulate by operator 1+3
379
3218e2f8d685 Make shift value of operator output to modulation input a define
Mike Pavone <pavone@retrodev.com>
parents: 378
diff changeset
424 mod = (context->operators[op-3].output + context->operators[op-2].output) >> YM_MOD_SHIFT;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
425 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
426 case 3:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
427 //modulate by operator 2+3
379
3218e2f8d685 Make shift value of operator output to modulation input a define
Mike Pavone <pavone@retrodev.com>
parents: 378
diff changeset
428 mod = (context->operators[op-1].output + context->operators[op-2].output) >> YM_MOD_SHIFT;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
429 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
430 case 5:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
431 //modulate by operator 1
379
3218e2f8d685 Make shift value of operator output to modulation input a define
Mike Pavone <pavone@retrodev.com>
parents: 378
diff changeset
432 mod = context->operators[op-3].output >> YM_MOD_SHIFT;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
433 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
434 }
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
435 break;
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
436 }
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
437 uint16_t env = operator->envelope + operator->total_level;
740
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
438 if (operator->am) {
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
439 uint16_t base_am = (context->lfo_am_step & 0x80 ? context->lfo_am_step : ~context->lfo_am_step) & 0x7E;
930
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
440 if (ams_shift[chan->ams] >= 0) {
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
441 env += base_am >> ams_shift[chan->ams];
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
442 } else {
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
443 env += base_am << (-ams_shift[chan->ams]);
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
444 }
740
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
445 }
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
446 if (env > MAX_ENVELOPE) {
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
447 env = MAX_ENVELOPE;
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
448 }
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
449 if (first_key_on) {
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
450 dfprintf(debug_file, "op %d, base phase: %d, mod: %d, sine: %d, out: %d\n", op, phase, mod, sine_table[(phase+mod) & 0x1FF], pow_table[sine_table[phase & 0x1FF] + env]);
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
451 }
527
7df7f493b3b6 Fix operator 1 self-feedback
Michael Pavone <pavone@retrodev.com>
parents: 522
diff changeset
452 //if ((channel != 0 && channel != 4) || chan->algorithm != 5) {
7df7f493b3b6 Fix operator 1 self-feedback
Michael Pavone <pavone@retrodev.com>
parents: 522
diff changeset
453 phase += mod;
7df7f493b3b6 Fix operator 1 self-feedback
Michael Pavone <pavone@retrodev.com>
parents: 522
diff changeset
454 //}
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
455
371
0f8a759f1ff4 Use signed ints for things that represent signed values in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 370
diff changeset
456 int16_t output = pow_table[sine_table[phase & 0x1FF] + env];
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
457 if (phase & 0x200) {
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
458 output = -output;
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
459 }
527
7df7f493b3b6 Fix operator 1 self-feedback
Michael Pavone <pavone@retrodev.com>
parents: 522
diff changeset
460 if (op % 4 == 0) {
7df7f493b3b6 Fix operator 1 self-feedback
Michael Pavone <pavone@retrodev.com>
parents: 522
diff changeset
461 chan->op1_old = operator->output;
7df7f493b3b6 Fix operator 1 self-feedback
Michael Pavone <pavone@retrodev.com>
parents: 522
diff changeset
462 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
463 operator->output = output;
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
464 //Update the channel output if we've updated all operators
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
465 if (op % 4 == 3) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
466 if (chan->algorithm < 4) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
467 chan->output = operator->output;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
468 } else if(chan->algorithm == 4) {
396
09328dbe6700 Fix output of algorithm 4 and make some other minor YM2612 core improvements
Mike Pavone <pavone@retrodev.com>
parents: 386
diff changeset
469 chan->output = operator->output + context->operators[channel * 4 + 2].output;
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
470 } else {
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
471 output = 0;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
472 for (uint32_t op = ((chan->algorithm == 7) ? 0 : 1) + channel*4; op < (channel+1)*4; op++) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
473 output += context->operators[op].output;
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
474 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
475 chan->output = output;
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
476 }
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
477 if (first_key_on) {
371
0f8a759f1ff4 Use signed ints for things that represent signed values in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 370
diff changeset
478 int16_t value = context->channels[channel].output & 0x3FE0;
0f8a759f1ff4 Use signed ints for things that represent signed values in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 370
diff changeset
479 if (value & 0x2000) {
0f8a759f1ff4 Use signed ints for things that represent signed values in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 370
diff changeset
480 value |= 0xC000;
0f8a759f1ff4 Use signed ints for things that represent signed values in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 370
diff changeset
481 }
522
6a14c5a95648 Adjust PSG and YM-2612 volume to be closer to the real console
Michael Pavone <pavone@retrodev.com>
parents: 521
diff changeset
482 dfprintf(debug_file, "channel %d output: %d\n", channel, (value * YM_VOLUME_MULTIPLIER) / YM_VOLUME_DIVIDER);
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
483 }
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
484 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
485 //puts("operator update done");
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
486 }
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
487 context->current_op++;
396
09328dbe6700 Fix output of algorithm 4 and make some other minor YM2612 core improvements
Mike Pavone <pavone@retrodev.com>
parents: 386
diff changeset
488 if (context->current_op == NUM_OPERATORS) {
09328dbe6700 Fix output of algorithm 4 and make some other minor YM2612 core improvements
Mike Pavone <pavone@retrodev.com>
parents: 386
diff changeset
489 context->current_op = 0;
965
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
490
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
491 context->buffer_fraction += context->buffer_inc;
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
492 int16_t left = 0, right = 0;
483
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
493 for (int i = 0; i < NUM_CHANNELS; i++) {
521
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
494 int16_t value = context->channels[i].output;
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
495 if (value > 0x1FE0) {
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
496 value = 0x1FE0;
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
497 } else if (value < -0x1FF0) {
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
498 value = -0x1FF0;
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
499 } else {
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
500 value &= 0x3FE0;
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
501 if (value & 0x2000) {
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
502 value |= 0xC000;
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
503 }
380
1c8d74f2ab0b Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run.
Mike Pavone <pavone@retrodev.com>
parents: 379
diff changeset
504 }
965
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
505 if (context->channels[i].logfile && context->buffer_fraction > BUFFER_INC_RES) {
483
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
506 fwrite(&value, sizeof(value), 1, context->channels[i].logfile);
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
507 }
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
508 if (context->channels[i].lr & 0x80) {
965
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
509 left += (value * YM_VOLUME_MULTIPLIER) / YM_VOLUME_DIVIDER;
380
1c8d74f2ab0b Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run.
Mike Pavone <pavone@retrodev.com>
parents: 379
diff changeset
510 }
483
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
511 if (context->channels[i].lr & 0x40) {
965
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
512 right += (value * YM_VOLUME_MULTIPLIER) / YM_VOLUME_DIVIDER;
483
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
513 }
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
514 }
965
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
515 int32_t tmp = left * context->lowpass_alpha + context->last_left * (0x10000 - context->lowpass_alpha);
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
516 left = tmp >> 16;
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
517 tmp = right * context->lowpass_alpha + context->last_right * (0x10000 - context->lowpass_alpha);
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
518 right = tmp >> 16;
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
519 if (context->buffer_fraction > BUFFER_INC_RES) {
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
520 context->buffer_fraction -= BUFFER_INC_RES;
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
521
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
522 int64_t tmp = context->last_left * ((context->buffer_fraction << 16) / context->buffer_inc);
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
523 tmp += left * (0x10000 - ((context->buffer_fraction << 16) / context->buffer_inc));
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
524 context->audio_buffer[context->buffer_pos] = tmp >> 16;
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
525
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
526 tmp = context->last_right * ((context->buffer_fraction << 16) / context->buffer_inc);
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
527 tmp += right * (0x10000 - ((context->buffer_fraction << 16) / context->buffer_inc));
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
528 context->audio_buffer[context->buffer_pos+1] = tmp >> 16;
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
529
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
530 context->buffer_pos += 2;
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
531 if (context->buffer_pos == context->sample_limit) {
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
532 if (!headless) {
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
533 render_wait_ym(context);
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
534 }
505
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment.
Michael Pavone <pavone@retrodev.com>
parents: 483
diff changeset
535 }
380
1c8d74f2ab0b Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run.
Mike Pavone <pavone@retrodev.com>
parents: 379
diff changeset
536 }
965
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
537 context->last_left = left;
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
538 context->last_right = right;
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
539 }
965
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
540
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
541 }
535
aaa77e351c24 Better emulation of the YM-2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 532
diff changeset
542 if (context->current_cycle >= context->write_cycle + (context->busy_cycles * context->clock_inc / 6)) {
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
543 context->status &= 0x7F;
374
d42a8a3e4894 Fix YM2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 371
diff changeset
544 context->write_cycle = CYCLE_NEVER;
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
545 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
546 //printf("Done running YM2612 at cycle %d\n", context->current_cycle, to_cycle);
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
547 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
548
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
549 void ym_address_write_part1(ym2612_context * context, uint8_t address)
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
550 {
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
551 //printf("address_write_part1: %X\n", address);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
552 context->selected_reg = address;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
553 context->selected_part = 0;
535
aaa77e351c24 Better emulation of the YM-2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 532
diff changeset
554 context->write_cycle = context->current_cycle;
aaa77e351c24 Better emulation of the YM-2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 532
diff changeset
555 context->busy_cycles = BUSY_CYCLES_ADDRESS;
650
55b550fe8891 Set the busy flag after a YM-2612 address write
Michael Pavone <pavone@retrodev.com>
parents: 535
diff changeset
556 context->status |= 0x80;
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
557 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
558
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
559 void ym_address_write_part2(ym2612_context * context, uint8_t address)
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
560 {
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
561 //printf("address_write_part2: %X\n", address);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
562 context->selected_reg = address;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
563 context->selected_part = 1;
535
aaa77e351c24 Better emulation of the YM-2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 532
diff changeset
564 context->write_cycle = context->current_cycle;
aaa77e351c24 Better emulation of the YM-2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 532
diff changeset
565 context->busy_cycles = BUSY_CYCLES_ADDRESS;
650
55b550fe8891 Set the busy flag after a YM-2612 address write
Michael Pavone <pavone@retrodev.com>
parents: 535
diff changeset
566 context->status |= 0x80;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
567 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
568
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
569 uint8_t fnum_to_keycode[] = {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
570 //F11 = 0
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
571 0,0,0,0,0,0,0,1,
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
572 //F11 = 1
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
573 2,3,3,3,3,3,3,3
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
574 };
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
575
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
576 //table courtesy of Nemesis
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
577 uint32_t detune_table[][4] = {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
578 {0, 0, 1, 2}, //0 (0x00)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
579 {0, 0, 1, 2}, //1 (0x01)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
580 {0, 0, 1, 2}, //2 (0x02)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
581 {0, 0, 1, 2}, //3 (0x03)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
582 {0, 1, 2, 2}, //4 (0x04)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
583 {0, 1, 2, 3}, //5 (0x05)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
584 {0, 1, 2, 3}, //6 (0x06)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
585 {0, 1, 2, 3}, //7 (0x07)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
586 {0, 1, 2, 4}, //8 (0x08)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
587 {0, 1, 3, 4}, //9 (0x09)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
588 {0, 1, 3, 4}, //10 (0x0A)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
589 {0, 1, 3, 5}, //11 (0x0B)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
590 {0, 2, 4, 5}, //12 (0x0C)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
591 {0, 2, 4, 6}, //13 (0x0D)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
592 {0, 2, 4, 6}, //14 (0x0E)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
593 {0, 2, 5, 7}, //15 (0x0F)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
594 {0, 2, 5, 8}, //16 (0x10)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
595 {0, 3, 6, 8}, //17 (0x11)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
596 {0, 3, 6, 9}, //18 (0x12)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
597 {0, 3, 7,10}, //19 (0x13)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
598 {0, 4, 8,11}, //20 (0x14)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
599 {0, 4, 8,12}, //21 (0x15)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
600 {0, 4, 9,13}, //22 (0x16)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
601 {0, 5,10,14}, //23 (0x17)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
602 {0, 5,11,16}, //24 (0x18)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
603 {0, 6,12,17}, //25 (0x19)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
604 {0, 6,13,19}, //26 (0x1A)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
605 {0, 7,14,20}, //27 (0x1B)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
606 {0, 8,16,22}, //28 (0x1C)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
607 {0, 8,16,22}, //29 (0x1D)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
608 {0, 8,16,22}, //30 (0x1E)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
609 {0, 8,16,22}
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
610 }; //31 (0x1F)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
611
935
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
612 uint32_t ym_calc_phase_inc(ym2612_context * context, ym_operator * operator, uint32_t op)
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
613 {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
614 uint32_t chan_num = op / 4;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
615 //printf("ym_update_phase_inc | channel: %d, op: %d\n", chan_num, op);
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
616 //base frequency
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
617 ym_channel * channel = context->channels + chan_num;
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
618 uint32_t inc, detune;
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
619 if (chan_num == 2 && context->ch3_mode && (op < (2*4 + 3))) {
738
8972378e314f Fix register to operator mapping for channel 3 special mode
Michael Pavone <pavone@retrodev.com>
parents: 650
diff changeset
620 //supplemental fnum registers are in a different order than normal slot paramters
936
f1a8124ad881 Fix register to operator mapping for channel 3 special mode and actually get it right this time
Michael Pavone <pavone@retrodev.com>
parents: 935
diff changeset
621 int index = op-2*4;
f1a8124ad881 Fix register to operator mapping for channel 3 special mode and actually get it right this time
Michael Pavone <pavone@retrodev.com>
parents: 935
diff changeset
622 if (index < 2) {
f1a8124ad881 Fix register to operator mapping for channel 3 special mode and actually get it right this time
Michael Pavone <pavone@retrodev.com>
parents: 935
diff changeset
623 index ^= 1;
f1a8124ad881 Fix register to operator mapping for channel 3 special mode and actually get it right this time
Michael Pavone <pavone@retrodev.com>
parents: 935
diff changeset
624 }
738
8972378e314f Fix register to operator mapping for channel 3 special mode
Michael Pavone <pavone@retrodev.com>
parents: 650
diff changeset
625 inc = context->ch3_supp[index].fnum;
935
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
626 if (channel->pms) {
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
627 inc = inc * 2 + lfo_pm_table[(inc & 0x7F0) * 16 + channel->pms + context->lfo_pm_step];
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
628 }
738
8972378e314f Fix register to operator mapping for channel 3 special mode
Michael Pavone <pavone@retrodev.com>
parents: 650
diff changeset
629 if (!context->ch3_supp[index].block) {
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
630 inc >>= 1;
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
631 } else {
738
8972378e314f Fix register to operator mapping for channel 3 special mode
Michael Pavone <pavone@retrodev.com>
parents: 650
diff changeset
632 inc <<= (context->ch3_supp[index].block-1);
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
633 }
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
634 //detune
738
8972378e314f Fix register to operator mapping for channel 3 special mode
Michael Pavone <pavone@retrodev.com>
parents: 650
diff changeset
635 detune = detune_table[context->ch3_supp[index].keycode][operator->detune & 0x3];
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
636 } else {
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
637 inc = channel->fnum;
935
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
638 if (channel->pms) {
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
639 inc = inc * 2 + lfo_pm_table[(inc & 0x7F0) * 16 + channel->pms + context->lfo_pm_step];
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
640 }
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
641 if (!channel->block) {
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
642 inc >>= 1;
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
643 } else {
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
644 inc <<= (channel->block-1);
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
645 }
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
646 //detune
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
647 detune = detune_table[channel->keycode][operator->detune & 0x3];
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
648 }
935
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
649 if (channel->pms) {
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
650 inc >>= 1;
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
651 }
739
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
652 if (operator->detune & 0x4) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
653 inc -= detune;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
654 //this can underflow, mask to 17-bit result
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
655 inc &= 0x1FFFF;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
656 } else {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
657 inc += detune;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
658 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
659 //multiple
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
660 if (operator->multiple) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
661 inc *= operator->multiple;
739
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
662 inc &= 0xFFFFF;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
663 } else {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
664 //0.5
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
665 inc >>= 1;
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
666 }
365
3ba3b6656fff Actually save the shifted phase inc after applying the block shift
Mike Pavone <pavone@retrodev.com>
parents: 364
diff changeset
667 //printf("phase_inc for operator %d: %d, block: %d, fnum: %d, detune: %d, multiple: %d\n", op, inc, channel->block, channel->fnum, detune, operator->multiple);
935
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
668 return inc;
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
669 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
670
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
671 void ym_data_write(ym2612_context * context, uint8_t value)
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
672 {
451
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
673 if (context->selected_reg >= YM_REG_END) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
674 return;
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
675 }
451
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
676 if (context->selected_part) {
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
677 if (context->selected_reg < YM_PART2_START) {
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
678 return;
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
679 }
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
680 context->part2_regs[context->selected_reg - YM_PART2_START] = value;
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
681 } else {
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
682 if (context->selected_reg < YM_PART1_START) {
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
683 return;
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
684 }
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
685 context->part1_regs[context->selected_reg - YM_PART1_START] = value;
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
686 }
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
687 dfprintf(debug_file, "write of %X to reg %X in part %d\n", value, context->selected_reg, context->selected_part+1);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
688 if (context->selected_reg < 0x30) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
689 //Shared regs
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
690 switch (context->selected_reg)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
691 {
411
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
692 //TODO: Test reg
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
693 case REG_LFO:
532
666210adf87b Comment out LFO debug printf
Mike Pavone <pavone@retrodev.com>
parents: 527
diff changeset
694 /*if ((value & 0x8) && !context->lfo_enable) {
411
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
695 printf("LFO Enabled, Freq: %d\n", value & 0x7);
532
666210adf87b Comment out LFO debug printf
Mike Pavone <pavone@retrodev.com>
parents: 527
diff changeset
696 }*/
411
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
697 context->lfo_enable = value & 0x8;
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
698 if (!context->lfo_enable) {
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
699 context->lfo_am_step = context->lfo_pm_step = 0;
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
700 }
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
701 context->lfo_freq = value & 0x7;
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
702
411
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
703 break;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
704 case REG_TIMERA_HIGH:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
705 context->timer_a_load &= 0x3;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
706 context->timer_a_load |= value << 2;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
707 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
708 case REG_TIMERA_LOW:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
709 context->timer_a_load &= 0xFFFC;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
710 context->timer_a_load |= value & 0x3;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
711 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
712 case REG_TIMERB:
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
713 context->timer_b_load = value;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
714 break;
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
715 case REG_TIME_CTRL: {
403
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
716 if (value & BIT_TIMERA_ENABLE && !(context->timer_control & BIT_TIMERA_ENABLE)) {
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
717 context->timer_a = TIMER_A_MAX;
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
718 context->timer_control |= BIT_TIMERA_LOAD;
403
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
719 }
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
720 if (value & BIT_TIMERB_ENABLE && !(context->timer_control & BIT_TIMERB_ENABLE)) {
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
721 context->timer_b = TIMER_B_MAX;
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
722 context->timer_control |= BIT_TIMERB_LOAD;
403
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
723 }
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
724 context->timer_control &= (BIT_TIMERA_LOAD | BIT_TIMERB_LOAD);
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
725 context->timer_control |= value & 0xF;
403
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
726 if (value & BIT_TIMERA_RESET) {
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
727 context->status &= ~BIT_STATUS_TIMERA;
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
728 }
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
729 if (value & BIT_TIMERB_RESET) {
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
730 context->status &= ~BIT_STATUS_TIMERB;
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
731 }
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
732 context->ch3_mode = value & 0xC0;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
733 break;
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
734 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
735 case REG_KEY_ONOFF: {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
736 uint8_t channel = value & 0x7;
386
6e5c4f3ab0e2 Fix channel mapping in key on/off register
Mike Pavone <pavone@retrodev.com>
parents: 383
diff changeset
737 if (channel != 3 && channel != 7) {
6e5c4f3ab0e2 Fix channel mapping in key on/off register
Mike Pavone <pavone@retrodev.com>
parents: 383
diff changeset
738 if (channel > 2) {
6e5c4f3ab0e2 Fix channel mapping in key on/off register
Mike Pavone <pavone@retrodev.com>
parents: 383
diff changeset
739 channel--;
6e5c4f3ab0e2 Fix channel mapping in key on/off register
Mike Pavone <pavone@retrodev.com>
parents: 383
diff changeset
740 }
851
b10cf2c921ad Fix mapping of key on/off reg bits to operators
Michael Pavone <pavone@retrodev.com>
parents: 848
diff changeset
741 uint8_t bits[] = {0x10, 0x40, 0x20, 0x80};
b10cf2c921ad Fix mapping of key on/off reg bits to operators
Michael Pavone <pavone@retrodev.com>
parents: 848
diff changeset
742 for (uint8_t op = channel * 4, bit = 0; op < (channel + 1) * 4; op++, bit++) {
b10cf2c921ad Fix mapping of key on/off reg bits to operators
Michael Pavone <pavone@retrodev.com>
parents: 848
diff changeset
743 if (value & bits[bit]) {
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
744 if (context->operators[op].env_phase == PHASE_RELEASE)
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
745 {
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
746 first_key_on = 1;
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
747 //printf("Key On for operator %d in channel %d\n", op, channel);
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
748 context->operators[op].phase_counter = 0;
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
749 context->operators[op].env_phase = PHASE_ATTACK;
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
750 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
751 } else {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
752 //printf("Key Off for operator %d in channel %d\n", op, channel);
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
753 context->operators[op].env_phase = PHASE_RELEASE;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
754 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
755 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
756 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
757 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
758 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
759 case REG_DAC:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
760 if (context->dac_enable) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
761 context->channels[5].output = (((int16_t)value) - 0x80) << 6;
396
09328dbe6700 Fix output of algorithm 4 and make some other minor YM2612 core improvements
Mike Pavone <pavone@retrodev.com>
parents: 386
diff changeset
762 //printf("DAC Write %X(%d) @ %d\n", value, context->channels[5].output, context->current_cycle);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
763 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
764 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
765 case REG_DAC_ENABLE:
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
766 //printf("DAC Enable: %X\n", value);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
767 context->dac_enable = value & 0x80;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
768 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
769 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
770 } else if (context->selected_reg < 0xA0) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
771 //part
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
772 uint8_t op = context->selected_part ? (NUM_OPERATORS/2) : 0;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
773 //channel in part
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
774 if ((context->selected_reg & 0x3) != 0x3) {
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
775 op += 4 * (context->selected_reg & 0x3) + ((context->selected_reg & 0xC) / 4);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
776 //printf("write targets operator %d (%d of channel %d)\n", op, op % 4, op / 4);
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
777 ym_operator * operator = context->operators + op;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
778 switch (context->selected_reg & 0xF0)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
779 {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
780 case REG_DETUNE_MULT:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
781 operator->detune = value >> 4 & 0x7;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
782 operator->multiple = value & 0xF;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
783 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
784 case REG_TOTAL_LEVEL:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
785 operator->total_level = (value & 0x7F) << 5;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
786 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
787 case REG_ATTACK_KS:
376
f6def5cdf1b4 Fix key scaling
Mike Pavone <pavone@retrodev.com>
parents: 374
diff changeset
788 operator->key_scaling = 3 - (value >> 6);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
789 operator->rates[PHASE_ATTACK] = value & 0x1F;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
790 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
791 case REG_DECAY_AM:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
792 //TODO: AM flag for LFO
739
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
793 operator->am = value & 0x80;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
794 operator->rates[PHASE_DECAY] = value & 0x1F;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
795 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
796 case REG_SUSTAIN_RATE:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
797 operator->rates[PHASE_SUSTAIN] = value & 0x1F;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
798 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
799 case REG_S_LVL_R_RATE:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
800 operator->rates[PHASE_RELEASE] = (value & 0xF) << 1 | 1;
852
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator
Michael Pavone <pavone@retrodev.com>
parents: 851
diff changeset
801 operator->sustain_level = (value & 0xF0) << 3;
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator
Michael Pavone <pavone@retrodev.com>
parents: 851
diff changeset
802 if (operator->sustain_level == 0x780) {
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator
Michael Pavone <pavone@retrodev.com>
parents: 851
diff changeset
803 operator->sustain_level = MAX_ENVELOPE;
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator
Michael Pavone <pavone@retrodev.com>
parents: 851
diff changeset
804 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
805 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
806 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
807 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
808 } else {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
809 uint8_t channel = context->selected_reg & 0x3;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
810 if (channel != 3) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
811 if (context->selected_part) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
812 channel += 3;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
813 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
814 //printf("write targets channel %d\n", channel);
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
815 switch (context->selected_reg & 0xFC)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
816 {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
817 case REG_FNUM_LOW:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
818 context->channels[channel].block = context->channels[channel].block_fnum_latch >> 3 & 0x7;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
819 context->channels[channel].fnum = (context->channels[channel].block_fnum_latch & 0x7) << 8 | value;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
820 context->channels[channel].keycode = context->channels[channel].block << 2 | fnum_to_keycode[context->channels[channel].fnum >> 7];
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
821 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
822 case REG_BLOCK_FNUM_H:{
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
823 context->channels[channel].block_fnum_latch = value;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
824 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
825 }
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
826 case REG_FNUM_LOW_CH3:
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
827 if (channel < 3) {
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
828 context->ch3_supp[channel].block = context->ch3_supp[channel].block_fnum_latch >> 3 & 0x7;
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
829 context->ch3_supp[channel].fnum = (context->ch3_supp[channel].block_fnum_latch & 0x7) << 8 | value;
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
830 context->ch3_supp[channel].keycode = context->ch3_supp[channel].block << 2 | fnum_to_keycode[context->ch3_supp[channel].fnum >> 7];
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
831 }
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
832 break;
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
833 case REG_BLOCK_FN_CH3:
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
834 if (channel < 3) {
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
835 context->ch3_supp[channel].block_fnum_latch = value;
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
836 }
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
837 break;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
838 case REG_ALG_FEEDBACK:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
839 context->channels[channel].algorithm = value & 0x7;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
840 context->channels[channel].feedback = value >> 3 & 0x7;
527
7df7f493b3b6 Fix operator 1 self-feedback
Michael Pavone <pavone@retrodev.com>
parents: 522
diff changeset
841 //printf("Algorithm %d, feedback %d for channel %d\n", value & 0x7, value >> 3 & 0x7, channel);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
842 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
843 case REG_LR_AMS_PMS:
411
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
844 context->channels[channel].pms = (value & 0x7) * 32;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
845 context->channels[channel].ams = value >> 4 & 0x3;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
846 context->channels[channel].lr = value & 0xC0;
369
fc820ab1394b Fix left/right enable default value
Mike Pavone <pavone@retrodev.com>
parents: 365
diff changeset
847 //printf("Write of %X to LR_AMS_PMS reg for channel %d\n", value, channel);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
848 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
849 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
850 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
851 }
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
852
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
853 context->write_cycle = context->current_cycle;
535
aaa77e351c24 Better emulation of the YM-2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 532
diff changeset
854 context->busy_cycles = context->selected_reg < 0xA0 ? BUSY_CYCLES_DATA_LOW : BUSY_CYCLES_DATA_HIGH;
374
d42a8a3e4894 Fix YM2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 371
diff changeset
855 context->status |= 0x80;
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
856 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
857
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
858 uint8_t ym_read_status(ym2612_context * context)
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
859 {
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
860 return context->status;
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
861 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
862
739
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
863 void ym_print_channel_info(ym2612_context *context, int channel)
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
864 {
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
865 ym_channel *chan = context->channels + channel;
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
866 printf("\n***Channel %d***\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
867 "Algorithm: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
868 "Feedback: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
869 "Pan: %s\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
870 "AMS: %d\n"
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
871 "PMS: %d\n",
739
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
872 channel+1, chan->algorithm, chan->feedback,
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
873 chan->lr == 0xC0 ? "LR" : chan->lr == 0x80 ? "L" : chan->lr == 0x40 ? "R" : "",
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
874 chan->ams, chan->pms);
930
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
875 if (channel == 2) {
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
876 printf(
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
877 "Mode: %X: %s\n",
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
878 context->ch3_mode, context->ch3_mode ? "special" : "normal");
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
879 }
739
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
880 for (int operator = channel * 4; operator < channel * 4+4; operator++)
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
881 {
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
882 int dispnum = operator - channel * 4 + 1;
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
883 if (dispnum == 2) {
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
884 dispnum = 3;
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
885 } else if (dispnum == 3) {
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
886 dispnum = 2;
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
887 }
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
888 ym_operator *op = context->operators + operator;
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
889 printf("\nOperator %d:\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
890 " Multiple: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
891 " Detune: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
892 " Total Level: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
893 " Attack Rate: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
894 " Key Scaling: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
895 " Decay Rate: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
896 " Sustain Level: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
897 " Sustain Rate: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
898 " Release Rate: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
899 " Amplitude Modulation %s\n",
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
900 dispnum, op->multiple, op->detune, op->total_level,
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
901 op->rates[PHASE_ATTACK], op->key_scaling, op->rates[PHASE_DECAY],
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
902 op->sustain_level, op->rates[PHASE_SUSTAIN], op->rates[PHASE_RELEASE],
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
903 op->am ? "On" : "Off");
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
904 }
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
905 }
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
906
930
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
907 void ym_print_timer_info(ym2612_context *context)
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
908 {
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
909 printf("***Timer A***\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
910 "Current Value: %d\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
911 "Load Value: %d\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
912 "Triggered: %s\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
913 "Enabled: %s\n\n",
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
914 context->timer_a,
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
915 context->timer_a_load,
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
916 context->status & BIT_STATUS_TIMERA ? "yes" : "no",
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
917 context->timer_control & BIT_TIMERA_ENABLE ? "yes" : "no");
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
918 printf("***Timer B***\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
919 "Current Value: %d\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
920 "Load Value: %d\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
921 "Triggered: %s\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
922 "Enabled: %s\n\n",
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
923 context->timer_b,
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
924 context->timer_b_load,
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
925 context->status & BIT_STATUS_TIMERB ? "yes" : "no",
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
926 context->timer_control & BIT_TIMERB_ENABLE ? "yes" : "no");
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
927 }
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
928