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annotate ym2612.c @ 1872:45be49d3a98b

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Forgot to commit the header changes
author Michael Pavone <pavone@retrodev.com>
date Sun, 28 Jul 2019 10:35:15 -0700
parents ce6881d64eef
children 43a6cee4fd00
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1 /*
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2 Copyright 2013 Michael Pavone
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3 This file is part of BlastEm.
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4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
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5 */
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6 #include <string.h>
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7 #include <math.h>
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8 #include <stdio.h>
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9 #include <stdlib.h>
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10 #include "ym2612.h"
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11 #include "render.h"
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12 #include "wave.h"
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13 #include "blastem.h"
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14
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15 //#define DO_DEBUG_PRINT
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16 #ifdef DO_DEBUG_PRINT
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17 #define dfprintf fprintf
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18 #define dfopen(var, fname, mode) var=fopen(fname, mode)
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19 #else
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20 #define dfprintf
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21 #define dfopen(var, fname, mode)
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22 #endif
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23
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24 #define BUSY_CYCLES_ADDRESS 17
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25 #define BUSY_CYCLES_DATA_LOW 83
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26 #define BUSY_CYCLES_DATA_HIGH 47
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27 #define OP_UPDATE_PERIOD 144
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29 #define BIT_TIMERA_ENABLE 0x1
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30 #define BIT_TIMERB_ENABLE 0x2
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31 #define BIT_TIMERA_OVEREN 0x4
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32 #define BIT_TIMERB_OVEREN 0x8
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33 #define BIT_TIMERA_RESET 0x10
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34 #define BIT_TIMERB_RESET 0x20
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35
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36 #define BIT_TIMERA_LOAD 0x40
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37 #define BIT_TIMERB_LOAD 0x80
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38
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39 #define BIT_STATUS_TIMERA 0x1
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40 #define BIT_STATUS_TIMERB 0x2
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41
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42 static uint32_t ym_calc_phase_inc(ym2612_context * context, ym_operator * operator, uint32_t op);
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43
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44 enum {
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45 PHASE_ATTACK,
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46 PHASE_DECAY,
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47 PHASE_SUSTAIN,
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48 PHASE_RELEASE
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49 };
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50
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51 uint8_t did_tbl_init = 0;
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52 //According to Nemesis, real hardware only uses a 256 entry quarter sine table; however,
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53 //memory is cheap so using a half sine table will probably save some cycles
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54 //a full sine table would be nice, but negative numbers don't get along with log2
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55 #define SINE_TABLE_SIZE 512
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56 static uint16_t sine_table[SINE_TABLE_SIZE];
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57 //Similar deal here with the power table for log -> linear conversion
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58 //According to Nemesis, real hardware only uses a 256 entry table for the fractional part
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59 //and uses the whole part as a shift amount.
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60 #define POW_TABLE_SIZE (1 << 13)
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61 static uint16_t pow_table[POW_TABLE_SIZE];
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62
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63 static uint16_t rate_table_base[] = {
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64 //main portion
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65 0,1,0,1,0,1,0,1,
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66 0,1,0,1,1,1,0,1,
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67 0,1,1,1,0,1,1,1,
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68 0,1,1,1,1,1,1,1,
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69 //top end
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70 1,1,1,1,1,1,1,1,
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71 1,1,1,2,1,1,1,2,
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72 1,2,1,2,1,2,1,2,
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73 1,2,2,2,1,2,2,2,
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74 };
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75
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76 static uint16_t rate_table[64*8];
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77
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78 static uint8_t lfo_timer_values[] = {108, 77, 71, 67, 62, 44, 8, 5};
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79 static uint8_t lfo_pm_base[][8] = {
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80 {0, 0, 0, 0, 0, 0, 0, 0},
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81 {0, 0, 0, 0, 4, 4, 4, 4},
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82 {0, 0, 0, 4, 4, 4, 8, 8},
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83 {0, 0, 4, 4, 8, 8, 0xc, 0xc},
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84 {0, 0, 4, 8, 8, 8, 0xc,0x10},
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85 {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
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86 {0, 0,0x10,0x18,0x20,0x20,0x28,0x30},
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87 {0, 0,0x20,0x30,0x40,0x40,0x50,0x60}
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88 };
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89 static int16_t lfo_pm_table[128 * 32 * 8];
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90
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91 int16_t ams_shift[] = {8, 1, -1, -2};
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92
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93 #define MAX_ENVELOPE 0xFFC
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94 #define YM_DIVIDER 2
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95 #define CYCLE_NEVER 0xFFFFFFFF
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96
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97 static uint16_t round_fixed_point(double value, int dec_bits)
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98 {
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99 return value * (1 << dec_bits) + 0.5;
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100 }
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101
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102 static FILE * debug_file = NULL;
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103 static uint32_t first_key_on=0;
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104
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105 static ym2612_context * log_context = NULL;
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106
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107 static void ym_finalize_log()
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108 {
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109 if (!log_context) {
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110 return;
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111 }
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112 for (int i = 0; i < NUM_CHANNELS; i++) {
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113 if (log_context->channels[i].logfile) {
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114 wave_finalize(log_context->channels[i].logfile);
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115 }
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116 }
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117 log_context = NULL;
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118 }
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119
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120 void ym_adjust_master_clock(ym2612_context * context, uint32_t master_clock)
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121 {
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122 render_audio_adjust_clock(context->audio, master_clock, context->clock_inc * NUM_OPERATORS);
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123 }
407
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parents: 406
diff changeset
124
859
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parents: 853
diff changeset
125 #ifdef __ANDROID__
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diff changeset
126 #define log2(x) (log(x)/log(2))
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diff changeset
127 #endif
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parents: 853
diff changeset
128
1308
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parents: 1301
diff changeset
129
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diff changeset
130 #define TIMER_A_MAX 1023
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131 #define TIMER_B_MAX 255
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parents: 1301
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132
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parents: 1301
diff changeset
133 void ym_reset(ym2612_context *context)
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parents: 1301
diff changeset
134 {
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parents: 1301
diff changeset
135 memset(context->part1_regs, 0, sizeof(context->part1_regs));
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parents: 1301
diff changeset
136 memset(context->part2_regs, 0, sizeof(context->part2_regs));
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon
Michael Pavone <pavone@retrodev.com>
parents: 1301
diff changeset
137 memset(context->operators, 0, sizeof(context->operators));
1654
4637ab86be8c Preserve WAVE logging FILE * across YM2612 device reset
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parents: 1555
diff changeset
138 FILE* savedlogs[NUM_CHANNELS];
4637ab86be8c Preserve WAVE logging FILE * across YM2612 device reset
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parents: 1555
diff changeset
139 for (int i = 0; i < NUM_CHANNELS; i++)
4637ab86be8c Preserve WAVE logging FILE * across YM2612 device reset
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parents: 1555
diff changeset
140 {
4637ab86be8c Preserve WAVE logging FILE * across YM2612 device reset
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diff changeset
141 savedlogs[i] = context->channels[i].logfile;
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parents: 1555
diff changeset
142 }
1308
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parents: 1301
diff changeset
143 memset(context->channels, 0, sizeof(context->channels));
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parents: 1301
diff changeset
144 memset(context->ch3_supp, 0, sizeof(context->ch3_supp));
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon
Michael Pavone <pavone@retrodev.com>
parents: 1301
diff changeset
145 context->selected_reg = 0;
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon
Michael Pavone <pavone@retrodev.com>
parents: 1301
diff changeset
146 context->csm_keyon = 0;
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon
Michael Pavone <pavone@retrodev.com>
parents: 1301
diff changeset
147 context->ch3_mode = 0;
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon
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parents: 1301
diff changeset
148 context->dac_enable = 0;
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parents: 1301
diff changeset
149 context->status = 0;
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parents: 1301
diff changeset
150 context->timer_a_load = 0;
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parents: 1301
diff changeset
151 context->timer_b_load = 0;
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parents: 1301
diff changeset
152 //TODO: Confirm these on hardware
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon
Michael Pavone <pavone@retrodev.com>
parents: 1301
diff changeset
153 context->timer_a = TIMER_A_MAX;
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Michael Pavone <pavone@retrodev.com>
parents: 1301
diff changeset
154 context->timer_b = TIMER_B_MAX;
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parents: 1301
diff changeset
155
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Michael Pavone <pavone@retrodev.com>
parents: 1301
diff changeset
156 //TODO: Reset LFO state
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon
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parents: 1301
diff changeset
157
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Michael Pavone <pavone@retrodev.com>
parents: 1301
diff changeset
158 //some games seem to expect that the LR flags start out as 1
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon
Michael Pavone <pavone@retrodev.com>
parents: 1301
diff changeset
159 for (int i = 0; i < NUM_CHANNELS; i++) {
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon
Michael Pavone <pavone@retrodev.com>
parents: 1301
diff changeset
160 context->channels[i].lr = 0xC0;
1654
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parents: 1555
diff changeset
161 context->channels[i].logfile = savedlogs[i];
1308
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon
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parents: 1301
diff changeset
162 }
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parents: 1301
diff changeset
163 context->write_cycle = CYCLE_NEVER;
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parents: 1301
diff changeset
164 for (int i = 0; i < NUM_OPERATORS; i++) {
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon
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parents: 1301
diff changeset
165 context->operators[i].envelope = MAX_ENVELOPE;
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parents: 1301
diff changeset
166 context->operators[i].env_phase = PHASE_RELEASE;
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon
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parents: 1301
diff changeset
167 }
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parents: 1301
diff changeset
168 }
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Michael Pavone <pavone@retrodev.com>
parents: 1301
diff changeset
169
1555
6ce36c3f250b More audio refactoring in preparation for allowing proper sync to video with dynamic audio rate control
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parents: 1551
diff changeset
170 void ym_init(ym2612_context * context, uint32_t master_clock, uint32_t clock_div, uint32_t options)
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
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parents:
diff changeset
171 {
884
252dfd29831d Selecting a second game from the menu now works
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parents: 859
diff changeset
172 static uint8_t registered_finalize;
370
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parents: 369
diff changeset
173 dfopen(debug_file, "ym_debug.txt", "w");
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
174 memset(context, 0, sizeof(*context));
380
1c8d74f2ab0b Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run.
Mike Pavone <pavone@retrodev.com>
parents: 379
diff changeset
175 context->clock_inc = clock_div * 6;
1555
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parents: 1551
diff changeset
176 context->audio = render_audio_source(master_clock, context->clock_inc * NUM_OPERATORS, 2);
1308
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parents: 1301
diff changeset
177
369
fc820ab1394b Fix left/right enable default value
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parents: 365
diff changeset
178 //some games seem to expect that the LR flags start out as 1
fc820ab1394b Fix left/right enable default value
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parents: 365
diff changeset
179 for (int i = 0; i < NUM_CHANNELS; i++) {
407
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parents: 406
diff changeset
180 if (options & YM_OPT_WAVE_LOG) {
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parents: 406
diff changeset
181 char fname[64];
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parents: 406
diff changeset
182 sprintf(fname, "ym_channel_%d.wav", i);
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parents: 406
diff changeset
183 FILE * f = context->channels[i].logfile = fopen(fname, "wb");
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parents: 406
diff changeset
184 if (!f) {
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parents: 406
diff changeset
185 fprintf(stderr, "Failed to open WAVE log file %s for writing\n", fname);
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parents: 406
diff changeset
186 continue;
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parents: 406
diff changeset
187 }
1555
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parents: 1551
diff changeset
188 if (!wave_init(f, master_clock / (context->clock_inc * NUM_OPERATORS), 16, 1)) {
407
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parents: 406
diff changeset
189 fclose(f);
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
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parents: 406
diff changeset
190 context->channels[i].logfile = NULL;
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parents: 406
diff changeset
191 }
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
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parents: 406
diff changeset
192 }
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
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parents: 406
diff changeset
193 }
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
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parents: 406
diff changeset
194 if (options & YM_OPT_WAVE_LOG) {
c3abc4ada43d Add support for logging YM2612 channels to WAVE files
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parents: 406
diff changeset
195 log_context = context;
884
252dfd29831d Selecting a second game from the menu now works
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parents: 859
diff changeset
196 if (!registered_finalize) {
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Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
197 atexit(ym_finalize_log);
252dfd29831d Selecting a second game from the menu now works
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parents: 859
diff changeset
198 registered_finalize = 1;
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
199 }
369
fc820ab1394b Fix left/right enable default value
Mike Pavone <pavone@retrodev.com>
parents: 365
diff changeset
200 }
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
201 if (!did_tbl_init) {
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
202 //populate sine table
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
203 for (int32_t i = 0; i < 512; i++) {
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
204 double sine = sin( ((double)(i*2+1) / SINE_TABLE_SIZE) * M_PI_2 );
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
205
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
206 //table stores 4.8 fixed pointed representation of the base 2 log
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
207 sine_table[i] = round_fixed_point(-log2(sine), 8);
cc39629e8d06 YM2612 WIP snapshot before register refactor
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parents: 288
diff changeset
208 }
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
209 //populate power table
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
210 for (int32_t i = 0; i < POW_TABLE_SIZE; i++) {
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
211 double linear = pow(2, -((double)((i & 0xFF)+1) / 256.0));
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
212 int32_t tmp = round_fixed_point(linear, 11);
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
213 int32_t shift = (i >> 8) - 2;
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
214 if (shift < 0) {
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
215 tmp <<= 0-shift;
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
216 } else {
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
217 tmp >>= shift;
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
218 }
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
219 pow_table[i] = tmp;
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
220 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
221 //populate envelope generator rate table, from small base table
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
222 for (int rate = 0; rate < 64; rate++) {
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
223 for (int cycle = 0; cycle < 8; cycle++) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
224 uint16_t value;
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
225 if (rate < 2) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
226 value = 0;
365
3ba3b6656fff Actually save the shifted phase inc after applying the block shift
Mike Pavone <pavone@retrodev.com>
parents: 364
diff changeset
227 } else if (rate >= 60) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
228 value = 8;
365
3ba3b6656fff Actually save the shifted phase inc after applying the block shift
Mike Pavone <pavone@retrodev.com>
parents: 364
diff changeset
229 } else if (rate < 8) {
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
230 value = rate_table_base[((rate & 6) == 6 ? 16 : 0) + cycle];
365
3ba3b6656fff Actually save the shifted phase inc after applying the block shift
Mike Pavone <pavone@retrodev.com>
parents: 364
diff changeset
231 } else if (rate < 48) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
232 value = rate_table_base[(rate & 0x3) * 8 + cycle];
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
233 } else {
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
234 value = rate_table_base[32 + (rate & 0x3) * 8 + cycle] << ((rate - 48) >> 2);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
235 }
365
3ba3b6656fff Actually save the shifted phase inc after applying the block shift
Mike Pavone <pavone@retrodev.com>
parents: 364
diff changeset
236 rate_table[rate * 8 + cycle] = value;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
237 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
238 }
411
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
239 //populate LFO PM table from small base table
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
240 //seems like there must be a better way to derive this
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
241 for (int freq = 0; freq < 128; freq++) {
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
242 for (int pms = 0; pms < 8; pms++) {
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
243 for (int step = 0; step < 32; step++) {
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
244 int16_t value = 0;
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
245 for (int bit = 0x40, shift = 0; bit > 0; bit >>= 1, shift++) {
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
246 if (freq & bit) {
baf4688901f2 Initial stab at LFO phase modulation
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parents: 407
diff changeset
247 value += lfo_pm_base[pms][(step & 0x8) ? 7-step & 7 : step & 7] >> shift;
baf4688901f2 Initial stab at LFO phase modulation
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parents: 407
diff changeset
248 }
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
249 }
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
250 if (step & 0x10) {
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
251 value = -value;
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
252 }
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
253 lfo_pm_table[freq * 256 + pms * 32 + step] = value;
baf4688901f2 Initial stab at LFO phase modulation
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parents: 407
diff changeset
254 }
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
255 }
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
256 }
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
257 }
1308
1b3fe6e03e7b Reset YM2612 whenver the Z80 is reset. Fixes issue with stuck notes in Fantastic Dizzy and Kid Chameleon
Michael Pavone <pavone@retrodev.com>
parents: 1301
diff changeset
258 ym_reset(context);
1798
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
259 ym_enable_zero_offset(context, 1);
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
260 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
261
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
262 void ym_free(ym2612_context *context)
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
263 {
1551
ce1f93be0104 Small cleanup to audio interface between emulation code and renderer backend
Michael Pavone <pavone@retrodev.com>
parents: 1450
diff changeset
264 render_free_source(context->audio);
884
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
265 if (context == log_context) {
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
266 ym_finalize_log();
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
267 }
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
268 free(context);
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
269 }
252dfd29831d Selecting a second game from the menu now works
Michael Pavone <pavone@retrodev.com>
parents: 859
diff changeset
270
1798
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
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parents: 1656
diff changeset
271 void ym_enable_zero_offset(ym2612_context *context, uint8_t enabled)
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
272 {
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
273 if (enabled) {
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
274 context->zero_offset = 0x70;
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
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parents: 1656
diff changeset
275 context->volume_mult = 79;
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
276 context->volume_div = 120;
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
277 } else {
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
278 context->zero_offset = 0;
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
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parents: 1656
diff changeset
279 context->volume_mult = 2;
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
280 context->volume_div = 3;
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
281 }
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
282 }
381
7815ebbbd705 Fix modulation shift value
Mike Pavone <pavone@retrodev.com>
parents: 380
diff changeset
283 #define YM_MOD_SHIFT 1
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
284
1300
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
285 #define CSM_MODE 0x80
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
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parents: 1102
diff changeset
286
1301
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
287 #define SSG_ENABLE 8
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
288 #define SSG_INVERT 4
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
289 #define SSG_ALTERNATE 2
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
290 #define SSG_HOLD 1
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
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parents: 1300
diff changeset
291
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
292 #define SSG_CENTER 0x800
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
293
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
294 static void start_envelope(ym_operator *op, ym_channel *channel)
1300
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
295 {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
296 //Deal with "infinite" attack rates
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
297 uint8_t rate = op->rates[PHASE_ATTACK];
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
298 if (rate) {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
299 uint8_t ks = channel->keycode >> op->key_scaling;;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
300 rate = rate*2 + ks;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
301 }
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
302 if (rate >= 62) {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
303 op->env_phase = PHASE_DECAY;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
304 op->envelope = 0;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
305 } else {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
306 op->env_phase = PHASE_ATTACK;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
307 }
1301
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
308 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
309
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
310 static void keyon(ym_operator *op, ym_channel *channel)
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
311 {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
312 start_envelope(op, channel);
1300
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
313 op->phase_counter = 0;
1301
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
314 op->inverted = op->ssg & SSG_INVERT;
1300
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
315 }
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
316
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
317 static const uint8_t keyon_bits[] = {0x10, 0x40, 0x20, 0x80};
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
318
1301
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
319 static void keyoff(ym_operator *op)
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
320 {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
321 op->env_phase = PHASE_RELEASE;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
322 if (op->inverted) {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
323 //Nemesis says the inversion state doesn't change here, but I don't see how that is observable either way
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
324 op->inverted = 0;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
325 op->envelope = (SSG_CENTER - op->envelope) & MAX_ENVELOPE;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
326 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
327 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
328
1300
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
329 static void csm_keyoff(ym2612_context *context)
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
330 {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
331 context->csm_keyon = 0;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
332 uint8_t changes = 0xF0 ^ context->channels[2].keyon;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
333 for (uint8_t op = 2*4, bit = 0; op < 3*4; op++, bit++)
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
334 {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
335 if (changes & keyon_bits[bit]) {
1301
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
336 keyoff(context->operators + op);
1300
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
337 }
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
338 }
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
339 }
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
340
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
341 void ym_run(ym2612_context * context, uint32_t to_cycle)
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
342 {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
343 //printf("Running YM2612 from cycle %d to cycle %d\n", context->current_cycle, to_cycle);
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
344 //TODO: Fix channel update order OR remap channels in register write
380
1c8d74f2ab0b Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run.
Mike Pavone <pavone@retrodev.com>
parents: 379
diff changeset
345 for (; context->current_cycle < to_cycle; context->current_cycle += context->clock_inc) {
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
346 //Update timers at beginning of 144 cycle period
403
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
347 if (!context->current_op) {
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
348 if (context->timer_control & BIT_TIMERA_ENABLE) {
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
349 if (context->timer_a != TIMER_A_MAX) {
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
350 context->timer_a++;
1300
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
351 if (context->csm_keyon) {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
352 csm_keyoff(context);
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
353 }
403
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
354 } else {
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
355 if (context->timer_control & BIT_TIMERA_LOAD) {
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
356 context->timer_control &= ~BIT_TIMERA_LOAD;
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
357 } else if (context->timer_control & BIT_TIMERA_OVEREN) {
403
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
358 context->status |= BIT_STATUS_TIMERA;
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
359 }
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
360 context->timer_a = context->timer_a_load;
1300
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
361 if (!context->csm_keyon && context->ch3_mode == CSM_MODE) {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
362 context->csm_keyon = 0xF0;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
363 uint8_t changes = 0xF0 ^ context->channels[2].keyon;;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
364 for (uint8_t op = 2*4, bit = 0; op < 3*4; op++, bit++)
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
365 {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
366 if (changes & keyon_bits[bit]) {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
367 keyon(context->operators + op, context->channels + 2);
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
368 }
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
369 }
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
370 }
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
371 }
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
372 }
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
373 if (!context->sub_timer_b) {
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
374 if (context->timer_control & BIT_TIMERB_ENABLE) {
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
375 if (context->timer_b != TIMER_B_MAX) {
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
376 context->timer_b++;
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
377 } else {
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
378 if (context->timer_control & BIT_TIMERB_LOAD) {
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
379 context->timer_control &= ~BIT_TIMERB_LOAD;
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
380 } else if (context->timer_control & BIT_TIMERB_OVEREN) {
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
381 context->status |= BIT_STATUS_TIMERB;
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
382 }
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
383 context->timer_b = context->timer_b_load;
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
384 }
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
385 }
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
386 }
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
387 context->sub_timer_b += 0x10;
740
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
388 //Update LFO
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
389 if (context->lfo_enable) {
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
390 if (context->lfo_counter) {
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
391 context->lfo_counter--;
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
392 } else {
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
393 context->lfo_counter = lfo_timer_values[context->lfo_freq];
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
394 context->lfo_am_step += 2;
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
395 context->lfo_am_step &= 0xFE;
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
396 context->lfo_pm_step = context->lfo_am_step / 8;
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
397 }
411
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
398 }
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
399 }
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
400 //Update Envelope Generator
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
401 if (!(context->current_op % 3)) {
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
402 uint32_t env_cyc = context->env_counter;
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
403 uint32_t op = context->current_env_op;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
404 ym_operator * operator = context->operators + op;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
405 ym_channel * channel = context->channels + op/4;
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
406 uint8_t rate;
929
0ee8cfcc06d1 Change where decay to sustain transition happens to match hardware when decay rate is slow or 0
Michael Pavone <pavone@retrodev.com>
parents: 884
diff changeset
407 if (operator->env_phase == PHASE_DECAY && operator->envelope >= operator->sustain_level) {
0ee8cfcc06d1 Change where decay to sustain transition happens to match hardware when decay rate is slow or 0
Michael Pavone <pavone@retrodev.com>
parents: 884
diff changeset
408 //operator->envelope = operator->sustain_level;
0ee8cfcc06d1 Change where decay to sustain transition happens to match hardware when decay rate is slow or 0
Michael Pavone <pavone@retrodev.com>
parents: 884
diff changeset
409 operator->env_phase = PHASE_SUSTAIN;
0ee8cfcc06d1 Change where decay to sustain transition happens to match hardware when decay rate is slow or 0
Michael Pavone <pavone@retrodev.com>
parents: 884
diff changeset
410 }
1300
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
411 rate = operator->rates[operator->env_phase];
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
412 if (rate) {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
413 uint8_t ks = channel->keycode >> operator->key_scaling;;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
414 rate = rate*2 + ks;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
415 if (rate > 63) {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
416 rate = 63;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
417 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
418 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
419 uint32_t cycle_shift = rate < 0x30 ? ((0x2F - rate) >> 2) : 0;
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
420 if (first_key_on) {
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
421 dfprintf(debug_file, "Operator: %d, env rate: %d (2*%d+%d), env_cyc: %d, cycle_shift: %d, env_cyc & ((1 << cycle_shift) - 1): %d\n", op, rate, operator->rates[operator->env_phase], channel->keycode >> operator->key_scaling,env_cyc, cycle_shift, env_cyc & ((1 << cycle_shift) - 1));
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
422 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
423 if (!(env_cyc & ((1 << cycle_shift) - 1))) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
424 uint32_t update_cycle = env_cyc >> cycle_shift & 0x7;
852
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator
Michael Pavone <pavone@retrodev.com>
parents: 851
diff changeset
425 uint16_t envelope_inc = rate_table[rate * 8 + update_cycle];
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
426 if (operator->env_phase == PHASE_ATTACK) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
427 //this can probably be optimized to a single shift rather than a multiply + shift
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
428 if (first_key_on) {
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
429 dfprintf(debug_file, "Changing op %d envelope %d by %d(%d * %d) in attack phase\n", op, operator->envelope, (~operator->envelope * envelope_inc) >> 4, ~operator->envelope, envelope_inc);
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
430 }
513
24ebabd89162 Properly clamp envelope value to zero when it overflows during the attack phase. This fixes a number of instruments that sounded rather wrong as well as the missing melody line from Mushroom Hill Zone in Sonic and Knuckles
Michael Pavone <pavone@retrodev.com>
parents: 505
diff changeset
431 uint16_t old_env = operator->envelope;
852
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator
Michael Pavone <pavone@retrodev.com>
parents: 851
diff changeset
432 operator->envelope += ((~operator->envelope * envelope_inc) >> 4) & 0xFFFFFFFC;
513
24ebabd89162 Properly clamp envelope value to zero when it overflows during the attack phase. This fixes a number of instruments that sounded rather wrong as well as the missing melody line from Mushroom Hill Zone in Sonic and Knuckles
Michael Pavone <pavone@retrodev.com>
parents: 505
diff changeset
433 if (operator->envelope > old_env) {
24ebabd89162 Properly clamp envelope value to zero when it overflows during the attack phase. This fixes a number of instruments that sounded rather wrong as well as the missing melody line from Mushroom Hill Zone in Sonic and Knuckles
Michael Pavone <pavone@retrodev.com>
parents: 505
diff changeset
434 //Handle overflow
24ebabd89162 Properly clamp envelope value to zero when it overflows during the attack phase. This fixes a number of instruments that sounded rather wrong as well as the missing melody line from Mushroom Hill Zone in Sonic and Knuckles
Michael Pavone <pavone@retrodev.com>
parents: 505
diff changeset
435 operator->envelope = 0;
24ebabd89162 Properly clamp envelope value to zero when it overflows during the attack phase. This fixes a number of instruments that sounded rather wrong as well as the missing melody line from Mushroom Hill Zone in Sonic and Knuckles
Michael Pavone <pavone@retrodev.com>
parents: 505
diff changeset
436 }
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
437 if (!operator->envelope) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
438 operator->env_phase = PHASE_DECAY;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
439 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
440 } else {
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
441 if (first_key_on) {
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
442 dfprintf(debug_file, "Changing op %d envelope %d by %d in %s phase\n", op, operator->envelope, envelope_inc,
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
443 operator->env_phase == PHASE_SUSTAIN ? "sustain" : (operator->env_phase == PHASE_DECAY ? "decay": "release"));
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
444 }
1301
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
445 if (operator->ssg) {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
446 if (operator->envelope < SSG_CENTER) {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
447 envelope_inc *= 4;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
448 } else {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
449 envelope_inc = 0;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
450 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
451 }
852
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator
Michael Pavone <pavone@retrodev.com>
parents: 851
diff changeset
452 //envelope value is 10-bits, but it will be used as a 4.8 value
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator
Michael Pavone <pavone@retrodev.com>
parents: 851
diff changeset
453 operator->envelope += envelope_inc << 2;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
454 //clamp to max attenuation value
1301
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
455 if (
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
456 operator->envelope > MAX_ENVELOPE
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
457 || (operator->env_phase == PHASE_RELEASE && operator->envelope >= SSG_CENTER)
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
458 ) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
459 operator->envelope = MAX_ENVELOPE;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
460 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
461 }
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
462 }
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
463 context->current_env_op++;
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
464 if (context->current_env_op == NUM_OPERATORS) {
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
465 context->current_env_op = 0;
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
466 context->env_counter++;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
467 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
468 }
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
469
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
470 //Update Phase Generator
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
471 uint32_t channel = context->current_op / 4;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
472 if (channel != 5 || !context->dac_enable) {
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
473 uint32_t op = context->current_op;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
474 //printf("updating operator %d of channel %d\n", op, channel);
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
475 ym_operator * operator = context->operators + op;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
476 ym_channel * chan = context->channels + channel;
396
09328dbe6700 Fix output of algorithm 4 and make some other minor YM2612 core improvements
Mike Pavone <pavone@retrodev.com>
parents: 386
diff changeset
477 uint16_t phase = operator->phase_counter >> 10 & 0x3FF;
935
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
478 operator->phase_counter += ym_calc_phase_inc(context, operator, context->current_op);
371
0f8a759f1ff4 Use signed ints for things that represent signed values in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 370
diff changeset
479 int16_t mod = 0;
1656
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
480 if (op & 3) {
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
481 if (operator->mod_src[0]) {
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
482 mod = *operator->mod_src[0];
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
483 if (operator->mod_src[1]) {
1808
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
484 mod += *operator->mod_src[1];
1656
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
485 }
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
486 mod >>= YM_MOD_SHIFT;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
487 }
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
488 } else {
377
da8d53dc914b Initial stab at feedback
Mike Pavone <pavone@retrodev.com>
parents: 376
diff changeset
489 if (chan->feedback) {
527
7df7f493b3b6 Fix operator 1 self-feedback
Michael Pavone <pavone@retrodev.com>
parents: 522
diff changeset
490 mod = (chan->op1_old + operator->output) >> (10-chan->feedback);
377
da8d53dc914b Initial stab at feedback
Mike Pavone <pavone@retrodev.com>
parents: 376
diff changeset
491 }
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
492 }
1301
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
493 uint16_t env = operator->envelope;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
494 if (operator->ssg) {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
495 if (env >= SSG_CENTER) {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
496 if (operator->ssg & SSG_ALTERNATE) {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
497 if (operator->env_phase != PHASE_RELEASE && (
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
498 !(operator->ssg & SSG_HOLD) || ((operator->ssg ^ operator->inverted) & SSG_INVERT) == 0
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
499 )) {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
500 operator->inverted ^= SSG_INVERT;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
501 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
502 } else if (!(operator->ssg & SSG_HOLD)) {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
503 phase = operator->phase_counter = 0;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
504 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
505 if (
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
506 (operator->env_phase == PHASE_DECAY || operator->env_phase == PHASE_SUSTAIN)
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
507 && !(operator->ssg & SSG_HOLD)
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
508 ) {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
509 start_envelope(operator, chan);
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
510 env = operator->envelope;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
511 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
512 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
513 if (operator->inverted) {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
514 env = (SSG_CENTER - env) & MAX_ENVELOPE;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
515 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
516 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
517 env += operator->total_level;
740
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
518 if (operator->am) {
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
519 uint16_t base_am = (context->lfo_am_step & 0x80 ? context->lfo_am_step : ~context->lfo_am_step) & 0x7E;
930
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
520 if (ams_shift[chan->ams] >= 0) {
1802
1d1198f16279 Fix a couple of minor cases of extra precision in LFO implementation
Michael Pavone <pavone@retrodev.com>
parents: 1798
diff changeset
521 env += (base_am >> ams_shift[chan->ams]) & MAX_ENVELOPE;
930
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
522 } else {
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
523 env += base_am << (-ams_shift[chan->ams]);
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
524 }
740
25c9e9d39997 Fix LFO counter update speed and implement amplitude modulation
Michael Pavone <pavone@retrodev.com>
parents: 739
diff changeset
525 }
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
526 if (env > MAX_ENVELOPE) {
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
527 env = MAX_ENVELOPE;
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
528 }
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
529 if (first_key_on) {
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
530 dfprintf(debug_file, "op %d, base phase: %d, mod: %d, sine: %d, out: %d\n", op, phase, mod, sine_table[(phase+mod) & 0x1FF], pow_table[sine_table[phase & 0x1FF] + env]);
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
531 }
527
7df7f493b3b6 Fix operator 1 self-feedback
Michael Pavone <pavone@retrodev.com>
parents: 522
diff changeset
532 //if ((channel != 0 && channel != 4) || chan->algorithm != 5) {
7df7f493b3b6 Fix operator 1 self-feedback
Michael Pavone <pavone@retrodev.com>
parents: 522
diff changeset
533 phase += mod;
7df7f493b3b6 Fix operator 1 self-feedback
Michael Pavone <pavone@retrodev.com>
parents: 522
diff changeset
534 //}
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
535
371
0f8a759f1ff4 Use signed ints for things that represent signed values in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 370
diff changeset
536 int16_t output = pow_table[sine_table[phase & 0x1FF] + env];
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
537 if (phase & 0x200) {
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
538 output = -output;
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
539 }
527
7df7f493b3b6 Fix operator 1 self-feedback
Michael Pavone <pavone@retrodev.com>
parents: 522
diff changeset
540 if (op % 4 == 0) {
7df7f493b3b6 Fix operator 1 self-feedback
Michael Pavone <pavone@retrodev.com>
parents: 522
diff changeset
541 chan->op1_old = operator->output;
1808
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
542 } else if (op % 4 == 2) {
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
543 chan->op2_old = operator->output;
527
7df7f493b3b6 Fix operator 1 self-feedback
Michael Pavone <pavone@retrodev.com>
parents: 522
diff changeset
544 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
545 operator->output = output;
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
546 //Update the channel output if we've updated all operators
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
547 if (op % 4 == 3) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
548 if (chan->algorithm < 4) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
549 chan->output = operator->output;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
550 } else if(chan->algorithm == 4) {
396
09328dbe6700 Fix output of algorithm 4 and make some other minor YM2612 core improvements
Mike Pavone <pavone@retrodev.com>
parents: 386
diff changeset
551 chan->output = operator->output + context->operators[channel * 4 + 2].output;
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
552 } else {
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
553 output = 0;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
554 for (uint32_t op = ((chan->algorithm == 7) ? 0 : 1) + channel*4; op < (channel+1)*4; op++) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
555 output += context->operators[op].output;
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
556 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
557 chan->output = output;
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
558 }
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
559 if (first_key_on) {
371
0f8a759f1ff4 Use signed ints for things that represent signed values in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 370
diff changeset
560 int16_t value = context->channels[channel].output & 0x3FE0;
0f8a759f1ff4 Use signed ints for things that represent signed values in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 370
diff changeset
561 if (value & 0x2000) {
0f8a759f1ff4 Use signed ints for things that represent signed values in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 370
diff changeset
562 value |= 0xC000;
0f8a759f1ff4 Use signed ints for things that represent signed values in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 370
diff changeset
563 }
1798
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
564 dfprintf(debug_file, "channel %d output: %d\n", channel, (value * context->volume_mult) / context->volume_div);
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
565 }
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
566 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
567 //puts("operator update done");
359
cc39629e8d06 YM2612 WIP snapshot before register refactor
Mike Pavone <pavone@retrodev.com>
parents: 288
diff changeset
568 }
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
569 context->current_op++;
396
09328dbe6700 Fix output of algorithm 4 and make some other minor YM2612 core improvements
Mike Pavone <pavone@retrodev.com>
parents: 386
diff changeset
570 if (context->current_op == NUM_OPERATORS) {
09328dbe6700 Fix output of algorithm 4 and make some other minor YM2612 core improvements
Mike Pavone <pavone@retrodev.com>
parents: 386
diff changeset
571 context->current_op = 0;
965
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
572
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
573 int16_t left = 0, right = 0;
483
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
574 for (int i = 0; i < NUM_CHANNELS; i++) {
521
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
575 int16_t value = context->channels[i].output;
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
576 if (value > 0x1FE0) {
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
577 value = 0x1FE0;
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
578 } else if (value < -0x1FF0) {
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
579 value = -0x1FF0;
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
580 } else {
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
581 value &= 0x3FE0;
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
582 if (value & 0x2000) {
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
583 value |= 0xC000;
7565ec2ac652 Fix overflow handling on FM channel output
Michael Pavone <pavone@retrodev.com>
parents: 513
diff changeset
584 }
380
1c8d74f2ab0b Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run.
Mike Pavone <pavone@retrodev.com>
parents: 379
diff changeset
585 }
1798
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
586 if (value >= 0) {
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
587 value += context->zero_offset;
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
588 } else {
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
589 value -= context->zero_offset;
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
590 }
1555
6ce36c3f250b More audio refactoring in preparation for allowing proper sync to video with dynamic audio rate control
Michael Pavone <pavone@retrodev.com>
parents: 1551
diff changeset
591 if (context->channels[i].logfile) {
483
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
592 fwrite(&value, sizeof(value), 1, context->channels[i].logfile);
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
593 }
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
594 if (context->channels[i].lr & 0x80) {
1798
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
595 left += (value * context->volume_mult) / context->volume_div;
1803
a851d36e24bb Zero offset should also impact output channels that a channel is panned away from
Michael Pavone <pavone@retrodev.com>
parents: 1802
diff changeset
596 } else if (context->zero_offset) {
a851d36e24bb Zero offset should also impact output channels that a channel is panned away from
Michael Pavone <pavone@retrodev.com>
parents: 1802
diff changeset
597 if (value >= 0) {
a851d36e24bb Zero offset should also impact output channels that a channel is panned away from
Michael Pavone <pavone@retrodev.com>
parents: 1802
diff changeset
598 left += (context->zero_offset * context->volume_mult) / context->volume_div;
a851d36e24bb Zero offset should also impact output channels that a channel is panned away from
Michael Pavone <pavone@retrodev.com>
parents: 1802
diff changeset
599 } else {
a851d36e24bb Zero offset should also impact output channels that a channel is panned away from
Michael Pavone <pavone@retrodev.com>
parents: 1802
diff changeset
600 left -= (context->zero_offset * context->volume_mult) / context->volume_div;
a851d36e24bb Zero offset should also impact output channels that a channel is panned away from
Michael Pavone <pavone@retrodev.com>
parents: 1802
diff changeset
601 }
380
1c8d74f2ab0b Make the PSG and YM2612 use the master clock internal with an increment based on clock divider so that they stay perflectly in sync. Run both the PSG and YM2612 whenver one of them needs to be run.
Mike Pavone <pavone@retrodev.com>
parents: 379
diff changeset
602 }
483
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
603 if (context->channels[i].lr & 0x40) {
1798
5278b6e44fc1 Optionally emulate the offset around zero in the imperfect DAC of a discrete YM2612
Michael Pavone <pavone@retrodev.com>
parents: 1656
diff changeset
604 right += (value * context->volume_mult) / context->volume_div;
1803
a851d36e24bb Zero offset should also impact output channels that a channel is panned away from
Michael Pavone <pavone@retrodev.com>
parents: 1802
diff changeset
605 } else if (context->zero_offset) {
a851d36e24bb Zero offset should also impact output channels that a channel is panned away from
Michael Pavone <pavone@retrodev.com>
parents: 1802
diff changeset
606 if (value >= 0) {
a851d36e24bb Zero offset should also impact output channels that a channel is panned away from
Michael Pavone <pavone@retrodev.com>
parents: 1802
diff changeset
607 right += (context->zero_offset * context->volume_mult) / context->volume_div;
a851d36e24bb Zero offset should also impact output channels that a channel is panned away from
Michael Pavone <pavone@retrodev.com>
parents: 1802
diff changeset
608 } else {
a851d36e24bb Zero offset should also impact output channels that a channel is panned away from
Michael Pavone <pavone@retrodev.com>
parents: 1802
diff changeset
609 right -= (context->zero_offset * context->volume_mult) / context->volume_div;
a851d36e24bb Zero offset should also impact output channels that a channel is panned away from
Michael Pavone <pavone@retrodev.com>
parents: 1802
diff changeset
610 }
483
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
611 }
3e1573fa22cf Implement turbo/slow motion feature that overclocks or underclocks the entire system at the push of a button
Mike Pavone <pavone@retrodev.com>
parents: 467
diff changeset
612 }
1555
6ce36c3f250b More audio refactoring in preparation for allowing proper sync to video with dynamic audio rate control
Michael Pavone <pavone@retrodev.com>
parents: 1551
diff changeset
613 render_put_stereo_sample(context->audio, left, right);
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
614 }
965
5257e85364ed Implemented linear resampling and low pass filter for the YM2612
Michael Pavone <pavone@retrodev.com>
parents: 936
diff changeset
615
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
616 }
535
aaa77e351c24 Better emulation of the YM-2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 532
diff changeset
617 if (context->current_cycle >= context->write_cycle + (context->busy_cycles * context->clock_inc / 6)) {
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
618 context->status &= 0x7F;
374
d42a8a3e4894 Fix YM2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 371
diff changeset
619 context->write_cycle = CYCLE_NEVER;
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
620 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
621 //printf("Done running YM2612 at cycle %d\n", context->current_cycle, to_cycle);
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
622 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
623
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
624 void ym_address_write_part1(ym2612_context * context, uint8_t address)
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
625 {
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
626 //printf("address_write_part1: %X\n", address);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
627 context->selected_reg = address;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
628 context->selected_part = 0;
535
aaa77e351c24 Better emulation of the YM-2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 532
diff changeset
629 context->write_cycle = context->current_cycle;
aaa77e351c24 Better emulation of the YM-2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 532
diff changeset
630 context->busy_cycles = BUSY_CYCLES_ADDRESS;
650
55b550fe8891 Set the busy flag after a YM-2612 address write
Michael Pavone <pavone@retrodev.com>
parents: 535
diff changeset
631 context->status |= 0x80;
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
632 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
633
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
634 void ym_address_write_part2(ym2612_context * context, uint8_t address)
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
635 {
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
636 //printf("address_write_part2: %X\n", address);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
637 context->selected_reg = address;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
638 context->selected_part = 1;
535
aaa77e351c24 Better emulation of the YM-2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 532
diff changeset
639 context->write_cycle = context->current_cycle;
aaa77e351c24 Better emulation of the YM-2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 532
diff changeset
640 context->busy_cycles = BUSY_CYCLES_ADDRESS;
650
55b550fe8891 Set the busy flag after a YM-2612 address write
Michael Pavone <pavone@retrodev.com>
parents: 535
diff changeset
641 context->status |= 0x80;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
642 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
643
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1002
diff changeset
644 static uint8_t fnum_to_keycode[] = {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
645 //F11 = 0
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
646 0,0,0,0,0,0,0,1,
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
647 //F11 = 1
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
648 2,3,3,3,3,3,3,3
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
649 };
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
650
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
651 //table courtesy of Nemesis
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1002
diff changeset
652 static uint32_t detune_table[][4] = {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
653 {0, 0, 1, 2}, //0 (0x00)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
654 {0, 0, 1, 2}, //1 (0x01)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
655 {0, 0, 1, 2}, //2 (0x02)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
656 {0, 0, 1, 2}, //3 (0x03)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
657 {0, 1, 2, 2}, //4 (0x04)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
658 {0, 1, 2, 3}, //5 (0x05)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
659 {0, 1, 2, 3}, //6 (0x06)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
660 {0, 1, 2, 3}, //7 (0x07)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
661 {0, 1, 2, 4}, //8 (0x08)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
662 {0, 1, 3, 4}, //9 (0x09)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
663 {0, 1, 3, 4}, //10 (0x0A)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
664 {0, 1, 3, 5}, //11 (0x0B)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
665 {0, 2, 4, 5}, //12 (0x0C)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
666 {0, 2, 4, 6}, //13 (0x0D)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
667 {0, 2, 4, 6}, //14 (0x0E)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
668 {0, 2, 5, 7}, //15 (0x0F)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
669 {0, 2, 5, 8}, //16 (0x10)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
670 {0, 3, 6, 8}, //17 (0x11)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
671 {0, 3, 6, 9}, //18 (0x12)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
672 {0, 3, 7,10}, //19 (0x13)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
673 {0, 4, 8,11}, //20 (0x14)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
674 {0, 4, 8,12}, //21 (0x15)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
675 {0, 4, 9,13}, //22 (0x16)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
676 {0, 5,10,14}, //23 (0x17)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
677 {0, 5,11,16}, //24 (0x18)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
678 {0, 6,12,17}, //25 (0x19)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
679 {0, 6,13,19}, //26 (0x1A)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
680 {0, 7,14,20}, //27 (0x1B)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
681 {0, 8,16,22}, //28 (0x1C)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
682 {0, 8,16,22}, //29 (0x1D)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
683 {0, 8,16,22}, //30 (0x1E)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
684 {0, 8,16,22}
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
685 }; //31 (0x1F)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
686
1102
c15896605bf2 Clean up symbol visiblity and delete a ltitle bit of dead code
Michael Pavone <pavone@retrodev.com>
parents: 1002
diff changeset
687 static uint32_t ym_calc_phase_inc(ym2612_context * context, ym_operator * operator, uint32_t op)
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
688 {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
689 uint32_t chan_num = op / 4;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
690 //printf("ym_update_phase_inc | channel: %d, op: %d\n", chan_num, op);
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
691 //base frequency
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
692 ym_channel * channel = context->channels + chan_num;
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
693 uint32_t inc, detune;
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
694 if (chan_num == 2 && context->ch3_mode && (op < (2*4 + 3))) {
738
8972378e314f Fix register to operator mapping for channel 3 special mode
Michael Pavone <pavone@retrodev.com>
parents: 650
diff changeset
695 //supplemental fnum registers are in a different order than normal slot paramters
936
f1a8124ad881 Fix register to operator mapping for channel 3 special mode and actually get it right this time
Michael Pavone <pavone@retrodev.com>
parents: 935
diff changeset
696 int index = op-2*4;
f1a8124ad881 Fix register to operator mapping for channel 3 special mode and actually get it right this time
Michael Pavone <pavone@retrodev.com>
parents: 935
diff changeset
697 if (index < 2) {
f1a8124ad881 Fix register to operator mapping for channel 3 special mode and actually get it right this time
Michael Pavone <pavone@retrodev.com>
parents: 935
diff changeset
698 index ^= 1;
f1a8124ad881 Fix register to operator mapping for channel 3 special mode and actually get it right this time
Michael Pavone <pavone@retrodev.com>
parents: 935
diff changeset
699 }
738
8972378e314f Fix register to operator mapping for channel 3 special mode
Michael Pavone <pavone@retrodev.com>
parents: 650
diff changeset
700 inc = context->ch3_supp[index].fnum;
935
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
701 if (channel->pms) {
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
702 inc = inc * 2 + lfo_pm_table[(inc & 0x7F0) * 16 + channel->pms + context->lfo_pm_step];
1802
1d1198f16279 Fix a couple of minor cases of extra precision in LFO implementation
Michael Pavone <pavone@retrodev.com>
parents: 1798
diff changeset
703 inc &= 0xFFF;
935
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
704 }
738
8972378e314f Fix register to operator mapping for channel 3 special mode
Michael Pavone <pavone@retrodev.com>
parents: 650
diff changeset
705 if (!context->ch3_supp[index].block) {
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
706 inc >>= 1;
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
707 } else {
738
8972378e314f Fix register to operator mapping for channel 3 special mode
Michael Pavone <pavone@retrodev.com>
parents: 650
diff changeset
708 inc <<= (context->ch3_supp[index].block-1);
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
709 }
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
710 //detune
738
8972378e314f Fix register to operator mapping for channel 3 special mode
Michael Pavone <pavone@retrodev.com>
parents: 650
diff changeset
711 detune = detune_table[context->ch3_supp[index].keycode][operator->detune & 0x3];
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
712 } else {
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
713 inc = channel->fnum;
935
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
714 if (channel->pms) {
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
715 inc = inc * 2 + lfo_pm_table[(inc & 0x7F0) * 16 + channel->pms + context->lfo_pm_step];
1808
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
716 inc &= 0xFFF;
935
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
717 }
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
718 if (!channel->block) {
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
719 inc >>= 1;
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
720 } else {
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
721 inc <<= (channel->block-1);
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
722 }
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
723 //detune
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
724 detune = detune_table[channel->keycode][operator->detune & 0x3];
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
725 }
935
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
726 if (channel->pms) {
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
727 inc >>= 1;
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
728 }
739
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
729 if (operator->detune & 0x4) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
730 inc -= detune;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
731 //this can underflow, mask to 17-bit result
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
732 inc &= 0x1FFFF;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
733 } else {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
734 inc += detune;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
735 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
736 //multiple
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
737 if (operator->multiple) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
738 inc *= operator->multiple;
739
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
739 inc &= 0xFFFFF;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
740 } else {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
741 //0.5
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
742 inc >>= 1;
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
743 }
365
3ba3b6656fff Actually save the shifted phase inc after applying the block shift
Mike Pavone <pavone@retrodev.com>
parents: 364
diff changeset
744 //printf("phase_inc for operator %d: %d, block: %d, fnum: %d, detune: %d, multiple: %d\n", op, inc, channel->block, channel->fnum, detune, operator->multiple);
935
01fb50390b27 Remove phase increment caching. Fix LFO phase modulation calculation
Michael Pavone <pavone@retrodev.com>
parents: 930
diff changeset
745 return inc;
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
746 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
747
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
748 void ym_data_write(ym2612_context * context, uint8_t value)
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
749 {
451
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
750 if (context->selected_reg >= YM_REG_END) {
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
751 return;
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
752 }
451
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
753 if (context->selected_part) {
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
754 if (context->selected_reg < YM_PART2_START) {
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
755 return;
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
756 }
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
757 context->part2_regs[context->selected_reg - YM_PART2_START] = value;
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
758 } else {
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
759 if (context->selected_reg < YM_PART1_START) {
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
760 return;
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
761 }
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
762 context->part1_regs[context->selected_reg - YM_PART1_START] = value;
b7c3b2d22858 Added support for saving savestates. Added gst savestate format test harness
Mike Pavone <pavone@retrodev.com>
parents: 448
diff changeset
763 }
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
764 dfprintf(debug_file, "write of %X to reg %X in part %d\n", value, context->selected_reg, context->selected_part+1);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
765 if (context->selected_reg < 0x30) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
766 //Shared regs
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
767 switch (context->selected_reg)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
768 {
411
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
769 //TODO: Test reg
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
770 case REG_LFO:
532
666210adf87b Comment out LFO debug printf
Mike Pavone <pavone@retrodev.com>
parents: 527
diff changeset
771 /*if ((value & 0x8) && !context->lfo_enable) {
411
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
772 printf("LFO Enabled, Freq: %d\n", value & 0x7);
532
666210adf87b Comment out LFO debug printf
Mike Pavone <pavone@retrodev.com>
parents: 527
diff changeset
773 }*/
411
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
774 context->lfo_enable = value & 0x8;
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
775 if (!context->lfo_enable) {
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
776 context->lfo_am_step = context->lfo_pm_step = 0;
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
777 }
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
778 context->lfo_freq = value & 0x7;
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
779
411
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
780 break;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
781 case REG_TIMERA_HIGH:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
782 context->timer_a_load &= 0x3;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
783 context->timer_a_load |= value << 2;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
784 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
785 case REG_TIMERA_LOW:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
786 context->timer_a_load &= 0xFFFC;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
787 context->timer_a_load |= value & 0x3;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
788 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
789 case REG_TIMERB:
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
790 context->timer_b_load = value;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
791 break;
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
792 case REG_TIME_CTRL: {
403
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
793 if (value & BIT_TIMERA_ENABLE && !(context->timer_control & BIT_TIMERA_ENABLE)) {
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
794 context->timer_a = TIMER_A_MAX;
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
795 context->timer_control |= BIT_TIMERA_LOAD;
403
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
796 }
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
797 if (value & BIT_TIMERB_ENABLE && !(context->timer_control & BIT_TIMERB_ENABLE)) {
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
798 context->timer_b = TIMER_B_MAX;
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
799 context->timer_control |= BIT_TIMERB_LOAD;
403
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
800 }
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
801 context->timer_control &= (BIT_TIMERA_LOAD | BIT_TIMERB_LOAD);
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
802 context->timer_control |= value & 0xF;
403
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
803 if (value & BIT_TIMERA_RESET) {
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
804 context->status &= ~BIT_STATUS_TIMERA;
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
805 }
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
806 if (value & BIT_TIMERB_RESET) {
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
807 context->status &= ~BIT_STATUS_TIMERB;
f0a3f86595ae Fix YM2612 timers
Mike Pavone <pavone@retrodev.com>
parents: 396
diff changeset
808 }
1300
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
809 if (context->ch3_mode == CSM_MODE && (value & 0xC0) != CSM_MODE && context->csm_keyon) {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
810 csm_keyoff(context);
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
811 }
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
812 context->ch3_mode = value & 0xC0;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
813 break;
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
814 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
815 case REG_KEY_ONOFF: {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
816 uint8_t channel = value & 0x7;
386
6e5c4f3ab0e2 Fix channel mapping in key on/off register
Mike Pavone <pavone@retrodev.com>
parents: 383
diff changeset
817 if (channel != 3 && channel != 7) {
6e5c4f3ab0e2 Fix channel mapping in key on/off register
Mike Pavone <pavone@retrodev.com>
parents: 383
diff changeset
818 if (channel > 2) {
6e5c4f3ab0e2 Fix channel mapping in key on/off register
Mike Pavone <pavone@retrodev.com>
parents: 383
diff changeset
819 channel--;
6e5c4f3ab0e2 Fix channel mapping in key on/off register
Mike Pavone <pavone@retrodev.com>
parents: 383
diff changeset
820 }
1300
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
821 uint8_t changes = channel == 2
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
822 ? (value | context->csm_keyon) ^ (context->channels[channel].keyon | context->csm_keyon)
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
823 : value ^ context->channels[channel].keyon;
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
824 context->channels[channel].keyon = value & 0xF0;
851
b10cf2c921ad Fix mapping of key on/off reg bits to operators
Michael Pavone <pavone@retrodev.com>
parents: 848
diff changeset
825 for (uint8_t op = channel * 4, bit = 0; op < (channel + 1) * 4; op++, bit++) {
1300
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
826 if (changes & keyon_bits[bit]) {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
827 if (value & keyon_bits[bit]) {
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
828 first_key_on = 1;
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
829 //printf("Key On for operator %d in channel %d\n", op, channel);
1300
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
830 keyon(context->operators + op, context->channels + channel);
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
831 } else {
4b893b02444e Basic implementation of CSM mode that should handle documented edge cases. Dodesn't handle the weird undocumented edge cases I don't have a good understanding of yet though
Michael Pavone <pavone@retrodev.com>
parents: 1102
diff changeset
832 //printf("Key Off for operator %d in channel %d\n", op, channel);
1301
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
833 keyoff(context->operators + op);
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
834 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
835 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
836 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
837 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
838 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
839 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
840 case REG_DAC:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
841 if (context->dac_enable) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
842 context->channels[5].output = (((int16_t)value) - 0x80) << 6;
396
09328dbe6700 Fix output of algorithm 4 and make some other minor YM2612 core improvements
Mike Pavone <pavone@retrodev.com>
parents: 386
diff changeset
843 //printf("DAC Write %X(%d) @ %d\n", value, context->channels[5].output, context->current_cycle);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
844 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
845 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
846 case REG_DAC_ENABLE:
364
62177cc39049 Incredibly broken YM2612 support plus a fix to Z80 bus request
Mike Pavone <pavone@retrodev.com>
parents: 362
diff changeset
847 //printf("DAC Enable: %X\n", value);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
848 context->dac_enable = value & 0x80;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
849 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
850 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
851 } else if (context->selected_reg < 0xA0) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
852 //part
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
853 uint8_t op = context->selected_part ? (NUM_OPERATORS/2) : 0;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
854 //channel in part
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
855 if ((context->selected_reg & 0x3) != 0x3) {
370
5f215603d001 Fix register to operator mapping. Fix rate table generation. Add TL to envelope value rather than using it as a limit for the attack phase.
Mike Pavone <pavone@retrodev.com>
parents: 369
diff changeset
856 op += 4 * (context->selected_reg & 0x3) + ((context->selected_reg & 0xC) / 4);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
857 //printf("write targets operator %d (%d of channel %d)\n", op, op % 4, op / 4);
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
858 ym_operator * operator = context->operators + op;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
859 switch (context->selected_reg & 0xF0)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
860 {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
861 case REG_DETUNE_MULT:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
862 operator->detune = value >> 4 & 0x7;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
863 operator->multiple = value & 0xF;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
864 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
865 case REG_TOTAL_LEVEL:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
866 operator->total_level = (value & 0x7F) << 5;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
867 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
868 case REG_ATTACK_KS:
376
f6def5cdf1b4 Fix key scaling
Mike Pavone <pavone@retrodev.com>
parents: 374
diff changeset
869 operator->key_scaling = 3 - (value >> 6);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
870 operator->rates[PHASE_ATTACK] = value & 0x1F;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
871 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
872 case REG_DECAY_AM:
739
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
873 operator->am = value & 0x80;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
874 operator->rates[PHASE_DECAY] = value & 0x1F;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
875 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
876 case REG_SUSTAIN_RATE:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
877 operator->rates[PHASE_SUSTAIN] = value & 0x1F;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
878 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
879 case REG_S_LVL_R_RATE:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
880 operator->rates[PHASE_RELEASE] = (value & 0xF) << 1 | 1;
852
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator
Michael Pavone <pavone@retrodev.com>
parents: 851
diff changeset
881 operator->sustain_level = (value & 0xF0) << 3;
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator
Michael Pavone <pavone@retrodev.com>
parents: 851
diff changeset
882 if (operator->sustain_level == 0x780) {
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator
Michael Pavone <pavone@retrodev.com>
parents: 851
diff changeset
883 operator->sustain_level = MAX_ENVELOPE;
5de8759b87af Fix some bugs in the attack phase and sustain level in the envelope generator
Michael Pavone <pavone@retrodev.com>
parents: 851
diff changeset
884 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
885 break;
1301
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
886 case REG_SSG_EG:
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
887 if (!(value & SSG_ENABLE)) {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
888 value = 0;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
889 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
890 if ((value ^ operator->ssg) & SSG_INVERT) {
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
891 operator->inverted ^= SSG_INVERT;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
892 }
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
893 operator->ssg = value;
babff81e4cfd Initial implementation of YM2612 SSG-EG mode
Michael Pavone <pavone@retrodev.com>
parents: 1300
diff changeset
894 break;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
895 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
896 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
897 } else {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
898 uint8_t channel = context->selected_reg & 0x3;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
899 if (channel != 3) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
900 if (context->selected_part) {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
901 channel += 3;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
902 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
903 //printf("write targets channel %d\n", channel);
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
904 switch (context->selected_reg & 0xFC)
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
905 {
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
906 case REG_FNUM_LOW:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
907 context->channels[channel].block = context->channels[channel].block_fnum_latch >> 3 & 0x7;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
908 context->channels[channel].fnum = (context->channels[channel].block_fnum_latch & 0x7) << 8 | value;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
909 context->channels[channel].keycode = context->channels[channel].block << 2 | fnum_to_keycode[context->channels[channel].fnum >> 7];
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
910 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
911 case REG_BLOCK_FNUM_H:{
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
912 context->channels[channel].block_fnum_latch = value;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
913 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
914 }
383
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
915 case REG_FNUM_LOW_CH3:
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
916 if (channel < 3) {
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
917 context->ch3_supp[channel].block = context->ch3_supp[channel].block_fnum_latch >> 3 & 0x7;
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
918 context->ch3_supp[channel].fnum = (context->ch3_supp[channel].block_fnum_latch & 0x7) << 8 | value;
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
919 context->ch3_supp[channel].keycode = context->ch3_supp[channel].block << 2 | fnum_to_keycode[context->ch3_supp[channel].fnum >> 7];
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
920 }
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
921 break;
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
922 case REG_BLOCK_FN_CH3:
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
923 if (channel < 3) {
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
924 context->ch3_supp[channel].block_fnum_latch = value;
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
925 }
72933100c55c Initial implementation of channel 3 special mode
Mike Pavone <pavone@retrodev.com>
parents: 382
diff changeset
926 break;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
927 case REG_ALG_FEEDBACK:
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
928 context->channels[channel].algorithm = value & 0x7;
1656
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
929 switch (context->channels[channel].algorithm)
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
930 {
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
931 case 0:
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
932 //operator 3 modulated by operator 2
1808
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
933 //this uses a special op2 result reg on HW, but that reg will have the most recent
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
934 //result from op2 when op3 starts executing
1656
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
935 context->operators[channel*4+1].mod_src[0] = &context->operators[channel*4+2].output;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
936 context->operators[channel*4+1].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
937
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
938 //operator 2 modulated by operator 1
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
939 context->operators[channel*4+2].mod_src[0] = &context->operators[channel*4+0].output;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
940
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
941 //operator 4 modulated by operator 3
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
942 context->operators[channel*4+3].mod_src[0] = &context->operators[channel*4+1].output;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
943 context->operators[channel*4+3].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
944 break;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
945 case 1:
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
946 //operator 3 modulated by operator 1+2
1808
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
947 //op1 starts executing before this, but due to pipeline length the most current result is
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
948 //not available and instead the previous result is used
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
949 context->operators[channel*4+1].mod_src[0] = &context->channels[channel].op1_old;
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
950 //this uses a special op2 result reg on HW, but that reg will have the most recent
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
951 //result from op2 when op3 starts executing
1656
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
952 context->operators[channel*4+1].mod_src[1] = &context->operators[channel*4+2].output;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
953
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
954 //operator 2 unmodulated
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
955 context->operators[channel*4+2].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
956
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
957 //operator 4 modulated by operator 3
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
958 context->operators[channel*4+3].mod_src[0] = &context->operators[channel*4+1].output;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
959 context->operators[channel*4+3].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
960 break;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
961 case 2:
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
962 //operator 3 modulated by operator 2
1808
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
963 //this uses a special op2 result reg on HW, but that reg will have the most recent
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
964 //result from op2 when op3 starts executing
1656
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
965 context->operators[channel*4+1].mod_src[0] = &context->operators[channel*4+2].output;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
966 context->operators[channel*4+1].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
967
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
968 //operator 2 unmodulated
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
969 context->operators[channel*4+2].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
970
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
971 //operator 4 modulated by operator 1+3
1808
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
972 //this uses a special op1 result reg on HW, but that reg will have the most recent
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
973 //result from op1 when op4 starts executing
1656
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
974 context->operators[channel*4+3].mod_src[0] = &context->operators[channel*4+0].output;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
975 context->operators[channel*4+3].mod_src[1] = &context->operators[channel*4+1].output;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
976 break;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
977 case 3:
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
978 //operator 3 unmodulated
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
979 context->operators[channel*4+1].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
980 context->operators[channel*4+1].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
981
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
982 //operator 2 modulated by operator 1
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
983 context->operators[channel*4+2].mod_src[0] = &context->operators[channel*4+0].output;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
984
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
985 //operator 4 modulated by operator 2+3
1808
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
986 //op2 starts executing before this, but due to pipeline length the most current result is
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
987 //not available and instead the previous result is used
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
988 context->operators[channel*4+3].mod_src[0] = &context->channels[channel].op2_old;
1656
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
989 context->operators[channel*4+3].mod_src[1] = &context->operators[channel*4+1].output;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
990 break;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
991 case 4:
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
992 //operator 3 unmodulated
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
993 context->operators[channel*4+1].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
994 context->operators[channel*4+1].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
995
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
996 //operator 2 modulated by operator 1
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
997 context->operators[channel*4+2].mod_src[0] = &context->operators[channel*4+0].output;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
998
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
999 //operator 4 modulated by operator 3
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1000 context->operators[channel*4+3].mod_src[0] = &context->operators[channel*4+1].output;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1001 context->operators[channel*4+3].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1002 break;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1003 case 5:
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1004 //operator 3 modulated by operator 1
1808
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
1005 //op1 starts executing before this, but due to pipeline length the most current result is
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
1006 //not available and instead the previous result is used
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
1007 context->operators[channel*4+1].mod_src[0] = &context->channels[channel].op1_old;
1656
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1008 context->operators[channel*4+1].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1009
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1010 //operator 2 modulated by operator 1
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1011 context->operators[channel*4+2].mod_src[0] = &context->operators[channel*4+0].output;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1012
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1013 //operator 4 modulated by operator 1
1808
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
1014 //this uses a special op1 result reg on HW, but that reg will have the most recent
ce6881d64eef Operator results should be delayed by one sample when used as a modulator in some cases based on relative execution time and pipeline length
Michael Pavone <pavone@retrodev.com>
parents: 1803
diff changeset
1015 //result from op1 when op4 starts executing
1656
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1016 context->operators[channel*4+3].mod_src[0] = &context->operators[channel*4+0].output;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1017 context->operators[channel*4+3].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1018 break;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1019 case 6:
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1020 //operator 3 unmodulated
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1021 context->operators[channel*4+1].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1022 context->operators[channel*4+1].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1023
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1024 //operator 2 modulated by operator 1
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1025 context->operators[channel*4+2].mod_src[0] = &context->operators[channel*4+0].output;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1026
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1027 //operator 4 unmodulated
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1028 context->operators[channel*4+3].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1029 context->operators[channel*4+3].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1030 break;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1031 case 7:
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1032 //everything is an output so no modulation (except for op 1 feedback)
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1033 context->operators[channel*4+1].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1034 context->operators[channel*4+1].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1035
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1036 context->operators[channel*4+2].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1037
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1038 context->operators[channel*4+3].mod_src[0] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1039 context->operators[channel*4+3].mod_src[1] = NULL;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1040 break;
804f13c090b4 Optimize YM operator modulation
Mike Pavone <pavone@retrodev.com>
parents: 1654
diff changeset
1041 }
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
1042 context->channels[channel].feedback = value >> 3 & 0x7;
527
7df7f493b3b6 Fix operator 1 self-feedback
Michael Pavone <pavone@retrodev.com>
parents: 522
diff changeset
1043 //printf("Algorithm %d, feedback %d for channel %d\n", value & 0x7, value >> 3 & 0x7, channel);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
1044 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
1045 case REG_LR_AMS_PMS:
411
baf4688901f2 Initial stab at LFO phase modulation
Mike Pavone <pavone@retrodev.com>
parents: 407
diff changeset
1046 context->channels[channel].pms = (value & 0x7) * 32;
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
1047 context->channels[channel].ams = value >> 4 & 0x3;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
1048 context->channels[channel].lr = value & 0xC0;
369
fc820ab1394b Fix left/right enable default value
Mike Pavone <pavone@retrodev.com>
parents: 365
diff changeset
1049 //printf("Write of %X to LR_AMS_PMS reg for channel %d\n", value, channel);
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
1050 break;
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
1051 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
1052 }
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
1053 }
448
e85a107e6ec0 Fix handling of key on in YM2612 core
Mike Pavone <pavone@retrodev.com>
parents: 424
diff changeset
1054
362
b7c3facee762 YM2612 WIP update
Mike Pavone <pavone@retrodev.com>
parents: 359
diff changeset
1055 context->write_cycle = context->current_cycle;
535
aaa77e351c24 Better emulation of the YM-2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 532
diff changeset
1056 context->busy_cycles = context->selected_reg < 0xA0 ? BUSY_CYCLES_DATA_LOW : BUSY_CYCLES_DATA_HIGH;
374
d42a8a3e4894 Fix YM2612 busy flag
Mike Pavone <pavone@retrodev.com>
parents: 371
diff changeset
1057 context->status |= 0x80;
288
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1058 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1059
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1060 uint8_t ym_read_status(ym2612_context * context)
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1061 {
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1062 return context->status;
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1063 }
a8ee7934a1f8 Add a YM2612 stub implementation with just timers and status registers so that games that depend on it can run.
Mike Pavone <pavone@retrodev.com>
parents:
diff changeset
1064
739
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1065 void ym_print_channel_info(ym2612_context *context, int channel)
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1066 {
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1067 ym_channel *chan = context->channels + channel;
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1068 printf("\n***Channel %d***\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1069 "Algorithm: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1070 "Feedback: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1071 "Pan: %s\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1072 "AMS: %d\n"
845
3a18b5f63afc Small fix to how manual YM-2612 timer reloads work. Seems to better match a small test program and gets audio to match up in TM.EE's "I've got Italo Inside" track.
Michael Pavone <pavone@retrodev.com>
parents: 740
diff changeset
1073 "PMS: %d\n",
739
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1074 channel+1, chan->algorithm, chan->feedback,
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1075 chan->lr == 0xC0 ? "LR" : chan->lr == 0x80 ? "L" : chan->lr == 0x40 ? "R" : "",
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1076 chan->ams, chan->pms);
930
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1077 if (channel == 2) {
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1078 printf(
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1079 "Mode: %X: %s\n",
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1080 context->ch3_mode, context->ch3_mode ? "special" : "normal");
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1081 }
739
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1082 for (int operator = channel * 4; operator < channel * 4+4; operator++)
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1083 {
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1084 int dispnum = operator - channel * 4 + 1;
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1085 if (dispnum == 2) {
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1086 dispnum = 3;
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1087 } else if (dispnum == 3) {
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1088 dispnum = 2;
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1089 }
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1090 ym_operator *op = context->operators + operator;
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1091 printf("\nOperator %d:\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1092 " Multiple: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1093 " Detune: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1094 " Total Level: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1095 " Attack Rate: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1096 " Key Scaling: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1097 " Decay Rate: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1098 " Sustain Level: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1099 " Sustain Rate: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1100 " Release Rate: %d\n"
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1101 " Amplitude Modulation %s\n",
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1102 dispnum, op->multiple, op->detune, op->total_level,
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1103 op->rates[PHASE_ATTACK], op->key_scaling, op->rates[PHASE_DECAY],
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1104 op->sustain_level, op->rates[PHASE_SUSTAIN], op->rates[PHASE_RELEASE],
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1105 op->am ? "On" : "Off");
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1106 }
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1107 }
2317bdca03b4 Add a basic YM-2612 command to the debugger. Fix negative detune values and get the correct precision for the multiplication step of phase inc calculation
Michael Pavone <pavone@retrodev.com>
parents: 738
diff changeset
1108
930
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1109 void ym_print_timer_info(ym2612_context *context)
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1110 {
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1111 printf("***Timer A***\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1112 "Current Value: %d\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1113 "Load Value: %d\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1114 "Triggered: %s\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1115 "Enabled: %s\n\n",
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1116 context->timer_a,
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1117 context->timer_a_load,
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1118 context->status & BIT_STATUS_TIMERA ? "yes" : "no",
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1119 context->timer_control & BIT_TIMERA_ENABLE ? "yes" : "no");
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1120 printf("***Timer B***\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1121 "Current Value: %d\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1122 "Load Value: %d\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1123 "Triggered: %s\n"
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1124 "Enabled: %s\n\n",
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1125 context->timer_b,
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1126 context->timer_b_load,
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1127 context->status & BIT_STATUS_TIMERB ? "yes" : "no",
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1128 context->timer_control & BIT_TIMERB_ENABLE ? "yes" : "no");
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1129 }
f33e8d88ab6f Add yt debug command for printing YM-2612 timer info. Fix AMS shift values.
Michael Pavone <pavone@retrodev.com>
parents: 929
diff changeset
1130
1427
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1131 void ym_serialize(ym2612_context *context, serialize_buffer *buf)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1132 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1133 save_buffer8(buf, context->part1_regs, YM_PART1_REGS);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1134 save_buffer8(buf, context->part2_regs, YM_PART2_REGS);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1135 for (int i = 0; i < NUM_OPERATORS; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1136 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1137 save_int32(buf, context->operators[i].phase_counter);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1138 save_int16(buf, context->operators[i].envelope);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1139 save_int16(buf, context->operators[i].output);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1140 save_int8(buf, context->operators[i].env_phase);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1141 save_int8(buf, context->operators[i].inverted);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1142 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1143 for (int i = 0; i < NUM_CHANNELS; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1144 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1145 save_int16(buf, context->channels[i].output);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1146 save_int16(buf, context->channels[i].op1_old);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1147 //Due to the latching behavior, these need to be saved
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1148 //even though duplicate info is probably in the regs array
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1149 save_int8(buf, context->channels[i].block);
1450
08bc099a622f Save entirety of fnum register, not just the low 8 bits
Michael Pavone <pavone@retrodev.com>
parents: 1447
diff changeset
1150 save_int16(buf, context->channels[i].fnum);
1447
a094815b1168 Save and restore YM2612 timer control and keyon/off state in native save states
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
1151 save_int8(buf, context->channels[i].keyon);
1427
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1152 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1153 for (int i = 0; i < 3; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1154 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1155 //Due to the latching behavior, these need to be saved
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1156 //even though duplicate info is probably in the regs array
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1157 save_int8(buf, context->ch3_supp[i].block);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1158 save_int8(buf, context->ch3_supp[i].fnum);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1159 }
1447
a094815b1168 Save and restore YM2612 timer control and keyon/off state in native save states
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
1160 save_int8(buf, context->timer_control);
1427
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1161 save_int16(buf, context->timer_a);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1162 save_int8(buf, context->timer_b);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1163 save_int8(buf, context->sub_timer_b);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1164 save_int16(buf, context->env_counter);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1165 save_int8(buf, context->current_op);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1166 save_int8(buf, context->current_env_op);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1167 save_int8(buf, context->lfo_counter);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1168 save_int8(buf, context->csm_keyon);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1169 save_int8(buf, context->status);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1170 save_int8(buf, context->selected_reg);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1171 save_int8(buf, context->selected_part);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1172 save_int32(buf, context->current_cycle);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1173 save_int32(buf, context->write_cycle);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1174 save_int32(buf, context->busy_cycles);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1175 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1176
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1177 void ym_deserialize(deserialize_buffer *buf, void *vcontext)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1178 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1179 ym2612_context *context = vcontext;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1180 uint8_t temp_regs[YM_PART1_REGS];
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1181 load_buffer8(buf, temp_regs, YM_PART1_REGS);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1182 context->selected_part = 0;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1183 for (int i = 0; i < YM_PART1_REGS; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1184 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1185 uint8_t reg = YM_PART1_START + i;
1447
a094815b1168 Save and restore YM2612 timer control and keyon/off state in native save states
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
1186 if (reg == REG_TIME_CTRL) {
a094815b1168 Save and restore YM2612 timer control and keyon/off state in native save states
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
1187 context->ch3_mode = temp_regs[i] & 0xC0;
a094815b1168 Save and restore YM2612 timer control and keyon/off state in native save states
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
1188 } else if (reg != REG_FNUM_LOW && reg != REG_KEY_ONOFF) {
1427
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1189 context->selected_reg = reg;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1190 ym_data_write(context, temp_regs[i]);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1191 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1192 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1193 load_buffer8(buf, temp_regs, YM_PART2_REGS);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1194 context->selected_part = 1;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1195 for (int i = 0; i < YM_PART2_REGS; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1196 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1197 uint8_t reg = YM_PART2_START + i;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1198 if (reg != REG_FNUM_LOW) {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1199 context->selected_reg = reg;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1200 ym_data_write(context, temp_regs[i]);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1201 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1202 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1203 for (int i = 0; i < NUM_OPERATORS; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1204 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1205 context->operators[i].phase_counter = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1206 context->operators[i].envelope = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1207 context->operators[i].output = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1208 context->operators[i].env_phase = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1209 if (context->operators[i].env_phase > PHASE_RELEASE) {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1210 context->operators[i].env_phase = PHASE_RELEASE;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1211 }
1450
08bc099a622f Save entirety of fnum register, not just the low 8 bits
Michael Pavone <pavone@retrodev.com>
parents: 1447
diff changeset
1212 context->operators[i].inverted = load_int8(buf) != 0 ? SSG_INVERT : 0;
1427
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1213 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1214 for (int i = 0; i < NUM_CHANNELS; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1215 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1216 context->channels[i].output = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1217 context->channels[i].op1_old = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1218 context->channels[i].block = load_int8(buf);
1450
08bc099a622f Save entirety of fnum register, not just the low 8 bits
Michael Pavone <pavone@retrodev.com>
parents: 1447
diff changeset
1219 context->channels[i].fnum = load_int16(buf);
1427
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1220 context->channels[i].keycode = context->channels[i].block << 2 | fnum_to_keycode[context->channels[i].fnum >> 7];
1447
a094815b1168 Save and restore YM2612 timer control and keyon/off state in native save states
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
1221 context->channels[i].keyon = load_int8(buf);
1427
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1222 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1223 for (int i = 0; i < 3; i++)
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1224 {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1225 context->ch3_supp[i].block = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1226 context->ch3_supp[i].fnum = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1227 context->ch3_supp[i].keycode = context->ch3_supp[i].block << 2 | fnum_to_keycode[context->ch3_supp[i].fnum >> 7];
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1228 }
1447
a094815b1168 Save and restore YM2612 timer control and keyon/off state in native save states
Michael Pavone <pavone@retrodev.com>
parents: 1427
diff changeset
1229 context->timer_control = load_int8(buf);
1427
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1230 context->timer_a = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1231 context->timer_b = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1232 context->sub_timer_b = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1233 context->env_counter = load_int16(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1234 context->current_op = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1235 if (context->current_op >= NUM_OPERATORS) {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1236 context->current_op = 0;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1237 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1238 context->current_env_op = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1239 if (context->current_env_op >= NUM_OPERATORS) {
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1240 context->current_env_op = 0;
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1241 }
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1242 context->lfo_counter = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1243 context->csm_keyon = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1244 context->status = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1245 context->selected_reg = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1246 context->selected_part = load_int8(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1247 context->current_cycle = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1248 context->write_cycle = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1249 context->busy_cycles = load_int32(buf);
4e5797b3935a WIP - New savestate format
Michael Pavone <pavone@retrodev.com>
parents: 1356
diff changeset
1250 }