repos/blastem: m68k_to_x86.c annotate

annotate m68k_to_x86.c @ 161:6748022656b7

Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst

author	Mike Pavone <pavone@retrodev.com>
date	Sat, 05 Jan 2013 01:55:11 -0800
parents	c1530501c215
children	eba78ad49a11

rev	line source
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	1 #include "gen_x86.h"
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2 #include "m68k_to_x86.h"
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3 #include "mem.h"
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	4 #include <stdio.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	5 #include <stddef.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	6 #include <stdlib.h>
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	7 #include <string.h>
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	8
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	9 #define BUS 4
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	10 #define PREDEC_PENALTY 2
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	11 #define CYCLES RAX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	12 #define LIMIT RBP
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	13 #define SCRATCH1 RCX
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	14 #define SCRATCH2 RDI
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 #define CONTEXT RSI
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	16
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 #define FLAG_N RBX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	18 #define FLAG_V BH
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 #define FLAG_Z RDX
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 #define FLAG_C DH
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	21
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	22 typedef struct {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	23 int32_t disp;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	24 uint8_t mode;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	25 uint8_t base;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	26 uint8_t index;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	27 uint8_t cycles;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	28 } x86_ea;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	29
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	30 char disasm_buf[1024];
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	31
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	32 void handle_cycle_limit_int();
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	33 void m68k_read_word_scratch1();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	34 void m68k_read_long_scratch1();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	35 void m68k_read_byte_scratch1();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	36 void m68k_write_word();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	37 void m68k_write_long_lowfirst();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	38 void m68k_write_long_highfirst();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	39 void m68k_write_byte();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	40 void m68k_save_context();
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	41 void m68k_modified_ret_addr();
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	42 void m68k_native_addr();
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	43 void m68k_native_addr_and_sync();
152 79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	44 void m68k_trap();
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	45 void set_sr();
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	46 void set_ccr();
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	47 void get_sr();
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	48 void do_sync();
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	49 void m68k_start_context(uint8_t * addr, m68k_context * context);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	50
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 uint8_t * cycles(uint8_t * dst, uint32_t num)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	52 {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	53 dst = add_ir(dst, num, CYCLES, SZ_D);
118 d9ff99ef5533 cycles should return dst Mike Pavone <pavone@retrodev.com> parents: 116 diff changeset	54 return dst;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	55 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	56
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	57 uint8_t * check_cycles_int(uint8_t * dst, uint32_t address)
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	58 {
87 60b5c9e2f4e0 vertical interrupts now work Mike Pavone <pavone@retrodev.com> parents: 86 diff changeset	59 dst = cmp_rr(dst, CYCLES, LIMIT, SZ_D);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	60 uint8_t * jmp_off = dst+1;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	61 dst = jcc(dst, CC_NC, dst + 7);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	62 dst = mov_ir(dst, address, SCRATCH1, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	63 dst = call(dst, (uint8_t *)handle_cycle_limit_int);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	64 *jmp_off = dst - (jmp_off+1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	65 return dst;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	66 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	67
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	68 int8_t native_reg(m68k_op_info * op, x86_68k_options * opts)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	69 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	70 if (op->addr_mode == MODE_REG) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	71 return opts->dregs[op->params.regs.pri];
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	72 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	73 if (op->addr_mode == MODE_AREG) {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	74 return opts->aregs[op->params.regs.pri];
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	75 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	76 return -1;
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	77 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	78
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	79 //must be called with an m68k_op_info that uses a register
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	80 size_t reg_offset(m68k_op_info *op)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	81 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	82 if (op->addr_mode == MODE_REG) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	83 return offsetof(m68k_context, dregs) + sizeof(uint32_t) * op->params.regs.pri;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	84 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	85 return offsetof(m68k_context, aregs) + sizeof(uint32_t) * op->params.regs.pri;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	86 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	87
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	88 void print_regs_exit(m68k_context * context)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	89 {
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	90 printf("XNVZC\n%d%d%d%d%d\n", context->flags[0], context->flags[1], context->flags[2], context->flags[3], context->flags[4]);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	91 for (int i = 0; i < 8; i++) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	92 printf("d%d: %X\n", i, context->dregs[i]);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	93 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	94 for (int i = 0; i < 8; i++) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	95 printf("a%d: %X\n", i, context->aregs[i]);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	96 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	97 exit(0);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	98 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	99
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	100 uint8_t * translate_m68k_src(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	101 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	102 int8_t reg = native_reg(&(inst->src), opts);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	103 uint8_t sec_reg;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	104 int32_t dec_amount,inc_amount;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	105 if (reg >= 0) {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	106 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	107 ea->base = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	108 return out;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	109 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	110 switch (inst->src.addr_mode)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	111 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	112 case MODE_REG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	113 case MODE_AREG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	114 //We only get one memory parameter, so if the dst operand is a register in memory,
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	115 //we need to copy this to a temp register first
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	116 reg = native_reg(&(inst->dst), opts);
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	117 if (reg >= 0 \|\| inst->dst.addr_mode == MODE_UNUSED \|\| !(inst->dst.addr_mode == MODE_REG \|\| inst->dst.addr_mode == MODE_AREG)
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	118 \|\| inst->op == M68K_EXG) {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	119
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	120 ea->mode = MODE_REG_DISPLACE8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	121 ea->base = CONTEXT;
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	122 ea->disp = reg_offset(&(inst->src));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	123 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	124 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, inst->extra.size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	125 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	126 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	127 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	128 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	129 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	130 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	131 out = cycles(out, PREDEC_PENALTY);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	132 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
158 a2ab895d9708 Fix predec address mode when used as source Mike Pavone <pavone@retrodev.com> parents: 157 diff changeset	133 out = sub_ir(out, dec_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	134 } else {
158 a2ab895d9708 Fix predec address mode when used as source Mike Pavone <pavone@retrodev.com> parents: 157 diff changeset	135 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	136 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	137 case MODE_AREG_INDIRECT:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	138 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	139 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	140 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	141 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	142 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	143 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	144 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	145 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	146 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	147 out = call(out, (char *)m68k_read_byte_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	148 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	149 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	150 out = call(out, (char *)m68k_read_word_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	151 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	152 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	153 out = call(out, (char *)m68k_read_long_scratch1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	154 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	155 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	156
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	157 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	158 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	159 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	160 out = add_ir(out, inc_amount, opts->aregs[inst->src.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	161 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	162 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->src)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	163 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	164 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	165 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	166 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	167 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	168 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	169 out = cycles(out, BUS);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	170 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	171 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	172 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	173 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	174 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	175 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	176 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	177 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	178 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	179 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	180 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	181 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	182 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	183 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	184 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	185 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	186 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	187 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	188 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	189 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	190 break;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	191 case MODE_AREG_INDEX_DISP8:
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	192 out = cycles(out, 6);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	193 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	194 out = mov_rr(out, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	195 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	196 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	197 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	198 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	199 if (inst->src.params.regs.sec & 1) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	200 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	201 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	202 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	203 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	204 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	205 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	206 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	207 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	208 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	209 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	210 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	211 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	212 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	213 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	214 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	215 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	216 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	217 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	218 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	219 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	220 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	221 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	222 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	223 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	224 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	225 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	226 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	227 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	228 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	229 if (inst->src.params.regs.displacement) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	230 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	231 }
97 c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	232 switch (inst->extra.size)
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	233 {
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	234 case OPSIZE_BYTE:
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	235 out = call(out, (char *)m68k_read_byte_scratch1);
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	236 break;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	237 case OPSIZE_WORD:
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	238 out = call(out, (char *)m68k_read_word_scratch1);
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	239 break;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	240 case OPSIZE_LONG:
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	241 out = call(out, (char *)m68k_read_long_scratch1);
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	242 break;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	243 }
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	244 ea->mode = MODE_REG_DIRECT;
c7185fd840fc Fix address register indexed addressing (probably) Mike Pavone <pavone@retrodev.com> parents: 96 diff changeset	245 ea->base = SCRATCH1;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	246 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	247 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	248 out = cycles(out, BUS);
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	249 out = mov_ir(out, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	250 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	251 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	252 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	253 out = call(out, (char *)m68k_read_byte_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	254 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	255 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	256 out = call(out, (char *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	257 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	258 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	259 out = call(out, (char *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	260 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	261 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	262 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	263 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	264 break;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	265 case MODE_PC_INDEX_DISP8:
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	266 out = cycles(out, 6);
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	267 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	268 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	269 if (inst->src.params.regs.sec & 1) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	270 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	271 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	272 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	273 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	274 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	275 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	276 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	277 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	278 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	279 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	280 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	281 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	282 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	283 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	284 if (inst->src.params.regs.sec & 0x10) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	285 if (opts->aregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	286 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	287 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	288 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	289 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	290 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	291 if (opts->dregs[sec_reg] >= 0) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	292 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	293 } else {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	294 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	295 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	296 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	297 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	298 }
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	299 if (inst->src.params.regs.displacement) {
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	300 out = add_ir(out, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	301 }
96 f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	302 switch (inst->extra.size)
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	303 {
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	304 case OPSIZE_BYTE:
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	305 out = call(out, (char *)m68k_read_byte_scratch1);
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	306 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	307 case OPSIZE_WORD:
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	308 out = call(out, (char *)m68k_read_word_scratch1);
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	309 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	310 case OPSIZE_LONG:
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	311 out = call(out, (char *)m68k_read_long_scratch1);
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	312 break;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	313 }
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	314 ea->mode = MODE_REG_DIRECT;
f894f85cf39d Fix pc indexed addressing (probably) when used as a source Mike Pavone <pavone@retrodev.com> parents: 95 diff changeset	315 ea->base = SCRATCH1;
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	316 break;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	317 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	318 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	319 if (inst->src.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	320 out = cycles(out, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	321 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	322 out = cycles(out, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	323 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	324 out = mov_ir(out, inst->src.params.immed, SCRATCH1, SZ_D);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	325 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	326 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	327 case OPSIZE_BYTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	328 out = call(out, (char *)m68k_read_byte_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	329 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	330 case OPSIZE_WORD:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	331 out = call(out, (char *)m68k_read_word_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	332 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	333 case OPSIZE_LONG:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	334 out = call(out, (char *)m68k_read_long_scratch1);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	335 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	336 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	337 ea->mode = MODE_REG_DIRECT;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	338 ea->base = SCRATCH1;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	339 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	340 case MODE_IMMEDIATE:
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	341 case MODE_IMMEDIATE_WORD:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	342 if (inst->variant != VAR_QUICK) {
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	343 out = cycles(out, (inst->extra.size == OPSIZE_LONG && inst->src.addr_mode == MODE_IMMEDIATE) ? BUS*2 : BUS);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	344 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	345 ea->mode = MODE_IMMED;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	346 ea->disp = inst->src.params.immed;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	347 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	348 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	349 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	350 printf("%X: %s\naddress mode %d not implemented (src)\n", inst->address, disasm_buf, inst->src.addr_mode);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	351 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	352 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	353 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	354 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	355
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	356 uint8_t * translate_m68k_dst(m68kinst * inst, x86_ea * ea, uint8_t * out, x86_68k_options * opts, uint8_t fake_read)
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	357 {
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	358 int8_t reg = native_reg(&(inst->dst), opts), sec_reg;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	359 int32_t dec_amount, inc_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	360 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	361 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	362 ea->base = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	363 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	364 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	365 switch (inst->dst.addr_mode)
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	366 {
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	367 case MODE_REG:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	368 case MODE_AREG:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	369 ea->mode = MODE_REG_DISPLACE8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	370 ea->base = CONTEXT;
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	371 ea->disp = reg_offset(&(inst->dst));
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	372 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	373 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	374 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	375 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	376 out = sub_ir(out, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	377 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	378 out = sub_irdisp8(out, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	379 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	380 case MODE_AREG_INDIRECT:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	381 case MODE_AREG_POSTINC:
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	382 if (fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	383 out = cycles(out, inst->extra.size == OPSIZE_LONG ? 8 : 4);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	384 } else {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	385 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	386 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	387 } else {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	388 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	389 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	390 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	391 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	392 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	393 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	394 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	395 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	396 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	397 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	398 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	399 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	400 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	401 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	402 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	403 //save reg value in SCRATCH2 so we can use it to save the result in memory later
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	404 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	405 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	406 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	407 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	408 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	409
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	410 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	411 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	412 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	413 out = add_ir(out, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	414 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	415 out = add_irdisp8(out, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	416 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	417 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	418 ea->mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	419 ea->base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	420 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	421 case MODE_AREG_DISPLACE:
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	422 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	423 reg = fake_read ? SCRATCH2 : SCRATCH1;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	424 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	425 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], reg, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	426 } else {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	427 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), reg, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	428 }
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	429 out = add_ir(out, inst->dst.params.regs.displacement, reg, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	430 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	431 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	432 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	433 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	434 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	435 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	436 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	437 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	438 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	439 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	440 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	441 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	442 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	443 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	444 out = pop_r(out, SCRATCH2);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	445 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	446 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	447 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	448 break;
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	449 case MODE_AREG_INDEX_DISP8:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	450 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	451 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	452 out = mov_rr(out, opts->aregs[inst->dst.params.regs.pri], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	453 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	454 out = mov_rdisp8r(out, CONTEXT, reg_offset(&(inst->dst)), SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	455 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	456 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	457 if (inst->dst.params.regs.sec & 1) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	458 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	459 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	460 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	461 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	462 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	463 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	464 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	465 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	466 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	467 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	468 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	469 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	470 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	471 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	472 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	473 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	474 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	475 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	476 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	477 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	478 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	479 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	480 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	481 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	482 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	483 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	484 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	485 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	486 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	487 if (inst->dst.params.regs.displacement) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	488 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	489 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	490 if (fake_read) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	491 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	492 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	493 out = push_r(out, SCRATCH1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	494 switch (inst->extra.size)
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	495 {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	496 case OPSIZE_BYTE:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	497 out = call(out, (char *)m68k_read_byte_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	498 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	499 case OPSIZE_WORD:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	500 out = call(out, (char *)m68k_read_word_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	501 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	502 case OPSIZE_LONG:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	503 out = call(out, (char *)m68k_read_long_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	504 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	505 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	506 out = pop_r(out, SCRATCH2);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	507 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	508 ea->mode = MODE_REG_DIRECT;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	509 ea->base = SCRATCH1;
161 6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	510 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	511 case MODE_PC_DISPLACE:
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	512 out = cycles(out, fake_read ? BUS+(inst->extra.size == OPSIZE_LONG ? BUS*2 : BUS) : BUS);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	513 out = mov_ir(out, inst->dst.params.regs.displacement + inst->address+2, fake_read ? SCRATCH2 : SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	514 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	515 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	516 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	517 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	518 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	519 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	520 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	521 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	522 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	523 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	524 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	525 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	526 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	527 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	528 out = pop_r(out, SCRATCH2);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	529 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	530 ea->mode = MODE_REG_DIRECT;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	531 ea->base = SCRATCH1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	532 break;
98 104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	533 case MODE_PC_INDEX_DISP8:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	534 out = cycles(out, fake_read ? (6 + inst->extra.size == OPSIZE_LONG ? 8 : 4) : 6);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	535 out = mov_ir(out, inst->address+2, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	536 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	537 if (inst->dst.params.regs.sec & 1) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	538 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	539 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	540 out = add_rr(out, opts->aregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	541 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	542 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	543 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	544 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	545 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	546 out = add_rr(out, opts->dregs[sec_reg], SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	547 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	548 out = add_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	549 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	550 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	551 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	552 if (inst->dst.params.regs.sec & 0x10) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	553 if (opts->aregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	554 out = movsx_rr(out, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	555 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	556 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	557 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	558 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	559 if (opts->dregs[sec_reg] >= 0) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	560 out = movsx_rr(out, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	561 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	562 out = movsx_rdisp8r(out, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	563 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	564 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	565 out = add_rr(out, SCRATCH2, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	566 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	567 if (inst->dst.params.regs.displacement) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	568 out = add_ir(out, inst->dst.params.regs.displacement, SCRATCH1, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	569 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	570 if (fake_read) {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	571 out = mov_rr(out, SCRATCH1, SCRATCH2, SZ_D);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	572 } else {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	573 out = push_r(out, SCRATCH1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	574 switch (inst->extra.size)
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	575 {
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	576 case OPSIZE_BYTE:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	577 out = call(out, (char *)m68k_read_byte_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	578 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	579 case OPSIZE_WORD:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	580 out = call(out, (char *)m68k_read_word_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	581 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	582 case OPSIZE_LONG:
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	583 out = call(out, (char *)m68k_read_long_scratch1);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	584 break;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	585 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	586 out = pop_r(out, SCRATCH2);
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	587 }
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	588 ea->mode = MODE_REG_DIRECT;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	589 ea->base = SCRATCH1;
104e257fb93c Allow indexed modes to be used as a destination Mike Pavone <pavone@retrodev.com> parents: 97 diff changeset	590 break;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	591 case MODE_ABSOLUTE:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	592 case MODE_ABSOLUTE_SHORT:
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	593 //Add cycles for reading address from instruction stream
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	594 out = cycles(out, (inst->dst.addr_mode == MODE_ABSOLUTE ? BUS2 : BUS) + (fake_read ? (inst->extra.size == OPSIZE_LONG ? BUS2 : BUS) : 0));
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	595 out = mov_ir(out, inst->dst.params.immed, fake_read ? SCRATCH2 : SCRATCH1, SZ_D);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	596 if (!fake_read) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	597 out = push_r(out, SCRATCH1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	598 switch (inst->extra.size)
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	599 {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	600 case OPSIZE_BYTE:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	601 out = call(out, (char *)m68k_read_byte_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	602 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	603 case OPSIZE_WORD:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	604 out = call(out, (char *)m68k_read_word_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	605 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	606 case OPSIZE_LONG:
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	607 out = call(out, (char *)m68k_read_long_scratch1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	608 break;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	609 }
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	610 out = pop_r(out, SCRATCH2);
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	611 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	612 ea->mode = MODE_REG_DIRECT;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	613 ea->base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	614 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	615 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	616 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	617 printf("%X: %s\naddress mode %d not implemented (dst)\n", inst->address, disasm_buf, inst->dst.addr_mode);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	618 exit(1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	619 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	620 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	621 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	622
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	623 uint8_t * m68k_save_result(m68kinst * inst, uint8_t * out, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	624 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	625 if (inst->dst.addr_mode != MODE_REG && inst->dst.addr_mode != MODE_AREG) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	626 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	627 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	628 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	629 out = call(out, (char *)m68k_write_byte);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	630 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	631 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	632 out = call(out, (char *)m68k_write_word);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	633 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	634 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	635 out = call(out, (char *)m68k_write_long_lowfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	636 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	637 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	638 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	639 return out;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	640 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	641
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	642 uint8_t * get_native_address(native_map_slot * native_code_map, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	643 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	644 address &= 0xFFFFFF;
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	645 if (address > 0x400000) {
86 3d3966c254b2 RTE doesn't crash the emulator anymore Mike Pavone <pavone@retrodev.com> parents: 82 diff changeset	646 printf("get_native_address: %X\n", address);
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	647 }
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	648 address /= 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	649 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	650 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	651 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	652 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	653 uint32_t offset = address % NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	654 if (native_code_map[chunk].offsets[offset] == INVALID_OFFSET) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	655 return NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	656 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	657 return native_code_map[chunk].base + native_code_map[chunk].offsets[offset];
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	658 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	659
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	660 deferred_addr * defer_address(deferred_addr * old_head, uint32_t address, uint8_t *dest)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	661 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	662 deferred_addr * new_head = malloc(sizeof(deferred_addr));
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	663 new_head->next = old_head;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	664 new_head->address = address & 0xFFFFFF;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	665 new_head->dest = dest;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	666 return new_head;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	667 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	668
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	669 void process_deferred(x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	670 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	671 deferred_addr * cur = opts->deferred;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	672 deferred_addr **last_next = &(opts->deferred);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	673 while(cur)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	674 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	675 uint8_t * native = get_native_address(opts->native_code_map, cur->address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	676 if (native) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	677 int32_t disp = native - (cur->dest + 4);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	678 uint8_t * out = cur->dest;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	679 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	680 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	681 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	682 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	683 *(out++) = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	684 disp >>= 8;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	685 *out = disp;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	686 *last_next = cur->next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	687 free(cur);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	688 cur = *last_next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	689 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	690 last_next = &(cur->next);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	691 cur = cur->next;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	692 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	693 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	694 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	695
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	696 void map_native_address(native_map_slot * native_code_map, uint32_t address, uint8_t * native_addr)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	697 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	698 address &= 0xFFFFFF;
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	699 address/= 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	700 uint32_t chunk = address / NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	701 if (!native_code_map[chunk].base) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	702 native_code_map[chunk].base = native_addr;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	703 native_code_map[chunk].offsets = malloc(sizeof(int32_t) * NATIVE_CHUNK_SIZE);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	704 memset(native_code_map[chunk].offsets, 0xFF, sizeof(int32_t) * NATIVE_CHUNK_SIZE);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	705 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	706 uint32_t offset = address % NATIVE_CHUNK_SIZE;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	707 native_code_map[chunk].offsets[offset] = native_addr-native_code_map[chunk].base;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	708 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	709
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	710 uint8_t * translate_m68k_move(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	711 {
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	712 int8_t reg, flags_reg, sec_reg;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	713 uint8_t dir = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	714 int32_t offset;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	715 int32_t inc_amount, dec_amount;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	716 x86_ea src;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	717 dst = translate_m68k_src(inst, &src, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	718 reg = native_reg(&(inst->dst), opts);
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	719 //update statically set flags
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	720 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	721 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	722
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	723 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	724 flags_reg = src.base;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	725 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	726 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	727 flags_reg = reg;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	728 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	729 if(src.mode == MODE_REG_DISPLACE8) {
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	730 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	731 } else {
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	732 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	733 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	734 src.mode = MODE_REG_DIRECT;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	735 flags_reg = src.base = SCRATCH1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	736 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	737 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	738 switch(inst->dst.addr_mode)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	739 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	740 case MODE_REG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	741 case MODE_AREG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	742 if (reg >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	743 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	744 dst = mov_rr(dst, src.base, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	745 } else if (src.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	746 dst = mov_rdisp8r(dst, src.base, src.disp, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	747 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	748 dst = mov_ir(dst, src.disp, reg, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	749 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	750 } else if(src.mode == MODE_REG_DIRECT) {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	751 dst = mov_rrdisp8(dst, src.base, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	752 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	753 dst = mov_irdisp8(dst, src.disp, CONTEXT, reg_offset(&(inst->dst)), inst->extra.size);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	754 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	755 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	756 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	757 dst = setcc_r(dst, CC_S, FLAG_N);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	758 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	759 case MODE_AREG_PREDEC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	760 dec_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	761 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	762 dst = sub_ir(dst, dec_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	763 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	764 dst = sub_irdisp8(dst, dec_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	765 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	766 case MODE_AREG_INDIRECT:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	767 case MODE_AREG_POSTINC:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	768 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	769 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	770 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	771 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	772 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	773 if (src.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	774 if (src.base != SCRATCH1) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	775 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	776 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	777 } else if (src.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	778 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	779 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	780 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	781 }
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	782 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	783 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	784 dst = setcc_r(dst, CC_S, FLAG_N);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	785 switch (inst->extra.size)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	786 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	787 case OPSIZE_BYTE:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	788 dst = call(dst, (char *)m68k_write_byte);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	789 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	790 case OPSIZE_WORD:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	791 dst = call(dst, (char *)m68k_write_word);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	792 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	793 case OPSIZE_LONG:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	794 dst = call(dst, (char *)m68k_write_long_highfirst);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	795 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	796 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	797 if (inst->dst.addr_mode == MODE_AREG_POSTINC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	798 inc_amount = inst->extra.size == OPSIZE_WORD ? 2 : (inst->extra.size == OPSIZE_LONG ? 4 : 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	799 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	800 dst = add_ir(dst, inc_amount, opts->aregs[inst->dst.params.regs.pri], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	801 } else {
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	802 dst = add_irdisp8(dst, inc_amount, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	803 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	804 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	805 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	806 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	807 dst = cycles(dst, BUS);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	808 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	809 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	810 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	811 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	812 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	813 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	814 if (src.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	815 if (src.base != SCRATCH1) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	816 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	817 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	818 } else if (src.mode == MODE_REG_DISPLACE8) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	819 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	820 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	821 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	822 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	823 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	824 dst = setcc_r(dst, CC_Z, FLAG_Z);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	825 dst = setcc_r(dst, CC_S, FLAG_N);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	826 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	827 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	828 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	829 dst = call(dst, (char *)m68k_write_byte);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	830 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	831 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	832 dst = call(dst, (char *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	833 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	834 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	835 dst = call(dst, (char *)m68k_write_long_highfirst);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	836 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	837 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	838 break;
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	839 case MODE_AREG_INDEX_DISP8:
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	840 dst = cycles(dst, 6);//TODO: Check to make sure this is correct
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	841 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	842 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	843 } else {
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	844 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	845 }
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	846 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	847 if (inst->dst.params.regs.sec & 1) {
9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	848 if (inst->dst.params.regs.sec & 0x10) {
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	849 if (opts->aregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	850 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	851 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	852 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	853 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	854 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	855 if (opts->dregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	856 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	857 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	858 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	859 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	860 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	861 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	862 if (src.base == SCRATCH1) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	863 dst = push_r(dst, SCRATCH1);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	864 }
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	865 if (inst->dst.params.regs.sec & 0x10) {
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	866 if (opts->aregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	867 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	868 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	869 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	870 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	871 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	872 if (opts->dregs[sec_reg] >= 0) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	873 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	874 } else {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	875 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	876 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	877 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	878 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	879 if (src.base == SCRATCH1) {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	880 dst = pop_r(dst, SCRATCH1);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	881 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	882 }
107 9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	883 if (inst->dst.params.regs.displacement) {
9705075fcf36 Fix areg indexed mode for move dst Mike Pavone <pavone@retrodev.com> parents: 106 diff changeset	884 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
99 8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	885 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	886 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	887 dst = setcc_r(dst, CC_Z, FLAG_Z);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	888 dst = setcc_r(dst, CC_S, FLAG_N);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	889 switch (inst->extra.size)
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	890 {
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	891 case OPSIZE_BYTE:
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	892 dst = call(dst, (char *)m68k_write_byte);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	893 break;
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	894 case OPSIZE_WORD:
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	895 dst = call(dst, (char *)m68k_write_word);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	896 break;
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	897 case OPSIZE_LONG:
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	898 dst = call(dst, (char *)m68k_write_long_highfirst);
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	899 break;
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	900 }
8491de5d6c06 Allow use of indexed modes as move dst Mike Pavone <pavone@retrodev.com> parents: 98 diff changeset	901 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	902 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	903 dst = cycles(dst, BUS);
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	904 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	905 if (src.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	906 if (src.base != SCRATCH1) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	907 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	908 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	909 } else if (src.mode == MODE_REG_DISPLACE8) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	910 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	911 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	912 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	913 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	914 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	915 dst = setcc_r(dst, CC_Z, FLAG_Z);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	916 dst = setcc_r(dst, CC_S, FLAG_N);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	917 switch (inst->extra.size)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	918 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	919 case OPSIZE_BYTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	920 dst = call(dst, (char *)m68k_write_byte);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	921 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	922 case OPSIZE_WORD:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	923 dst = call(dst, (char *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	924 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	925 case OPSIZE_LONG:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	926 dst = call(dst, (char *)m68k_write_long_highfirst);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	927 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	928 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	929 break;
54 3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	930 case MODE_ABSOLUTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	931 case MODE_ABSOLUTE_SHORT:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	932 if (src.mode == MODE_REG_DIRECT) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	933 if (src.base != SCRATCH1) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	934 dst = mov_rr(dst, src.base, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	935 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	936 } else if (src.mode == MODE_REG_DISPLACE8) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	937 dst = mov_rdisp8r(dst, src.base, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	938 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	939 dst = mov_ir(dst, src.disp, SCRATCH1, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	940 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	941 if (inst->dst.addr_mode == MODE_ABSOLUTE) {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	942 dst = cycles(dst, BUS*2);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	943 } else {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	944 dst = cycles(dst, BUS);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	945 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	946 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	947 dst = cmp_ir(dst, 0, flags_reg, inst->extra.size);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	948 dst = setcc_r(dst, CC_Z, FLAG_Z);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	949 dst = setcc_r(dst, CC_S, FLAG_N);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	950 switch (inst->extra.size)
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	951 {
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	952 case OPSIZE_BYTE:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	953 dst = call(dst, (char *)m68k_write_byte);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	954 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	955 case OPSIZE_WORD:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	956 dst = call(dst, (char *)m68k_write_word);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	957 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	958 case OPSIZE_LONG:
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	959 dst = call(dst, (char *)m68k_write_long_highfirst);
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	960 break;
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	961 }
3b79cbcf6846 Get Flavio's color bar demo kind of sort of working Mike Pavone <pavone@retrodev.com> parents: 53 diff changeset	962 break;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	963 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	964 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	965 printf("%X: %s\naddress mode %d not implemented (move dst)\n", inst->address, disasm_buf, inst->dst.addr_mode);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	966 exit(1);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	967 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	968
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	969 //add cycles for prefetch
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	970 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	971 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	972 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	973
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	974 uint8_t * translate_m68k_movem(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	975 {
161 6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	976 int8_t bit,reg,sec_reg;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	977 uint8_t early_cycles;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	978 if(inst->src.addr_mode == MODE_REG) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	979 //reg to mem
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	980 early_cycles = 8;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	981 int8_t dir;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	982 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	983 reg = 15;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	984 dir = -1;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	985 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	986 reg = 0;
159 c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode Mike Pavone <pavone@retrodev.com> parents: 158 diff changeset	987 dir = 1;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	988 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	989 switch (inst->dst.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	990 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	991 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	992 case MODE_AREG_PREDEC:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	993 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	994 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	995 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	996 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	997 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	998 break;
161 6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	999 case MODE_AREG_DISPLACE:
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1000 early_cycles += BUS;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1001 reg = SCRATCH2;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1002 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1003 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1004 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1005 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1006 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1007 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1008 break;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1009 case MODE_AREG_INDEX_DISP8:
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1010 early_cycles += 6;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1011 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1012 dst = mov_rr(dst, opts->aregs[inst->dst.params.regs.pri], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1013 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1014 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->dst)), SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1015 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1016 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1017 if (inst->dst.params.regs.sec & 1) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1018 if (inst->dst.params.regs.sec & 0x10) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1019 if (opts->aregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1020 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1021 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1022 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1023 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1024 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1025 if (opts->dregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1026 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1027 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1028 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1029 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1030 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1031 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1032 if (inst->dst.params.regs.sec & 0x10) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1033 if (opts->aregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1034 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1035 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1036 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1037 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1038 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1039 if (opts->dregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1040 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1041 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1042 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1043 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1044 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1045 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1046 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1047 if (inst->dst.params.regs.displacement) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1048 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1049 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1050 break;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1051 case MODE_PC_DISPLACE:
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1052 early_cycles += BUS;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1053 dst = mov_ir(dst, inst->dst.params.regs.displacement + inst->address+2, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1054 break;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1055 case MODE_PC_INDEX_DISP8:
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1056 early_cycles += 6;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1057 dst = mov_ir(dst, inst->address+2, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1058 sec_reg = (inst->dst.params.regs.sec >> 1) & 0x7;
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1059 if (inst->dst.params.regs.sec & 1) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1060 if (inst->dst.params.regs.sec & 0x10) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1061 if (opts->aregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1062 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1063 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1064 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1065 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1066 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1067 if (opts->dregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1068 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1069 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1070 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1071 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1072 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1073 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1074 if (inst->dst.params.regs.sec & 0x10) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1075 if (opts->aregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1076 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1077 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1078 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1079 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1080 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1081 if (opts->dregs[sec_reg] >= 0) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1082 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1083 } else {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1084 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1085 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1086 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1087 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1088 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1089 if (inst->dst.params.regs.displacement) {
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1090 dst = add_ir(dst, inst->dst.params.regs.displacement, SCRATCH2, SZ_D);
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1091 }
6748022656b7 Implement more address modes for movem dst and fix a missing break statement in translate_m68k_dst Mike Pavone <pavone@retrodev.com> parents: 159 diff changeset	1092 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1093 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1094 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1095 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1096 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1097 dst = mov_ir(dst, inst->dst.params.immed, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1098 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1099 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	1100 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1101 printf("%X: %s\naddress mode %d not implemented (movem dst)\n", inst->address, disasm_buf, inst->dst.addr_mode);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1102 exit(1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1103 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1104 dst = cycles(dst, early_cycles);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1105 for(bit=0; reg < 16 && reg >= 0; reg += dir, bit++) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1106 if (inst->src.params.immed & (1 << bit)) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1107 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1108 dst = sub_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1109 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1110 dst = push_r(dst, SCRATCH2);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1111 if (reg > 7) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1112 if (opts->aregs[reg-8] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1113 dst = mov_rr(dst, opts->aregs[reg-8], SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1114 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1115 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1116 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1117 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1118 if (opts->dregs[reg] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1119 dst = mov_rr(dst, opts->dregs[reg], SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1120 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1121 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), SCRATCH1, inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1122 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1123 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1124 if (inst->extra.size == OPSIZE_LONG) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1125 dst = call(dst, (uint8_t *)m68k_write_long_lowfirst);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1126 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1127 dst = call(dst, (uint8_t *)m68k_write_word);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1128 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1129 dst = pop_r(dst, SCRATCH2);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1130 if (inst->dst.addr_mode != MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1131 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1132 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1133 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1134 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1135 if (inst->dst.addr_mode == MODE_AREG_PREDEC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1136 if (opts->aregs[inst->dst.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1137 dst = mov_rr(dst, SCRATCH2, opts->aregs[inst->dst.params.regs.pri], SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1138 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1139 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1140 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1141 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1142 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1143 //mem to reg
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1144 early_cycles = 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1145 switch (inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1146 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1147 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1148 case MODE_AREG_POSTINC:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1149 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1150 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1151 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1152 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1153 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1154 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1155 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1156 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1157 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1158 early_cycles += 4;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1159 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1160 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1161 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	1162 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1163 printf("%X: %s\naddress mode %d not implemented (movem src)\n", inst->address, disasm_buf, inst->src.addr_mode);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1164 exit(1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1165 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1166 dst = cycles(dst, early_cycles);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1167 for(reg = 0; reg < 16; reg ++) {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1168 if (inst->dst.params.immed & (1 << reg)) {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1169 dst = push_r(dst, SCRATCH1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1170 if (inst->extra.size == OPSIZE_LONG) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1171 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1172 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1173 dst = call(dst, (uint8_t *)m68k_read_word_scratch1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1174 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1175 if (reg > 7) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1176 if (opts->aregs[reg-8] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1177 dst = mov_rr(dst, SCRATCH1, opts->aregs[reg-8], inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1178 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1179 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * (reg-8), inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1180 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1181 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1182 if (opts->dregs[reg] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1183 dst = mov_rr(dst, SCRATCH1, opts->dregs[reg], inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1184 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1185 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t) * (reg), inst->extra.size);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1186 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1187 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1188 dst = pop_r(dst, SCRATCH1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1189 dst = add_ir(dst, (inst->extra.size == OPSIZE_LONG) ? 4 : 2, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1190 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1191 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1192 if (inst->src.addr_mode == MODE_AREG_POSTINC) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1193 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1194 dst = mov_rr(dst, SCRATCH1, opts->aregs[inst->src.params.regs.pri], SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1195 } else {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1196 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->src)), SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1197 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1198 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1199 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1200 //prefetch
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1201 dst = cycles(dst, 4);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1202 return dst;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1203 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1204
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1205 uint8_t * translate_m68k_clr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1206 {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1207 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1208 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1209 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1210 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1211 int8_t reg = native_reg(&(inst->dst), opts);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1212 if (reg >= 0) {
64 2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1213 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 6 : 4));
2b1a65f4b85d Cleanup 68K timing code. Temporarily omment out fFPS counter as it was causing segfaults Mike Pavone <pavone@retrodev.com> parents: 61 diff changeset	1214 return xor_rr(dst, reg, reg, inst->extra.size);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1215 }
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1216 x86_ea dst_op;
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1217 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1218 if (dst_op.mode == MODE_REG_DIRECT) {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1219 dst = xor_rr(dst, dst_op.base, dst_op.base, inst->extra.size);
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1220 } else {
c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1221 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1222 }
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	1223 dst = m68k_save_result(inst, dst, opts);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1224 return dst;
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1225 }
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	1226
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1227 uint8_t * translate_m68k_ext(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1228 {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1229 x86_ea dst_op;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1230 uint8_t dst_size = inst->extra.size;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1231 inst->extra.size--;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1232 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1233 if (dst_op.mode == MODE_REG_DIRECT) {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1234 dst = movsx_rr(dst, dst_op.base, dst_op.base, inst->extra.size, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1235 dst = cmp_ir(dst, 0, dst_op.base, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1236 } else {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1237 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH1, inst->extra.size, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1238 dst = cmp_ir(dst, 0, SCRATCH1, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1239 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, dst_size);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1240 }
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1241 inst->extra.size = dst_size;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1242 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1243 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1244 dst = setcc_r(dst, CC_Z, FLAG_Z);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1245 dst = setcc_r(dst, CC_S, FLAG_N);
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1246 //M68K EXT only operates on registers so no need for a call to save result here
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1247 return dst;
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1248 }
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	1249
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1250 uint8_t * translate_m68k_lea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1251 {
100 45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1252 int8_t dst_reg = native_reg(&(inst->dst), opts), sec_reg;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1253 switch(inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1254 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1255 case MODE_AREG_INDIRECT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1256 dst = cycles(dst, BUS);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1257 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1258 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1259 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1260 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1261 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1262 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1263 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1264 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1265 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1266 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1267 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1268 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1269 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1270 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1271 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1272 case MODE_AREG_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1273 dst = cycles(dst, 8);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1274 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1275 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1276 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1277 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1278 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1279 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1280 dst = add_ir(dst, inst->src.params.regs.displacement, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1281 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1282 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1283 dst = mov_rrdisp8(dst, opts->aregs[inst->src.params.regs.pri], CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1284 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1285 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1286 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1287 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1288 dst = add_irdisp8(dst, inst->src.params.regs.displacement, CONTEXT, reg_offset(&(inst->src)), SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1289 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1290 break;
100 45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1291 case MODE_AREG_INDEX_DISP8:
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1292 dst = cycles(dst, 6);//TODO: Check to make sure this is correct
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1293 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1294 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1295 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1296 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1297 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1298 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1299 if (inst->src.params.regs.sec & 1) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1300 if (inst->src.params.regs.sec & 0x10) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1301 if (opts->aregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1302 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1303 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1304 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1305 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1306 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1307 if (opts->dregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1308 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1309 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1310 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1311 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1312 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1313 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1314 if (inst->src.params.regs.sec & 0x10) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1315 if (opts->aregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1316 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1317 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1318 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1319 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1320 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1321 if (opts->dregs[sec_reg] >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1322 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1323 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1324 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_W, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1325 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1326 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1327 dst = add_rr(dst, SCRATCH1, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1328 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1329 if (inst->src.params.regs.displacement) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1330 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH2, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1331 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1332 if (dst_reg >= 0) {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1333 dst = mov_rr(dst, SCRATCH2, dst_reg, SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1334 } else {
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1335 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, reg_offset(&(inst->src)), SZ_D);
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1336 }
45cd7d3e7918 Implement areg indexed mode for lea Mike Pavone <pavone@retrodev.com> parents: 99 diff changeset	1337 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1338 case MODE_PC_DISPLACE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1339 dst = cycles(dst, 8);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1340 if (dst_reg >= 0) {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1341 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, dst_reg, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1342 } else {
74 6396dc91f61e Fix some bugs in movem with a register list destination Mike Pavone <pavone@retrodev.com> parents: 73 diff changeset	1343 dst = mov_irdisp8(dst, inst->src.params.regs.displacement + inst->address+2, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->dst.params.regs.pri, SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1344 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1345 break;
133 c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1346 case MODE_PC_INDEX_DISP8:
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1347 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1348 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1349 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1350 if (inst->src.params.regs.sec & 1) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1351 if (inst->src.params.regs.sec & 0x10) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1352 if (opts->aregs[sec_reg] >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1353 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1354 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1355 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1356 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1357 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1358 if (opts->dregs[sec_reg] >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1359 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1360 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1361 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1362 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1363 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1364 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1365 if (inst->src.params.regs.sec & 0x10) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1366 if (opts->aregs[sec_reg] >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1367 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1368 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1369 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1370 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1371 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1372 if (opts->dregs[sec_reg] >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1373 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1374 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1375 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1376 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1377 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1378 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1379 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1380 if (inst->src.params.regs.displacement) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1381 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1382 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1383 if (dst_reg >= 0) {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1384 dst = mov_rr(dst, SCRATCH1, dst_reg, SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1385 } else {
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1386 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1387 }
c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1388 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1389 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1390 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1391 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1392 if (dst_reg >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1393 dst = mov_ir(dst, inst->src.params.immed, dst_reg, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1394 } else {
133 c4d10c2aaee2 Add support for pc indexed addressing mode to lea Mike Pavone <pavone@retrodev.com> parents: 132 diff changeset	1395 dst = mov_irdisp8(dst, inst->src.params.immed, CONTEXT, reg_offset(&(inst->dst)), SZ_D);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1396 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1397 break;
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1398 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	1399 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1400 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1401 exit(1);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1402 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1403 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1404 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1405
116 9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1406 uint8_t * translate_m68k_pea(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1407 {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1408 uint8_t sec_reg;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1409 switch(inst->src.addr_mode)
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1410 {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1411 case MODE_AREG_INDIRECT:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1412 dst = cycles(dst, BUS);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1413 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1414 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1415 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1416 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1417 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1418 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1419 case MODE_AREG_DISPLACE:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1420 dst = cycles(dst, 8);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1421 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1422 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1423 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1424 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1425 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1426 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1427 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1428 case MODE_AREG_INDEX_DISP8:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1429 dst = cycles(dst, 6);//TODO: Check to make sure this is correct
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1430 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1431 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1432 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1433 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1434 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1435 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1436 if (inst->src.params.regs.sec & 1) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1437 if (inst->src.params.regs.sec & 0x10) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1438 if (opts->aregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1439 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1440 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1441 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1442 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1443 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1444 if (opts->dregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1445 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1446 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1447 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1448 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1449 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1450 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1451 if (inst->src.params.regs.sec & 0x10) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1452 if (opts->aregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1453 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1454 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1455 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1456 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1457 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1458 if (opts->dregs[sec_reg] >= 0) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1459 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1460 } else {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1461 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1462 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1463 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1464 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1465 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1466 if (inst->src.params.regs.displacement) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1467 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1468 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1469 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1470 case MODE_PC_DISPLACE:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1471 dst = cycles(dst, 8);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1472 dst = mov_ir(dst, inst->src.params.regs.displacement + inst->address+2, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1473 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1474 case MODE_ABSOLUTE:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1475 case MODE_ABSOLUTE_SHORT:
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1476 dst = cycles(dst, (inst->src.addr_mode == MODE_ABSOLUTE) ? BUS * 3 : BUS * 2);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1477 dst = mov_ir(dst, inst->src.params.immed, SCRATCH1, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1478 break;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1479 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	1480 m68k_disasm(inst, disasm_buf);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1481 printf("%X: %s\naddress mode %d not implemented (lea src)\n", inst->address, disasm_buf, inst->src.addr_mode);
116 9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1482 exit(1);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1483 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1484 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1485 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1486 dst = call(dst, (uint8_t *)m68k_write_long_lowfirst);
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1487 return dst;
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1488 }
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	1489
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1490 uint8_t * translate_m68k_bsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1491 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1492 int32_t disp = inst->src.params.immed;
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1493 uint32_t after = inst->address + (inst->variant == VAR_BYTE ? 2 : 4);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1494 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1495 dst = cycles(dst, 10);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1496 dst = mov_ir(dst, after, SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1497 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1498 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1499 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1500 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1501 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1502 dst = call(dst, (char *)m68k_write_long_highfirst);
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1503 uint8_t * dest_addr = get_native_address(opts->native_code_map, (inst->address+2) + disp);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1504 if (!dest_addr) {
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	1505 opts->deferred = defer_address(opts->deferred, (inst->address+2) + disp, dst + 1);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1506 //dummy address to be replaced later
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1507 dest_addr = dst + 256;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1508 }
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1509 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1510 dst = call(dst, (char *)dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1511 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1512 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1513 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1514 dst = jmp(dst, (char *)dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1515 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1516 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1517 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1518
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1519 uint8_t * translate_m68k_bcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1520 {
156 3900cfde9dbb Add cycles for Bcc (needs work, but this changes keeps some ROMs from making the emulator unresponsive) Mike Pavone <pavone@retrodev.com> parents: 155 diff changeset	1521 dst = cycles(dst, 10);//TODO: Adjust this for branch not taken case
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1522 int32_t disp = inst->src.params.immed;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	1523 uint32_t after = inst->address + 2;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1524 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + disp);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1525 if (inst->extra.cond == COND_TRUE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1526 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1527 opts->deferred = defer_address(opts->deferred, after + disp, dst + 1);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1528 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1529 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1530 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1531 dst = jmp(dst, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1532 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1533 uint8_t cond = CC_NZ;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1534 switch (inst->extra.cond)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1535 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1536 case COND_HIGH:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1537 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1538 case COND_LOW_SAME:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1539 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1540 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1541 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1542 case COND_CARRY_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1543 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1544 case COND_CARRY_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1545 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1546 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1547 case COND_NOT_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1548 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1549 case COND_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1550 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1551 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1552 case COND_OVERF_CLR:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1553 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1554 case COND_OVERF_SET:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1555 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1556 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1557 case COND_PLUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1558 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1559 case COND_MINUS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1560 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1561 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1562 case COND_GREATER_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1563 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1564 case COND_LESS:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1565 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1566 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1567 case COND_GREATER:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1568 cond = CC_Z;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1569 case COND_LESS_EQ:
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1570 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1571 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1572 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1573 break;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1574 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1575 if (!dest_addr) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1576 opts->deferred = defer_address(opts->deferred, after + disp, dst + 2);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1577 //dummy address to be replaced later, make sure it generates a 4-byte displacement
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1578 dest_addr = dst + 256;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1579 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1580 dst = jcc(dst, cond, dest_addr);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1581 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1582 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1583 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	1584
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1585 uint8_t * translate_m68k_scc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1586 {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1587 uint8_t cond = inst->extra.cond;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1588 x86_ea dst_op;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1589 inst->extra.size = OPSIZE_BYTE;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1590 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 1);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1591 if (cond == COND_TRUE \|\| cond == COND_FALSE) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1592 if ((inst->dst.addr_mode == MODE_REG \|\| inst->dst.addr_mode == MODE_AREG) && inst->extra.cond == COND_TRUE) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1593 dst = cycles(dst, 6);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1594 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1595 dst = cycles(dst, BUS);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1596 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1597 if (dst_op.mode == MODE_REG_DIRECT) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1598 dst = mov_ir(dst, cond == COND_TRUE, dst_op.base, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1599 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1600 dst = mov_irdisp8(dst, cond == COND_TRUE, dst_op.base, dst_op.disp, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1601 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1602 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1603 uint8_t cc = CC_NZ;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1604 switch (cond)
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1605 {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1606 case COND_HIGH:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1607 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1608 case COND_LOW_SAME:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1609 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1610 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1611 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1612 case COND_CARRY_CLR:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1613 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1614 case COND_CARRY_SET:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1615 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1616 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1617 case COND_NOT_EQ:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1618 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1619 case COND_EQ:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1620 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1621 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1622 case COND_OVERF_CLR:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1623 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1624 case COND_OVERF_SET:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1625 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1626 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1627 case COND_PLUS:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1628 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1629 case COND_MINUS:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1630 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1631 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1632 case COND_GREATER_EQ:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1633 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1634 case COND_LESS:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1635 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1636 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1637 case COND_GREATER:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1638 cc = CC_Z;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1639 case COND_LESS_EQ:
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1640 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1641 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1642 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1643 break;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1644 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1645 if ((inst->dst.addr_mode == MODE_REG \|\| inst->dst.addr_mode == MODE_AREG)) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1646 uint8_t *true_off = dst + 1;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1647 dst = jcc(dst, cc, dst+2);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1648 dst = cycles(dst, BUS);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1649 if (dst_op.mode == MODE_REG_DIRECT) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1650 dst = mov_ir(dst, 0, dst_op.base, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1651 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1652 dst = mov_irdisp8(dst, 0, dst_op.base, dst_op.disp, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1653 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1654 uint8_t *end_off = dst+1;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1655 dst = jmp(dst, dst+2);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1656 *true_off = dst - (true_off+1);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1657 dst = cycles(dst, 6);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1658 if (dst_op.mode == MODE_REG_DIRECT) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1659 dst = mov_ir(dst, 1, dst_op.base, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1660 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1661 dst = mov_irdisp8(dst, 1, dst_op.base, dst_op.disp, SZ_B);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1662 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1663 *end_off = dst - (end_off+1);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1664 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1665 dst = cycles(dst, BUS);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1666 if (dst_op.mode == MODE_REG_DIRECT) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1667 dst = setcc_r(dst, cc, dst_op.base);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1668 } else {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1669 dst = setcc_rdisp8(dst, cc, dst_op.base, dst_op.disp);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1670 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1671 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1672 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1673 dst = m68k_save_result(inst, dst, opts);
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1674 return dst;
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1675 }
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	1676
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1677 uint8_t * translate_m68k_jmp(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	1678 {
132 0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1679 uint8_t * dest_addr, sec_reg;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1680 uint32_t m68k_addr;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1681 switch(inst->src.addr_mode)
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1682 {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1683 case MODE_AREG_INDIRECT:
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1684 dst = cycles(dst, BUS*2);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1685 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1686 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1687 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1688 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1689 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1690 dst = call(dst, (uint8_t *)m68k_native_addr);
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1691 dst = jmp_r(dst, SCRATCH1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1692 break;
132 0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1693 case MODE_AREG_INDEX_DISP8:
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1694 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1695 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1696 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1697 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1698 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1699 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1700 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1701 if (inst->src.params.regs.sec & 1) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1702 if (inst->src.params.regs.sec & 0x10) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1703 if (opts->aregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1704 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1705 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1706 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1707 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1708 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1709 if (opts->dregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1710 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1711 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1712 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1713 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1714 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1715 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1716 if (inst->src.params.regs.sec & 0x10) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1717 if (opts->aregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1718 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1719 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1720 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1721 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1722 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1723 if (opts->dregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1724 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1725 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1726 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1727 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1728 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1729 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1730 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1731 if (inst->src.params.regs.displacement) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1732 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1733 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1734 dst = call(dst, (uint8_t *)m68k_native_addr);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1735 dst = jmp_r(dst, SCRATCH1);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1736 break;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1737 case MODE_PC_DISPLACE:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1738 dst = cycles(dst, 10);
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1739 m68k_addr = inst->src.params.regs.displacement + inst->address + 2;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1740 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1741 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1742 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1743 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1744 //dummy address to be replaced later, make sure it generates a 4-byte displacement
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1745 dest_addr = dst + 256;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1746 }
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1747 dst = jmp(dst, dest_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1748 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1749 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1750 dst = call(dst, (uint8_t *)m68k_native_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1751 dst = jmp_r(dst, SCRATCH1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1752 }
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1753 break;
132 0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1754 case MODE_PC_INDEX_DISP8:
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1755 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1756 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1757 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1758 if (inst->src.params.regs.sec & 1) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1759 if (inst->src.params.regs.sec & 0x10) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1760 if (opts->aregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1761 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1762 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1763 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1764 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1765 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1766 if (opts->dregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1767 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1768 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1769 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1770 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1771 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1772 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1773 if (inst->src.params.regs.sec & 0x10) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1774 if (opts->aregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1775 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1776 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1777 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1778 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1779 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1780 if (opts->dregs[sec_reg] >= 0) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1781 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1782 } else {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1783 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1784 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1785 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1786 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1787 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1788 if (inst->src.params.regs.displacement) {
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1789 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1790 }
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1791 dst = call(dst, (uint8_t *)m68k_native_addr);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1792 dst = jmp_r(dst, SCRATCH1);
0969d8363a20 Support more address modes for jmp Mike Pavone <pavone@retrodev.com> parents: 129 diff changeset	1793 break;
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1794 case MODE_ABSOLUTE:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1795 case MODE_ABSOLUTE_SHORT:
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1796 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1797 m68k_addr = inst->src.params.immed;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1798 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1799 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1800 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1801 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1802 //dummy address to be replaced later, make sure it generates a 4-byte displacement
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1803 dest_addr = dst + 256;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1804 }
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1805 dst = jmp(dst, dest_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1806 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1807 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1808 dst = call(dst, (uint8_t *)m68k_native_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1809 dst = jmp_r(dst, SCRATCH1);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1810 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	1811 break;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1812 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	1813 m68k_disasm(inst, disasm_buf);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	1814 printf("%s\naddress mode %d not yet supported (jmp)\n", disasm_buf, inst->src.addr_mode);
104 a0fdaa134964 Use unsigned comparisons for address decoding, exit when we hit an unhandled addressing mode for jmp Mike Pavone <pavone@retrodev.com> parents: 102 diff changeset	1815 exit(1);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1816 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1817 return dst;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1818 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1819
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1820 uint8_t * translate_m68k_jsr(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1821 {
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1822 uint8_t * dest_addr, sec_reg;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1823 uint32_t after;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1824 uint32_t m68k_addr;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1825 switch(inst->src.addr_mode)
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1826 {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1827 case MODE_AREG_INDIRECT:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1828 dst = cycles(dst, BUS*2);
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	1829 dst = mov_ir(dst, inst->address + 2, SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1830 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1831 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1832 }
81 6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1833 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1834 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
6d231dbe75ab Add support for indexed modes as a source, some work on jmp and jsr with areg indirect mode Mike Pavone <pavone@retrodev.com> parents: 78 diff changeset	1835 dst = call(dst, (char *)m68k_write_long_highfirst);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1836 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1837 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1838 } else {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1839 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + 4 * inst->src.params.regs.pri, SCRATCH1, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1840 }
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1841 dst = call(dst, (uint8_t *)m68k_native_addr);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1842 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1843 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1844 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1845 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1846 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1847 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1848 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1849 break;
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1850 case MODE_AREG_INDEX_DISP8:
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1851 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	1852 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1853 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1854 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1855 }
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1856 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1857 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1858 dst = call(dst, (char *)m68k_write_long_highfirst);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1859 if (opts->aregs[inst->src.params.regs.pri] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1860 dst = mov_rr(dst, opts->aregs[inst->src.params.regs.pri], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1861 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1862 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1863 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1864 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1865 if (inst->src.params.regs.sec & 1) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1866 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1867 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1868 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1869 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1870 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1871 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1872 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1873 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1874 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1875 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1876 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1877 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1878 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1879 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1880 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1881 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1882 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1883 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1884 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1885 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1886 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1887 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1888 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1889 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1890 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1891 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1892 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1893 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1894 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1895 if (inst->src.params.regs.displacement) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1896 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1897 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1898 dst = call(dst, (uint8_t *)m68k_native_addr);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1899 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1900 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1901 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1902 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1903 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1904 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1905 }
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1906 break;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1907 case MODE_PC_DISPLACE:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1908 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1909 dst = cycles(dst, 10);
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	1910 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1911 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1912 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1913 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1914 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1915 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1916 dst = call(dst, (char *)m68k_write_long_highfirst);
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1917 m68k_addr = inst->src.params.regs.displacement + inst->address + 2;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1918 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1919 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1920 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1921 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1922 //dummy address to be replaced later, make sure it generates a 4-byte displacement
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1923 dest_addr = dst + 256;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1924 }
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1925 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1926 dst = call(dst, (char *)dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1927 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1928 dst = jmp(dst, dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1929 }
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1930 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1931 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	1932 dst = call(dst, (uint8_t *)m68k_native_addr);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1933 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1934 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1935 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1936 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1937 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1938 }
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1939 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1940 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1941 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1942 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1943 break;
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1944 case MODE_PC_INDEX_DISP8:
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1945 dst = cycles(dst, BUS*3);//TODO: CHeck that this is correct
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	1946 dst = mov_ir(dst, inst->address + 4, SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1947 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1948 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1949 }
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1950 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1951 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1952 dst = call(dst, (char *)m68k_write_long_highfirst);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1953 dst = mov_ir(dst, inst->address+2, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1954 sec_reg = (inst->src.params.regs.sec >> 1) & 0x7;
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1955 if (inst->src.params.regs.sec & 1) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1956 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1957 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1958 dst = add_rr(dst, opts->aregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1959 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1960 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1961 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1962 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1963 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1964 dst = add_rr(dst, opts->dregs[sec_reg], SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1965 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1966 dst = add_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1967 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1968 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1969 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1970 if (inst->src.params.regs.sec & 0x10) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1971 if (opts->aregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1972 dst = movsx_rr(dst, opts->aregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1973 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1974 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1975 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1976 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1977 if (opts->dregs[sec_reg] >= 0) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1978 dst = movsx_rr(dst, opts->dregs[sec_reg], SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1979 } else {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1980 dst = movsx_rdisp8r(dst, CONTEXT, offsetof(m68k_context, dregs) + sizeof(uint32_t)*sec_reg, SCRATCH2, SZ_W, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1981 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1982 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1983 dst = add_rr(dst, SCRATCH2, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1984 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1985 if (inst->src.params.regs.displacement) {
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1986 dst = add_ir(dst, inst->src.params.regs.displacement, SCRATCH1, SZ_D);
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1987 }
a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1988 dst = call(dst, (uint8_t *)m68k_native_addr);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1989 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1990 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1991 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1992 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1993 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1994 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	1995 }
110 a575808dd90b Implement more address modes for jsr Mike Pavone <pavone@retrodev.com> parents: 107 diff changeset	1996 break;
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1997 case MODE_ABSOLUTE:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1998 case MODE_ABSOLUTE_SHORT:
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	1999 //TODO: Add cycles in the right place relative to pushing the return address on the stack
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2000 dst = cycles(dst, inst->src.addr_mode == MODE_ABSOLUTE ? 12 : 10);
119 ee19ddadb398 Fix return address pushed to stack for jsr Mike Pavone <pavone@retrodev.com> parents: 118 diff changeset	2001 dst = mov_ir(dst, inst->address + (inst->src.addr_mode == MODE_ABSOLUTE ? 6 : 4), SCRATCH1, SZ_D);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2002 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2003 dst = push_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2004 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2005 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2006 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2007 dst = call(dst, (char *)m68k_write_long_highfirst);
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2008 m68k_addr = inst->src.params.immed;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2009 if ((m68k_addr & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2010 dest_addr = get_native_address(opts->native_code_map, m68k_addr);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2011 if (!dest_addr) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2012 opts->deferred = defer_address(opts->deferred, m68k_addr, dst + 1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2013 //dummy address to be replaced later, make sure it generates a 4-byte displacement
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2014 dest_addr = dst + 256;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2015 }
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2016 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2017 dst = call(dst, (char *)dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2018 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2019 dst = jmp(dst, dest_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2020 }
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2021 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2022 dst = mov_ir(dst, m68k_addr, SCRATCH1, SZ_D);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	2023 dst = call(dst, (uint8_t *)m68k_native_addr);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2024 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2025 dst = call_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2026 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2027 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2028 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2029 }
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2030 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2031 //would add_ir(dst, 8, RSP, SZ_Q) be faster here?
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2032 dst = pop_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2033 }
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2034 break;
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2035 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2036 m68k_disasm(inst, disasm_buf);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2037 printf("%s\naddress mode %d not yet supported (jsr)\n", disasm_buf, inst->src.addr_mode);
105 1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2038 exit(1);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2039 }
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	2040 return dst;
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	2041 }
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	2042
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2043 uint8_t * translate_m68k_rts(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2044 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2045 //TODO: Add cycles
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2046 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2047 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2048 dst = call(dst, (char *)m68k_read_long_scratch1);
155 94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2049 if (opts->flags & OPT_NATIVE_CALL_STACK) {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2050 dst = cmp_rdisp8r(dst, RSP, 8, SCRATCH1, SZ_D);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2051 dst = jcc(dst, CC_NZ, dst+3);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2052 dst = retn(dst);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2053 dst = jmp(dst, (char *)m68k_modified_ret_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2054 } else {
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2055 dst = call(dst, (uint8_t *)m68k_native_addr);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2056 dst = jmp_r(dst, SCRATCH1);
94a65fb4e1c7 Don't use the native call stack for M68K calls by default Mike Pavone <pavone@retrodev.com> parents: 154 diff changeset	2057 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2058 return dst;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2059 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2060
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2061 uint8_t * translate_m68k_dbcc(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2062 {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2063 //best case duration
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2064 dst = cycles(dst, 10);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2065 uint8_t * skip_loc = NULL;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2066 //TODO: Check if COND_TRUE technically valid here even though
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2067 //it's basically a slow NOP
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2068 if (inst->extra.cond != COND_FALSE) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2069 uint8_t cond = CC_NZ;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2070 switch (inst->extra.cond)
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2071 {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2072 case COND_HIGH:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2073 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2074 case COND_LOW_SAME:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2075 dst = mov_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2076 dst = or_rr(dst, FLAG_C, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2077 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2078 case COND_CARRY_CLR:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2079 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2080 case COND_CARRY_SET:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2081 dst = cmp_ir(dst, 0, FLAG_C, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2082 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2083 case COND_NOT_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2084 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2085 case COND_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2086 dst = cmp_ir(dst, 0, FLAG_Z, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2087 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2088 case COND_OVERF_CLR:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2089 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2090 case COND_OVERF_SET:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2091 dst = cmp_ir(dst, 0, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2092 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2093 case COND_PLUS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2094 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2095 case COND_MINUS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2096 dst = cmp_ir(dst, 0, FLAG_N, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2097 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2098 case COND_GREATER_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2099 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2100 case COND_LESS:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2101 dst = cmp_rr(dst, FLAG_N, FLAG_V, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2102 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2103 case COND_GREATER:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2104 cond = CC_Z;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2105 case COND_LESS_EQ:
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2106 dst = mov_rr(dst, FLAG_V, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2107 dst = xor_rr(dst, FLAG_N, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2108 dst = or_rr(dst, FLAG_Z, SCRATCH1, SZ_B);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2109 break;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2110 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2111 skip_loc = dst + 1;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2112 dst = jcc(dst, cond, dst + 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2113 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2114 if (opts->dregs[inst->dst.params.regs.pri] >= 0) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2115 dst = sub_ir(dst, 1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2116 dst = cmp_ir(dst, -1, opts->dregs[inst->dst.params.regs.pri], SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2117 } else {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2118 dst = sub_irdisp8(dst, 1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2119 dst = cmp_irdisp8(dst, -1, CONTEXT, offsetof(m68k_context, dregs) + 4 * inst->dst.params.regs.pri, SZ_W);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2120 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2121 uint8_t *loop_end_loc = dst+1;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2122 dst = jcc(dst, CC_Z, dst+2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2123 uint32_t after = inst->address + 2;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2124 uint8_t * dest_addr = get_native_address(opts->native_code_map, after + inst->src.params.immed);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2125 if (!dest_addr) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2126 opts->deferred = defer_address(opts->deferred, after + inst->src.params.immed, dst + 1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2127 //dummy address to be replaced later, make sure it generates a 4-byte displacement
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2128 dest_addr = dst + 256;
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2129 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2130 dst = jmp(dst, dest_addr);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2131 *loop_end_loc = dst - (loop_end_loc+1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2132 if (skip_loc) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2133 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2134 *skip_loc = dst - (skip_loc+1);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2135 dst = cycles(dst, 2);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2136 } else {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2137 dst = cycles(dst, 4);
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2138 }
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	2139 return dst;
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2140 }
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2141
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2142 uint8_t * translate_m68k_link(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2143 {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2144 int8_t reg = native_reg(&(inst->src), opts);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2145 //compensate for displacement word
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2146 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2147 dst = sub_ir(dst, 4, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2148 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2149 if (reg >= 0) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2150 dst = mov_rr(dst, reg, SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2151 } else {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2152 dst = mov_rdisp8r(dst, CONTEXT, reg_offset(&(inst->src)), SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2153 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2154 dst = call(dst, (char *)m68k_write_long_highfirst);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2155 if (reg >= 0) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2156 dst = mov_rr(dst, opts->aregs[7], reg, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2157 } else {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2158 dst = mov_rrdisp8(dst, opts->aregs[7], CONTEXT, reg_offset(&(inst->src)), SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2159 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2160 dst = add_ir(dst, inst->dst.params.immed, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2161 //prefetch
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2162 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2163 return dst;
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2164 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2165
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2166 typedef uint8_t * (shift_ir_t)(uint8_t out, uint8_t val, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2167 typedef uint8_t * (shift_irdisp8_t)(uint8_t out, uint8_t val, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2168 typedef uint8_t * (shift_clr_t)(uint8_t out, uint8_t dst, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2169 typedef uint8_t * (shift_clrdisp8_t)(uint8_t out, uint8_t dst_base, int8_t disp, uint8_t size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2170
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2171 uint8_t * translate_shift(uint8_t * dst, m68kinst * inst, x86_ea src_op, x86_ea dst_op, x86_68k_options * opts, shift_ir_t shift_ir, shift_irdisp8_t shift_irdisp8, shift_clr_t shift_clr, shift_clrdisp8_t shift_clrdisp8, shift_ir_t special, shift_irdisp8_t special_disp8)
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2172 {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2173 uint8_t * end_off = NULL;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2174 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2175 dst = cycles(dst, BUS);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2176 //Memory shift
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2177 dst = shift_ir(dst, 1, dst_op->base, SZ_W);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2178 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2179 dst = cycles(dst, inst->extra.size == OPSIZE_LONG ? 8 : 6);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2180 if (src_op->mode == MODE_IMMED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2181 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2182 dst = shift_ir(dst, src_op->disp, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2183 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2184 dst = shift_irdisp8(dst, src_op->disp, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2185 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2186 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2187 if (src_op->base != RCX) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2188 if (src_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2189 dst = mov_rr(dst, src_op->base, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2190 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2191 dst = mov_rdisp8r(dst, src_op->base, src_op->disp, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2192 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2193 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2194 dst = and_ir(dst, 63, RCX, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2195 //add 2 cycles for every bit shifted
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2196 dst = add_rr(dst, RCX, CYCLES, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2197 dst = add_rr(dst, RCX, CYCLES, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2198 //x86 shifts modulo 32 for operand sizes less than 64-bits
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2199 //but M68K shifts modulo 64, so we need to check for large shifts here
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2200 dst = cmp_ir(dst, 32, RCX, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2201 uint8_t * norm_shift_off = dst + 1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2202 dst = jcc(dst, CC_L, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2203 if (special) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2204 if (inst->extra.size == OPSIZE_LONG) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2205 uint8_t * neq_32_off = dst + 1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2206 dst = jcc(dst, CC_NZ, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2207
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2208 //set the carry bit to the lsb
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2209 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2210 dst = special(dst, 1, dst_op->base, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2211 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2212 dst = special_disp8(dst, 1, dst_op->base, dst_op->disp, SZ_D);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2213 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2214 dst = setcc_r(dst, CC_C, FLAG_C);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2215 dst = jmp(dst, dst+4);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2216 *neq_32_off = dst - (neq_32_off+1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2217 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2218 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2219 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2220 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2221 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2222 dst = xor_rr(dst, dst_op->base, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2223 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2224 dst = mov_irdisp8(dst, 0, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2225 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2226 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2227 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2228 dst = shift_ir(dst, 31, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2229 dst = shift_ir(dst, 1, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2230 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2231 dst = shift_irdisp8(dst, 31, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2232 dst = shift_irdisp8(dst, 1, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2233 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2234
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2235 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2236 end_off = dst+1;
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2237 dst = jmp(dst, dst+2);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2238 *norm_shift_off = dst - (norm_shift_off+1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2239 if (dst_op->mode == MODE_REG_DIRECT) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2240 dst = shift_clr(dst, dst_op->base, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2241 } else {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2242 dst = shift_clrdisp8(dst, dst_op->base, dst_op->disp, inst->extra.size);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2243 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2244
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2245 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2246
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2247 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2248 if (!special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2249 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2250 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2251 dst = setcc_r(dst, CC_C, FLAG_C);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2252 dst = setcc_r(dst, CC_Z, FLAG_Z);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2253 dst = setcc_r(dst, CC_S, FLAG_N);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2254 if (special && end_off) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2255 *end_off = dst - (end_off + 1);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2256 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2257 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2258 //set X flag to same as C flag
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2259 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2260 if (inst->src.addr_mode == MODE_UNUSED) {
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2261 dst = m68k_save_result(inst, dst, opts);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2262 }
66 7a22a0e6c004 Gamepad support Mike Pavone <pavone@retrodev.com> parents: 64 diff changeset	2263 return dst;
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2264 }
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2265
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2266 #define BIT_SUPERVISOR 5
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2267
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2268 uint8_t * translate_m68k(uint8_t * dst, m68kinst * inst, x86_68k_options * opts)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2269 {
122 0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2270 uint8_t * end_off, zero_off, norm_off;
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2271 uint8_t dst_reg;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2272 map_native_address(opts->native_code_map, inst->address, dst);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2273 dst = check_cycles_int(dst, inst->address);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2274 if (inst->op == M68K_MOVE) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2275 return translate_m68k_move(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2276 } else if(inst->op == M68K_LEA) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2277 return translate_m68k_lea(dst, inst, opts);
116 9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	2278 } else if(inst->op == M68K_PEA) {
9eaba47c429d Implement pea (untested). Mike Pavone <pavone@retrodev.com> parents: 113 diff changeset	2279 return translate_m68k_pea(dst, inst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2280 } else if(inst->op == M68K_BSR) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2281 return translate_m68k_bsr(dst, inst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2282 } else if(inst->op == M68K_BCC) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2283 return translate_m68k_bcc(dst, inst, opts);
53 44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	2284 } else if(inst->op == M68K_JMP) {
44e661913a51 Add preliminary support for JMP Mike Pavone <pavone@retrodev.com> parents: 52 diff changeset	2285 return translate_m68k_jmp(dst, inst, opts);
76 187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2286 } else if(inst->op == M68K_JSR) {
187c65f40a64 Implement JSR for some addressing modes Mike Pavone <pavone@retrodev.com> parents: 74 diff changeset	2287 return translate_m68k_jsr(dst, inst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2288 } else if(inst->op == M68K_RTS) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2289 return translate_m68k_rts(dst, inst, opts);
46 f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2290 } else if(inst->op == M68K_DBCC) {
f2aaaf36c875 Add support for dbcc instruction Mike Pavone <pavone@retrodev.com> parents: 19 diff changeset	2291 return translate_m68k_dbcc(dst, inst, opts);
52 f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	2292 } else if(inst->op == M68K_CLR) {
f02ba3808757 Implement CLR, minor refactor of register offset calculation in context struct Mike Pavone <pavone@retrodev.com> parents: 51 diff changeset	2293 return translate_m68k_clr(dst, inst, opts);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2294 } else if(inst->op == M68K_MOVEM) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2295 return translate_m68k_movem(dst, inst, opts);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2296 } else if(inst->op == M68K_LINK) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	2297 return translate_m68k_link(dst, inst, opts);
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	2298 } else if(inst->op == M68K_EXT) {
f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	2299 return translate_m68k_ext(dst, inst, opts);
112 e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	2300 } else if(inst->op == M68K_SCC) {
e3594572fb98 Implement scc (untested) Mike Pavone <pavone@retrodev.com> parents: 110 diff changeset	2301 return translate_m68k_scc(dst, inst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2302 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2303 x86_ea src_op, dst_op;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2304 if (inst->src.addr_mode != MODE_UNUSED) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2305 dst = translate_m68k_src(inst, &src_op, dst, opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2306 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2307 if (inst->dst.addr_mode != MODE_UNUSED) {
92 c3d034e076ee Fix some bugs in emulation of CLR Mike Pavone <pavone@retrodev.com> parents: 87 diff changeset	2308 dst = translate_m68k_dst(inst, &dst_op, dst, opts, 0);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2309 }
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2310 switch(inst->op)
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2311 {
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2312 //case M68K_ABCD:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2313 // break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2314 case M68K_ADD:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2315 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2316 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2317 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2318 dst = add_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2319 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2320 dst = add_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2321 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2322 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2323 dst = add_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2324 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2325 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2326 dst = add_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2327 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2328 dst = add_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2329 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2330 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2331 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2332 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2333 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2334 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2335 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2336 dst = m68k_save_result(inst, dst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2337 break;
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2338 case M68K_ADDX:
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2339 dst = cycles(dst, BUS);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2340 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2341 if (src_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2342 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2343 dst = adc_rr(dst, src_op.base, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2344 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2345 dst = adc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2346 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2347 } else if (src_op.mode == MODE_REG_DISPLACE8) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2348 dst = adc_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2349 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2350 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2351 dst = adc_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2352 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2353 dst = adc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2354 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2355 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2356 dst = setcc_r(dst, CC_C, FLAG_C);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2357 dst = setcc_r(dst, CC_Z, FLAG_Z);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2358 dst = setcc_r(dst, CC_S, FLAG_N);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2359 dst = setcc_r(dst, CC_O, FLAG_V);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2360 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2361 dst = m68k_save_result(inst, dst, opts);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2362 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2363 case M68K_AND:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2364 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2365 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2366 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2367 dst = and_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2368 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2369 dst = and_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2370 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2371 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2372 dst = and_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2373 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2374 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2375 dst = and_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2376 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2377 dst = and_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2378 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2379 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2380 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2381 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2382 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2383 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2384 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2385 break;
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2386 case M68K_ANDI_CCR:
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2387 case M68K_ANDI_SR:
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2388 dst = cycles(dst, 20);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2389 //TODO: If ANDI to SR, trap if not in supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2390 if (!(inst->src.params.immed & 0x1)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2391 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2392 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2393 if (!(inst->src.params.immed & 0x2)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2394 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2395 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2396 if (!(inst->src.params.immed & 0x4)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2397 dst = mov_ir(dst, 0, FLAG_Z, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2398 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2399 if (!(inst->src.params.immed & 0x8)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2400 dst = mov_ir(dst, 0, FLAG_N, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2401 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2402 if (!(inst->src.params.immed & 0x10)) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2403 dst = mov_irind(dst, 0, CONTEXT, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2404 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2405 if (inst->op == M68K_ANDI_SR) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2406 dst = and_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2407 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2408 //leave supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2409 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2410 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2411 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2412 }
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	2413 if (inst->src.params.immed & 0x700) {
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	2414 dst = call(dst, (uint8_t *)do_sync);
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	2415 }
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2416 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2417 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2418 case M68K_ASL:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2419 case M68K_LSL:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2420 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shl_ir, shl_irdisp8, shl_clr, shl_clrdisp8, shr_ir, shr_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2421 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2422 case M68K_ASR:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2423 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, sar_ir, sar_irdisp8, sar_clr, sar_clrdisp8, NULL, NULL);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2424 break;
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2425 case M68K_LSR:
51 937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2426 dst = translate_shift(dst, inst, &src_op, &dst_op, opts, shr_ir, shr_irdisp8, shr_clr, shr_clrdisp8, shl_ir, shl_irdisp8);
937b47c9b79b Implement shift instructions (asl, lsl, asr, lsr). Add flags to register printout. Fix minor bug in shift/rotate instruction decoding. Mike Pavone <pavone@retrodev.com> parents: 49 diff changeset	2427 break;
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2428 case M68K_BCHG:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2429 case M68K_BCLR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2430 case M68K_BSET:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2431 case M68K_BTST:
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2432 dst = cycles(dst, inst->extra.size == OPSIZE_BYTE ? 4 : 6);
67 534eb4976423 Fix BTST Mike Pavone <pavone@retrodev.com> parents: 66 diff changeset	2433 if (src_op.mode == MODE_IMMED) {
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2434 if (inst->extra.size == OPSIZE_BYTE) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2435 src_op.disp &= 0x7;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2436 }
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2437 if (inst->op == M68K_BTST) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2438 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2439 dst = bt_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2440 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2441 dst = bt_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2442 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2443 } else if (inst->op == M68K_BSET) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2444 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2445 dst = bts_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2446 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2447 dst = bts_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2448 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2449 } else if (inst->op == M68K_BCLR) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2450 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2451 dst = btr_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2452 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2453 dst = btr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2454 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2455 } else {
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2456 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2457 dst = btc_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2458 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2459 dst = btc_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2460 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2461 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2462 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2463 if (src_op.mode == MODE_REG_DISPLACE8) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2464 if (dst_op.base == SCRATCH1) {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2465 dst = push_r(dst, SCRATCH2);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2466 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_B);
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2467 src_op.base = SCRATCH2;
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2468 } else {
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2469 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2470 src_op.base = SCRATCH1;
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2471 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2472 }
154 4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	2473 if (dst_op.mode == MODE_REG_DISPLACE8) {
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	2474 if (src_op.base != SCRATCH1 && src_op.base != SCRATCH2) {
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	2475 if (src_op.mode == MODE_REG_DIRECT) {
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	2476 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_D);
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	2477 } else {
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	2478 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	2479 src_op.mode = MODE_REG_DIRECT;
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	2480 }
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	2481 src_op.base = SCRATCH1;
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	2482 }
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	2483 dst = and_ir(dst, 31, SCRATCH1, SZ_D);
4791c0204410 Small fix for bit instructions Mike Pavone <pavone@retrodev.com> parents: 152 diff changeset	2484 }
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2485 if (inst->op == M68K_BTST) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2486 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2487 dst = bt_rr(dst, src_op.base, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2488 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2489 dst = bt_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2490 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2491 } else if (inst->op == M68K_BSET) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2492 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2493 dst = bts_rr(dst, src_op.base, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2494 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2495 dst = bts_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2496 }
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2497 } else if (inst->op == M68K_BCLR) {
bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2498 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2499 dst = btr_rr(dst, src_op.base, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2500 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2501 dst = btr_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2502 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2503 } else {
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2504 if (dst_op.mode == MODE_REG_DIRECT) {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2505 dst = btc_rr(dst, src_op.base, dst_op.base, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2506 } else {
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2507 dst = btc_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
123 bd3858121ab0 Implement the rest of the bit instructions Mike Pavone <pavone@retrodev.com> parents: 122 diff changeset	2508 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2509 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2510 }
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2511 if (src_op.base == SCRATCH2) {
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2512 dst = pop_r(dst, SCRATCH2);
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2513 }
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2514 //x86 sets the carry flag to the value of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2515 //68K sets the zero flag to the complement of the bit tested
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2516 dst = setcc_r(dst, CC_NC, FLAG_Z);
128 fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2517 if (inst->op != M68K_BTST) {
fe598ffd85ce Cleanup bit instructions and fix bug in translate_m68k_move that caused incorrect results once translate_m68k_src was fixed Mike Pavone <pavone@retrodev.com> parents: 126 diff changeset	2518 dst = m68k_save_result(inst, dst, opts);
61 918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2519 }
918468c623e9 Add support for BTST instruction (untested), absolute addressing mode for instructions other than move (untested) and fix decoding of MOVEM. Mike Pavone <pavone@retrodev.com> parents: 59 diff changeset	2520 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2521 /*case M68K_CHK:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2522 break;*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2523 case M68K_CMP:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2524 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2525 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2526 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2527 dst = cmp_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2528 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2529 dst = cmp_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2530 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2531 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2532 dst = cmp_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2533 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2534 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2535 dst = cmp_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2536 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2537 dst = cmp_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2538 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2539 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2540 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2541 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2542 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2543 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2544 break;
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2545 case M68K_DIVS:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2546 case M68K_DIVU:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2547 //TODO: Trap on division by zero
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2548 dst = cycles(dst, inst->op == M68K_DIVS ? 158 : 140);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2549 dst = push_r(dst, RDX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2550 dst = push_r(dst, RAX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2551 if (dst_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2552 dst = mov_rr(dst, dst_op.base, RAX, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2553 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2554 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, RAX, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2555 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2556 if (src_op.mode == MODE_IMMED) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2557 dst = mov_ir(dst, src_op.disp, SCRATCH2, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2558 } else if (src_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2559 if (inst->op == M68K_DIVS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2560 dst = movsx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2561 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2562 dst = movzx_rr(dst, src_op.base, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2563 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2564 } else if (src_op.mode == MODE_REG_DISPLACE8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2565 if (inst->op == M68K_DIVS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2566 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2567 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2568 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2569 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2570 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2571 if (inst->op == M68K_DIVS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2572 dst = cdq(dst);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2573 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2574 dst = xor_rr(dst, RDX, RDX, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2575 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2576 if (inst->op == M68K_DIVS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2577 dst = idiv_r(dst, SCRATCH2, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2578 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2579 dst = div_r(dst, SCRATCH2, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2580 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2581 dst = cmp_ir(dst, 0x10000, RAX, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2582 norm_off = dst+1;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2583 dst = jcc(dst, CC_NC, dst+2);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2584 if (dst_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2585 dst = mov_rr(dst, RDX, dst_op.base, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2586 dst = shl_ir(dst, 16, dst_op.base, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2587 dst = mov_rr(dst, RAX, dst_op.base, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2588 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2589 dst = mov_rrdisp8(dst, RDX, dst_op.base, dst_op.disp, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2590 dst = shl_irdisp8(dst, 16, dst_op.base, dst_op.disp, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2591 dst = mov_rrdisp8(dst, RAX, dst_op.base, dst_op.disp, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2592 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2593 dst = pop_r(dst, RAX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2594 dst = pop_r(dst, RDX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2595 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2596 dst = cmp_ir(dst, 0, RAX, SZ_W);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2597 dst = setcc_r(dst, CC_Z, FLAG_Z);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2598 dst = setcc_r(dst, CC_S, FLAG_N);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2599 end_off = dst+1;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2600 dst = jmp(dst, dst+2);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2601 *norm_off = dst - (norm_off + 1);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2602 dst = pop_r(dst, RAX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2603 dst = pop_r(dst, RDX);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2604 dst = mov_ir(dst, 1, FLAG_V, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2605 *end_off = dst - (end_off + 1);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2606 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2607 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2608 case M68K_EOR:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2609 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2610 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2611 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2612 dst = xor_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2613 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2614 dst = xor_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2615 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2616 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2617 dst = xor_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2618 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2619 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2620 dst = xor_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2621 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2622 dst = xor_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2623 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2624 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2625 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2626 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2627 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2628 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2629 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2630 break;
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2631 /*case M68K_EORI_CCR:
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2632 case M68K_EORI_SR:*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2633 case M68K_EXG:
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2634 dst = cycles(dst, 6);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2635 if (dst_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2636 dst = mov_rr(dst, dst_op.base, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2637 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2638 dst = mov_rr(dst, src_op.base, dst_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2639 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2640 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2641 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2642 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2643 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2644 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2645 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2646 if (src_op.mode == MODE_REG_DIRECT) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2647 dst = mov_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2648 dst = mov_rr(dst, SCRATCH2, src_op.base, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2649 } else {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2650 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2651 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2652 dst = mov_rrdisp8(dst, SCRATCH2, src_op.base, src_op.disp, SZ_D);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2653 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2654 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2655 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2656 case M68K_ILLEGAL:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2657 dst = call(dst, (uint8_t *)m68k_save_context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2658 dst = mov_rr(dst, CONTEXT, RDI, SZ_Q);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2659 dst = call(dst, (uint8_t *)print_regs_exit);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	2660 break;
105 1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2661 case M68K_MOVE_FROM_SR:
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2662 //TODO: Trap if not in system mode
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2663 dst = call(dst, (uint8_t *)get_sr);
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2664 if (dst_op.mode == MODE_REG_DIRECT) {
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2665 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_W);
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2666 } else {
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2667 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_W);
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2668 }
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2669 dst = m68k_save_result(inst, dst, opts);
1a0fd122ca8f Implemented move from SR Mike Pavone <pavone@retrodev.com> parents: 104 diff changeset	2670 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2671 case M68K_MOVE_CCR:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2672 case M68K_MOVE_SR:
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2673 //TODO: Privilege check for MOVE to SR
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2674 if (src_op.mode == MODE_IMMED) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2675 dst = mov_ir(dst, src_op.disp & 0x1, FLAG_C, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2676 dst = mov_ir(dst, (src_op.disp >> 1) & 0x1, FLAG_V, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2677 dst = mov_ir(dst, (src_op.disp >> 2) & 0x1, FLAG_Z, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2678 dst = mov_ir(dst, (src_op.disp >> 3) & 0x1, FLAG_N, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2679 dst = mov_irind(dst, (src_op.disp >> 4) & 0x1, CONTEXT, SZ_B);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2680 if (inst->op == M68K_MOVE_SR) {
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2681 dst = mov_irdisp8(dst, (src_op.disp >> 8), CONTEXT, offsetof(m68k_context, status), SZ_B);
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2682 if (!((inst->src.params.immed >> 8) & (1 << BIT_SUPERVISOR))) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2683 //leave supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2684 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2685 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2686 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2687 }
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	2688 dst = call(dst, (uint8_t *)do_sync);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2689 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2690 dst = cycles(dst, 12);
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2691 } else {
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2692 if (src_op.base != SCRATCH1) {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2693 if (src_op.mode == MODE_REG_DIRECT) {
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2694 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_W);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2695 } else {
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2696 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W);
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2697 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2698 }
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2699 dst = call(dst, (uint8_t *)(inst->op == M68K_MOVE_SR ? set_sr : set_ccr));
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2700 dst = cycles(dst, 12);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2701
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2702 }
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	2703 break;
73 8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2704 case M68K_MOVE_USP:
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2705 dst = cycles(dst, BUS);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2706 //TODO: Trap if not in supervisor mode
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2707 //dst = bt_irdisp8(dst, BIT_SUPERVISOR, CONTEXT, offsetof(m68k_context, status), SZ_B);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2708 if (inst->src.addr_mode == MODE_UNUSED) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2709 if (dst_op.mode == MODE_REG_DIRECT) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2710 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, dst_op.base, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2711 } else {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2712 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2713 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2714 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2715 } else {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2716 if (src_op.mode == MODE_REG_DIRECT) {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2717 dst = mov_rrdisp8(dst, src_op.base, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2718 } else {
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2719 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2720 dst = mov_rrdisp8(dst, SCRATCH1, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2721 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2722 }
8da611e69b32 Implement a couple of supervisor instructions Mike Pavone <pavone@retrodev.com> parents: 71 diff changeset	2723 break;
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2724 //case M68K_MOVEP:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2725 case M68K_MULS:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2726 case M68K_MULU:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2727 dst = cycles(dst, 70); //TODO: Calculate the actual value based on the value of the <ea> parameter
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2728 if (src_op.mode == MODE_IMMED) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2729 //immediate value should already be sign extended to 32-bits
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2730 dst = mov_ir(dst, inst->op == M68K_MULU ? (src_op.disp & 0xFFFF) : src_op.disp, SCRATCH1, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2731 } else if (src_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2732 if (inst->op == M68K_MULS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2733 dst = movsx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2734 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2735 dst = movzx_rr(dst, src_op.base, SCRATCH1, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2736 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2737 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2738 if (inst->op == M68K_MULS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2739 dst = movsx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2740 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2741 dst = movzx_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2742 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2743 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2744 if (dst_op.mode == MODE_REG_DIRECT) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2745 dst_reg = dst_op.base;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2746 if (inst->op == M68K_MULS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2747 dst = movsx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2748 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2749 dst = movzx_rr(dst, dst_reg, dst_reg, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2750 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2751 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2752 dst_reg = SCRATCH2;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2753 if (inst->op == M68K_MULS) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2754 dst = movsx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2755 } else {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2756 dst = movzx_rdisp8r(dst, dst_op.base, dst_op.disp, SCRATCH2, SZ_W, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2757 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2758 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2759 dst = imul_rr(dst, SCRATCH1, dst_reg, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2760 if (dst_op.mode == MODE_REG_DISPLACE8) {
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2761 dst = mov_rrdisp8(dst, dst_reg, dst_op.base, dst_op.disp, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2762 }
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2763 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2764 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2765 dst = cmp_ir(dst, 0, dst_reg, SZ_D);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2766 dst = setcc_r(dst, CC_Z, FLAG_Z);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2767 dst = setcc_r(dst, CC_S, FLAG_N);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2768 break;
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	2769 //case M68K_NBCD:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2770 case M68K_NEG:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2771 if (dst_op.mode == MODE_REG_DIRECT) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2772 dst = neg_r(dst, dst_op.base, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2773 } else {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2774 dst = not_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2775 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2776 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2777 dst = setcc_r(dst, CC_Z, FLAG_Z);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2778 dst = setcc_r(dst, CC_S, FLAG_N);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2779 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2780 dst = m68k_save_result(inst, dst, opts);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2781 break;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2782 /*case M68K_NEGX:
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	2783 break;*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2784 case M68K_NOP:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2785 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2786 break;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2787 case M68K_NOT:
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2788 if (dst_op.mode == MODE_REG_DIRECT) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2789 dst = not_r(dst, dst_op.base, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2790 } else {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2791 dst = not_rdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2792 }
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2793 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2794 dst = setcc_r(dst, CC_Z, FLAG_Z);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2795 dst = setcc_r(dst, CC_S, FLAG_N);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2796 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2797 dst = m68k_save_result(inst, dst, opts);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	2798 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2799 case M68K_OR:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2800 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2801 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2802 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2803 dst = or_rr(dst, src_op.base, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2804 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2805 dst = or_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2806 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2807 } else if (src_op.mode == MODE_REG_DISPLACE8) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2808 dst = or_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2809 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2810 if (dst_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2811 dst = or_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2812 } else {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2813 dst = or_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2814 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2815 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2816 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2817 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2818 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2819 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2820 dst = m68k_save_result(inst, dst, opts);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	2821 break;
106 1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2822 case M68K_ORI_CCR:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2823 case M68K_ORI_SR:
106 1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2824 dst = cycles(dst, 20);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2825 //TODO: If ANDI to SR, trap if not in supervisor mode
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2826 if (inst->src.params.immed & 0x1) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2827 dst = mov_ir(dst, 1, FLAG_C, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2828 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2829 if (inst->src.params.immed & 0x2) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2830 dst = mov_ir(dst, 1, FLAG_V, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2831 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2832 if (inst->src.params.immed & 0x4) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2833 dst = mov_ir(dst, 1, FLAG_Z, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2834 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2835 if (inst->src.params.immed & 0x8) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2836 dst = mov_ir(dst, 1, FLAG_N, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2837 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2838 if (inst->src.params.immed & 0x10) {
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2839 dst = mov_irind(dst, 1, CONTEXT, SZ_B);
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2840 }
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	2841 if (inst->op == M68K_ORI_SR) {
106 1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2842 dst = or_irdisp8(dst, inst->src.params.immed >> 8, CONTEXT, offsetof(m68k_context, status), SZ_B);
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	2843 if (inst->src.params.immed & 0x700) {
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	2844 dst = call(dst, (uint8_t *)do_sync);
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	2845 }
106 1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2846 }
1eba2b9455f8 Implement ORI to CCR/SR Mike Pavone <pavone@retrodev.com> parents: 105 diff changeset	2847 break;
122 0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2848 /case M68K_RESET:/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2849 case M68K_ROL:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	2850 case M68K_ROR:
122 0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2851 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2852 if (inst->src.addr_mode == MODE_UNUSED) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2853 dst = cycles(dst, BUS);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2854 //Memory rotate
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2855 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2856 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2857 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2858 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2859 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2860 dst = setcc_r(dst, CC_C, FLAG_C);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2861 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2862 dst = setcc_r(dst, CC_Z, FLAG_Z);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2863 dst = setcc_r(dst, CC_S, FLAG_N);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2864 dst = m68k_save_result(inst, dst, opts);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2865 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2866 if (src_op.mode == MODE_IMMED) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2867 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2868 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2869 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2870 dst = rol_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2871 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2872 dst = ror_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2873 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2874 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2875 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2876 dst = rol_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2877 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2878 dst = ror_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2879 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2880 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2881 dst = setcc_r(dst, CC_C, FLAG_C);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2882 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2883 if (src_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2884 if (src_op.base != SCRATCH1) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2885 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2886 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2887 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2888 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2889 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2890 dst = and_ir(dst, 63, SCRATCH1, SZ_D);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2891 zero_off = dst+1;
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	2892 dst = jcc(dst, CC_Z, dst+2);
122 0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2893 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2894 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2895 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2896 norm_off = dst+1;
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2897 dst = jcc(dst, CC_L, dst+2);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2898 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2899 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2900 dst = rol_ir(dst, 31, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2901 dst = rol_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2902 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2903 dst = ror_ir(dst, 31, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2904 dst = ror_ir(dst, 1, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2905 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2906 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2907 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2908 dst = rol_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2909 dst = rol_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2910 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2911 dst = ror_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2912 dst = ror_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2913 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2914 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2915 dst = sub_ir(dst, 32, SCRATCH1, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2916 *norm_off = dst - (norm_off+1);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2917 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2918 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2919 dst = rol_clr(dst, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2920 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2921 dst = ror_clr(dst, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2922 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2923 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2924 if (inst->op == M68K_ROL) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2925 dst = rol_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2926 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2927 dst = ror_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2928 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2929 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2930 dst = setcc_r(dst, CC_C, FLAG_C);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2931 end_off = dst + 1;
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2932 dst = jmp(dst, dst+2);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2933 *zero_off = dst - (zero_off+1);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2934 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2935 *end_off = dst - (end_off+1);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2936 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2937 if (dst_op.mode == MODE_REG_DIRECT) {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2938 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2939 } else {
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2940 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2941 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2942 dst = setcc_r(dst, CC_Z, FLAG_Z);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2943 dst = setcc_r(dst, CC_S, FLAG_N);
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2944 }
0a6da6c7c463 Implemented ROL and ROR Mike Pavone <pavone@retrodev.com> parents: 121 diff changeset	2945 break;
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2946 case M68K_ROXL:
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2947 case M68K_ROXR:
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2948 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2949 if (inst->src.addr_mode == MODE_UNUSED) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2950 dst = cycles(dst, BUS);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2951 //Memory rotate
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2952 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2953 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	2954 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2955 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	2956 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2957 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2958 dst = setcc_r(dst, CC_C, FLAG_C);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2959 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2960 dst = setcc_r(dst, CC_Z, FLAG_Z);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2961 dst = setcc_r(dst, CC_S, FLAG_N);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2962 dst = m68k_save_result(inst, dst, opts);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2963 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2964 if (src_op.mode == MODE_IMMED) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2965 dst = cycles(dst, (inst->extra.size == OPSIZE_LONG ? 8 : 6) + src_op.disp*2);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2966 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2967 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2968 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	2969 dst = rcl_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2970 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	2971 dst = rcr_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2972 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2973 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2974 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	2975 dst = rcl_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2976 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	2977 dst = rcr_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2978 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2979 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2980 dst = setcc_r(dst, CC_C, FLAG_C);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2981 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2982 if (src_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2983 if (src_op.base != SCRATCH1) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2984 dst = mov_rr(dst, src_op.base, SCRATCH1, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2985 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2986 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2987 dst = mov_rdisp8r(dst, src_op.base, src_op.disp, SCRATCH1, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2988 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2989 dst = and_ir(dst, 63, SCRATCH1, SZ_D);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2990 zero_off = dst+1;
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	2991 dst = jcc(dst, CC_Z, dst+2);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2992 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2993 dst = add_rr(dst, SCRATCH1, CYCLES, SZ_D);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2994 dst = cmp_ir(dst, 32, SCRATCH1, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2995 norm_off = dst+1;
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2996 dst = jcc(dst, CC_L, dst+2);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2997 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2998 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	2999 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3000 dst = rcl_ir(dst, 31, dst_op.base, inst->extra.size);
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3001 dst = rcl_ir(dst, 1, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3002 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3003 dst = rcr_ir(dst, 31, dst_op.base, inst->extra.size);
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3004 dst = rcr_ir(dst, 1, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3005 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3006 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3007 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3008 dst = rcl_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3009 dst = rcl_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3010 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3011 dst = rcr_irdisp8(dst, 31, dst_op.base, dst_op.disp, inst->extra.size);
301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3012 dst = rcr_irdisp8(dst, 1, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3013 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3014 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3015 dst = sub_ir(dst, 32, SCRATCH1, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3016 *norm_off = dst - (norm_off+1);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3017 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3018 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3019 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3020 dst = rcl_clr(dst, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3021 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3022 dst = rcr_clr(dst, dst_op.base, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3023 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3024 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3025 if (inst->op == M68K_ROXL) {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3026 dst = rcl_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3027 } else {
157 301470eb870b Fix rotate instructions that use a register source. Fix ROXL/ROXR to actually use the appropriate x86 instruction. Mike Pavone <pavone@retrodev.com> parents: 156 diff changeset	3028 dst = rcr_clrdisp8(dst, dst_op.base, dst_op.disp, inst->extra.size);
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3029 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3030 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3031 dst = setcc_r(dst, CC_C, FLAG_C);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3032 end_off = dst + 1;
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3033 dst = jmp(dst, dst+2);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3034 *zero_off = dst - (zero_off+1);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3035 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3036 *end_off = dst - (end_off+1);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3037 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3038 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3039 dst = cmp_ir(dst, 0, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3040 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3041 dst = cmp_irdisp8(dst, 0, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3042 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3043 dst = setcc_r(dst, CC_Z, FLAG_Z);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3044 dst = setcc_r(dst, CC_S, FLAG_N);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3045 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3046 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3047 case M68K_RTE:
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3048 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3049 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3050 dst = push_r(dst, SCRATCH1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3051 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3052 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3053 dst = call(dst, (uint8_t *)m68k_read_word_scratch1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3054 dst = add_ir(dst, 2, opts->aregs[7], SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3055 dst = call(dst, (uint8_t *)set_sr);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3056 dst = pop_r(dst, SCRATCH1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3057 dst = bt_irdisp8(dst, 5, CONTEXT, offsetof(m68k_context, status), SZ_B);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3058 end_off = dst+1;
121 f848aad2abef Fix logic for switching between USP and SSP Mike Pavone <pavone@retrodev.com> parents: 119 diff changeset	3059 dst = jcc(dst, CC_C, dst+2);
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3060 dst = mov_rr(dst, opts->aregs[7], SCRATCH2, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3061 dst = mov_rdisp8r(dst, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, opts->aregs[7], SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3062 dst = mov_rrdisp8(dst, SCRATCH2, CONTEXT, offsetof(m68k_context, aregs) + sizeof(uint32_t) * 8, SZ_D);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3063 *end_off = dst - (end_off+1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3064 dst = call(dst, (uint8_t *)m68k_native_addr_and_sync);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3065 dst = jmp_r(dst, SCRATCH1);
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3066 break;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3067 /*case M68K_RTR:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3068 case M68K_SBCD:
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3069 case M68K_STOP:
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	3070 break;*/
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3071 case M68K_SUB:
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3072 dst = cycles(dst, BUS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3073 if (src_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3074 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3075 dst = sub_rr(dst, src_op.base, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3076 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3077 dst = sub_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3078 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3079 } else if (src_op.mode == MODE_REG_DISPLACE8) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3080 dst = sub_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3081 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3082 if (dst_op.mode == MODE_REG_DIRECT) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3083 dst = sub_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3084 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3085 dst = sub_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3086 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3087 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3088 dst = setcc_r(dst, CC_C, FLAG_C);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3089 dst = setcc_r(dst, CC_Z, FLAG_Z);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3090 dst = setcc_r(dst, CC_S, FLAG_N);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3091 dst = setcc_r(dst, CC_O, FLAG_V);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3092 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3093 dst = m68k_save_result(inst, dst, opts);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3094 break;
146 5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3095 case M68K_SUBX:
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3096 dst = cycles(dst, BUS);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3097 dst = bt_irdisp8(dst, 0, CONTEXT, 0, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3098 if (src_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3099 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3100 dst = sbb_rr(dst, src_op.base, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3101 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3102 dst = sbb_rrdisp8(dst, src_op.base, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3103 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3104 } else if (src_op.mode == MODE_REG_DISPLACE8) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3105 dst = sbb_rdisp8r(dst, src_op.base, src_op.disp, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3106 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3107 if (dst_op.mode == MODE_REG_DIRECT) {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3108 dst = sbb_ir(dst, src_op.disp, dst_op.base, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3109 } else {
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3110 dst = sbb_irdisp8(dst, src_op.disp, dst_op.base, dst_op.disp, inst->extra.size);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3111 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3112 }
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3113 dst = setcc_r(dst, CC_C, FLAG_C);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3114 dst = setcc_r(dst, CC_Z, FLAG_Z);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3115 dst = setcc_r(dst, CC_S, FLAG_N);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3116 dst = setcc_r(dst, CC_O, FLAG_V);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3117 dst = mov_rrind(dst, FLAG_C, CONTEXT, SZ_B);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3118 dst = m68k_save_result(inst, dst, opts);
5416a5c4628e Implement most of the "X" instructions Mike Pavone <pavone@retrodev.com> parents: 133 diff changeset	3119 break;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3120 case M68K_SWAP:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3121 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3122 if (src_op.mode == MODE_REG_DIRECT) {
129 691e4b147cea Fix swap Mike Pavone <pavone@retrodev.com> parents: 128 diff changeset	3123 dst = rol_ir(dst, 16, src_op.base, SZ_D);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3124 } else{
129 691e4b147cea Fix swap Mike Pavone <pavone@retrodev.com> parents: 128 diff changeset	3125 dst = rol_irdisp8(dst, 16, src_op.base, src_op.disp, SZ_D);
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3126 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3127 dst = mov_ir(dst, 0, FLAG_C, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3128 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3129 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3130 dst = mov_ir(dst, 0, FLAG_V, SZ_B);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3131 break;
152 79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	3132 //case M68K_TAS:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3133 case M68K_TRAP:
152 79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	3134 dst = mov_ir(dst, src_op.disp, SCRATCH2, SZ_D);
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	3135 dst = mov_ir(dst, inst->address, SCRATCH1, SZ_D);
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	3136 dst = jmp(dst, (uint8_t *)m68k_trap);
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	3137 break;
79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	3138 //case M68K_TRAPV:
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3139 case M68K_TST:
49 d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3140 dst = cycles(dst, BUS);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3141 if (src_op.mode == MODE_REG_DIRECT) {
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3142 dst = cmp_ir(dst, 0, src_op.base, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3143 } else { //M68000 doesn't support immedate operand for tst, so this must be MODE_REG_DISPLACE8
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3144 dst = cmp_irdisp8(dst, 0, src_op.base, src_op.disp, inst->extra.size);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3145 }
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3146 dst = setcc_r(dst, CC_C, FLAG_C);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3147 dst = setcc_r(dst, CC_Z, FLAG_Z);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3148 dst = setcc_r(dst, CC_S, FLAG_N);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3149 dst = setcc_r(dst, CC_O, FLAG_V);
d2e43d64e999 Add untested support for and, eor, or, swap, tst and nop instructions. Add call to m68k_save_result for add and sub so that they will properly save results for memory destinations Mike Pavone <pavone@retrodev.com> parents: 46 diff changeset	3150 break;
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3151 case M68K_UNLK:
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3152 dst = cycles(dst, BUS);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3153 if (dst_op.mode == MODE_REG_DIRECT) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3154 dst = mov_rr(dst, dst_op.base, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3155 } else {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3156 dst = mov_rdisp8r(dst, dst_op.base, dst_op.disp, opts->aregs[7], SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3157 }
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3158 dst = mov_rr(dst, opts->aregs[7], SCRATCH1, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3159 dst = call(dst, (uint8_t *)m68k_read_long_scratch1);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3160 if (dst_op.mode == MODE_REG_DIRECT) {
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3161 dst = mov_rr(dst, SCRATCH1, dst_op.base, SZ_D);
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3162 } else {
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	3163 dst = mov_rrdisp8(dst, SCRATCH1, dst_op.base, dst_op.disp, SZ_D);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3164 }
93 f63b0e58e2d5 Implement EXT, add some fixes to LINK/UNLK Mike Pavone <pavone@retrodev.com> parents: 92 diff changeset	3165 dst = add_ir(dst, 4, opts->aregs[7], SZ_D);
78 463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3166 break;
463641032588 Added untested support for LINK and UNLK Mike Pavone <pavone@retrodev.com> parents: 77 diff changeset	3167 /*case M68K_INVALID:
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	3168 break;*/
cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	3169 default:
151 6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3170 m68k_disasm(inst, disasm_buf);
6b593ea0ed90 Implement MULU/MULS and DIVU/DIVS Mike Pavone <pavone@retrodev.com> parents: 150 diff changeset	3171 printf("%X: %s\ninstruction %d not yet implemented\n", inst->address, disasm_buf, inst->op);
70 cebd0b5ac7f0 Make the translator bail out if it hits an instruction I haven't implemented yet Mike Pavone <pavone@retrodev.com> parents: 67 diff changeset	3172 exit(1);
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3173 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3174 return dst;
14 2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3175 }
2bdad0f52f42 x86 code gen, initial work on translator Mike Pavone <pavone@retrodev.com> parents: diff changeset	3176
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3177 uint8_t * translate_m68k_stream(uint32_t address, m68k_context * context)
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3178 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3179 m68kinst instbuf;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3180 x86_68k_options * opts = context->options;
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3181 uint8_t * dst = opts->cur_code;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3182 uint8_t * dst_end = opts->code_end;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3183 if(get_native_address(opts->native_code_map, address)) {
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3184 return dst;
6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3185 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3186 char disbuf[1024];
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3187 uint16_t encoded, next;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3188 if ((address & 0xFFFFFF) < 0x400000) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3189 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3190 } else if ((address & 0xFFFFFF) > 0xE00000) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3191 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3192 } else {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3193 printf("attempt to translate non-memory address: %X\n", address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3194 exit(1);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3195 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3196 do {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3197 do {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3198 if (dst_end-dst < 128) {
102 bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3199 if (dst_end-dst < 5) {
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3200 puts("out of code memory, not enough space for jmp to next chunk");
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3201 exit(1);
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3202 }
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3203 size_t size = 1024*1024;
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3204 opts->cur_code = alloc_code(&size);
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3205 opts->code_end = opts->cur_code + size;
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3206 jmp(dst, opts->cur_code);
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3207 dst = opts->cur_code;
bfaca67eeb78 allocate a new native code chunk when we run out of space Mike Pavone <pavone@retrodev.com> parents: 100 diff changeset	3208 dst_end = opts->code_end;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3209 }
159 c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode Mike Pavone <pavone@retrodev.com> parents: 158 diff changeset	3210 if (address >= 0x400000 && address < 0xE00000) {
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode Mike Pavone <pavone@retrodev.com> parents: 158 diff changeset	3211 dst = xor_rr(dst, RDI, RDI, SZ_D);
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode Mike Pavone <pavone@retrodev.com> parents: 158 diff changeset	3212 dst = call(dst, (uint8_t *)exit);
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode Mike Pavone <pavone@retrodev.com> parents: 158 diff changeset	3213 break;
c1530501c215 FIx movem when src is reg list and dst is not a areg predec mode Mike Pavone <pavone@retrodev.com> parents: 158 diff changeset	3214 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3215 next = m68k_decode(encoded, &instbuf, address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3216 address += (next-encoded)*2;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3217 encoded = next;
150 3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	3218 //m68k_disasm(&instbuf, disbuf);
3e68e517cc01 Do a sync when interrupt mask changes so we can recompute the next interrupt cycle. Also fix a bug in which the SR part of ORI to SR was not being performed. Mike Pavone <pavone@retrodev.com> parents: 146 diff changeset	3219 //printf("%X: %s\n", instbuf.address, disbuf);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3220 dst = translate_m68k(dst, &instbuf, opts);
152 79958b95526f Implement TRAP (untested) Mike Pavone <pavone@retrodev.com> parents: 151 diff changeset	3221 } while(instbuf.op != M68K_ILLEGAL && instbuf.op != M68K_TRAP && instbuf.op != M68K_RTS && instbuf.op != M68K_RTE && !(instbuf.op == M68K_BCC && instbuf.extra.cond == COND_TRUE) && instbuf.op != M68K_JMP);
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3222 process_deferred(opts);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3223 if (opts->deferred) {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3224 address = opts->deferred->address;
124 da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	3225 if ((address & 0xFFFFFF) < 0x400000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	3226 encoded = context->mem_pointers[0] + (address & 0xFFFFFF)/2;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	3227 } else if ((address & 0xFFFFFF) > 0xE00000) {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	3228 encoded = context->mem_pointers[1] + (address & 0xFFFF)/2;
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	3229 } else {
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	3230 printf("attempt to translate non-memory address: %X\n", address);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	3231 exit(1);
da95566514f3 Some fixes for translating code in located in RAM Mike Pavone <pavone@retrodev.com> parents: 123 diff changeset	3232 }
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3233 } else {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3234 encoded = NULL;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3235 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3236 } while(encoded != NULL);
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3237 opts->cur_code = dst;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3238 return dst;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3239 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3240
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3241 uint8_t * get_native_address_trans(m68k_context * context, uint32_t address)
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3242 {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3243 address &= 0xFFFFFF;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3244 uint8_t * ret = get_native_address(context->native_code_map, address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3245 if (!ret) {
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3246 translate_m68k_stream(address, context);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3247 ret = get_native_address(context->native_code_map, address);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3248 }
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3249 return ret;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3250 }
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3251
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3252 void start_68k_context(m68k_context * context, uint32_t address)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3253 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3254 uint8_t * addr = get_native_address(context->native_code_map, address);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3255 m68k_start_context(addr, context);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3256 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3257
19 4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	3258 void m68k_reset(m68k_context * context)
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	3259 {
71 f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3260 //TODO: Make this actually use the normal read functions
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3261 context->aregs[7] = context->mem_pointers[0][0] << 16 \| context->mem_pointers[0][1];
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3262 uint32_t address = context->mem_pointers[0][2] << 16 \| context->mem_pointers[0][3];
f80fa1776507 Implement more instructions and address modes Mike Pavone <pavone@retrodev.com> parents: 70 diff changeset	3263 start_68k_context(context, address);
19 4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	3264 }
4717146a7606 Initial support for M68k reset vector, rather than starting at an arbitrary address Mike Pavone <pavone@retrodev.com> parents: 18 diff changeset	3265
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3266 void init_x86_68k_opts(x86_68k_options * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3267 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3268 opts->flags = 0;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3269 for (int i = 0; i < 8; i++)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3270 opts->dregs[i] = opts->aregs[i] = -1;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3271 opts->dregs[0] = R10;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3272 opts->dregs[1] = R11;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3273 opts->dregs[2] = R12;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3274 opts->aregs[0] = R13;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3275 opts->aregs[1] = R14;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3276 opts->aregs[7] = R15;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3277 opts->native_code_map = malloc(sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3278 memset(opts->native_code_map, 0, sizeof(native_map_slot) * NATIVE_MAP_CHUNKS);
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3279 opts->deferred = NULL;
95 dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3280 size_t size = 1024 * 1024;
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3281 opts->cur_code = alloc_code(&size);
dd3c680c618c Initial work on allowing dynamic branches and code in RAM plus a small fix to effective address decoding Mike Pavone <pavone@retrodev.com> parents: 93 diff changeset	3282 opts->code_end = opts->cur_code + size;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3283 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3284
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3285 void init_68k_context(m68k_context * context, native_map_slot * native_code_map, void * opts)
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3286 {
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3287 memset(context, 0, sizeof(m68k_context));
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3288 context->native_code_map = native_code_map;
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3289 context->options = opts;
82 6331ddec228f Initial stab at interrupt support. Make native code offsets bigger so I don't have to worry about overflowing the offset. Implement neg and not (untested). Mike Pavone <pavone@retrodev.com> parents: 81 diff changeset	3290 context->int_cycle = 0xFFFFFFFF;
18 3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3291 }
3e7bfde7606e M68K to x86 translation works for a limited subset of instructions and addressing modes Mike Pavone <pavone@retrodev.com> parents: 14 diff changeset	3292

Mercurial > repos > blastem

annotate m68k_to_x86.c @ 161:6748022656b7