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annotate z80.cpu @ 1803:a851d36e24bb

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Zero offset should also impact output channels that a channel is panned away from
author Michael Pavone <pavone@retrodev.com>
date Tue, 26 Mar 2019 22:34:41 -0700
parents 1dc718581aac
children 338c78da3fff
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1 info
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
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2 prefix z80_
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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3 opcode_size 8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
4 extra_tables cb ed dded fded ddcb fdcb dd fd
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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5 body z80_run_op
1752
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
6 sync_cycle z80_sync_cycle
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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parents: 1750
diff changeset
7 interrupt z80_interrupt
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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8 include z80_util.c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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9 header z80.h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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10
1748
48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents: 1745
diff changeset
11 declare
48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents: 1745
diff changeset
12 void init_z80_opts(z80_options * options, memmap_chunk const * chunks, uint32_t num_chunks, memmap_chunk const * io_chunks, uint32_t num_io_chunks, uint32_t clock_divider, uint32_t io_address_mask);
48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one
Michael Pavone <pavone@retrodev.com>
parents: 1745
diff changeset
13 z80_context * init_z80_context(z80_options *options);
1752
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
14 void z80_run(z80_context *context, uint32_t target_cycle);
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
15 void z80_assert_reset(z80_context * context, uint32_t cycle);
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
16 void z80_clear_reset(z80_context * context, uint32_t cycle);
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
17 void z80_assert_busreq(z80_context * context, uint32_t cycle);
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
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18 void z80_clear_busreq(z80_context * context, uint32_t cycle);
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
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19 void z80_assert_nmi(z80_context *context, uint32_t cycle);
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
20 uint8_t z80_get_busack(z80_context * context, uint32_t cycle);
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
21 void z80_invalidate_code_range(z80_context *context, uint32_t start, uint32_t end);
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
22 void z80_adjust_cycles(z80_context * context, uint32_t deduction);
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
23 void z80_serialize(z80_context *context, serialize_buffer *buf);
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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parents: 1750
diff changeset
24 void z80_deserialize(deserialize_buffer *buf, void *vcontext);
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
25 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler);
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
26 void zremove_breakpoint(z80_context * context, uint16_t address);
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
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27 void z80_options_free(z80_options *opts);
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
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28 void z80_sync_cycle(z80_context *context, uint32_t target_cycle);
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d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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29
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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30 regs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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31 main 8 b c d e h l f a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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32 alt 8 b' c' d' e' h' l' f' a'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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33 i 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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34 r 8
1732
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
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35 rhigh 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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36 iff1 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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37 iff2 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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38 imode 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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39 sp 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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40 ix 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
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41 iy 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
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42 pc 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
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43 wz 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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44 nflag 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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45 last_flag_result 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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46 pvflag 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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47 chflags 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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48 zflag 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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49 scratch1 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
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50 scratch2 16
1752
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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parents: 1750
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51 busreq 8
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
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52 busack 8
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
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53 reset 8
1735
ca2336469397 Get new Z80 core running in CPM harness
Michael Pavone <pavone@retrodev.com>
parents: 1734
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54 io_map ptrmemmap_chunk
ca2336469397 Get new Z80 core running in CPM harness
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55 io_chunks 32
ca2336469397 Get new Z80 core running in CPM harness
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56 io_mask 32
1752
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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57 int_cycle 32
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
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58 int_end_cycle 32
1752
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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59 int_value 8
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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60 nmi_cycle 32
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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61 system ptrvoid
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
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62 fastread ptr8 64
33ec5df77fac Integration of new Z80 core is sort of working now
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63 fastwrite ptr8 64
1752
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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parents: 1750
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64 mem_pointers ptr8 4
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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65
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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66 flags
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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67 register f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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68 S 7 sign last_flag_result.7
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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69 Z 6 zero zflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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70 Y 5 bit-5 last_flag_result.5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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71 H 4 half-carry chflags.3
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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72 P 2 parity pvflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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73 V 2 overflow pvflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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74 X 3 bit-3 last_flag_result.3
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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75 N 1 none nflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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76 C 0 carry chflags.7
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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77
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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78
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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79 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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80 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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81 add 1 r r
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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82 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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83 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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84 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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85
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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86 z80_run_op
1766
1dc718581aac Fix Z80 interrupts in Gen/MD mode when using new core. Disable CPU debug log in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1764
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87 #printf "Z80: %X @ %d\n" pc cycles
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
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88 #printf "Z80: %X - A: %X, B: %X, C: %X D: %X, E: %X, H: %X, L: %X, SP: %X, IX: %X, IY: %X @ %d\n" pc a b c d e h l sp ix iy cycles
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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89 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
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90 dispatch scratch1
1752
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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91
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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92 z80_interrupt
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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93 cmp int_cycle cycles
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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94 if >=U
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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95
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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96 mov 0 iff1
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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97 mov 0 iff2
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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98 cycles 6
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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99 update_sync
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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100
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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101 switch imode
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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102 case 0
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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103 dispatch int_value
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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104
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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105 case 1
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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106 dispatch 0xFF
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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parents: 1750
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107
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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parents: 1750
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108 case 2
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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109 lsl i 8 pc
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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110 or int_value pc pc
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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111 #CD is call
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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112 dispatch 0xCD
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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113 end
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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114
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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115 else
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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116
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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117 cmp nmi_cycle cycles
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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118 if >=U
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119
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120 mov 0xFFFFFFFF nmi_cycle
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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121 mov 0 iff1
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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122 local pch 8
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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parents: 1750
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123 lsr pc 8 pch
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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124 meta high pch
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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parents: 1750
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125 meta low pc
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
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126 z80_push
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
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diff changeset
127 mov 0x66 pc
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
128 update_sync
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
129
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
130 end
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
131 end
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
132
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
133
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
134 11001011 cb_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
135 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
136 dispatch scratch1 cb
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
137
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
138 11011101 dd_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
139 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
140 dispatch scratch1 dd
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
141
1712
0a9a88b3d061 Fix ED prefix in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1706
diff changeset
142 11101101 ed_prefix
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
143 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
144 dispatch scratch1 ed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
145
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
146 11111101 fd_prefix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
147 z80_op_fetch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
148 dispatch scratch1 fd
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
149
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
150 dd 11001011 ddcb_prefix
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
151 z80_calc_index ix
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
152 cycles 2
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
153 mov pc scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
154 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
155 add 1 pc pc
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
156 dispatch scratch1 ddcb
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
157
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
158 fd 11001011 fdcb_prefix
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
159 z80_calc_index iy
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
160 cycles 2
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
161 mov pc scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
162 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
163 add 1 pc pc
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
164 dispatch scratch1 fdcb
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
165
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
166 z80_check_cond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
167 arg cond 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
168 local invert 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
169 switch cond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
170 case 0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
171 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
172 lnot zflag invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
173
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
174 case 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
175 meta istrue zflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
176
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
177 case 2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
178 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
179 not chflags invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
180 and 0x80 invert invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
181
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
182 case 3
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
183 meta istrue invert
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
184 and 0x80 chflags invert
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
185
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
186 case 4
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
187 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
188 lnot pvflag invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
189
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
190 case 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
191 meta istrue pvflag
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
192
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
193 case 6
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
194 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
195 not last_flag_result invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
196 and 0x80 invert invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
197
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
198 case 7
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
199 meta istrue invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
200 and 0x80 last_flag_result invert
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
201
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
202 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
203
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
204 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
205 lsl h 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
206 or l scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
207 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
208
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
209 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
210 lsl h 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
211 or l scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
212 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
213
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
214 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
215 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
216 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
217 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
218
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
219 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
220 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
221 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
222 mov scratch1 wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
223 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
224 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
225 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
226 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
227 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
228 or scratch1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
229
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
230 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
231 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
232 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
233 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
234 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
235 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
236 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
237 mov scratch1 high
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
238 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
239
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
240 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
241 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
242 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
243 mov scratch1 reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
244 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
245 mov pc scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
246 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
247 add 1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
248 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
249 or scratch1 reg reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
250
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
251 01RRR110 ld_from_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
252 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
253 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
254
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
255 01DDDSSS ld_from_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
256 mov main.S main.D
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
257
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
258 dd 01DDD100 ld_from_ixh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
259 invalid D 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
260 lsr ix 8 main.D
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
261
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
262 dd 01100SSS ld_to_ixh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
263 invalid S 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
264 local tmp 16
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
265 and 0xFF ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
266 lsl main.S 8 tmp
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
267 or tmp ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
268
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
269 dd 0110D10S ld_ixb_to_ixb
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
270
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
271 dd 01DDD101 ld_from_ixl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
272 invalid D 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
273 mov ix main.D
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
274
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
275 dd 01101SSS ld_to_ixl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
276 invalid S 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
277 and 0xFF00 ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
278 or main.S ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
279
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
280 dd 01100101 ld_ixl_to_ixh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
281 local tmp 16
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
282 lsl ix 8 tmp
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
283 and 0xFF ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
284 or tmp ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
285
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
286 dd 01101100 ld_ixh_to_ixl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
287 local tmp 16
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
288 lsr ix 8 tmp
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
289 and 0xFF00 ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
290 or tmp ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
291
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
292 fd 01DDD100 ld_from_iyh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
293 invalid D 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
294 lsr iy 8 main.D
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
295
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
296 fd 01100SSS ld_to_iyh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
297 invalid S 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
298 local tmp 16
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
299 and 0xFF iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
300 lsl main.S 8 tmp
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
301 or tmp iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
302
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
303 fd 0110D10S ld_iyb_to_iyb
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
304
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
305 fd 01DDD101 ld_from_iyl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
306 invalid D 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
307 mov iy main.D
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
308
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
309 fd 01101SSS ld_to_iyl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
310 invalid S 6
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
311 and 0xFF00 iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
312 or main.S iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
313
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
314 fd 01100101 ld_iyl_to_iyh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
315 local tmp 16
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
316 lsl iy 8 tmp
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
317 and 0xFF iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
318 or tmp iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
319
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
320 fd 01101100 ld_iyh_to_iyl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
321 local tmp 16
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
322 lsr iy 8 tmp
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
323 and 0xFF00 iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
324 or tmp iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
325
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
326 z80_calc_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
327 arg index 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
328 mov index wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
329 z80_fetch_immed
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
330 sext 16 scratch1 scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
331 add scratch1 wz wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
332
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
333 z80_fetch_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
334 arg index 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
335 z80_calc_index index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
336 mov wz scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
337 cycles 5
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
338 ocall read_8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
339
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
340 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
341 mov wz scratch2
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
342 ocall write_8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
343
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
344 dd 01RRR110 ld_from_ix
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
345 z80_fetch_index ix
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
346 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
347
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
348 fd 01RRR110 ld_from_iy
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
349 z80_fetch_index iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
350 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
351
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
352 00RRR110 ld_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
353 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
354 mov scratch1 main.R
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
355
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
356 dd 00100110 ld_immed_ixh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
357 z80_fetch_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
358 lsl scratch1 8 scratch1
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
359 and 0xFF ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
360 or scratch1 ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
361
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
362 dd 00101110 ld_immed_ixl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
363 z80_fetch_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
364 and 0xFF00 ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
365 or scratch1 ix ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
366
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
367 fd 00100110 ld_immed_iyh
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
368 z80_fetch_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
369 lsl scratch1 8 scratch1
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
370 and 0xFF iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
371 or scratch1 iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
372
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
373 fd 00101110 ld_immed_iyl
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
374 z80_fetch_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
375 and 0xFF00 iy iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
376 or scratch1 iy iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
377
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
378 01110RRR ld_to_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
379 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
380 z80_store_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
381
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
382 dd 01110RRR ld_to_ix
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
383 z80_calc_index ix
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
384 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
385 mov main.R scratch1
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
386 cycles 5
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
387 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
388
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
389 fd 01110RRR ld_to_iy
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
390 z80_calc_index iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
391 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
392 mov main.R scratch1
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
393 cycles 5
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
394 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
395
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
396 00110110 ld_to_hl_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
397 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
398 z80_store_hl
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
399
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
400 dd 00110110 ld_to_ixd_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
401 z80_calc_index ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
402 z80_fetch_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
403 cycles 2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
404 mov wz scratch2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
405 ocall write_8
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
406
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
407 fd 00110110 ld_to_iyd_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
408 z80_calc_index iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
409 z80_fetch_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
410 cycles 2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
411 mov wz scratch2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
412 ocall write_8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
413
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
414 00001010 ld_a_from_bc
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
415 lsl b 8 wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
416 or c wz wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
417 mov wz scratch1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
418 add 1 wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
419 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
420 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
421
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
422 00011010 ld_a_from_de
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
423 lsl d 8 wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
424 or e wz wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
425 mov wz scratch1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
426 add 1 wz wz
1724
9a74c2d05672 Fixed a few ld instructions in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1723
diff changeset
427 ocall read_8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
428 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
429
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
430 00111010 ld_a_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
431 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
432 mov wz scratch1
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
433 add 1 wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
434 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
435 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
436
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
437 00000010 ld_a_to_bc
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
438 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
439 lsl b 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
440 or c scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
441 mov a scratch1
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
442 add c 1 tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
443 lsl a 8 wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
444 or tmp wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
445 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
446
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
447 00010010 ld_a_to_de
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
448 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
449 lsl d 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
450 or e scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
451 mov a scratch1
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
452 add e 1 tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
453 lsl a 8 wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
454 or tmp wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
455 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
456
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
457 00110010 ld_a_to_immed
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
458 local tmp 16
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
459 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
460 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
461 mov a scratch1
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
462 add 1 wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
463 ocall write_8
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
464 and 0xFF wz wz
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
465 lsl a 8 tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
466 or tmp wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
467
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
468 ed 01000111 ld_i_a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
469 mov a i
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
470 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
471
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
472 ed 01001111 ld_r_a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
473 mov a r
1732
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
474 and 0x80 a rhigh
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
475 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
476
1732
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
477 ed 01011111 ld_a_r
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
478 cycles 1
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
479 and 0x7F r a
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
480 or rhigh a a
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
481 update_flags SZYH0XN0
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
482 mov iff2 pvflag
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
483
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
484 ed 01010111 ld_a_i
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
485 cycles 1
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
486 mov i a
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
487 update_flags SZYH0XN0
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
488 mov iff2 pvflag
3b286be82ea5 Implemented ld a,r and ld a,i in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1731
diff changeset
489
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
490 00000001 ld_bc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
491 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
492 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
493 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
494
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
495 00010001 ld_de_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
496 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
497 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
498 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
499
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
500 00100001 ld_hl_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
501 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
502 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
503 z80_fetch_immed_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
504
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
505 00110001 ld_sp_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
506 meta reg sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
507 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
508
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
509 dd 00100001 ld_ix_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
510 meta reg ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
511 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
512
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
513 fd 00100001 ld_iy_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
514 meta reg iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
515 z80_fetch_immed_to_reg16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
516
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
517 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
518 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
519 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
520 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
521 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
522 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
523 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
524 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
525 mov scratch1 high
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
526 add 1 wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
527
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
528 00101010 ld_hl_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
529 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
530 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
531 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
532
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
533 ed 01001011 ld_bc_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
534 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
535 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
536 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
537
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
538 ed 01011011 ld_de_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
539 meta low e
1724
9a74c2d05672 Fixed a few ld instructions in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1723
diff changeset
540 meta high d
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
541 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
542
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
543 ed 01101011 ld_hl_from_immed_slow
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
544 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
545 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
546 z80_fetch16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
547
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
548 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
549 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
550 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
551 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
552 mov scratch1 reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
553 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
554 mov wz scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
555 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
556 lsl scratch1 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
557 or scratch1 reg reg
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
558 add 1 wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
559
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
560 ed 01111011 ld_sp_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
561 meta reg sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
562 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
563
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
564 dd 00101010 ld_ix_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
565 meta reg ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
566 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
567
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
568 fd 00101010 ld_iy_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
569 meta reg iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
570 z80_fetch_reg16_from_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
571
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
572 00100010 ld_hl_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
573 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
574 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
575 mov l scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
576 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
577 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
578 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
579 mov h scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
580 ocall write_8
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
581 add 1 wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
582
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
583 dd 00100010 ld_ix_to_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
584 z80_fetch_immed16
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
585 mov wz scratch2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
586 mov ix scratch1
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
587 ocall write_8
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
588 add 1 wz wz
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
589 mov wz scratch2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
590 lsr ix 8 scratch1
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
591 ocall write_8
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
592 add 1 wz wz
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
593
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
594 fd 00100010 ld_iy_to_immed
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
595 z80_fetch_immed16
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
596 mov wz scratch2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
597 mov iy scratch1
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
598 ocall write_8
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
599 add 1 wz wz
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
600 mov wz scratch2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
601 lsr iy 8 scratch1
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
602 ocall write_8
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
603 add 1 wz wz
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
604
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
605 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
606 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
607 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
608 mov low scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
609 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
610 add 1 wz wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
611 mov high scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
612 mov wz scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
613 ocall write_8
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
614 add 1 wz wz
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
615
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
616 ed 01000011 ld_bc_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
617 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
618 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
619 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
620
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
621 ed 01010011 ld_de_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
622 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
623 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
624 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
625
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
626 ed 01100011 ld_hl_to_immed_slow
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
627 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
628 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
629 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
630
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
631 ed 01110011 ld_sp_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
632 meta low sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
633 local sph 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
634 lsr sp 8 sph
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
635 meta high sph
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
636 z80_regpair_to_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
637
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
638 11111001 ld_sp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
639 cycles 2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
640 lsl h 8 sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
641 or l sp sp
1730
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
642
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
643 dd 11111001 ld_sp_ix
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
644 cycles 2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
645 mov ix sp
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
646
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
647 fd 11111001 ld_sp_iy
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
648 cycles 2
71f7827ff30a Implemented remaining DD/FD prefixes for LD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1729
diff changeset
649 mov iy sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
650
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
651 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
652 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
653 sub 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
654 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
655 mov high scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
656 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
657 sub 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
658 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
659 mov low scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
660 ocall write_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
661
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
662 11000101 push_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
663 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
664 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
665 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
666
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
667 11010101 push_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
668 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
669 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
670 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
671
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
672 11100101 push_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
673 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
674 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
675 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
676
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
677 11110101 push_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
678 meta high a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
679 meta low f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
680 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
681
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
682 dd 11100101 push_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
683 local ixh 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
684 lsr ix 8 ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
685 meta high ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
686 meta low ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
687 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
688
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
689 fd 11100101 push_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
690 local iyh 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
691 lsr iy 8 iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
692 meta high iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
693 meta low iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
694 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
695
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
696 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
697 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
698 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
699 add 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
700 mov scratch1 low
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
701 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
702 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
703 add 1 sp sp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
704 mov scratch1 high
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
705
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
706 11000001 pop_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
707 meta high b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
708 meta low c
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
709 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
710
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
711 11010001 pop_de
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
712 meta high d
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
713 meta low e
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
714 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
715
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
716 11100001 pop_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
717 meta high h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
718 meta low l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
719 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
720
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
721 11110001 pop_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
722 meta high a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
723 meta low f
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
724 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
725
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
726 dd 11100001 pop_ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
727 local ixh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
728 meta high ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
729 meta low ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
730 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
731 lsl ixh 8 ixh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
732 or ixh ix ix
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
733
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
734 fd 11100001 pop_iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
735 local iyh 16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
736 meta high iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
737 meta low iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
738 z80_pop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
739 lsl iyh 8 iyh
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
740 or iyh iy iy
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
741
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
742 11101011 ex_de_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
743 xchg e l
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
744 xchg d h
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
745
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
746 00001000 ex_af_af
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
747 xchg a a'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
748 xchg f f'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
749
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
750 11011001 exx
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
751 xchg b b'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
752 xchg c c'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
753 xchg d d'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
754 xchg e e'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
755 xchg h h'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
756 xchg l l'
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
757
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
758 11100011 ex_sp_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
759 mov sp scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
760 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
761 xchg l scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
762 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
763 mov sp scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
764 ocall write_8
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
765 add 1 sp scratch1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
766 ocall read_8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
767 xchg h scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
768 cycles 2
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
769 add 1 sp scratch2
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
770 ocall write_8
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
771 lsl h 8 wz
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
772 or l wz wz
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
773
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
774 dd 11100011 ex_sp_ix
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
775 mov sp scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
776 ocall read_8
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
777 mov scratch1 wz
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
778 mov ix scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
779 cycles 1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
780 mov sp scratch2
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
781 ocall write_8
1731
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
782 add 1 sp scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
783 ocall read_8
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
784 lsl scratch1 8 scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
785 or scratch1 wz wz
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
786 lsr ix 8 scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
787 cycles 2
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
788 add 1 sp scratch2
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
789 ocall write_8
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
790 mov wz ix
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
791
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
792 fd 11100011 ex_sp_iy
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
793 mov sp scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
794 ocall read_8
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
795 mov scratch1 wz
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
796 mov iy scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
797 cycles 1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
798 mov sp scratch2
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
799 ocall write_8
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
800 add 1 sp scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
801 ocall read_8
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
802 lsl scratch1 8 scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
803 or scratch1 wz wz
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
804 lsr iy 8 scratch1
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
805 cycles 2
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
806 add 1 sp scratch2
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
807 ocall write_8
366b65d91614 Implemented DD/FD prefixes for EX in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1730
diff changeset
808 mov wz iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
809
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
810 10000RRR add_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
811 add a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
812 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
813
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
814 dd 10000100 add_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
815 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
816 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
817 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
818
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
819 dd 10000101 add_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
820 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
821 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
822 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
823
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
824 fd 10000100 add_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
825 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
826 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
827 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
828
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
829 fd 10000101 add_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
830 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
831 add a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
832 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
833
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
834 10000110 add_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
835 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
836 add a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
837 update_flags SZYHVXN0C
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
838
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
839 dd 10000110 add_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
840 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
841 add a scratch1 a
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
842 update_flags SZYHVXN0C
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
843
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
844 fd 10000110 add_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
845 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
846 add a scratch1 a
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
847 update_flags SZYHVXN0C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
848
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
849 11000110 add_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
850 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
851 add a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
852 update_flags SZYHVXN0C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
853
1715
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
854 z80_add16_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
855 arg src 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
856 lsl h 8 hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
857 or l hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
858 add 1 hlt wz
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
859 add src hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
860 update_flags YHXN0C
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
861 mov hlt l
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
862 lsr hlt 8 h
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
863 cycles 7
1715
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
864
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
865 00001001 add_hl_bc
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
866 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
867 local bcw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
868 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
869 lsl b 8 bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
870 or c bcw bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
871 z80_add16_hl bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
872
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
873 00011001 add_hl_de
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
874 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
875 local dew 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
876 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
877 lsl d 8 dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
878 or e dew dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
879 z80_add16_hl dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
880
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
881 00101001 add_hl_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
882 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
883 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
884 z80_add16_hl hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
885
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
886 00111001 add_hl_sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
887 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
888 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
889 z80_add16_hl sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
890
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
891 dd 00001001 add_ix_bc
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
892 lsl b 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
893 or c scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
894 add scratch1 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
895 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
896 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
897
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
898 dd 00011001 add_ix_de
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
899 lsl d 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
900 or e scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
901 add scratch1 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
902 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
903 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
904
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
905 dd 00101001 add_ix_ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
906 add ix ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
907 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
908 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
909
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
910 dd 00111001 add_ix_sp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
911 add sp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
912 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
913 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
914
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
915 fd 00001001 add_iy_bc
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
916 lsl b 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
917 or c scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
918 add scratch1 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
919 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
920 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
921
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
922 fd 00011001 add_iy_de
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
923 lsl d 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
924 or e scratch1 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
925 add scratch1 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
926 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
927 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
928
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
929 fd 00101001 add_iy_iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
930 add iy iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
931 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
932 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
933
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
934 fd 00111001 add_iy_sp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
935 add sp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
936 update_flags YHXN0C
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
937 cycles 7
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
938
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
939 10001RRR adc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
940 adc a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
941 update_flags SZYHVXN0C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
942
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
943 dd 10001100 adc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
944 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
945 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
946 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
947
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
948 dd 10001101 adc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
949 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
950 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
951 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
952
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
953 fd 10001100 adc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
954 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
955 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
956 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
957
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
958 fd 10001101 adc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
959 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
960 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
961 update_flags SZYHVXN0C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
962
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
963 10001110 adc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
964 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
965 adc a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
966 update_flags SZYHVXN0C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
967
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
968 dd 10001110 adc_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
969 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
970 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
971 update_flags SZYHVXN0C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
972
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
973 fd 10001110 adc_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
974 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
975 adc a scratch1 a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
976 update_flags SZYHVXN0C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
977
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
978 11001110 adc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
979 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
980 adc a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
981 update_flags SZYHVXN0C
1715
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
982
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
983 z80_adc16_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
984 arg src 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
985 lsl h 8 hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
986 or l hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
987 add 1 hlt wz
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
988 adc src hlt hlt
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
989 update_flags SZYHVXN0C
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
990 mov hlt l
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
991 lsr hlt 8 h
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
992 cycles 7
1715
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
993
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
994 ed 01001010 adc_hl_bc
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
995 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
996 local bcw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
997 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
998 lsl b 8 bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
999 or c bcw bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1000 z80_adc16_hl bcw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1001
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1002 ed 01011010 adc_hl_de
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1003 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1004 local dew 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1005 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1006 lsl d 8 dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1007 or e dew dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1008 z80_adc16_hl dew
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1009
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1010 ed 01101010 adc_hl_hl
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1011 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1012 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1013 z80_adc16_hl hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1014
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1015
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1016 ed 01111010 adc_hl_sp
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1017 local hlw 16
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1018 meta hlt hlw
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right
Michael Pavone <pavone@retrodev.com>
parents: 1714
diff changeset
1019 z80_adc16_hl sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1020
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1021 10010RRR sub_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1022 sub main.R a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1023 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1024
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1025 dd 10010100 sub_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1026 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1027 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1028 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1029
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1030 dd 10010101 sub_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1031 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1032 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1033 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1034
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1035 fd 10010100 sub_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1036 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1037 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1038 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1039
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1040 fd 10010101 sub_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1041 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1042 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1043 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1044
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1045 10010110 sub_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1046 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1047 sub scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1048 update_flags SZYHVXN1C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1049
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1050 dd 10010110 sub_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1051 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1052 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1053 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1054
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1055 fd 10010110 sub_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1056 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1057 sub scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1058 update_flags SZYHVXN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1059
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1060 11010110 sub_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1061 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1062 sub scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1063 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1064
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1065 10011RRR sbc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1066 sbc main.R a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1067 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1068
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1069 dd 10011100 sbc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1070 lsr ix 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1071 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1072 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1073
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1074 dd 10011101 sbc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1075 and ix 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1076 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1077 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1078
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1079 fd 10011100 sbc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1080 lsr iy 8 scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1081 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1082 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1083
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1084 fd 10011101 sbc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1085 and iy 0xFF scratch1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1086 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1087 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1088
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1089
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1090 10011110 sbc_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1091 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1092 sbc scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1093 update_flags SZYHVXN1C
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1094
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1095 dd 10011110 sbc_ixd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1096 z80_fetch_index ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1097 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1098 update_flags SZYHVXN1C
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1099
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1100 fd 10011110 sbc_iyd
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1101 z80_fetch_index iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1102 sbc scratch1 a a
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1103 update_flags SZYHVXN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1104
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1105 11011110 sbc_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1106 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1107 sbc scratch1 a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1108 update_flags SZYHVXN1C
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1109
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1110 z80_sbc16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1111 arg src 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1112 lsl h 8 hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1113 or l hlt hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1114 add 1 hlt wz
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1115 sbc src hlt hlt
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1116 update_flags SZYHVXN1C
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1117 mov hlt l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1118 lsr hlt 8 h
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
1119 cycles 7
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1120
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1121 ed 01000010 sbc_hl_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1122 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1123 local bcw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1124 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1125 lsl b 8 bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1126 or c bcw bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1127 z80_sbc16_hl bcw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1128
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1129 ed 01010010 sbc_hl_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1130 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1131 local dew 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1132 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1133 lsl d 8 dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1134 or e dew dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1135 z80_sbc16_hl dew
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1136
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1137 ed 01100010 sbc_hl_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1138 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1139 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1140 z80_sbc16_hl hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1141
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1142
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1143 ed 01110010 sbc_hl_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1144 local hlw 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1145 meta hlt hlw
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1146 z80_sbc16_hl sp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1147
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1148 10100RRR and_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1149 and a main.R a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1150 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1151
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1152 dd 10100100 and_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1153 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1154 and scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1155 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1156
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1157 dd 10100101 and_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1158 and ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1159 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1160
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1161 fd 10100100 and_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1162 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1163 and scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1164 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1165
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1166 fd 10100101 and_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1167 and iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1168 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1169
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1170 10100110 and_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1171 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1172 and a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1173 update_flags SZYH1PXN0C0
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1174
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1175 dd 10100110 and_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1176 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1177 and a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1178 update_flags SZYH1PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1179
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1180 fd 10100110 and_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1181 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1182 and a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1183 update_flags SZYH1PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1184
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1185 11100110 and_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1186 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1187 and a scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1188 update_flags SZYH1PXN0C0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1189
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1190 10110RRR or_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1191 or a main.R a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1192 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1193
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1194 dd 10110100 or_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1195 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1196 or scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1197 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1198
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1199 dd 10110101 or_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1200 or ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1201 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1202
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1203 fd 10110100 or_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1204 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1205 or scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1206 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1207
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1208 fd 10110101 or_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1209 or iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1210 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1211
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1212 10110110 or_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1213 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1214 or a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1215 update_flags SZYH0PXN0C0
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1216
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1217 dd 10110110 or_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1218 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1219 or a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1220 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1221
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1222 fd 10110110 or_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1223 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1224 or a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1225 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1226
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1227 11110110 or_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1228 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1229 or a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1230 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1231
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1232 10101RRR xor_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1233 xor a main.R a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1234 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1235
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1236 dd 10101100 xor_ixh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1237 lsr ix 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1238 xor scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1239 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1240
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1241 dd 10101101 xor_ixl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1242 xor ix a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1243 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1244
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1245 fd 10101100 xor_iyh
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1246 lsr iy 8 scratch1
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1247 xor scratch1 a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1248 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1249
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1250 fd 10101101 xor_iyl
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1251 xor iy a a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1252 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1253
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1254 10101110 xor_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1255 z80_fetch_hl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1256 xor a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1257 update_flags SZYH0PXN0C0
1720
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1258
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1259 dd 10101110 xor_ixd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1260 z80_fetch_index ix
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1261 xor a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1262 update_flags SZYH0PXN0C0
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1263
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1264 fd 10101110 xor_iyd
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1265 z80_fetch_index iy
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1266 xor a scratch1 a
1648c685083a Implemented DD/FD prefixes for and/or/xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1719
diff changeset
1267 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1268
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1269 11101110 xor_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1270 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1271 xor a scratch1 a
1714
e170a0f75c4f fix half-carry for or and xor in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1712
diff changeset
1272 update_flags SZYH0PXN0C0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1273
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1274 10111RRR cp_reg
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1275 mov main.R last_flag_result
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1276 cmp main.R a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1277 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1278
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1279 dd 10111100 cp_ixh
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1280 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1281 lsr ix 8 tmp
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1282 mov tmp last_flag_result
1743
a1663a83dcab Fixed cp ixh in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1742
diff changeset
1283 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1284 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1285
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1286 dd 10111101 cp_ixl
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1287 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1288 mov ix tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1289 mov ix last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1290 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1291 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1292
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1293 fd 10111100 cp_iyh
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1294 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1295 lsr iy 8 tmp
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1296 mov tmp last_flag_result
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1297 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1298 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1299
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1300 fd 10111101 cp_iyl
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1301 local tmp 8
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1302 mov iy tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1303 mov iy last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1304 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1305 update_flags SZHVN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1306
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1307 10111110 cp_hl
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1308 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1309 z80_fetch_hl
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1310 mov scratch1 tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1311 mov scratch1 last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1312 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1313 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1314
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1315 dd 10111110 cp_ixd
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1316 local tmp 8
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1317 z80_fetch_index ix
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1318 mov scratch1 tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1319 mov scratch1 last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1320 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1321 update_flags SZHVN1C
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1322
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1323 fd 10111110 cp_iyd
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1324 local tmp 8
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1325 z80_fetch_index iy
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1326 mov scratch1 tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1327 mov scratch1 last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1328 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1329 update_flags SZHVN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1330
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1331 11111110 cp_immed
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1332 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1333 z80_fetch_immed
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1334 mov scratch1 tmp
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1335 mov scratch1 last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1336 cmp tmp a
1719
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes
Michael Pavone <pavone@retrodev.com>
parents: 1718
diff changeset
1337 update_flags SZHVN1C
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1338
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1339 00RRR100 inc_reg
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1340 add 1 main.R main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1341 update_flags SZYHVXN0
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1342
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1343 dd 00100100 inc_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1344 add 0x100 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1345 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1346
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1347 dd 00101100 inc_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1348 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1349 mov ix tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1350 add 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1351 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1352 and 0xFF00 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1353 or tmp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1354
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1355 fd 00100100 inc_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1356 add 0x100 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1357 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1358
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1359 fd 00101100 inc_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1360 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1361 mov iy tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1362 add 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1363 update_flags SZYHVXN0
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1364 and 0xFF00 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1365 or tmp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1366
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1367 00110100 inc_hl
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1368 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1369 z80_fetch_hl
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1370 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1371 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1372 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1373 add 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1374 update_flags SZYHVXN0
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1375 mov tmp scratch1
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
1376 cycles 1
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1377 z80_store_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1378
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1379 dd 00110100 inc_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1380 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1381 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1382 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1383 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1384 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1385 add 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1386 update_flags SZYHVXN0
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1387 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1388 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1389 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1390
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1391 fd 00110100 inc_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1392 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1393 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1394 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1395 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1396 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1397 add 1 tmp tmp
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1398 update_flags SZYHVXN0
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1399 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1400 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1401 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1402
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1403 z80_inc_pair
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1404 arg high 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1405 arg low 8
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
1406 cycles 2
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1407 local word 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1408 lsl high 8 word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1409 or low word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1410 add 1 word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1411 mov word low
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1412 lsr word 8 high
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1413
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1414 00000011 inc_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1415 z80_inc_pair b c
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1416
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1417 00010011 inc_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1418 z80_inc_pair d e
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1419
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1420 00100011 inc16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1421 z80_inc_pair h l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1422
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1423 00110011 inc_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1424 add 1 sp sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1425
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1426 dd 00100011 inc_ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1427 add 1 ix ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1428
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1429 fd 00100011 inc_iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1430 add 1 iy iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1431
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1432 00RRR101 dec_reg
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1433 sub 1 main.R main.R
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1434 update_flags SZYHVXN1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1435
1718
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1436 dd 00100101 dec_ixh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1437 sub 0x100 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1438 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1439
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1440 dd 00101101 dec_ixl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1441 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1442 mov ix tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1443 sub 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1444 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1445 and 0xFF00 ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1446 or tmp ix ix
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1447
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1448 fd 00100101 dec_iyh
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1449 sub 0x100 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1450 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1451
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1452 fd 00101101 dec_iyl
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1453 local tmp 8
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1454 mov iy tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1455 sub 1 tmp tmp
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1456 update_flags SZYHVXN1
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1457 and 0xFF00 iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1458 or tmp iy iy
c7d18b8ec29a Implemented the rest of the dd/fd prefixes for the add/adc/sub/sbc/inc/dec instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1717
diff changeset
1459
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1460 00110101 dec_hl
1739
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1461 local tmp 8
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1462 z80_fetch_hl
1739
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1463 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1464 #or add some syntax to force a certain size on an operation so they are unnecessary
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1465 mov scratch1 tmp
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1466 sub 1 tmp tmp
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1467 update_flags SZYHVXN1
1739
435877da5837 Fixed flag calculation in dec (hl) in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1738
diff changeset
1468 mov tmp scratch1
1764
6cc2fa6a1955 A couple more instruction timing fixes in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1763
diff changeset
1469 cycles 1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1470 z80_store_hl
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1471
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1472 dd 00110101 dec_ixd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1473 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1474 z80_fetch_index ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1475 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1476 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1477 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1478 sub 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1479 update_flags SZYHVXN1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1480 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1481 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1482 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1483
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1484 fd 00110101 dec_iyd
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1485 local tmp 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1486 z80_fetch_index iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1487 #TODO: Either make DSL compiler smart enough to optimize these unnecessary moves out
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1488 #or add some syntax to force a certain size on an operation so they are unnecessary
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1489 mov scratch1 tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1490 sub 1 tmp tmp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1491 update_flags SZYHVXN1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1492 mov tmp scratch1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1493 cycles 1
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1494 z80_store_index
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1495
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1496 z80_dec_pair
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1497 arg high 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1498 arg low 8
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1499 local word 16
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1500 lsl high 8 word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1501 or low word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1502 sub 1 word word
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1503 mov word low
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1504 lsr word 8 high
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
1505 cycles 2
1717
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1506
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1507 00001011 dec_bc
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1508 z80_dec_pair b c
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1509
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1510 00011011 dec_de
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1511 z80_dec_pair d e
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1512
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1513 00101011 dec16_hl
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1514 z80_dec_pair h l
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1515
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1516 00111011 dec_sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1517 sub 1 sp sp
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1518
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1519 dd 00101011 dec_ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1520 sub 1 ix ix
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1521
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1522 fd 00101011 dec_iy
b11cfa655c61 Added implementations of a bunch of 16-bit arithmetic instructions and some DD/FD prefix instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1715
diff changeset
1523 sub 1 iy iy
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1524
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1525 00101111 cpl
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1526 not a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1527 update_flags YH1XN1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1528
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1529 ed 01DDD100 neg
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1530 neg a a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1531 update_flags SZYHVXN1C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1532
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1533 00111111 ccf
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1534 local tmp 8
1745
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1535 and 0x80 last_flag_result last_flag_result
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1536 and 0x7F a tmp
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1537 or tmp last_flag_result last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1538 and 0x80 chflags chflags
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1539 lsr chflags 4 tmp
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1540 or tmp chflags chflags
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1541 xor 0x80 chflags chflags
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1542 update_flags N0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1543
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1544 00110111 scf
1745
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1545 local tmp 8
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1546 and 0x80 last_flag_result last_flag_result
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1547 and 0x7F a tmp
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
1548 or tmp last_flag_result last_flag_result
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1549 update_flags H0N0C1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1550
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1551 00000000 nop
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1552
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1553 01110110 halt
1763
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1554 cmp nmi_cycle cycles
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1555 if >=U
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1556
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1557 else
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1558 cmp int_cycle cycles
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1559 if >=U
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1560
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1561 if iff1
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1562 else
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1563 sub 1 pc pc
1763
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1564 end
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1565
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1566 else
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1567 sub 1 pc pc
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1568 end
7e97d820b491 Fix implementation of halt in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1759
diff changeset
1569 end
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1570
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1571 11110011 di
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1572 mov 0 iff1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1573 mov 0 iff2
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1574 update_sync
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1575
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1576 11111011 ei
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1577 mov 1 iff1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1578 mov 1 iff2
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1579 update_sync
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1580 cmp int_cycle cycles
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1581 if >=U
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1582
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1583 add 1 cycles int_cycle
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1584
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1585 end
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1586
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1587 ed 01D00110 im0
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1588 mov 0 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1589
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1590 ed 01D10110 im1
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1591 mov 1 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1592
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1593 ed 01D11110 im2
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1594 mov 2 imode
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1595
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1596 ed 01D01110 im3
1752
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
1597 #some sources call this mode 0/1, but unclear
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
1598 #if the behavior is really different from im 0
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable
Michael Pavone <pavone@retrodev.com>
parents: 1750
diff changeset
1599 mov 0 imode
1725
89ee53a149ea Miscellaneous small fixes to new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1724
diff changeset
1600
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1601 11000011 jp
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1602 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1603 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1604
1726
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1605 11101001 jp_hl
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1606 lsl h 8 pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1607 or l pc pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1608
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1609 dd 11101001 jp_ix
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1610 mov ix pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1611
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1612 fd 11101001 jp_iy
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1613 mov iy pc
4f064b575e57 Implemented jp (hl), jp (ix) and jp (iy) in the new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1725
diff changeset
1614
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1615 11CCC010 jp_cc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1616 z80_check_cond C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1617 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1618 if istrue
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1619
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1620 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1621
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1622 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1623
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1624 00011000 jr
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1625 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1626 #TODO: determine if this updates wz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1627 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1628 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1629 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1630
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1631 001CC000 jr_cc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1632 z80_check_cond C
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1633 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1634
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1635 if istrue
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1636
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1637 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1638 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1639 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1640
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1641 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1642
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1643 00010000 djnz
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1644 cycles 1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1645 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1646 sub 1 b b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1647
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1648 if b
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1649
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1650 sext 16 scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1651 add scratch1 pc pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1652 cycles 5
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1653
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1654 end
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1655
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1656
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1657 11001101 call_uncond
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1658 z80_fetch_immed16
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1659 local pch 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1660 lsr pc 8 pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1661 meta high pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1662 meta low pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1663 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1664 mov wz pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1665
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1666 11CCC100 call_cond
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1667 local pch 8
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1668 z80_fetch_immed16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1669 z80_check_cond C
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1670
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1671 if istrue
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1672
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1673 lsr pc 8 pch
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1674 meta high pch
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1675 meta low pc
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1676 z80_push
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1677 mov wz pc
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1678
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1679 end
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1680
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1681 11TTT111 rst
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1682 local pch 8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1683 lsr pc 8 pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1684 meta high pch
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1685 meta low pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1686 z80_push
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1687 lsl T 3 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1688 mov scratch1 pc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1689
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1690 11001001 ret
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1691 local pch 16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1692 meta high pch
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1693 meta low pc
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1694 z80_pop
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1695 lsl pch 8 pch
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1696 or pch pc pc
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1697
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1698 ed 01001101 reti
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1699 local pch 16
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1700 cycles 1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1701 meta high pch
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1702 meta low pc
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1703 z80_pop
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1704 lsl pch 8 pch
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1705 or pch pc pc
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1706
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1707 ed 01NN1101 retn
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1708 mov iff2 iff1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1709 local pch 16
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1710 cycles 1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1711 meta high pch
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1712 meta low pc
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1713 z80_pop
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1714 lsl pch 8 pch
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1715 or pch pc pc
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1716
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1717 11CCC000 ret_cond
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1718 local pch 16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1719 cycles 1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1720 z80_check_cond C
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1721 if istrue
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1722
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1723 meta high pch
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1724 meta low pc
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1725 z80_pop
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1726 lsl pch 8 pch
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1727 or pch pc pc
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1728
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
1729 end
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1730
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1731 11011011 in_abs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1732 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1733 ocall io_read8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1734 mov scratch1 a
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1735
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1736 ed 01RRR000 in_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1737 lsl b 8 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1738 or c scratch1 scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1739 ocall io_read8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1740 mov scratch1 main.R
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1741
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1742 z80_ini_ind
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1743 arg change 16
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1744 local tmp 8
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1745 cycles 1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1746
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1747 lsl 8 b wz
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1748 or c wz wz
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1749 add change wz wz
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1750
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1751 sub 1 b b
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1752 update_flags SZYX
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1753
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1754 lsl b 8 scratch1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1755 or c scratch1 scratch1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1756 ocall io_read8
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1757
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1758 and 0x80 scratch1 nflag
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1759
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1760 mov wz tmp
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1761 add tmp scratch1 tmp
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1762 update_flags C
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1763
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1764 z80_store_hl
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1765
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1766 lsl h 8 scratch2
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1767 or l scratch2 scratch2
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1768 add change scratch2 scratch2
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1769 mov scratch2 l
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1770 lsr scratch2 8 h
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1771
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1772 and 7 tmp tmp
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1773 xor b tmp tmp
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1774 update_flags P
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1775 lsr chflags 4 tmp
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1776 or tmp chflags chflags
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1777
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1778 ed 10100010 ini
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1779 z80_ini_ind 1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1780
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1781 ed 10110010 inir
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1782 z80_ini_ind 1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1783 if zflag
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1784 else
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1785 sub 2 pc pc
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1786 cycles 5
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1787 end
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1788
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1789 ed 10101010 ind
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1790 z80_ini_ind -1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1791
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1792 ed 10111010 indr
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1793 z80_ini_ind -1
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1794 if zflag
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1795 else
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1796 sub 2 pc pc
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1797 cycles 5
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1798 end
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1799
1706
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1800 11010011 out_abs
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1801 z80_fetch_immed
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1802 mov scratch1 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1803 mov a scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1804 ocall io_write8
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1805
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1806 ed 01RRR001 out_bc
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1807 lsl b 8 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1808 or c scratch2 scratch2
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1809 mov main.R scratch1
c2324849a5e5 Initial checkin of new WIP Z80 core using CPU DSL
Michael Pavone <pavone@retrodev.com>
parents:
diff changeset
1810 ocall io_write8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1811
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1812 z80_outi_outd
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1813 arg change 16
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1814 local tmp 8
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1815 cycles 1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1816 z80_fetch_hl
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1817
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1818 and 0x80 scratch1 nflag
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1819
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1820 lsl h 8 scratch2
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1821 or l scratch2 scratch2
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1822 add change scratch2 scratch2
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1823 mov scratch2 l
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1824 lsr scratch2 8 h
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1825
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1826 add l scratch1 tmp
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1827 update_flags C
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1828 and 7 tmp tmp
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1829
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1830 lsl b 8 scratch2
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1831 or c scratch2 scratch2
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1832 ocall io_write8
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1833
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1834 sub 1 b b
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1835 update_flags SZYX
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1836
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1837 lsl 8 b wz
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1838 or c wz wz
1756
093e323dc683 Added in block instructions, fixed IO address calculation in out block instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1753
diff changeset
1839 add change wz wz
1753
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1840
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1841 xor b tmp tmp
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1842 update_flags P
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1843 lsr chflags 4 tmp
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1844 or tmp chflags chflags
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1845
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1846 ed 10100011 outi
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1847 z80_outi_outd 1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1848
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1849 ed 10110011 otir
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1850 z80_outi_outd 1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1851 if zflag
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1852 else
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1853 sub 2 pc pc
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1854 cycles 5
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1855 end
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1856
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1857 ed 10101011 outd
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1858 z80_outi_outd -1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1859
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1860 ed 10111011 otdr
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1861 z80_outi_outd -1
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1862 if zflag
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1863 else
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1864 sub 2 pc pc
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1865 cycles 5
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1866 end
33ec5df77fac Integration of new Z80 core is sort of working now
Michael Pavone <pavone@retrodev.com>
parents: 1752
diff changeset
1867
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1868 00000111 rlca
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1869 rol a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1870 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1871
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1872 00010111 rla
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1873 rlc a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1874 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1875
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1876 00001111 rrca
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1877 ror a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1878 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1879
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1880 00011111 rra
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1881 rrc a 1 a
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1882 update_flags YH0XN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1883
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1884 cb 00000RRR rlc
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1885 rol main.R 1 main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1886 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1887
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1888 cb 00000110 rlc_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1889 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1890 z80_fetch_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1891 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1892 rol tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1893 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1894 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1895 z80_store_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1896
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1897 z80_rlc_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1898 arg tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1899 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1900 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1901 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1902 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1903 rol tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1904 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1905 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1906 z80_store_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1907
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1908 ddcb 00000110 rlc_ixd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1909 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1910 z80_rlc_index tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1911
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1912 ddcb 00000RRR rlc_ixd_reg
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1913 z80_rlc_index main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1914
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1915 fdcb 00000110 rlc_iyd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1916 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1917 z80_rlc_index tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1918
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1919 fdcb 00000RRR rlc_iyd_reg
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1920 z80_rlc_index main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1921
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1922 cb 00010RRR rl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1923 rlc main.R 1 main.R
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1924 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1925
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1926 cb 00010110 rl_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1927 local tmp 8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1928 z80_fetch_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1929 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1930 rlc tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1931 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1932 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1933 z80_store_hl
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1934
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1935 z80_rl_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1936 arg tmp 8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1937 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1938 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1939 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1940 mov scratch1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1941 rlc tmp 1 tmp
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1942 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1943 mov tmp scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1944 z80_store_index
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1945
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1946 ddcb 00010110 rl_ixd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1947 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1948 z80_rl_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1949
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1950 fdcb 00010110 rl_iyd
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1951 local tmp 8
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1952 z80_rl_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1953
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1954
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1955 ddcb 00010RRR rl_ixd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1956 z80_rl_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1957
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1958 fdcb 00010RRR rl_iyd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1959 z80_rl_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1960
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1961 cb 00001RRR rrc
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1962 ror main.R 1 main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1963 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1964
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1965 cb 00001110 rrc_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1966 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1967 z80_fetch_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1968 mov scratch1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1969 ror tmp 1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1970 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1971 mov tmp scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1972 z80_store_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1973
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1974 z80_rrc_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1975 arg tmp 8
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1976 mov wz scratch1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1977 ocall read_8
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1978 cycles 1
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1979 mov scratch1 tmp
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1980 ror tmp 1 tmp
1721
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1981 update_flags SZYH0PXN0C
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1720
diff changeset
1982 mov tmp scratch1
1722
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1983 z80_store_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1984
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1985 ddcb 00001110 rrc_ixd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1986 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1987 z80_rrc_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1988
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1989 ddcb 00001RRR rrc_ixd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1990 z80_rrc_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1991
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1992 fdcb 00001110 rrc_iyd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1993 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1994 z80_rrc_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1995
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1996 fdcb 00001RRR rrc_iyd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1997 z80_rrc_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1998
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
1999 cb 00011RRR rr
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2000 rrc main.R 1 main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2001 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2002
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2003 cb 00011110 rr_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2004 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2005 z80_fetch_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2006 mov scratch1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2007 rrc tmp 1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2008 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2009 mov tmp scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2010 z80_store_hl
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2011
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2012 z80_rr_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2013 arg tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2014 mov wz scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2015 ocall read_8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2016 cycles 1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2017 mov scratch1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2018 rrc tmp 1 tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2019 update_flags SZYH0PXN0C
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2020 mov tmp scratch1
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2021 z80_store_index
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2022
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2023 ddcb 00011110 rr_ixd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2024 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2025 z80_rr_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2026
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2027 ddcb 00011RRR rr_ixd_reg
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2028 z80_rr_index main.R
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2029
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2030 fdcb 00011110 rr_iyd
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2031 local tmp 8
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2032 z80_rr_index tmp
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2033
ac809d044cab Implemented the rest of the rotate instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1721
diff changeset
2034 fdcb 00011RRR rr_iyd_reg
1723
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2035 z80_rr_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2036
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2037 cb 00100RRR sla
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2038 lsl main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2039 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2040
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2041 cb 00100110 sla_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2042 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2043 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2044 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2045 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2046 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2047 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2048 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2049
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2050 z80_sla_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2051 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2052 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2053 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2054 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2055 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2056 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2057 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2058 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2059 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2060
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2061 ddcb 00100110 sla_ixd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2062 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2063 z80_sla_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2064
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2065 ddcb 00100RRR sla_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2066 z80_sla_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2067
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2068 fdcb 00100110 sla_iyd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2069 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2070 z80_sla_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2071
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2072 fdcb 00100RRR sla_iyd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2073 z80_sla_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2074
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2075 cb 00101RRR sra
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2076 asr main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2077 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2078
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2079 cb 00101110 sra_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2080 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2081 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2082 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2083 asr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2084 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2085 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2086 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2087
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2088 z80_sra_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2089 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2090 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2091 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2092 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2093 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2094 asr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2095 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2096 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2097 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2098
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2099 ddcb 00101110 sra_ixd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2100 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2101 z80_sra_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2102
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2103 ddcb 00101RRR sra_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2104 z80_sra_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2105
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2106 fdcb 00101110 sra_iyd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2107 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2108 z80_sra_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2109
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2110 fdcb 00101RRR sra_iyd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2111 z80_sra_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2112
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2113 cb 00110RRR sll
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2114 lsl main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2115 update_flags SZ0YH0XN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2116 or 1 main.R main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2117 update_flags P
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2118
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2119 cb 00110110 sll_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2120 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2121 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2122 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2123 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2124 update_flags SZ0YH0XN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2125 or 1 tmp tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2126 update_flags P
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2127 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2128 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2129
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2130 z80_sll_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2131 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2132 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2133 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2134 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2135 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2136 lsl tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2137 update_flags SZ0YH0XN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2138 or 1 tmp tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2139 update_flags P
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2140 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2141 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2142
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2143 ddcb 00110110 sll_ixd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2144 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2145 z80_sll_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2146
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2147 ddcb 00110RRR sll_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2148 z80_sll_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2149
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2150 fdcb 00110110 sll_iyd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2151 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2152 z80_sll_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2153
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2154 fdcb 00110RRR sll_iyd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2155 z80_sll_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2156
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2157 cb 00111RRR srl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2158 lsr main.R 1 main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2159 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2160
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2161 cb 00111110 srl_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2162 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2163 z80_fetch_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2164 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2165 lsr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2166 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2167 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2168 z80_store_hl
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2169
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2170 z80_srl_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2171 arg tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2172 mov wz scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2173 ocall read_8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2174 cycles 1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2175 mov scratch1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2176 lsr tmp 1 tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2177 update_flags SZYH0PXN0C
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2178 mov tmp scratch1
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2179 z80_store_index
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2180
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2181 ddcb 00111110 srl_ixd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2182 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2183 z80_srl_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2184
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2185 ddcb 00111RRR srl_ixd_reg
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2186 z80_srl_index main.R
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2187
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2188 fdcb 00111110 srl_iyd
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2189 local tmp 8
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2190 z80_srl_index tmp
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2191
b757ebc59851 Implemented shift instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1722
diff changeset
2192 fdcb 00111RRR srl_iyd_reg
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2193 z80_srl_index main.R
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2194
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2195 cb 01BBBRRR bit_reg
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2196 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2197 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2198 mov main.R last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2199 and main.R tmp tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2200 update_flags SZH1PN0
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2201
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2202 cb 01BBB110 bit_hl
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2203 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2204 z80_fetch_hl
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
2205 cycles 1
1727
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2206 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2207 lsr wz 8 last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2208 and scratch1 tmp tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2209 update_flags SZH1PN0
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2210
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2211
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2212 ddcb 01BBBRRR bit_ixd
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2213 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2214 mov wz scratch1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2215 ocall read_8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2216 cycles 1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2217 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2218 lsr wz 8 last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2219 and scratch1 tmp tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2220 update_flags SZH1PN0
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2221
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2222 fdcb 01BBBRRR bit_iyd
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2223 local tmp 8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2224 mov wz scratch1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2225 ocall read_8
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2226 cycles 1
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2227 lsl 1 B tmp
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2228 lsr wz 8 last_flag_result
9ea0b4cc8f02 Implemented BIT instruction in new Z80 core and fixed a bunch of WZ register calculations
Michael Pavone <pavone@retrodev.com>
parents: 1726
diff changeset
2229 and scratch1 tmp tmp
1728
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2230 update_flags SZH1PN0
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2231
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2232 cb 10BBBRRR res_reg
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2233 local tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2234 lsl 1 B tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2235 not tmp tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2236 and main.R tmp main.R
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2237
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2238 cb 10BBB110 res_hl
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2239 z80_fetch_hl
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2240 cycles 1
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2241 local tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2242 lsl 1 B tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2243 not tmp tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2244 and scratch1 tmp scratch1
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2245 z80_store_hl
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2246
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2247 z80_res_index
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2248 arg bit 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2249 arg tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2250 lsl 1 bit tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2251 not tmp tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2252 mov wz scratch1
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2253 ocall read_8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2254 cycles 1
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2255 and scratch1 tmp tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2256 mov tmp scratch1
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2257 z80_store_index
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2258
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2259 ddcb 10BBB110 res_ixd
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2260 local tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2261 z80_res_index B tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2262
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2263 ddcb 10BBBRRR res_ixd_reg
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2264 z80_res_index B main.R
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2265
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2266 fdcb 10BBB110 res_iyd
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2267 local tmp 8
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2268 z80_res_index B tmp
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2269
b0e01e64d76d Implemented RES instruction in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1727
diff changeset
2270 fdcb 10BBBRRR res_iyd_reg
1729
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2271 z80_res_index B main.R
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2272
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2273 cb 11BBBRRR set_reg
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2274 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2275 lsl 1 B tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2276 or main.R tmp main.R
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2277
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2278 cb 11BBB110 set_hl
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2279 z80_fetch_hl
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2280 cycles 1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2281 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2282 lsl 1 B tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2283 or scratch1 tmp scratch1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2284 z80_store_hl
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2285
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2286 z80_set_index
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2287 arg bit 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2288 arg tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2289 lsl 1 bit tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2290 mov wz scratch1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2291 ocall read_8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2292 cycles 1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2293 or scratch1 tmp tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2294 mov tmp scratch1
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2295 z80_store_index
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2296
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2297 ddcb 11BBB110 set_ixd
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2298 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2299 z80_set_index B tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2300
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2301 ddcb 11BBBRRR set_ixd_reg
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2302 z80_set_index B main.R
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2303
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2304 fdcb 11BBB110 set_iyd
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2305 local tmp 8
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2306 z80_set_index B tmp
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2307
bd13d017f16f Implemented SET instruction in Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1728
diff changeset
2308 fdcb 11BBBRRR set_iyd_reg
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2309 z80_set_index B main.R
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2310
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2311 z80_fetch_mod_hl
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2312 local tmp 16
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2313 arg change 16
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2314 lsl h 8 tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2315 or l tmp tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2316 mov tmp scratch1
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2317 add change tmp tmp
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2318 mov tmp l
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2319 lsr tmp 8 h
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2320 ocall read_8
1759
6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1756
diff changeset
2321 cycles 2
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2322
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2323 z80_ldd_ldi
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2324 arg change 16
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2325 local tmp 16
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2326 local tmp8 8
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2327 z80_fetch_mod_hl change
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2328
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2329 add a scratch1 tmp8
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2330 update_flags H0XN0
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2331
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2332 and 0x2 tmp8 tmp8
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2333 lsl tmp8 4 tmp8
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2334 and 0x88 last_flag_result last_flag_result
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2335 or tmp8 last_flag_result last_flag_result
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2336
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2337 lsl d 8 tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2338 or e tmp tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2339 mov tmp scratch2
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2340 add change tmp tmp
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2341 mov tmp e
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2342 lsr tmp 8 d
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2343 ocall write_8
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2344
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2345 lsl b 8 tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2346 or c tmp tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2347 sub 1 tmp tmp
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2348
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2349 mov tmp c
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2350 lsr tmp 8 b
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2351 mov c pvflag
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2352 or b pvflag pvflag
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2353
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2354
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2355 ed 10100000 ldi
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2356 z80_ldd_ldi 1
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2357
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2358 ed 10101000 ldd
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2359 z80_ldd_ldi -1
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2360
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2361 ed 10110000 ldir
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2362 z80_ldd_ldi 1
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2363 if pvflag
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2364
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2365 add 1 pc wz
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2366 sub 2 pc pc
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2367 cycles 5
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2368
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2369 end
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2370
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2371 ed 10111000 lddr
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2372 z80_ldd_ldi -1
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2373 if pvflag
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2374
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2375 add 1 pc wz
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2376 sub 2 pc pc
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2377 cycles 5
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2378
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2379 end
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2380
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2381 z80_cpd_cpi
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2382 local tmp 16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2383 local tmp8 8
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2384 local hf 8
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2385 arg change 16
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2386
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2387 z80_fetch_mod_hl change
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2388 sub scratch1 a tmp8
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2389 update_flags SZHN1
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2390
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2391 lsr chflags 3 hf
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2392 and 1 hf hf
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2393
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2394 sub hf tmp8 tmp8
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2395 update_flags X
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2396
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2397 and 0x2 tmp8 tmp8
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2398 lsl tmp8 4 tmp8
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2399 and 0x88 last_flag_result last_flag_result
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2400 or tmp8 last_flag_result last_flag_result
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2401
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2402 lsl b 8 tmp
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2403 or c tmp tmp
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2404 sub 1 tmp tmp
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2405
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2406 mov tmp c
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2407 lsr tmp 8 b
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2408 mov c pvflag
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2409 or b pvflag pvflag
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2410
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2411 cycles 5
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2412
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2413 ed 10100001 cpi
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2414 z80_cpd_cpi 1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2415
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2416 ed 10101001 cpd
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2417 z80_cpd_cpi -1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2418
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2419 ed 10110001 cpir
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2420 z80_cpd_cpi 1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2421 if pvflag
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2422
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2423 if zflag
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2424
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2425 else
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2426
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2427 add 1 pc wz
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2428 sub 2 pc pc
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2429 cycles 5
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2430
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2431 end
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2432 end
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2433
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2434 ed 10111001 cpdr
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2435 z80_cpd_cpi -1
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2436 if pvflag
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2437
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2438 if zflag
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2439
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2440 else
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2441
1736
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2442 add 1 pc wz
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2443 sub 2 pc pc
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2444 cycles 5
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2445
06c2438c7641 Implemented conditional call/ret, cpi/cpd/cpir/cpdr and fixed ldir/lddr in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1735
diff changeset
2446 end
1742
6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1741
diff changeset
2447 end
1734
88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1733
diff changeset
2448
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2449 00100111 daa
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2450 local diff 8
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2451 local tmp 8
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2452 local low 8
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2453 and 0xF a low
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2454 and 0x8 chflags tmp
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2455 if tmp
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2456
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2457 mov 6 diff
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2458
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2459 else
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2460
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2461 cmp 0xA low
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2462 if >=U
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2463 mov 6 diff
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2464 else
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2465 mov 0 diff
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2466 end
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2467
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2468 end
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2469
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2470 and 0x80 chflags tmp
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2471 if tmp
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2472
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2473 or 0x60 diff diff
1745
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
2474 update_flags C1
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2475
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2476 else
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2477
1745
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
2478 cmp 0x9A a
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2479 if >=U
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2480 or 0x60 diff diff
1745
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
2481 update_flags C1
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
2482 else
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
2483 update_flags C0
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2484 end
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2485 end
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2486
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2487 if nflag
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2488
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2489 sub diff a a
1745
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
2490 update_flags SZYHPX
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2491
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2492 else
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2493
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2494 add diff a a
1745
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1743
diff changeset
2495 update_flags SZYHPX
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2496
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2497 end
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2498
1740
28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents: 1739
diff changeset
2499 dd OOOOOOOO dd_normal
28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents: 1739
diff changeset
2500 dispatch O
1738
d6157b7eb20c Implemented DAA in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1736
diff changeset
2501
1740
28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents: 1739
diff changeset
2502 fd OOOOOOOO fd_normal
28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL
Michael Pavone <pavone@retrodev.com>
parents: 1739
diff changeset
2503 dispatch O
1741
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2504
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2505 ed 01101111 rld
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2506 local tmp 8
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2507 local tmp2 8
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2508 z80_fetch_hl
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2509 cycles 4
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2510
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2511 lsr scratch1 4 tmp
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2512
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2513 lsl scratch1 4 scratch1
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2514
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2515 and 0xF a tmp2
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2516 or tmp2 scratch1 scratch1
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2517
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2518 and 0xF0 a a
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2519 or tmp a a
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2520 update_flags SZYH0XPN0
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2521 z80_store_hl
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2522
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2523 ed 01100111 rrd
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2524 local tmp 8
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2525 local tmp2 8
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2526 z80_fetch_hl
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2527 cycles 4
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2528
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2529 and 0xF scratch1 tmp
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2530 lsr scratch1 4 scratch1
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2531
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2532 lsl a 4 tmp2
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2533 or tmp2 scratch1 scratch1
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2534
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2535 and 0xF0 a a
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2536 or tmp a a
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2537 update_flags SZYH0XPN0
3dbfb4524ad2 Implemented RLD/RRD in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1740
diff changeset
2538 z80_store_hl
1733
1f0a86f5e055 Implemented LDI in new Z80 core
Michael Pavone <pavone@retrodev.com>
parents: 1732
diff changeset
2539