repos/blastem: cpu_dsl.py annotate

annotate cpu_dsl.py @ 1968:c16dabdb0aad

megawifi: use util module socket functions for WIN32 compatibility

author	doragasu <doragasu@hotmail.com>
date	Fri, 08 May 2020 00:24:25 -0700
parents	1dae90605199
children	7d4df6b74263

rev	line source
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1 #!/usr/bin/env python3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	2
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	3
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	4 class Block:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	5 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	6 pass
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	7
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	8 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	9 if parts[0] == 'switch':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	10 o = Switch(self, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	11 self.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	12 return o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	13 elif parts[0] == 'if':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	14 o = If(self, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	15 self.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	16 return o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	17 elif parts[0] == 'end':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	18 raise Exception('end is only allowed inside a switch or if block')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	19 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	20 self.addOp(NormalOp(parts))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	21 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	22
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	23 def processOps(self, prog, fieldVals, output, otype, oplist):
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	24 for i in range(0, len(oplist)):
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	25 if i + 1 < len(oplist) and oplist[i+1].op == 'update_flags':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	26 flagUpdates, _ = prog.flags.parseFlagUpdate(oplist[i+1].params[0])
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	27 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	28 flagUpdates = None
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	29 oplist[i].generate(prog, self, fieldVals, output, otype, flagUpdates)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	30
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	31 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	32 return None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	33
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	34 class ChildBlock(Block):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	35 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	36 if parts[0] == 'end':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	37 return self.parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	38 return super().processLine(parts)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	39
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	40 #Represents an instruction of the emulated CPU
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	41 class Instruction(Block):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	42 def __init__(self, value, fields, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	43 self.value = value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	44 self.fields = fields
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	45 self.name = name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	46 self.implementation = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	47 self.locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	48 self.regValues = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	49 self.varyingBits = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	50 self.invalidFieldValues = {}
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	51 self.invalidCombos = []
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	52 self.newLocals = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	53 for field in fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	54 self.varyingBits += fields[field][1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	55
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	56 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	57 if op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	58 name = op.params[0]
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	59 size = int(op.params[1])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	60 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	61 elif op.op == 'invalid':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	62 if len(op.params) < 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	63 name = op.params[0]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	64 value = int(op.params[1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	65 self.invalidFieldValues.setdefault(name, set()).add(value)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	66 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	67 vmap = {}
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	68 for i in range(0, len(op.params), 2):
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	69 name = op.params[i]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	70 value = int(op.params[i+1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	71 vmap[name] = value
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	72 self.invalidCombos.append(vmap)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	73 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	74 self.implementation.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	75
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	76 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	77 if name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	78 return name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	79 return None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	80
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	81 def addLocal(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	82 self.locals[name] = size
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	83 self.newLocals.append(name)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	84
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	85 def localSize(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	86 return self.locals.get(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	87
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	88 def __lt__(self, other):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	89 if isinstance(other, Instruction):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	90 if self.varyingBits != other.varyingBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	91 return self.varyingBits < other.varyingBits
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	92 return self.value < other.value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	93 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	94 return NotImplemented
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	95
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	96 def allValues(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	97 values = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	98 for i in range(0, 1 << self.varyingBits):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	99 iword = self.value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	100 doIt = True
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	101 combos = []
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	102 for combo in self.invalidCombos:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	103 combos.append(dict(combo))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	104 for field in self.fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	105 shift,bits = self.fields[field]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	106 val = i & ((1 << bits) - 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	107 if field in self.invalidFieldValues and val in self.invalidFieldValues[field]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	108 doIt = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	109 break
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	110 nextcombos = []
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	111 for combo in combos:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	112 if field in combo:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	113 if combo[field] == val:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	114 del combo[field]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	115 if not combo:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	116 doIt = False
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	117 break
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	118 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	119 continue
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	120 nextcombos.append(combo)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	121 combos = nextcombos
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	122 if not doIt:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	123 break
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	124 i >>= bits
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	125 iword \|= val << shift
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	126 if doIt:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	127 values.append(iword)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	128 return values
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	129
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	130 def getFieldVals(self, value):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	131 fieldVals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	132 fieldBits = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	133 for field in self.fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	134 shift,bits = self.fields[field]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	135 val = (value >> shift) & ((1 << bits) - 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	136 fieldVals[field] = val
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	137 fieldBits[field] = bits
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	138 return (fieldVals, fieldBits)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	139
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	140 def generateName(self, value):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	141 fieldVals,fieldBits = self.getFieldVals(value)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	142 names = list(fieldVals.keys())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	143 names.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	144 funName = self.name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	145 for name in names:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	146 funName += '_{0}_{1:0>{2}}'.format(name, bin(fieldVals[name])[2:], fieldBits[name])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	147 return funName
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	148
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	149 def generateBody(self, value, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	150 output = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	151 prog.meta = {}
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	152 prog.pushScope(self)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	153 self.regValues = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	154 for var in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	155 output.append('\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	156 self.newLocals = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	157 fieldVals,_ = self.getFieldVals(value)
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	158 self.processOps(prog, fieldVals, output, otype, self.implementation)
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	159
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	160 if prog.dispatch == 'call':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	161 begin = '\nvoid ' + self.generateName(value) + '(' + prog.context_type + ' *context, uint32_t target_cycle)\n{'
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	162 elif prog.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	163 begin = '\n' + self.generateName(value) + ': {'
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	164 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	165 raise Exception('Unsupported dispatch type ' + prog.dispatch)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	166 if prog.needFlagCoalesce:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	167 begin += prog.flags.coalesceFlags(prog, otype)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	168 if prog.needFlagDisperse:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	169 output.append(prog.flags.disperseFlags(prog, otype))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	170 for var in self.newLocals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	171 begin += '\n\tuint{sz}_t {name};'.format(sz=self.locals[var], name=var)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	172 for size in prog.temp:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	173 begin += '\n\tuint{sz}_t gen_tmp{sz}__;'.format(sz=size)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	174 prog.popScope()
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	175 if prog.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	176 output += prog.nextInstruction(otype)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	177 return begin + ''.join(output) + '\n}'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	178
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	179 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	180 pieces = [self.name + ' ' + hex(self.value) + ' ' + str(self.fields)]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	181 for name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	182 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	183 for op in self.implementation:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	184 pieces.append(str(op))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	185 return ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	186
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	187 #Represents the definition of a helper function
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	188 class SubRoutine(Block):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	189 def __init__(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	190 self.name = name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	191 self.implementation = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	192 self.args = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	193 self.arg_map = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	194 self.locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	195 self.regValues = {}
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	196 self.argValues = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	197
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	198 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	199 if op.op == 'arg':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	200 name = op.params[0]
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	201 size = int(op.params[1])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	202 self.arg_map[name] = len(self.args)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	203 self.args.append((name, size))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	204 elif op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	205 name = op.params[0]
1734 88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1733 diff changeset	206 size = int(op.params[1])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	207 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	208 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	209 self.implementation.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	210
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	211 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	212 if name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	213 return self.name + '_' + name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	214 return None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	215
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	216 def addLocal(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	217 self.locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	218
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	219 def localSize(self, name):
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	220 if name in self.locals:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	221 return self.locals[name]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	222 if name in self.arg_map:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	223 argIndex = self.arg_map[name]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	224 return self.args[argIndex][1]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	225 return None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	226
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	227 def inline(self, prog, params, output, otype, parent):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	228 if len(params) != len(self.args):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	229 raise Exception('{0} expects {1} arguments, but was called with {2}'.format(self.name, len(self.args), len(params)))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	230 argValues = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	231 if parent:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	232 self.regValues = parent.regValues
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	233 prog.pushScope(self)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	234 i = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	235 for name,size in self.args:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	236 argValues[name] = params[i]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	237 i += 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	238 for name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	239 size = self.locals[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	240 output.append('\n\tuint{size}_t {sub}_{local};'.format(size=size, sub=self.name, local=name))
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	241 self.argValues = argValues
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	242 self.processOps(prog, argValues, output, otype, self.implementation)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	243 prog.popScope()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	244
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	245 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	246 pieces = [self.name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	247 for name,size in self.args:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	248 pieces.append('\n\targ {0} {1}'.format(name, size))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	249 for name in self.locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	250 pieces.append('\n\tlocal {0} {1}'.format(name, self.locals[name]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	251 for op in self.implementation:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	252 pieces.append(str(op))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	253 return ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	254
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	255 class Op:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	256 def __init__(self, evalFun = None):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	257 self.evalFun = evalFun
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	258 self.impls = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	259 self.outOp = ()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	260 def cBinaryOperator(self, op):
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	261 def _impl(prog, params, rawParams, flagUpdates):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	262 if op == '-':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	263 a = params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	264 b = params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	265 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	266 a = params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	267 b = params[1]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	268 needsSizeAdjust = False
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	269 if len(params) > 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	270 size = params[3]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	271 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	272 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	273 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	274 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	275 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	276 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	277 prog.lastSize = size
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	278 destSize = prog.paramSize(rawParams[2])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	279 if destSize > size:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	280 needsSizeAdjust = True
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	281 prog.sizeAdjust = size
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	282 needsCarry = needsOflow = needsHalf = False
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	283 if flagUpdates:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	284 for flag in flagUpdates:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	285 calc = prog.flags.flagCalc[flag]
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	286 if calc == 'carry':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	287 needsCarry = True
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	288 elif calc == 'half-carry':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	289 needsHalf = True
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	290 elif calc == 'overflow':
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	291 needsOflow = True
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	292 decl = ''
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	293 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	294 if len(params) <= 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	295 size = prog.paramSize(rawParams[2])
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	296 if needsCarry and op != 'lsr':
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	297 size *= 2
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	298 decl,name = prog.getTemp(size)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	299 dst = prog.carryFlowDst = name
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	300 prog.lastA = a
1708 5bfed2eedc9d Fixed flag calculation for sub instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1707 diff changeset	301 prog.lastB = b
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	302 if size == 64:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	303 a = '((uint64_t){a})'.format(a=a)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	304 b = '((uint64_t){b})'.format(b=b)
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	305 prog.lastBFlow = b if op == '-' else '(~{b})'.format(b=b)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	306 elif needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	307 decl,name = prog.getTemp(size)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	308 dst = params[2]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	309 return '{decl}\n\t{tmp} = ({a} & {mask}) {op} ({b} & {mask});\n\t{dst} = ({dst} & ~{mask}) \| {tmp};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	310 decl = decl, tmp = name, a = a, b = b, op = op, dst = dst, mask = ((1 << size) - 1)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	311 )
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	312 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	313 dst = params[2]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	314 if needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	315 return decl + '\n\t{dst} = ({a} & {mask}) {op} ({b} & {mask});'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	316 dst = dst, a = a, b = b, op = op, mask = (1 << prog.sizeAdjust) - 1
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	317 )
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	318 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	319 return decl + '\n\t{dst} = {a} {op} {b};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	320 dst = dst, a = a, b = b, op = op
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	321 )
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	322 self.impls['c'] = _impl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	323 self.outOp = (2,)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	324 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	325 def cUnaryOperator(self, op):
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	326 def _impl(prog, params, rawParams, flagUpdates):
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	327 dst = params[1]
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	328 decl = ''
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	329 needsSizeAdjust = False
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	330 if len(params) > 2:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	331 size = params[2]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	332 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	333 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	334 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	335 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	336 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	337 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	338 prog.lastSize = size
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	339 destSize = prog.paramSize(rawParams[1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	340 if destSize > size:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	341 needsSizeAdjust = True
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	342 prog.sizeAdjust = size
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	343 if op == '-':
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	344 if flagUpdates:
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	345 for flag in flagUpdates:
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	346 calc = prog.flags.flagCalc[flag]
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	347 if calc == 'carry':
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	348 needsCarry = True
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	349 elif calc == 'half-carry':
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	350 needsHalf = True
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	351 elif calc == 'overflow':
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	352 needsOflow = True
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	353 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
1725 89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	354 size = prog.paramSize(rawParams[1])
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	355 if needsCarry:
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	356 size *= 2
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	357 decl,name = prog.getTemp(size)
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	358 dst = prog.carryFlowDst = name
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	359 prog.lastA = 0
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	360 prog.lastB = params[0]
89ee53a149ea Miscellaneous small fixes to new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1723 diff changeset	361 prog.lastBFlow = params[0]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	362 if needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	363 return decl + '\n\t{dst} = ({dst} & ~{mask}) \| (({op}{a}) & {mask});'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	364 dst = dst, a = params[0], op = op, mask = (1 << prog.sizeAdjust) - 1
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	365 )
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	366 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	367 return decl + '\n\t{dst} = {op}{a};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	368 dst = dst, a = params[0], op = op
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	369 )
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	370 self.impls['c'] = _impl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	371 self.outOp = (1,)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	372 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	373 def addImplementation(self, lang, outOp, impl):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	374 self.impls[lang] = impl
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	375 if not outOp is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	376 if type(outOp) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	377 self.outOp = outOp
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	378 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	379 self.outOp = (outOp,)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	380 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	381 def evaluate(self, params):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	382 return self.evalFun(*params)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	383 def canEval(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	384 return not self.evalFun is None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	385 def numArgs(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	386 return self.evalFun.__code__.co_argcount
1716 04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	387 def numParams(self):
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	388 if self.outOp:
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	389 params = max(self.outOp) + 1
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	390 else:
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	391 params = 0
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	392 if self.evalFun:
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	393 params = max(params, self.numArgs())
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	394 return params
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	395 def generate(self, otype, prog, params, rawParams, flagUpdates):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	396 if self.impls[otype].__code__.co_argcount == 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	397 return self.impls[otype](prog, params)
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	398 elif self.impls[otype].__code__.co_argcount == 3:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	399 return self.impls[otype](prog, params, rawParams)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	400 else:
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	401 return self.impls[otype](prog, params, rawParams, flagUpdates)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	402
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	403
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	404 def _xchgCImpl(prog, params, rawParams):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	405 size = prog.paramSize(rawParams[0])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	406 decl,name = prog.getTemp(size)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	407 return decl + '\n\t{tmp} = {a};\n\t{a} = {b};\n\t{b} = {tmp};'.format(a = params[0], b = params[1], tmp = name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	408
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	409 def _dispatchCImpl(prog, params):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	410 if len(params) == 1:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	411 table = 'main'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	412 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	413 table = params[1]
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	414 if prog.dispatch == 'call':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	415 return '\n\timpl_{tbl}[{op}](context, target_cycle);'.format(tbl = table, op = params[0])
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	416 elif prog.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	417 return '\n\tgoto *impl_{tbl}[{op}];'.format(tbl = table, op = params[0])
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	418 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	419 raise Exception('Unsupported dispatch type ' + prog.dispatch)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	420
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	421 def _updateFlagsCImpl(prog, params, rawParams):
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	422 autoUpdate, explicit = prog.flags.parseFlagUpdate(params[0])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	423 output = []
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	424 parity = None
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	425 directFlags = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	426 for flag in autoUpdate:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	427 calc = prog.flags.flagCalc[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	428 calc,_,resultBit = calc.partition('-')
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	429 if prog.carryFlowDst:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	430 lastDst = prog.carryFlowDst
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	431 else:
1734 88fbc4e711fd Implemented the rest of the block move instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1733 diff changeset	432 lastDst = prog.resolveParam(prog.lastDst, prog.currentScope, {})
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	433 storage = prog.flags.getStorage(flag)
1705 9ab64ef5cba0 Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction Michael Pavone <pavone@retrodev.com> parents: 1704 diff changeset	434 if calc == 'bit' or calc == 'sign' or calc == 'carry' or calc == 'half' or calc == 'overflow':
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	435 myRes = lastDst
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	436 if calc == 'sign':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	437 resultBit = prog.getLastSize() - 1
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	438 elif calc == 'carry':
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	439 if prog.lastOp.op in ('asr', 'lsr'):
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	440 resultBit = 0
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	441 myRes = prog.lastA
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	442 else:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	443 resultBit = prog.getLastSize()
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	444 if prog.lastOp.op == 'ror':
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	445 resultBit -= 1
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	446 elif calc == 'half':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	447 resultBit = prog.getLastSize() - 4
1708 5bfed2eedc9d Fixed flag calculation for sub instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1707 diff changeset	448 myRes = '({a} ^ {b} ^ {res})'.format(a = prog.lastA, b = prog.lastB, res = lastDst)
1705 9ab64ef5cba0 Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction Michael Pavone <pavone@retrodev.com> parents: 1704 diff changeset	449 elif calc == 'overflow':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	450 resultBit = prog.getLastSize() - 1
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	451 myRes = '((({a} ^ {b})) & ({a} ^ {res}))'.format(a = prog.lastA, b = prog.lastBFlow, res = lastDst)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	452 else:
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	453 #Note: offsetting this by the operation size - 8 makes sense for the Z80
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	454 #but might not for other CPUs with this kind of fixed bit flag behavior
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	455 resultBit = int(resultBit) + prog.getLastSize() - 8
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	456 if type(storage) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	457 reg,storageBit = storage
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	458 if storageBit == resultBit:
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	459 directFlags.setdefault((reg, myRes), []).append(resultBit)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	460 else:
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	461 reg = prog.resolveParam(reg, None, {})
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	462 if resultBit > storageBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	463 op = '>>'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	464 shift = resultBit - storageBit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	465 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	466 op = '<<'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	467 shift = storageBit - resultBit
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	468 output.append('\n\t{reg} = ({reg} & ~{mask}U) \| ({res} {op} {shift}U & {mask}U);'.format(
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	469 reg = reg, mask = 1 << storageBit, res = myRes, op = op, shift = shift
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	470 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	471 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	472 reg = prog.resolveParam(storage, None, {})
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	473 maxBit = prog.paramSize(storage) - 1
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	474 if resultBit > maxBit:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	475 output.append('\n\t{reg} = {res} >> {shift} & {mask}U;'.format(reg=reg, res=myRes, shift = resultBit - maxBit, mask = 1 << maxBit))
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	476 else:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	477 output.append('\n\t{reg} = {res} & {mask}U;'.format(reg=reg, res=myRes, mask = 1 << resultBit))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	478 elif calc == 'zero':
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	479 if prog.carryFlowDst:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	480 realSize = prog.getLastSize()
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	481 if realSize != prog.paramSize(prog.carryFlowDst):
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	482 lastDst = '({res} & {mask})'.format(res=lastDst, mask = (1 << realSize) - 1)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	483 if type(storage) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	484 reg,storageBit = storage
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	485 reg = prog.resolveParam(reg, None, {})
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	486 output.append('\n\t{reg} = {res} ? ({reg} & {mask}U) : ({reg} \| {bit}U);'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	487 reg = reg, mask = ~(1 << storageBit), res = lastDst, bit = 1 << storageBit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	488 ))
1703 49a52c737bf0 Fix zero flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1702 diff changeset	489 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	490 reg = prog.resolveParam(storage, None, {})
1703 49a52c737bf0 Fix zero flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1702 diff changeset	491 output.append('\n\t{reg} = {res} == 0;'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	492 reg = reg, res = lastDst
1705 9ab64ef5cba0 Initial stab at overflow flag implementation in CPU DSL. Probably broken for subtraction Michael Pavone <pavone@retrodev.com> parents: 1704 diff changeset	493 ))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	494 elif calc == 'parity':
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	495 parity = storage
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	496 paritySize = prog.getLastSize()
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	497 if prog.carryFlowDst:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	498 parityDst = paritySrc = prog.carryFlowDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	499 else:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	500 paritySrc = lastDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	501 decl,name = prog.getTemp(paritySize)
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	502 output.append(decl)
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	503 parityDst = name
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	504 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	505 raise Exception('Unknown flag calc type: ' + calc)
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	506 for reg, myRes in directFlags:
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	507 bits = directFlags[(reg, myRes)]
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	508 resolved = prog.resolveParam(reg, None, {})
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	509 if len(bits) == len(prog.flags.storageToFlags[reg]):
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	510 output.append('\n\t{reg} = {res};'.format(reg = resolved, res = myRes))
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	511 else:
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	512 mask = 0
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	513 for bit in bits:
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	514 mask \|= 1 << bit
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	515 output.append('\n\t{reg} = ({reg} & ~{mask}U) \| ({res} & {mask}U);'.format(
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	516 reg = resolved, mask = mask, res = myRes
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	517 ))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	518 if prog.carryFlowDst:
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	519 if prog.lastOp.op != 'cmp':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	520 if prog.sizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	521 output.append('\n\t{dst} = ({dst} & ~{mask}) \| ({tmpdst} & {mask});'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	522 dst = prog.resolveParam(prog.lastDst, prog.currentScope, {}), tmpdst = prog.carryFlowDst, mask = ((1 << prog.sizeAdjust) - 1)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	523 ))
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	524 prog.sizeAdjust = None
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	525 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	526 output.append('\n\t{dst} = {tmpdst};'.format(dst = prog.resolveParam(prog.lastDst, prog.currentScope, {}), tmpdst = prog.carryFlowDst))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	527 prog.carryFlowDst = None
1713 0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	528 if parity:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	529 if paritySize > 8:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	530 if paritySize > 16:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	531 output.append('\n\t{dst} = {src} ^ ({src} >> 16);'.format(dst=parityDst, src=paritySrc))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	532 paritySrc = parityDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	533 output.append('\n\t{dst} = {src} ^ ({src} >> 8);'.format(dst=parityDst, src=paritySrc))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	534 paritySrc = parityDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	535 output.append('\n\t{dst} = ({src} ^ ({src} >> 4)) & 0xF;'.format(dst=parityDst, src=paritySrc))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	536 if type(parity) is tuple:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	537 reg,bit = parity
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	538 reg = prog.resolveParam(reg, None, {})
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	539 output.append('\n\t{flag} = ({flag} & ~{mask}U) \| ((0x6996 >> {parity}) << {bit} & {mask}U);'.format(
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	540 flag=reg, mask = 1 << bit, bit = bit, parity = parityDst
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	541 ))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	542 else:
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	543 reg = prog.resolveParam(parity, None, {})
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	544 output.append('\n\t{flag} = 0x9669 >> {parity} & 1;'.format(flag=reg, parity=parityDst))
0264d8b288e2 Implement parity flag calculation type Michael Pavone <pavone@retrodev.com> parents: 1711 diff changeset	545
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	546 #TODO: combine explicit flags targeting the same storage location
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	547 for flag in explicit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	548 location = prog.flags.getStorage(flag)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	549 if type(location) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	550 reg,bit = location
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	551 reg = prog.resolveReg(reg, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	552 value = str(1 << bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	553 if explicit[flag]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	554 operator = '\|='
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	555 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	556 operator = '&='
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	557 value = '~' + value
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	558 output.append('\n\t{reg} {op} {val};'.format(reg=reg, op=operator, val=value))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	559 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	560 reg = prog.resolveReg(location, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	561 output.append('\n\t{reg} = {val};'.format(reg=reg, val=explicit[flag]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	562 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	563
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	564 def _cmpCImpl(prog, params, rawParams, flagUpdates):
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	565 size = prog.paramSize(rawParams[1])
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	566 needsCarry = False
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	567 if flagUpdates:
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	568 for flag in flagUpdates:
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	569 calc = prog.flags.flagCalc[flag]
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	570 if calc == 'carry':
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	571 needsCarry = True
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	572 break
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	573 if needsCarry:
fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	574 size *= 2
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	575 tmpvar = 'cmp_tmp{sz}__'.format(sz=size)
1745 a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	576 if flagUpdates:
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	577 prog.carryFlowDst = tmpvar
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	578 prog.lastA = params[1]
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	579 prog.lastB = params[0]
a8f04b0ab744 Fixes to DAA, SCF and CCF to pass ZEXALL in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1744 diff changeset	580 prog.lastBFlow = params[0]
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	581 scope = prog.getRootScope()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	582 if not scope.resolveLocal(tmpvar):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	583 scope.addLocal(tmpvar, size)
1719 fb5ae8c20b85 Fix cp instruction in new Z80 core and implement its DD/FD prefixes Michael Pavone <pavone@retrodev.com> parents: 1716 diff changeset	584 prog.lastDst = rawParams[1]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	585 if len(params) > 2:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	586 size = params[2]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	587 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	588 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	589 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	590 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	591 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	592 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	593 prog.lastSize = size
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	594 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	595 prog.lastSize = None
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	596 return '\n\t{var} = {b} - {a};'.format(var = tmpvar, a = params[0], b = params[1])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	597
1723 b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	598 def _asrCImpl(prog, params, rawParams, flagUpdates):
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	599 needsCarry = False
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	600 if flagUpdates:
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	601 for flag in flagUpdates:
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	602 calc = prog.flags.flagCalc[flag]
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	603 if calc == 'carry':
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	604 needsCarry = True
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	605 decl = ''
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	606 size = prog.paramSize(rawParams[2])
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	607 if needsCarry:
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	608 decl,name = prog.getTemp(size * 2)
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	609 dst = prog.carryFlowDst = name
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	610 prog.lastA = params[0]
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	611 else:
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	612 dst = params[2]
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	613 mask = 1 << (size - 1)
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	614 return decl + '\n\t{dst} = ({a} >> {b}) \| ({a} & {mask} ? 0xFFFFFFFFU << ({size} - {b}) : 0);'.format(
b757ebc59851 Implemented shift instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1722 diff changeset	615 a = params[0], b = params[1], dst = dst, mask = mask, size=size)
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	616
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	617 def _sext(size, src):
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	618 if size == 16:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	619 return src \| 0xFF00 if src & 0x80 else src & 0x7F
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	620 else:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	621 return src \| 0xFFFF0000 if src & 0x8000 else src & 0x7FFF
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	622
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	623 def _sextCImpl(prog, params, rawParms):
44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	624 if params[0] == 16:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	625 fmt = '\n\t{dst} = {src} & 0x80 ? {src} \| 0xFF00 : {src} & 0x7F;'
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	626 else:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	627 fmt = '\n\t{dst} = {src} & 0x8000 ? {src} \| 0xFFFF0000 : {src} & 0x7FFF;'
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	628 return fmt.format(src=params[1], dst=params[2])
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	629
73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	630 def _getCarryCheck(prog):
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	631 carryFlag = None
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	632 for flag in prog.flags.flagOrder:
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	633 if prog.flags.flagCalc[flag] == 'carry':
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	634 carryFlag = flag
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	635 break
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	636 if carryFlag is None:
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	637 raise Exception('adc requires a defined carry flag')
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	638 carryStorage = prog.flags.getStorage(carryFlag)
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	639 if type(carryStorage) is tuple:
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	640 reg,bit = carryStorage
4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	641 reg = prog.resolveReg(reg, None, (), False)
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	642 return '({reg} & 1 << {bit})'.format(reg=reg, bit=bit)
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	643 else:
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	644 return prog.resolveReg(carryStorage, None, (), False)
73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	645
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	646 def _adcCImpl(prog, params, rawParams, flagUpdates):
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	647 needsSizeAdjust = False
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	648 if len(params) > 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	649 size = params[3]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	650 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	651 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	652 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	653 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	654 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	655 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	656 prog.lastSize = size
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	657 destSize = prog.paramSize(rawParams[2])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	658 if destSize > size:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	659 needsSizeAdjust = True
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	660 prog.sizeAdjust = size
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	661 needsCarry = needsOflow = needsHalf = False
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	662 if flagUpdates:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	663 for flag in flagUpdates:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	664 calc = prog.flags.flagCalc[flag]
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	665 if calc == 'carry':
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	666 needsCarry = True
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	667 elif calc == 'half-carry':
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	668 needsHalf = True
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	669 elif calc == 'overflow':
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	670 needsOflow = True
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	671 decl = ''
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	672 carryCheck = _getCarryCheck(prog)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	673 vals = '1 : 0'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	674 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	675 if len(params) <= 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	676 size = prog.paramSize(rawParams[2])
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	677 if needsCarry:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	678 size *= 2
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	679 decl,name = prog.getTemp(size)
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	680 dst = prog.carryFlowDst = name
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	681 prog.lastA = params[0]
1744 91aa789e57bd Fixed half-carry flag calcuation for adc/sbc in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1742 diff changeset	682 prog.lastB = params[1]
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	683 prog.lastBFlow = '(~{b})'.format(b=params[1])
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	684 if size == 64:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	685 params[0] = '((uint64_t){a})'.format(a=params[0])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	686 params[1] = '((uint64_t){b})'.format(b=params[1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	687 vals = '((uint64_t)1) : ((uint64_t)0)'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	688 elif needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	689 decl,name = prog.getTemp(size)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	690 dst = params[2]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	691 return '{decl}\n\t{tmp} = ({a} & {mask}) + ({b} & {mask}) + ({check} ? 1 : 0);\n\t{dst} = ({dst} & ~{mask}) \| {tmp};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	692 decl = decl, tmp = name, a = a, b = b, op = op, dst = dst, mask = ((1 << size) - 1), check = carryCheck
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	693 )
1709 9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	694 else:
9c058ea77b7a Implementation of carry/overflow flags for adc instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1708 diff changeset	695 dst = params[2]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	696 return decl + '\n\t{dst} = {a} + {b} + ({check} ? {vals});'.format(dst = dst,
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	697 a = params[0], b = params[1], check = carryCheck, vals = vals
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	698 )
73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	699
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	700 def _sbcCImpl(prog, params, rawParams, flagUpdates):
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	701 needsSizeAdjust = False
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	702 if len(params) > 3:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	703 size = params[3]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	704 if size == 0:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	705 size = 8
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	706 elif size == 1:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	707 size = 16
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	708 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	709 size = 32
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	710 prog.lastSize = size
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	711 destSize = prog.paramSize(rawParams[2])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	712 if destSize > size:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	713 needsSizeAdjust = True
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	714 prog.sizeAdjust = size
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	715 needsCarry = needsOflow = needsHalf = False
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	716 if flagUpdates:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	717 for flag in flagUpdates:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	718 calc = prog.flags.flagCalc[flag]
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	719 if calc == 'carry':
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	720 needsCarry = True
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	721 elif calc == 'half-carry':
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	722 needsHalf = True
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	723 elif calc == 'overflow':
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	724 needsOflow = True
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	725 decl = ''
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	726 carryCheck = _getCarryCheck(prog)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	727 vals = '1 : 0'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	728 if needsCarry or needsOflow or needsHalf or (flagUpdates and needsSizeAdjust):
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	729 size = prog.paramSize(rawParams[2])
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	730 if needsCarry:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	731 size *= 2
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	732 decl,name = prog.getTemp(size)
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	733 dst = prog.carryFlowDst = name
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	734 prog.lastA = params[1]
1744 91aa789e57bd Fixed half-carry flag calcuation for adc/sbc in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1742 diff changeset	735 prog.lastB = params[0]
1711 87d4f0b4bf1d Actually correct overflow flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1710 diff changeset	736 prog.lastBFlow = params[0]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	737 if size == 64:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	738 params[1] = '((uint64_t){a})'.format(a=params[1])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	739 params[0] = '((uint64_t){b})'.format(b=params[0])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	740 vals = '((uint64_t)1) : ((uint64_t)0)'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	741 elif needsSizeAdjust:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	742 decl,name = prog.getTemp(size)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	743 dst = params[2]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	744 return '{decl}\n\t{tmp} = ({b} & {mask}) - ({a} & {mask}) - ({check} ? 1 : 0);\n\t{dst} = ({dst} & ~{mask}) \| {tmp};'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	745 decl = decl, tmp = name, a = params[0], b = params[1], op = op, dst = dst, mask = ((1 << size) - 1), check = carryCheck
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	746 )
1710 2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	747 else:
2344b3650b38 Fix sbc and implement carry/overflow flags for it in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1709 diff changeset	748 dst = params[2]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	749 return decl + '\n\t{dst} = {b} - {a} - ({check} ? {vals});'.format(dst = dst,
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	750 a = params[0], b = params[1], check=_getCarryCheck(prog), vals = vals
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	751 )
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	752
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	753 def _rolCImpl(prog, params, rawParams, flagUpdates):
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	754 needsCarry = False
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	755 if flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	756 for flag in flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	757 calc = prog.flags.flagCalc[flag]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	758 if calc == 'carry':
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	759 needsCarry = True
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	760 decl = ''
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	761 size = prog.paramSize(rawParams[2])
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	762 if needsCarry:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	763 decl,name = prog.getTemp(size * 2)
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	764 dst = prog.carryFlowDst = name
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	765 else:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	766 dst = params[2]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	767 return decl + '\n\t{dst} = {a} << {b} \| {a} >> ({size} - {b});'.format(dst = dst,
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	768 a = params[0], b = params[1], size=size
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	769 )
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	770
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	771 def _rlcCImpl(prog, params, rawParams, flagUpdates):
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	772 needsCarry = False
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	773 if flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	774 for flag in flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	775 calc = prog.flags.flagCalc[flag]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	776 if calc == 'carry':
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	777 needsCarry = True
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	778 decl = ''
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	779 carryCheck = _getCarryCheck(prog)
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	780 size = prog.paramSize(rawParams[2])
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	781 if needsCarry:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	782 decl,name = prog.getTemp(size * 2)
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	783 dst = prog.carryFlowDst = name
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	784 else:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	785 dst = params[2]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	786 return decl + '\n\t{dst} = {a} << {b} \| {a} >> ({size} + 1 - {b}) \| ({check} ? 1 : 0) << ({b} - 1);'.format(dst = dst,
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	787 a = params[0], b = params[1], size=size, check=carryCheck
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	788 )
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	789
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	790 def _rorCImpl(prog, params, rawParams, flagUpdates):
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	791 size = prog.paramSize(rawParams[2])
1722 ac809d044cab Implemented the rest of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1721 diff changeset	792 return '\n\t{dst} = {a} >> {b} \| {a} << ({size} - {b});'.format(dst = params[2],
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	793 a = params[0], b = params[1], size=size
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	794 )
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	795
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	796 def _rrcCImpl(prog, params, rawParams, flagUpdates):
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	797 needsCarry = False
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	798 if flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	799 for flag in flagUpdates:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	800 calc = prog.flags.flagCalc[flag]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	801 if calc == 'carry':
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	802 needsCarry = True
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	803 decl = ''
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	804 carryCheck = _getCarryCheck(prog)
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	805 size = prog.paramSize(rawParams[2])
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	806 if needsCarry:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	807 decl,name = prog.getTemp(size * 2)
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	808 dst = prog.carryFlowDst = name
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	809 else:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	810 dst = params[2]
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	811 return decl + '\n\t{dst} = {a} >> {b} \| {a} << ({size} + 1 - {b}) \| ({check} ? 1 : 0) << ({size}-{b});'.format(dst = dst,
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	812 a = params[0], b = params[1], size=size, check=carryCheck
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	813 )
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	814
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	815 def _updateSyncCImpl(prog, params):
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	816 return '\n\t{sync}(context, target_cycle);'.format(sync=prog.sync_cycle)
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	817
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	818 _opMap = {
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	819 'mov': Op(lambda val: val).cUnaryOperator(''),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	820 'not': Op(lambda val: ~val).cUnaryOperator('~'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	821 'lnot': Op(lambda val: 0 if val else 1).cUnaryOperator('!'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	822 'neg': Op(lambda val: -val).cUnaryOperator('-'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	823 'add': Op(lambda a, b: a + b).cBinaryOperator('+'),
1701 4fd34fde390c Added adc instruction to CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1700 diff changeset	824 'adc': Op().addImplementation('c', 2, _adcCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	825 'sub': Op(lambda a, b: b - a).cBinaryOperator('-'),
1702 73ac2e59fa3f Implemented sbc instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1701 diff changeset	826 'sbc': Op().addImplementation('c', 2, _sbcCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	827 'lsl': Op(lambda a, b: a << b).cBinaryOperator('<<'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	828 'lsr': Op(lambda a, b: a >> b).cBinaryOperator('>>'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	829 'asr': Op(lambda a, b: a >> b).addImplementation('c', 2, _asrCImpl),
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	830 'rol': Op().addImplementation('c', 2, _rolCImpl),
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	831 'rlc': Op().addImplementation('c', 2, _rlcCImpl),
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	832 'ror': Op().addImplementation('c', 2, _rorCImpl),
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	833 'rrc': Op().addImplementation('c', 2, _rrcCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	834 'and': Op(lambda a, b: a & b).cBinaryOperator('&'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	835 'or': Op(lambda a, b: a \| b).cBinaryOperator('\|'),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	836 'xor': Op(lambda a, b: a ^ b).cBinaryOperator('^'),
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	837 'abs': Op(lambda val: abs(val)).addImplementation(
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	838 'c', 1, lambda prog, params: '\n\t{dst} = abs({src});'.format(dst=params[1], src=params[0])
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	839 ),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	840 'cmp': Op().addImplementation('c', None, _cmpCImpl),
1697 44d8c6e61ad4 Added new sext instruction for sign extension to CPU sdl Michael Pavone <pavone@retrodev.com> parents: 1621 diff changeset	841 'sext': Op(_sext).addImplementation('c', 2, _sextCImpl),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	842 'ocall': Op().addImplementation('c', None, lambda prog, params: '\n\t{pre}{fun}({args});'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	843 pre = prog.prefix, fun = params[0], args = ', '.join(['context'] + [str(p) for p in params[1:]])
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	844 )),
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	845 'pcall': Op().addImplementation('c', None, lambda prog, params: '\n\t(({typ}){fun})({args});'.format(
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	846 typ = params[1], fun = params[0], args = ', '.join([str(p) for p in params[2:]])
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	847 )),
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	848 'cycles': Op().addImplementation('c', None,
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	849 lambda prog, params: '\n\tcontext->cycles += context->opts->gen.clock_divider * {0};'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	850 params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	851 )
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	852 ),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	853 'addsize': Op(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	854 lambda a, b: b + (2 * a if a else 1)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	855 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} + ({sz} ? {sz} * 2 : 1);'.format(
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	856 dst = params[2], sz = params[0], val = params[1]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	857 )),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	858 'decsize': Op(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	859 lambda a, b: b - (2 * a if a else 1)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	860 ).addImplementation('c', 2, lambda prog, params: '\n\t{dst} = {val} - ({sz} ? {sz} * 2 : 1);'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	861 dst = params[2], sz = params[0], val = params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	862 )),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	863 'xchg': Op().addImplementation('c', (0,1), _xchgCImpl),
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	864 'dispatch': Op().addImplementation('c', None, _dispatchCImpl),
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	865 'update_flags': Op().addImplementation('c', None, _updateFlagsCImpl),
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	866 'update_sync': Op().addImplementation('c', None, _updateSyncCImpl)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	867 }
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	868
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	869 #represents a simple DSL instruction
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	870 class NormalOp:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	871 def __init__(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	872 self.op = parts[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	873 self.params = parts[1:]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	874
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	875 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	876 procParams = []
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	877 allParamsConst = flagUpdates is None and not prog.conditional
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	878 opDef = _opMap.get(self.op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	879 for param in self.params:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	880 isDst = (not opDef is None) and len(procParams) in opDef.outOp
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	881 allowConst = (self.op in prog.subroutines or not isDst) and param in parent.regValues
1765 7b6831305a6a Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1759 diff changeset	882 if isDst and self.op == 'xchg':
7b6831305a6a Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1759 diff changeset	883 #xchg uses its regs as both source and destination
7b6831305a6a Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1759 diff changeset	884 #we need to resolve as both so that disperse/coalesce flag stuff gets done
7b6831305a6a Fix calculation for whether coalesceFlags is needed for xchg instruction in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1759 diff changeset	885 prog.resolveParam(param, parent, fieldVals, allowConst, False)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	886 param = prog.resolveParam(param, parent, fieldVals, allowConst, isDst)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	887
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	888 if (not type(param) is int) and len(procParams) != len(self.params) - 1:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	889 allParamsConst = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	890 procParams.append(param)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	891
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	892 if self.op == 'meta':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	893 param,_,index = self.params[1].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	894 if index:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	895 index = (parent.resolveLocal(index) or index)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	896 if index in fieldVals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	897 index = str(fieldVals[index])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	898 param = param + '.' + index
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	899 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	900 param = parent.resolveLocal(param) or param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	901 if param in fieldVals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	902 param = fieldVals[index]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	903 prog.meta[self.params[0]] = param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	904 elif self.op == 'dis':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	905 #TODO: Disassembler
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	906 pass
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	907 elif not opDef is None:
1716 04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	908 if opDef.numParams() > len(procParams):
04cafe626118 Better error reporting when an instruction is given an insufficient number of parameters Michael Pavone <pavone@retrodev.com> parents: 1715 diff changeset	909 raise Exception('Insufficient params for ' + self.op + ' (' + ', '.join(self.params) + ')')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	910 if opDef.canEval() and allParamsConst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	911 #do constant folding
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	912 if opDef.numArgs() >= len(procParams):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	913 raise Exception('Insufficient args for ' + self.op + ' (' + ', '.join(self.params) + ')')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	914 dst = self.params[opDef.numArgs()]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	915 result = opDef.evaluate(procParams[:opDef.numArgs()])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	916 while dst in prog.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	917 dst = prog.meta[dst]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	918 maybeLocal = parent.resolveLocal(dst)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	919 if maybeLocal:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	920 dst = maybeLocal
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	921 parent.regValues[dst] = result
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	922 if prog.isReg(dst):
1699 93103ad9d7f7 Fix constant propagation to a non-ephemeral destination in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1698 diff changeset	923 shortProc = (procParams[0], procParams[-1])
93103ad9d7f7 Fix constant propagation to a non-ephemeral destination in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1698 diff changeset	924 shortParams = (self.params[0], self.params[-1])
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	925 output.append(_opMap['mov'].generate(otype, prog, shortProc, shortParams, None))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	926 else:
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	927 output.append(opDef.generate(otype, prog, procParams, self.params, flagUpdates))
1728 b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	928 for dstIdx in opDef.outOp:
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	929 dst = self.params[dstIdx]
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	930 while dst in prog.meta:
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	931 dst = prog.meta[dst]
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	932 if dst in parent.regValues:
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	933 del parent.regValues[dst]
b0e01e64d76d Implemented RES instruction in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1725 diff changeset	934
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	935 elif self.op in prog.subroutines:
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	936 procParams = []
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	937 for param in self.params:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	938 begin,sep,end = param.partition('.')
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	939 if sep:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	940 if end in fieldVals:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	941 param = begin + '.' + str(fieldVals[end])
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	942 else:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	943 if param in fieldVals:
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	944 param = fieldVals[param]
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	945 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	946 maybeLocal = parent.resolveLocal(param)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	947 if maybeLocal and maybeLocal in parent.regValues:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	948 param = parent.regValues[maybeLocal]
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	949 procParams.append(param)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	950 prog.subroutines[self.op].inline(prog, procParams, output, otype, parent)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	951 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	952 output.append('\n\t' + self.op + '(' + ', '.join([str(p) for p in procParams]) + ');')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	953 prog.lastOp = self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	954
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	955 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	956 return '\n\t' + self.op + ' ' + ' '.join(self.params)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	957
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	958 #represents a DSL switch construct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	959 class Switch(ChildBlock):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	960 def __init__(self, parent, param):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	961 self.op = 'switch'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	962 self.parent = parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	963 self.param = param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	964 self.cases = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	965 self.regValues = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	966 self.current_locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	967 self.case_locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	968 self.current_case = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	969 self.default = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	970 self.default_locals = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	971
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	972 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	973 if op.op == 'case':
1619 0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	974 val = int(op.params[0], 16) if op.params[0].startswith('0x') else int(op.params[0])
0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	975 self.cases[val] = self.current_case = []
0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	976 self.case_locals[val] = self.current_locals = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	977 elif op.op == 'default':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	978 self.default = self.current_case = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	979 self.default_locals = self.current_locals = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	980 elif self.current_case == None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	981 raise ion('Orphan instruction in switch')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	982 elif op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	983 name = op.params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	984 size = op.params[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	985 self.current_locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	986 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	987 self.current_case.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	988
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	989 def resolveLocal(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	990 if name in self.current_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	991 return name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	992 return self.parent.resolveLocal(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	993
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	994 def addLocal(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	995 self.current_locals[name] = size
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	996
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	997 def localSize(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	998 if name in self.current_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	999 return self.current_locals[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1000 return self.parent.localSize(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1001
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1002 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates):
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1003 prog.pushScope(self)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1004 param = prog.resolveParam(self.param, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1005 if type(param) is int:
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1006 self.regValues = self.parent.regValues
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1007 if param in self.cases:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1008 self.current_locals = self.case_locals[param]
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1009 output.append('\n\t{')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1010 for local in self.case_locals[param]:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1011 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[param][local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1012 self.processOps(prog, fieldVals, output, otype, self.cases[param])
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1013 output.append('\n\t}')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1014 elif self.default:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1015 self.current_locals = self.default_locals
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1016 output.append('\n\t{')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1017 for local in self.default_locals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1018 output.append('\n\tuint{0}_t {1};'.format(self.default[local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1019 self.processOps(prog, fieldVals, output, otype, self.default)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1020 output.append('\n\t}')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1021 else:
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1022 oldCond = prog.conditional
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1023 prog.conditional = True
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1024 output.append('\n\tswitch(' + param + ')')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1025 output.append('\n\t{')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1026 for case in self.cases:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1027 #temp = prog.temp.copy()
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1028 self.current_locals = self.case_locals[case]
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1029 self.regValues = dict(self.parent.regValues)
1619 0e8438a4c76f Clean up warnings from -1 case Michael Pavone <pavone@retrodev.com> parents: 1618 diff changeset	1030 output.append('\n\tcase {0}U: '.format(case) + '{')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1031 for local in self.case_locals[case]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1032 output.append('\n\tuint{0}_t {1};'.format(self.case_locals[case][local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1033 self.processOps(prog, fieldVals, output, otype, self.cases[case])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1034 output.append('\n\tbreak;')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1035 output.append('\n\t}')
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1036 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1037 if self.default:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1038 #temp = prog.temp.copy()
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1039 self.current_locals = self.default_locals
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1040 self.regValues = dict(self.parent.regValues)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1041 output.append('\n\tdefault: {')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1042 for local in self.default_locals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1043 output.append('\n\tuint{0}_t {1};'.format(self.default_locals[local], local))
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1044 self.processOps(prog, fieldVals, output, otype, self.default)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1045 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1046 output.append('\n\t}')
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1047 prog.conditional = oldCond
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1048 prog.popScope()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1049
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1050 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1051 keys = self.cases.keys()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1052 keys.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1053 lines = ['\n\tswitch']
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1054 for case in keys:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1055 lines.append('\n\tcase {0}'.format(case))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1056 lines.append(''.join([str(op) for op in self.cases[case]]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1057 lines.append('\n\tend')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1058 return ''.join(lines)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1059
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1060
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1061 def _geuCImpl(prog, parent, fieldVals, output):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1062 if prog.lastOp.op == 'cmp':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1063 output.pop()
1616 8c78543c4783 Fix implementation cmp+condition version of if in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1615 diff changeset	1064 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params]
8c78543c4783 Fix implementation cmp+condition version of if in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1615 diff changeset	1065 return '\n\tif ({a} >= {b}) '.format(a=params[1], b = params[0]) + '{'
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1066 else:
1733 1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1067 raise Exception(">=U not implemented in the general case yet")
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1068
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1069 def _eqCImpl(prog, parent, fieldVals, output):
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1070 if prog.lastOp.op == 'cmp':
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1071 output.pop()
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1072 params = [prog.resolveParam(p, parent, fieldVals) for p in prog.lastOp.params]
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1073 return '\n\tif ({a} == {b}) '.format(a=params[1], b = params[0]) + '{'
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1074 else:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1075 return '\n\tif (!{a}) {{'.format(a=prog.resolveParam(prog.lastDst, None, {}))
1733 1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1076
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1077 def _neqCImpl(prog, parent, fieldVals, output):
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1078 return '\n\tif ({a}) {{'.format(a=prog.resolveParam(prog.lastDst, None, {}))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1079
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1080 _ifCmpImpl = {
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1081 'c': {
1733 1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1082 '>=U': _geuCImpl,
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1083 '=': _eqCImpl,
1f0a86f5e055 Implemented LDI in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1728 diff changeset	1084 '!=': _neqCImpl
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1085 }
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1086 }
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1087 #represents a DSL conditional construct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1088 class If(ChildBlock):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1089 def __init__(self, parent, cond):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1090 self.op = 'if'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1091 self.parent = parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1092 self.cond = cond
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1093 self.body = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1094 self.elseBody = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1095 self.curBody = self.body
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1096 self.locals = {}
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1097 self.elseLocals = {}
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1098 self.curLocals = self.locals
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1099 self.regValues = None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1100
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1101 def addOp(self, op):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1102 if op.op in ('case', 'arg'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1103 raise Exception(self.op + ' is not allows inside an if block')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1104 if op.op == 'local':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1105 name = op.params[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1106 size = op.params[1]
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1107 self.curLocals[name] = size
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1108 elif op.op == 'else':
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1109 self.curLocals = self.elseLocals
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1110 self.curBody = self.elseBody
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1111 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1112 self.curBody.append(op)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1113
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1114 def localSize(self, name):
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1115 return self.curLocals.get(name)
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1116
c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1117 def resolveLocal(self, name):
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1118 if name in self.curLocals:
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1119 return name
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1120 return self.parent.resolveLocal(name)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1121
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1122 def _genTrueBody(self, prog, fieldVals, output, otype):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1123 self.curLocals = self.locals
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1124 subOut = []
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1125 self.processOps(prog, fieldVals, subOut, otype, self.body)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1126 for local in self.locals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1127 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.locals[local], nm=local))
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1128 output += subOut
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1129
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1130 def _genFalseBody(self, prog, fieldVals, output, otype):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1131 self.curLocals = self.elseLocals
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1132 subOut = []
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1133 self.processOps(prog, fieldVals, subOut, otype, self.elseBody)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1134 for local in self.elseLocals:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1135 output.append('\n\tuint{sz}_t {nm};'.format(sz=self.elseLocals[local], nm=local))
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1136 output += subOut
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1137
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1138 def _genConstParam(self, param, prog, fieldVals, output, otype):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1139 if param:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1140 self._genTrueBody(prog, fieldVals, output, otype)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1141 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1142 self._genFalseBody(prog, fieldVals, output, otype)
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1143
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1144 def generate(self, prog, parent, fieldVals, output, otype, flagUpdates):
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1145 self.regValues = parent.regValues
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1146 if self.cond in prog.booleans:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1147 self._genConstParam(prog.checkBool(self.cond), prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1148 else:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1149 if self.cond in _ifCmpImpl[otype]:
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1150 oldCond = prog.conditional
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1151 prog.conditional = True
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1152 #temp = prog.temp.copy()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1153 output.append(_ifCmpImpl[otype][self.cond](prog, parent, fieldVals, output))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1154 self._genTrueBody(prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1155 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1156 if self.elseBody:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1157 #temp = prog.temp.copy()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1158 output.append('\n\t} else {')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1159 self._genFalseBody(prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1160 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1161 output.append('\n\t}')
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1162 prog.conditional = oldCond
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1163 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1164 cond = prog.resolveParam(self.cond, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1165 if type(cond) is int:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1166 self._genConstParam(cond, prog, fieldVals, output, otype)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1167 else:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1168 #temp = prog.temp.copy()
1614 c9639139aedf Did some cleanup of SVP code using the newly more powerful DSL if block and fixed some issues in the DSL implementation that cropped up as a result Michael Pavone <pavone@retrodev.com> parents: 1613 diff changeset	1169 output.append('\n\tif ({cond}) '.format(cond=cond) + '{')
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1170 oldCond = prog.conditional
2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1171 prog.conditional = True
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1172 self._genTrueBody(prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1173 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1174 if self.elseBody:
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1175 #temp = prog.temp.copy()
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1176 output.append('\n\t} else {')
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1177 self._genFalseBody(prog, fieldVals, output, otype)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1178 #prog.temp = temp
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1179 output.append('\n\t}')
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1180 prog.conditional = oldCond
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1181
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1182
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1183 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1184 lines = ['\n\tif']
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1185 for op in self.body:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1186 lines.append(str(op))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1187 lines.append('\n\tend')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1188 return ''.join(lines)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1189
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1190 class Registers:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1191 def __init__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1192 self.regs = {}
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1193 self.pointers = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1194 self.regArrays = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1195 self.regToArray = {}
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1196 self.addReg('cycles', 32)
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	1197 self.addReg('sync_cycle', 32)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1198
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1199 def addReg(self, name, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1200 self.regs[name] = size
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1201
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1202 def addPointer(self, name, size, count):
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1203 self.pointers[name] = (size, count)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1204
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1205 def addRegArray(self, name, size, regs):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1206 self.regArrays[name] = (size, regs)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1207 idx = 0
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1208 if not type(regs) is int:
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1209 for reg in regs:
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1210 self.regs[reg] = size
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1211 self.regToArray[reg] = (name, idx)
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1212 idx += 1
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1213
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1214 def isReg(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1215 return name in self.regs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1216
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1217 def isRegArray(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1218 return name in self.regArrays
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1219
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1220 def isRegArrayMember(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1221 return name in self.regToArray
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1222
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1223 def arrayMemberParent(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1224 return self.regToArray[name][0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1225
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1226 def arrayMemberIndex(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1227 return self.regToArray[name][1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1228
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1229 def arrayMemberName(self, array, index):
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1230 if type(index) is int and not type(self.regArrays[array][1]) is int:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1231 return self.regArrays[array][1][index]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1232 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1233 return None
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1234
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1235 def isNamedArray(self, array):
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1236 return array in self.regArrays and type(self.regArrays[array][1]) is int
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1237
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1238 def processLine(self, parts):
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1239 if len(parts) == 3:
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1240 if parts[1].startswith('ptr'):
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1241 self.addPointer(parts[0], parts[1][3:], int(parts[2]))
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1242 else:
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1243 self.addRegArray(parts[0], int(parts[1]), int(parts[2]))
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1244 elif len(parts) > 2:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1245 self.addRegArray(parts[0], int(parts[1]), parts[2:])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1246 else:
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1247 if parts[1].startswith('ptr'):
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1248 self.addPointer(parts[0], parts[1][3:], 1)
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1249 else:
ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1250 self.addReg(parts[0], int(parts[1]))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1251 return self
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1252
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1253 def writeHeader(self, otype, hFile):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1254 fieldList = []
1621 ca158bc091f9 Implement program ROM reads Michael Pavone <pavone@retrodev.com> parents: 1620 diff changeset	1255 for pointer in self.pointers:
1735 ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1256 stars = '*'
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1257 ptype, count = self.pointers[pointer]
1735 ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1258 while ptype.startswith('ptr'):
ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1259 stars += '*'
ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1260 ptype = ptype[3:]
ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1261 if ptype.isdigit():
ca2336469397 Get new Z80 core running in CPM harness Michael Pavone <pavone@retrodev.com> parents: 1734 diff changeset	1262 ptype = 'uint{sz}_t'.format(sz=ptype)
1750 01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1263 if count > 1:
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1264 arr = '[{n}]'.format(n=count)
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1265 else:
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1266 arr = ''
01236179fc71 Optimization to memory access in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1749 diff changeset	1267 hFile.write('\n\t{ptype} {stars}{nm}{arr};'.format(nm=pointer, ptype=ptype, stars=stars, arr=arr))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1268 for reg in self.regs:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1269 if not self.isRegArrayMember(reg):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1270 fieldList.append((self.regs[reg], 1, reg))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1271 for arr in self.regArrays:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1272 size,regs = self.regArrays[arr]
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1273 if not type(regs) is int:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1274 regs = len(regs)
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1275 fieldList.append((size, regs, arr))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1276 fieldList.sort()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1277 fieldList.reverse()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1278 for size, count, name in fieldList:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1279 if count > 1:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1280 hFile.write('\n\tuint{sz}_t {nm}[{ct}];'.format(sz=size, nm=name, ct=count))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1281 else:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1282 hFile.write('\n\tuint{sz}_t {nm};'.format(sz=size, nm=name))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1283
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1284 class Flags:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1285 def __init__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1286 self.flagBits = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1287 self.flagCalc = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1288 self.flagStorage = {}
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1289 self.flagOrder = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1290 self.flagReg = None
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	1291 self.storageToFlags = {}
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1292 self.maxBit = -1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1293
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1294 def processLine(self, parts):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1295 if parts[0] == 'register':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1296 self.flagReg = parts[1]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1297 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1298 flag,bit,calc,storage = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1299 bit,_,top = bit.partition('-')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1300 bit = int(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1301 if top:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1302 top = int(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1303 if top > self.maxBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1304 self.maxBit = top
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1305 self.flagBits[flag] = (bit,top)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1306 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1307 if bit > self.maxBit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1308 self.maxBit = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1309 self.flagBits[flag] = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1310 self.flagCalc[flag] = calc
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1311 self.flagStorage[flag] = storage
1747 89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	1312 storage,_,storebit = storage.partition('.')
89ddf41a50bb Optimization of flag calculation for flags that just copy a bit from the result in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1745 diff changeset	1313 self.storageToFlags.setdefault(storage, []).append((storebit, flag))
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1314 self.flagOrder.append(flag)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1315 return self
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1316
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1317 def getStorage(self, flag):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1318 if not flag in self.flagStorage:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1319 raise Exception('Undefined flag ' + flag)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1320 loc,_,bit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1321 if bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1322 return (loc, int(bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1323 else:
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1324 return loc
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1325
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1326 def parseFlagUpdate(self, flagString):
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1327 last = ''
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1328 autoUpdate = set()
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1329 explicit = {}
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1330 for c in flagString:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1331 if c.isdigit():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1332 if last.isalpha():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1333 num = int(c)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1334 if num > 1:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1335 raise Exception(c + ' is not a valid digit for update_flags')
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1336 explicit[last] = num
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1337 last = c
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1338 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1339 raise Exception('Digit must follow flag letter in update_flags')
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1340 else:
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1341 if last.isalpha():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1342 autoUpdate.add(last)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1343 last = c
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1344 if last.isalpha():
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1345 autoUpdate.add(last)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1346 return (autoUpdate, explicit)
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1347
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1348 def disperseFlags(self, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1349 bitToFlag = [None] * (self.maxBit+1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1350 src = prog.resolveReg(self.flagReg, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1351 output = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1352 for flag in self.flagBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1353 bit = self.flagBits[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1354 if type(bit) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1355 bot,top = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1356 mask = ((1 << (top + 1 - bot)) - 1) << bot
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1357 output.append('\n\t{dst} = {src} & mask;'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1358 dst=prog.resolveReg(self.flagStorage[flag], None, {}), src=src, mask=mask
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1359 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1360 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1361 bitToFlag[self.flagBits[flag]] = flag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1362 multi = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1363 for bit in range(len(bitToFlag)-1,-1,-1):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1364 flag = bitToFlag[bit]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1365 if not flag is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1366 field,_,dstbit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1367 dst = prog.resolveReg(field, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1368 if dstbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1369 dstbit = int(dstbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1370 multi.setdefault(dst, []).append((dstbit, bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1371 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1372 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=(1 << bit)))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1373 for dst in multi:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1374 didClear = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1375 direct = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1376 for dstbit, bit in multi[dst]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1377 if dstbit == bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1378 direct.append(bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1379 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1380 if not didClear:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1381 output.append('\n\t{dst} = 0;'.format(dst=dst))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1382 didClear = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1383 if dstbit > bit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1384 shift = '<<'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1385 diff = dstbit - bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1386 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1387 shift = '>>'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1388 diff = bit - dstbit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1389 output.append('\n\t{dst} \|= {src} {shift} {diff} & {mask};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1390 src=src, dst=dst, shift=shift, diff=diff, mask=(1 << dstbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1391 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1392 if direct:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1393 if len(direct) == len(multi[dst]):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1394 output.append('\n\t{dst} = {src};'.format(dst=dst, src=src))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1395 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1396 mask = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1397 for bit in direct:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1398 mask = mask \| (1 << bit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1399 output.append('\n\t{dst} = {src} & {mask};'.format(dst=dst, src=src, mask=mask))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1400 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1401
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1402 def coalesceFlags(self, prog, otype):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1403 dst = prog.resolveReg(self.flagReg, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1404 output = ['\n\t{dst} = 0;'.format(dst=dst)]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1405 bitToFlag = [None] * (self.maxBit+1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1406 for flag in self.flagBits:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1407 bit = self.flagBits[flag]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1408 if type(bit) is tuple:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1409 bot,_ = bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1410 src = prog.resolveReg(self.flagStorage[flag], None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1411 if bot:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1412 output.append('\n\t{dst} \|= {src} << {shift};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1413 dst=dst, src = src, shift = bot
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1414 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1415 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1416 output.append('\n\t{dst} \|= {src};'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1417 dst=dst, src = src
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1418 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1419 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1420 bitToFlag[bit] = flag
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1421 multi = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1422 for bit in range(len(bitToFlag)-1,-1,-1):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1423 flag = bitToFlag[bit]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1424 if not flag is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1425 field,_,srcbit = self.flagStorage[flag].partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1426 src = prog.resolveReg(field, None, {})
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1427 if srcbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1428 srcbit = int(srcbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1429 multi.setdefault(src, []).append((srcbit,bit))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1430 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1431 output.append('\n\tif ({src}) {{\n\t\t{dst} \|= 1 << {bit};\n\t}}'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1432 dst=dst, src=src, bit=bit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1433 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1434 for src in multi:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1435 direct = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1436 for srcbit, dstbit in multi[src]:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1437 if srcbit == dstbit:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1438 direct = direct \| (1 << srcbit)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1439 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1440 output.append('\n\tif ({src} & (1 << {srcbit})) {{\n\t\t{dst} \|= 1 << {dstbit};\n\t}}'.format(
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1441 src=src, dst=dst, srcbit=srcbit, dstbit=dstbit
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1442 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1443 if direct:
1698 90272218469c Fixed missing semicolon in coalesceFlags Michael Pavone <pavone@retrodev.com> parents: 1697 diff changeset	1444 output.append('\n\t{dst} \|= {src} & {mask};'.format(
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1445 dst=dst, src=src, mask=direct
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1446 ))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1447 return ''.join(output)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1448
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1449
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1450 class Program:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1451 def __init__(self, regs, instructions, subs, info, flags):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1452 self.regs = regs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1453 self.instructions = instructions
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1454 self.subroutines = subs
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1455 self.meta = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1456 self.booleans = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1457 self.prefix = info.get('prefix', [''])[0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1458 self.opsize = int(info.get('opcode_size', ['8'])[0])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1459 self.extra_tables = info.get('extra_tables', [])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1460 self.context_type = self.prefix + 'context'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1461 self.body = info.get('body', [None])[0]
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1462 self.interrupt = info.get('interrupt', [None])[0]
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1463 self.sync_cycle = info.get('sync_cycle', [None])[0]
1620 a172f97d873f Add the ability for a CPU definition to reference arbitrary C includes and use it to add a placeholder definition of svp_read_16 Michael Pavone <pavone@retrodev.com> parents: 1619 diff changeset	1464 self.includes = info.get('include', [])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1465 self.flags = flags
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1466 self.lastDst = None
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1467 self.scopes = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1468 self.currentScope = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1469 self.lastOp = None
1704 89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1470 self.carryFlowDst = None
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1471 self.lastA = None
89932fd29abd First stab at carry and half-carry calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1703 diff changeset	1472 self.lastB = None
1708 5bfed2eedc9d Fixed flag calculation for sub instructions in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1707 diff changeset	1473 self.lastBFlow = None
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1474 self.sizeAdjust = None
1737 2207cd2bae14 Fixed some issues involving conditional execution and temporaries/constant folding Michael Pavone <pavone@retrodev.com> parents: 1735 diff changeset	1475 self.conditional = False
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	1476 self.declares = []
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1477 self.lastSize = None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1478
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1479 def __str__(self):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1480 pieces = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1481 for reg in self.regs:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1482 pieces.append(str(self.regs[reg]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1483 for name in self.subroutines:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1484 pieces.append('\n'+str(self.subroutines[name]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1485 for instruction in self.instructions:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1486 pieces.append('\n'+str(instruction))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1487 return ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1488
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1489 def writeHeader(self, otype, header):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1490 hFile = open(header, 'w')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1491 macro = header.upper().replace('.', '_')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1492 hFile.write('#ifndef {0}_'.format(macro))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1493 hFile.write('\n#define {0}_'.format(macro))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1494 hFile.write('\n#include "backend.h"')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1495 hFile.write('\n\ntypedef struct {')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1496 hFile.write('\n\tcpu_options gen;')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1497 hFile.write('\n}} {0}options;'.format(self.prefix))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1498 hFile.write('\n\ntypedef struct {')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1499 hFile.write('\n\t{0}options *opts;'.format(self.prefix))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1500 self.regs.writeHeader(otype, hFile)
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1501 hFile.write('\n}} {0}context;'.format(self.prefix))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1502 hFile.write('\n')
1703 49a52c737bf0 Fix zero flag calculation in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1702 diff changeset	1503 hFile.write('\nvoid {pre}execute({type} *context, uint32_t target_cycle);'.format(pre = self.prefix, type = self.context_type))
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	1504 for decl in self.declares:
48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	1505 hFile.write('\n' + decl)
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1506 hFile.write('\n#endif //{0}_'.format(macro))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1507 hFile.write('\n')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1508 hFile.close()
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1509
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1510 def _buildTable(self, otype, table, body, lateBody):
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1511 pieces = []
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1512 opmap = [None] * (1 << self.opsize)
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1513 bodymap = {}
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1514 if table in self.instructions:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1515 instructions = self.instructions[table]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1516 instructions.sort()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1517 for inst in instructions:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1518 for val in inst.allValues():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1519 if opmap[val] is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1520 self.meta = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1521 self.temp = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1522 self.needFlagCoalesce = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1523 self.needFlagDisperse = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1524 self.lastOp = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1525 opmap[val] = inst.generateName(val)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1526 bodymap[val] = inst.generateBody(val, self, otype)
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1527
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1528 if self.dispatch == 'call':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1529 pieces.append('\nstatic impl_fun impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap)))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1530 for inst in range(0, len(opmap)):
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1531 op = opmap[inst]
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1532 if op is None:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1533 pieces.append('\n\tunimplemented,')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1534 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1535 pieces.append('\n\t' + op + ',')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1536 body.append(bodymap[inst])
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1537 pieces.append('\n};')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1538 elif self.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1539 body.append('\n\tstatic void *impl_{name}[{sz}] = {{'.format(name = table, sz=len(opmap)))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1540 for inst in range(0, len(opmap)):
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1541 op = opmap[inst]
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1542 if op is None:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1543 body.append('\n\t\t&&unimplemented,')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1544 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1545 body.append('\n\t\t&&' + op + ',')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1546 lateBody.append(bodymap[inst])
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1547 body.append('\n\t};')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1548 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1549 raise Exception("unimplmeneted dispatch type " + self.dispatch)
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1550 body.extend(pieces)
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1551
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1552 def nextInstruction(self, otype):
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1553 output = []
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1554 if self.dispatch == 'goto':
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1555 if self.interrupt in self.subroutines:
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	1556 output.append('\n\tif (context->cycles >= context->sync_cycle) {')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1557 output.append('\n\tif (context->cycles >= target_cycle) { return; }')
1752 d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1558 if self.interrupt in self.subroutines:
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1559 self.meta = {}
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1560 self.temp = {}
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1561 self.subroutines[self.interrupt].inline(self, [], output, otype, None)
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1562 output.append('\n\t}')
d6d4c006a7b3 Initial attempt at interrupts in new Z80 core and integrating it into main executable Michael Pavone <pavone@retrodev.com> parents: 1750 diff changeset	1563
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1564 self.meta = {}
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1565 self.temp = {}
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1566 self.subroutines[self.body].inline(self, [], output, otype, None)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1567 return output
1700 e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1568
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1569 def build(self, otype):
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1570 body = []
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1571 pieces = []
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1572 for include in self.includes:
e4b4e21a37fa Output tables in order specified by the extra_tables field so the user can deal with dependencies between tables Michael Pavone <pavone@retrodev.com> parents: 1699 diff changeset	1573 body.append('#include "{0}"\n'.format(include))
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1574 if self.dispatch == 'call':
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1575 body.append('\nstatic void unimplemented({pre}context *context, uint32_t target_cycle)'.format(pre = self.prefix))
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1576 body.append('\n{')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1577 body.append('\n\tfatal_error("Unimplemented instruction\\n");')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1578 body.append('\n}\n')
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1579 body.append('\ntypedef void (impl_fun)({pre}context context, uint32_t target_cycle);'.format(pre=self.prefix))
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1580 for table in self.extra_tables:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1581 body.append('\nstatic impl_fun impl_{name}[{sz}];'.format(name = table, sz=(1 << self.opsize)))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1582 body.append('\nstatic impl_fun impl_main[{sz}];'.format(sz=(1 << self.opsize)))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1583 elif self.dispatch == 'goto':
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1584 body.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1585 body.append('\n{')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1586
1740 28ab56ff8cea Implement DD/FD prefixes for instructions that don't reference HL Michael Pavone <pavone@retrodev.com> parents: 1737 diff changeset	1587 for table in self.extra_tables:
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1588 self._buildTable(otype, table, body, pieces)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1589 self._buildTable(otype, 'main', body, pieces)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1590 if self.dispatch == 'call' and self.body in self.subroutines:
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1591 pieces.append('\nvoid {pre}execute({type} *context, uint32_t target_cycle)'.format(pre = self.prefix, type = self.context_type))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1592 pieces.append('\n{')
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	1593 pieces.append('\n\t{sync}(context, target_cycle);'.format(sync=self.sync_cycle))
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1594 pieces.append('\n\twhile (context->cycles < target_cycle)')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1595 pieces.append('\n\t{')
1883 9ab5184811ea Implement interrupts in call dispatch mode in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1838 diff changeset	1596 if self.interrupt in self.subroutines:
9ab5184811ea Implement interrupts in call dispatch mode in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1838 diff changeset	1597 pieces.append('\n\t\tif (context->cycles >= context->sync_cycle) {')
9ab5184811ea Implement interrupts in call dispatch mode in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1838 diff changeset	1598 self.meta = {}
9ab5184811ea Implement interrupts in call dispatch mode in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1838 diff changeset	1599 self.temp = {}
1938 1dae90605199 Fix autogenerated temp variables in interrupt subroutine in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1883 diff changeset	1600 intpieces = []
1dae90605199 Fix autogenerated temp variables in interrupt subroutine in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1883 diff changeset	1601 self.subroutines[self.interrupt].inline(self, [], intpieces, otype, None)
1dae90605199 Fix autogenerated temp variables in interrupt subroutine in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1883 diff changeset	1602 for size in self.temp:
1dae90605199 Fix autogenerated temp variables in interrupt subroutine in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1883 diff changeset	1603 pieces.append('\n\tuint{sz}_t gen_tmp{sz}__;'.format(sz=size))
1dae90605199 Fix autogenerated temp variables in interrupt subroutine in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1883 diff changeset	1604 pieces += intpieces
1883 9ab5184811ea Implement interrupts in call dispatch mode in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1838 diff changeset	1605 pieces.append('\n\t\t}')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1606 self.meta = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1607 self.temp = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1608 self.subroutines[self.body].inline(self, [], pieces, otype, None)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1609 pieces.append('\n\t}')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1610 pieces.append('\n}')
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1611 elif self.dispatch == 'goto':
1759 6e4faa10f9ee Store sync_cycle in context rather than in a local in CPU DSL. Fix the timing of a number of instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1754 diff changeset	1612 body.append('\n\t{sync}(context, target_cycle);'.format(sync=self.sync_cycle))
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1613 body += self.nextInstruction(otype)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1614 pieces.append('\nunimplemented:')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1615 pieces.append('\n\tfatal_error("Unimplemented instruction\\n");')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1616 pieces.append('\n}')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1617 return ''.join(body) + ''.join(pieces)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1618
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1619 def checkBool(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1620 if not name in self.booleans:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1621 raise Exception(name + ' is not a defined boolean flag')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1622 return self.booleans[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1623
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1624 def getTemp(self, size):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1625 if size in self.temp:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1626 return ('', self.temp[size])
1742 6290c88949bd Fixed CPI/CPD/CPIR/CPDR in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1740 diff changeset	1627 self.temp[size] = 'gen_tmp{sz}__'.format(sz=size);
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1628 return ('', self.temp[size])
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1629
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1630 def resolveParam(self, param, parent, fieldVals, allowConstant=True, isdst=False):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1631 keepGoing = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1632 while keepGoing:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1633 keepGoing = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1634 try:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1635 if type(param) is int:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1636 pass
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1637 elif param.startswith('0x'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1638 param = int(param, 16)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1639 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1640 param = int(param)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1641 except ValueError:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1642
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1643 if parent:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1644 if param in parent.regValues and allowConstant:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1645 return parent.regValues[param]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1646 maybeLocal = parent.resolveLocal(param)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1647 if maybeLocal:
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1648 if isdst:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1649 self.lastDst = param
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1650 self.lastSize = None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1651 return maybeLocal
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1652 if param in fieldVals:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1653 param = fieldVals[param]
1721 0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1654 fieldVals = {}
0e5df2bc0f9f Implementation of some of the rotate instructions in new Z80 core Michael Pavone <pavone@retrodev.com> parents: 1719 diff changeset	1655 keepGoing = True
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1656 elif param in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1657 param = self.meta[param]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1658 keepGoing = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1659 elif self.isReg(param):
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1660 return self.resolveReg(param, parent, fieldVals, isdst)
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1661 elif param in self.regs.pointers:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1662 return 'context->' + param
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1663 if isdst:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1664 self.lastDst = param
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1665 self.lastSize = None
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1666 return param
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1667
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1668 def isReg(self, name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1669 if not type(name) is str:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1670 return False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1671 begin,sep,_ = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1672 if sep:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1673 if begin in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1674 begin = self.meta[begin]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1675 return self.regs.isRegArray(begin)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1676 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1677 return self.regs.isReg(name)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1678
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1679 def resolveReg(self, name, parent, fieldVals, isDst=False):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1680 begin,sep,end = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1681 if sep:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1682 if begin in self.meta:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1683 begin = self.meta[begin]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1684 if not self.regs.isRegArrayMember(end):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1685 end = self.resolveParam(end, parent, fieldVals)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1686 if not type(end) is int and self.regs.isRegArrayMember(end):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1687 arrayName = self.regs.arrayMemberParent(end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1688 end = self.regs.arrayMemberIndex(end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1689 if arrayName != begin:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1690 end = 'context->{0}[{1}]'.format(arrayName, end)
1615 28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1691 if self.regs.isNamedArray(begin):
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1692 regName = self.regs.arrayMemberName(begin, end)
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1693 else:
28f80d1b343e Support immediate operands for ld and alu ops in SVP. Support double indirect and immediate address modes for alu ops. Fixed DSL issues revealed by those changes Michael Pavone <pavone@retrodev.com> parents: 1614 diff changeset	1694 regName = '{0}.{1}'.format(begin, end)
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1695 ret = 'context->{0}[{1}]'.format(begin, end)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1696 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1697 regName = name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1698 if self.regs.isRegArrayMember(name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1699 arr,idx = self.regs.regToArray[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1700 ret = 'context->{0}[{1}]'.format(arr, idx)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1701 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1702 ret = 'context->' + name
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1703 if regName == self.flags.flagReg:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1704 if isDst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1705 self.needFlagDisperse = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1706 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1707 self.needFlagCoalesce = True
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1708 if isDst:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1709 self.lastDst = regName
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1710 return ret
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1711
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1712
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1713
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1714 def paramSize(self, name):
1715 4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1715 if name in self.meta:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1716 return self.paramSize(self.meta[name])
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1717 for i in range(len(self.scopes) -1, -1, -1):
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1718 size = self.scopes[i].localSize(name)
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1719 if size:
4fd84c3efc72 Implement 16-bit addition in new Z80 core along with necessary CPU DSL fixes to make them work right Michael Pavone <pavone@retrodev.com> parents: 1713 diff changeset	1720 return size
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1721 begin,sep,_ = name.partition('.')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1722 if sep and self.regs.isRegArray(begin):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1723 return self.regs.regArrays[begin][0]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1724 if self.regs.isReg(name):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1725 return self.regs.regs[name]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1726 return 32
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1727
1838 0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1728 def getLastSize(self):
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1729 if self.lastSize:
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1730 return self.lastSize
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1731 return self.paramSize(self.lastDst)
0c1491818f4b WIP new 68K core using CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1765 diff changeset	1732
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1733 def pushScope(self, scope):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1734 self.scopes.append(scope)
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1735 self.currentScope = scope
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1736
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1737 def popScope(self):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1738 ret = self.scopes.pop()
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1739 self.currentScope = self.scopes[-1] if self.scopes else None
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1740 return ret
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1741
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1742 def getRootScope(self):
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1743 return self.scopes[0]
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1744
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1745 def parse(args):
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1746 f = args.source
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1747 instructions = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1748 subroutines = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1749 registers = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1750 flags = None
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	1751 declares = []
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1752 errors = []
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1753 info = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1754 line_num = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1755 cur_object = None
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1756 for line in f:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1757 line_num += 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1758 line,_,comment = line.partition('#')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1759 if not line.strip():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1760 continue
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1761 if line[0].isspace():
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1762 if not cur_object is None:
1754 043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	1763 sep = True
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	1764 parts = []
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	1765 while sep:
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	1766 before,sep,after = line.partition('"')
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	1767 before = before.strip()
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	1768 if before:
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	1769 parts += [el.strip() for el in before.split(' ')]
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	1770 if sep:
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	1771 #TODO: deal with escaped quotes
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	1772 inside,sep,after = after.partition('"')
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	1773 parts.append('"' + inside + '"')
043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	1774 line = after
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1775 if type(cur_object) is dict:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1776 cur_object[parts[0]] = parts[1:]
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	1777 elif type(cur_object) is list:
1754 043cf458704c Basic support for string operands in CPU DSL Michael Pavone <pavone@retrodev.com> parents: 1753 diff changeset	1778 cur_object.append(' '.join(parts))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1779 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1780 cur_object = cur_object.processLine(parts)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1781
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1782 # if type(cur_object) is Registers:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1783 # if len(parts) > 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1784 # cur_object.addRegArray(parts[0], int(parts[1]), parts[2:])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1785 # else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1786 # cur_object.addReg(parts[0], int(parts[1]))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1787 # elif type(cur_object) is dict:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1788 # cur_object[parts[0]] = parts[1:]
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1789 # elif parts[0] == 'switch':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1790 # o = Switch(cur_object, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1791 # cur_object.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1792 # cur_object = o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1793 # elif parts[0] == 'if':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1794 # o = If(cur_object, parts[1])
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1795 # cur_object.addOp(o)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1796 # cur_object = o
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1797 # elif parts[0] == 'end':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1798 # cur_object = cur_object.parent
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1799 # else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1800 # cur_object.addOp(NormalOp(parts))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1801 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1802 errors.append("Orphan instruction on line {0}".format(line_num))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1803 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1804 parts = line.split(' ')
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1805 if len(parts) > 1:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1806 if len(parts) > 2:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1807 table,bitpattern,name = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1808 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1809 bitpattern,name = parts
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1810 table = 'main'
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1811 value = 0
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1812 fields = {}
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1813 curbit = len(bitpattern) - 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1814 for char in bitpattern:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1815 value <<= 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1816 if char in ('0', '1'):
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1817 value \|= int(char)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1818 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1819 if char in fields:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1820 fields[char] = (curbit, fields[char][1] + 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1821 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1822 fields[char] = (curbit, 1)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1823 curbit -= 1
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1824 cur_object = Instruction(value, fields, name.strip())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1825 instructions.setdefault(table, []).append(cur_object)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1826 elif line.strip() == 'regs':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1827 if registers is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1828 registers = Registers()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1829 cur_object = registers
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1830 elif line.strip() == 'info':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1831 cur_object = info
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1832 elif line.strip() == 'flags':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1833 if flags is None:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1834 flags = Flags()
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1835 cur_object = flags
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	1836 elif line.strip() == 'declare':
48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	1837 cur_object = declares
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1838 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1839 cur_object = SubRoutine(line.strip())
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1840 subroutines[cur_object.name] = cur_object
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1841 if errors:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1842 print(errors)
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1843 else:
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1844 p = Program(registers, instructions, subroutines, info, flags)
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1845 p.dispatch = args.dispatch
1748 48a43dff4dc0 Added init functions to z80_util.c so new Z80 core is closer to a drop in replacement for the old one Michael Pavone <pavone@retrodev.com> parents: 1747 diff changeset	1846 p.declares = declares
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1847 p.booleans['dynarec'] = False
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1848 p.booleans['interp'] = True
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1849 if args.define:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1850 for define in args.define:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1851 name,sep,val = define.partition('=')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1852 name = name.strip()
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1853 val = val.strip()
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1854 if sep:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1855 p.booleans[name] = bool(val)
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1856 else:
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1857 p.booleans[name] = True
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1858
1618 5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1859 if 'header' in info:
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1860 print('#include "{0}"'.format(info['header'][0]))
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1861 p.writeHeader('c', info['header'][0])
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1862 print('#include "util.h"')
5dbc453cd345 Getting SVP core closer to compiling Michael Pavone <pavone@retrodev.com> parents: 1616 diff changeset	1863 print('#include <stdlib.h>')
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1864 print(p.build('c'))
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1865
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1866 def main(argv):
1749 e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1867 from argparse import ArgumentParser, FileType
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1868 argParser = ArgumentParser(description='CPU emulator DSL compiler')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1869 argParser.add_argument('source', type=FileType('r'))
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1870 argParser.add_argument('-D', '--define', action='append')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1871 argParser.add_argument('-d', '--dispatch', choices=('call', 'switch', 'goto'), default='call')
e4fe5a450d05 Added option to CPU DSL to produce a threaded interpreter using computed goto Michael Pavone <pavone@retrodev.com> parents: 1748 diff changeset	1872 parse(argParser.parse_args(argv[1:]))
1613 2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1873
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1874 if __name__ == '__main__':
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1875 from sys import argv
2d9e8a7b8ba2 Initial commit of CPU DSL and a WIP SVP implementation written in that DSL Michael Pavone <pavone@retrodev.com> parents: diff changeset	1876 main(argv)

Mercurial > repos > blastem

annotate cpu_dsl.py @ 1968:c16dabdb0aad