repos/blastem: z80_to_x86.c annotate

annotate z80_to_x86.c @ 620:9d6fed6501ba

Fix handling of code writes for Z80 core. This seems to get things close to being back to where they were before the big refactor that broke the Z80 core. Some problems remain. Notably the sound driver in Sonic 2 is still quite broken.

author	Michael Pavone <pavone@retrodev.com>
date	Mon, 29 Dec 2014 23:08:39 -0800
parents	f0061e3d2ad9
children	f822d9216968

rev	line source
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	1 /*
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	2 Copyright 2013 Michael Pavone
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	3 This file is part of BlastEm.
467 140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	4 BlastEm is free software distributed under the terms of the GNU General Public License version 3 or greater. See COPYING for full license text.
140af5509ce7 Added copyright notice to source files and added GPL license text in COPYING Mike Pavone <pavone@retrodev.com> parents: 424 diff changeset	5 */
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	6 #include "z80inst.h"
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	7 #include "z80_to_x86.h"
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	8 #include "gen_x86.h"
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	9 #include "mem.h"
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	10 #include <stdio.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	11 #include <stdlib.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	12 #include <stddef.h>
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	13 #include <string.h>
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	14
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	15 #define MODE_UNUSED (MODE_IMMED-1)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	16
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	17 #define ZCYCLES RBP
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	18 #define ZLIMIT RDI
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	19 #define SCRATCH1 R13
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	20 #define SCRATCH2 R14
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	21 #define CONTEXT RSI
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	22
315 684e71e9f0d0 Fix return address for RST Mike Pavone <pavone@retrodev.com> parents: 314 diff changeset	23 //#define DO_DEBUG_PRINT
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	24
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	25 #ifdef DO_DEBUG_PRINT
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	26 #define dprintf printf
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	27 #else
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	28 #define dprintf
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	29 #endif
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	30
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	31 uint8_t z80_size(z80inst * inst)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	32 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	33 uint8_t reg = (inst->reg & 0x1F);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	34 if (reg != Z80_UNUSED && reg != Z80_USE_IMMED) {
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	35 return reg < Z80_BC ? SZ_B : SZ_W;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	36 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	37 //TODO: Handle any necessary special cases
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	38 return SZ_B;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	39 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	40
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	41 void translate_z80_reg(z80inst * inst, host_ea * ea, z80_options * opts)
250 5f1b68cecfc7 Implemented basic interrupt support in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 248 diff changeset	42 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	43 code_info *code = &opts->gen.code;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	44 if (inst->reg == Z80_USE_IMMED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	45 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	46 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	47 } else if ((inst->reg & 0x1F) == Z80_UNUSED) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	48 ea->mode = MODE_UNUSED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	49 } else {
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	50 ea->mode = MODE_REG_DIRECT;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	51 if (inst->reg == Z80_IYH) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	52 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	53 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	54 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	55 ea->base = opts->gen.scratch1;
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	56 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	57 ea->base = opts->regs[Z80_IYL];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	58 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	59 }
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	60 } else if(opts->regs[inst->reg] >= 0) {
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	61 ea->base = opts->regs[inst->reg];
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	62 if (ea->base >= AH && ea->base <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	63 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	64 uint8_t other_reg = opts->regs[inst->ea_reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	65 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	66 //we can't mix an *H reg with a register that requires the REX prefix
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	67 ea->base = opts->regs[z80_low_reg(inst->reg)];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	68 ror_ir(code, 8, ea->base, SZ_W);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	69 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	70 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	71 //temp regs require REX prefix too
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	72 ea->base = opts->regs[z80_low_reg(inst->reg)];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	73 ror_ir(code, 8, ea->base, SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	74 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	75 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	76 } else {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	77 ea->mode = MODE_REG_DISPLACE8;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	78 ea->base = opts->gen.context_reg;
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	79 ea->disp = offsetof(z80_context, regs) + inst->reg;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	80 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	81 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	82 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	83
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	84 void z80_save_reg(z80inst * inst, z80_options * opts)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	85 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	86 code_info *code = &opts->gen.code;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	87 if (inst->reg == Z80_IYH) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	88 if ((inst->addr_mode & 0x1F) == Z80_REG && inst->ea_reg == Z80_IYL) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	89 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	90 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	91 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	92 } else {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	93 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	94 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	95 } else if (opts->regs[inst->reg] >= AH && opts->regs[inst->reg] <= BH) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	96 if ((inst->addr_mode & 0x1F) == Z80_REG) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	97 uint8_t other_reg = opts->regs[inst->ea_reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	98 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	99 //we can't mix an *H reg with a register that requires the REX prefix
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	100 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	101 }
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	102 } else if((inst->addr_mode & 0x1F) != Z80_UNUSED && (inst->addr_mode & 0x1F) != Z80_IMMED) {
6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	103 //temp regs require REX prefix too
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	104 ror_ir(code, 8, opts->regs[z80_low_reg(inst->reg)], SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	105 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	106 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	107 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	108
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	109 void translate_z80_ea(z80inst * inst, host_ea * ea, z80_options * opts, uint8_t read, uint8_t modify)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	110 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	111 code_info *code = &opts->gen.code;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	112 uint8_t size, reg, areg;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	113 ea->mode = MODE_REG_DIRECT;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	114 areg = read ? opts->gen.scratch1 : opts->gen.scratch2;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	115 switch(inst->addr_mode & 0x1F)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	116 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	117 case Z80_REG:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	118 if (inst->ea_reg == Z80_IYH) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	119 if (inst->reg == Z80_IYL) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	120 mov_rr(code, opts->regs[Z80_IY], opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	121 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	122 ea->base = opts->gen.scratch1;
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	123 } else {
cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	124 ea->base = opts->regs[Z80_IYL];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	125 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	126 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	127 } else {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	128 ea->base = opts->regs[inst->ea_reg];
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	129 if (ea->base >= AH && ea->base <= BH && inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	130 uint8_t other_reg = opts->regs[inst->reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	131 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	132 //we can't mix an *H reg with a register that requires the REX prefix
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	133 ea->base = opts->regs[z80_low_reg(inst->ea_reg)];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	134 ror_ir(code, 8, ea->base, SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	135 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	136 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	137 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	138 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	139 case Z80_REG_INDIRECT:
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	140 mov_rr(code, opts->regs[inst->ea_reg], areg, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	141 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	142 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	143 if (modify) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	144 //push_r(code, opts->gen.scratch1);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	145 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	146 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	147 if (size == SZ_B) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	148 call(code, opts->read_8);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	149 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	150 call(code, opts->read_16);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	151 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	152 if (modify) {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	153 //pop_r(code, opts->gen.scratch2);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	154 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	155 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	156 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	157 ea->base = opts->gen.scratch1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	158 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	159 case Z80_IMMED:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	160 ea->mode = MODE_IMMED;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	161 ea->disp = inst->immed;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	162 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	163 case Z80_IMMED_INDIRECT:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	164 mov_ir(code, inst->immed, areg, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	165 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	166 if (read) {
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	167 /*if (modify) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	168 push_r(code, opts->gen.scratch1);
277 765e132edd71 Using push/pop inside translated code is not compatible with the current way the Z80 core returns to the caller Mike Pavone <pavone@retrodev.com> parents: 275 diff changeset	169 }*/
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	170 if (size == SZ_B) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	171 call(code, opts->read_8);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	172 } else {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	173 call(code, opts->read_16);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	174 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	175 if (modify) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	176 //pop_r(code, opts->gen.scratch2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	177 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	178 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	179 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	180 ea->base = opts->gen.scratch1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	181 break;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	182 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	183 case Z80_IY_DISPLACE:
300 9adc1dce39bf Fix IX/IY register selection when the direction bit is set Mike Pavone <pavone@retrodev.com> parents: 299 diff changeset	184 reg = opts->regs[(inst->addr_mode & 0x1F) == Z80_IX_DISPLACE ? Z80_IX : Z80_IY];
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	185 mov_rr(code, reg, areg, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	186 add_ir(code, inst->ea_reg & 0x80 ? inst->ea_reg - 256 : inst->ea_reg, areg, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	187 size = z80_size(inst);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	188 if (read) {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	189 if (modify) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	190 //push_r(code, opts->gen.scratch1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	191 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	192 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	193 if (size == SZ_B) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	194 call(code, opts->read_8);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	195 } else {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	196 call(code, opts->read_16);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	197 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	198 if (modify) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	199 //pop_r(code, opts->gen.scratch2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	200 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, scratch1), opts->gen.scratch2, SZ_W);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	201 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	202 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	203 ea->base = opts->gen.scratch1;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	204 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	205 case Z80_UNUSED:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	206 ea->mode = MODE_UNUSED;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	207 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	208 default:
300 9adc1dce39bf Fix IX/IY register selection when the direction bit is set Mike Pavone <pavone@retrodev.com> parents: 299 diff changeset	209 fprintf(stderr, "Unrecognized Z80 addressing mode %d\n", inst->addr_mode & 0x1F);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	210 exit(1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	211 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	212 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	213
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	214 void z80_save_ea(code_info code, z80inst inst, z80_options * opts)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	215 {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	216 if ((inst->addr_mode & 0x1F) == Z80_REG) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	217 if (inst->ea_reg == Z80_IYH) {
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	218 if (inst->reg == Z80_IYL) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	219 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	220 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_IYL], SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	221 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	222 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	223 ror_ir(code, 8, opts->regs[Z80_IY], SZ_W);
312 cf7ecda060c7 Properly handle instructions that use boty IYH and IYL Mike Pavone <pavone@retrodev.com> parents: 311 diff changeset	224 }
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	225 } else if (inst->reg != Z80_UNUSED && inst->reg != Z80_USE_IMMED && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	226 uint8_t other_reg = opts->regs[inst->reg];
269 3c054d977175 Fix IX/IY displace modes. Fix check for registers requiring REX. Mike Pavone <pavone@retrodev.com> parents: 268 diff changeset	227 if (other_reg >= R8 \|\| (other_reg >= RSP && other_reg <= RDI)) {
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	228 //we can't mix an *H reg with a register that requires the REX prefix
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	229 ror_ir(code, 8, opts->regs[z80_low_reg(inst->ea_reg)], SZ_W);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	230 }
1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	231 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	232 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	233 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	234
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	235 void z80_save_result(z80_options opts, z80inst inst)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	236 {
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	237 switch(inst->addr_mode & 0x1f)
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	238 {
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	239 case Z80_REG_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	240 case Z80_IMMED_INDIRECT:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	241 case Z80_IX_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	242 case Z80_IY_DISPLACE:
3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	243 if (z80_size(inst) == SZ_B) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	244 call(&opts->gen.code, opts->write_8);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	245 } else {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	246 call(&opts->gen.code, opts->write_16_lowfirst);
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	247 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	248 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	249 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	250
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	251 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	252 DONT_READ=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	253 READ
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	254 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	255
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	256 enum {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	257 DONT_MODIFY=0,
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	258 MODIFY
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	259 };
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	260
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	261 uint8_t zf_off(uint8_t flag)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	262 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	263 return offsetof(z80_context, flags) + flag;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	264 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	265
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	266 uint8_t zaf_off(uint8_t flag)
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	267 {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	268 return offsetof(z80_context, alt_flags) + flag;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	269 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	270
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	271 uint8_t zar_off(uint8_t reg)
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	272 {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	273 return offsetof(z80_context, alt_regs) + reg;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	274 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	275
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	276 void z80_print_regs_exit(z80_context * context)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	277 {
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	278 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\nSP: %X\n\nIM: %d, IFF1: %d, IFF2: %d\n",
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	279 context->regs[Z80_A], context->regs[Z80_B], context->regs[Z80_C],
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	280 context->regs[Z80_D], context->regs[Z80_E],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	281 (context->regs[Z80_H] << 8) \| context->regs[Z80_L],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	282 (context->regs[Z80_IXH] << 8) \| context->regs[Z80_IXL],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	283 (context->regs[Z80_IYH] << 8) \| context->regs[Z80_IYL],
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	284 context->sp, context->im, context->iff1, context->iff2);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	285 puts("--Alternate Regs--");
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	286 printf("A: %X\nB: %X\nC: %X\nD: %X\nE: %X\nHL: %X\nIX: %X\nIY: %X\n",
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	287 context->alt_regs[Z80_A], context->alt_regs[Z80_B], context->alt_regs[Z80_C],
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	288 context->alt_regs[Z80_D], context->alt_regs[Z80_E],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	289 (context->alt_regs[Z80_H] << 8) \| context->alt_regs[Z80_L],
b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	290 (context->alt_regs[Z80_IXH] << 8) \| context->alt_regs[Z80_IXL],
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	291 (context->alt_regs[Z80_IYH] << 8) \| context->alt_regs[Z80_IYL]);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	292 exit(0);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	293 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	294
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	295 void translate_z80inst(z80inst * inst, z80_context * context, uint16_t address)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	296 {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	297 uint32_t num_cycles;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	298 host_ea src_op, dst_op;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	299 uint8_t size;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	300 z80_options *opts = context->options;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	301 uint8_t * start = opts->gen.code.cur;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	302 code_info *code = &opts->gen.code;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	303 check_cycles_int(&opts->gen, address);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	304 switch(inst->op)
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	305 {
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	306 case Z80_LD:
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	307 size = z80_size(inst);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	308 switch (inst->addr_mode & 0x1F)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	309 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	310 case Z80_REG:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	311 case Z80_REG_INDIRECT:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	312 num_cycles = size == SZ_B ? 4 : 6;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	313 if (inst->ea_reg == Z80_IX \|\| inst->ea_reg == Z80_IY) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	314 num_cycles += 4;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	315 }
506 a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core Michael Pavone <pavone@retrodev.com> parents: 505 diff changeset	316 if (inst->reg == Z80_I \|\| inst->ea_reg == Z80_I) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	317 num_cycles += 5;
506 a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core Michael Pavone <pavone@retrodev.com> parents: 505 diff changeset	318 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	319 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	320 case Z80_IMMED:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	321 num_cycles = size == SZ_B ? 7 : 10;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	322 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	323 case Z80_IMMED_INDIRECT:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	324 num_cycles = 10;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	325 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	326 case Z80_IX_DISPLACE:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	327 case Z80_IY_DISPLACE:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	328 num_cycles = 16;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	329 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	330 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	331 if ((inst->reg >= Z80_IXL && inst->reg <= Z80_IYH) \|\| inst->reg == Z80_IX \|\| inst->reg == Z80_IY) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	332 num_cycles += 4;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	333 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	334 cycles(&opts->gen, num_cycles);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	335 if (inst->addr_mode & Z80_DIR) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	336 translate_z80_ea(inst, &dst_op, opts, DONT_READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	337 translate_z80_reg(inst, &src_op, opts);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	338 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	339 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	340 translate_z80_reg(inst, &dst_op, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	341 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	342 if (src_op.mode == MODE_REG_DIRECT) {
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	343 if(dst_op.mode == MODE_REG_DISPLACE8) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	344 mov_rrdisp(code, src_op.base, dst_op.base, dst_op.disp, size);
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	345 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	346 mov_rr(code, src_op.base, dst_op.base, size);
262 d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	347 }
d97c9eca49f4 Implement ld to and from the I and R registers Mike Pavone <pavone@retrodev.com> parents: 261 diff changeset	348 } else if(src_op.mode == MODE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	349 mov_ir(code, src_op.disp, dst_op.base, size);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	350 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	351 mov_rdispr(code, src_op.base, src_op.disp, dst_op.base, size);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	352 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	353 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	354 z80_save_ea(code, inst, opts);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	355 if (inst->addr_mode & Z80_DIR) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	356 z80_save_result(opts, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	357 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	358 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	359 case Z80_PUSH:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	360 cycles(&opts->gen, (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) ? 9 : 5);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	361 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	362 if (inst->reg == Z80_AF) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	363 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	364 shl_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	365 mov_rdispr(code, opts->gen.context_reg, zf_off(ZF_S), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	366 shl_ir(code, 1, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	367 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_Z), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	368 shl_ir(code, 2, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	369 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_H), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	370 shl_ir(code, 2, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	371 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_PV), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	372 shl_ir(code, 1, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	373 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_N), opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	374 shl_ir(code, 1, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	375 or_rdispr(code, opts->gen.context_reg, zf_off(ZF_C), opts->gen.scratch1, SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	376 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	377 translate_z80_reg(inst, &src_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	378 mov_rr(code, src_op.base, opts->gen.scratch1, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	379 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	380 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	381 call(code, opts->write_16_highfirst);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	382 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	383 //the upper half of a register pair
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	384 break;
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	385 case Z80_POP:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	386 cycles(&opts->gen, (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) ? 8 : 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	387 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	388 call(code, opts->read_16);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	389 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	390 if (inst->reg == Z80_AF) {
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	391
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	392 bt_ir(code, 0, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	393 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	394 bt_ir(code, 1, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	395 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_N));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	396 bt_ir(code, 2, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	397 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	398 bt_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	399 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_H));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	400 bt_ir(code, 6, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	401 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	402 bt_ir(code, 7, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	403 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	404 shr_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	405 mov_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	406 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	407 translate_z80_reg(inst, &src_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	408 mov_rr(code, opts->gen.scratch1, src_op.base, SZ_W);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	409 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	410 //no call to save_z80_reg needed since there's no chance we'll use the only
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	411 //the upper half of a register pair
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	412 break;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	413 case Z80_EX:
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	414 if (inst->addr_mode == Z80_REG \|\| inst->reg == Z80_HL) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	415 num_cycles = 4;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	416 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	417 num_cycles = 8;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	418 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	419 cycles(&opts->gen, num_cycles);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	420 if (inst->addr_mode == Z80_REG) {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	421 if(inst->reg == Z80_AF) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	422 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	423 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_A), opts->regs[Z80_A], SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	424 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_A), SZ_B);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	425
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	426 //Flags are currently word aligned, so we can move
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	427 //them efficiently a word at a time
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	428 for (int f = ZF_C; f < ZF_NUM; f+=2) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	429 mov_rdispr(code, opts->gen.context_reg, zf_off(f), opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	430 mov_rdispr(code, opts->gen.context_reg, zaf_off(f), opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	431 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zaf_off(f), SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	432 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zf_off(f), SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	433 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	434 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	435 xchg_rr(code, opts->regs[Z80_DE], opts->regs[Z80_HL], SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	436 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	437 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	438 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	439 call(code, opts->read_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	440 xchg_rr(code, opts->regs[inst->reg], opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	441 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	442 call(code, opts->write_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	443 cycles(&opts->gen, 1);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	444 uint8_t high_reg = z80_high_reg(inst->reg);
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	445 uint8_t use_reg;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	446 //even though some of the upper halves can be used directly
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	447 //the limitations on mixing *H regs with the REX prefix
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	448 //prevent us from taking advantage of it
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	449 use_reg = opts->regs[inst->reg];
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	450 ror_ir(code, 8, use_reg, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	451 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	452 add_ir(code, 1, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	453 call(code, opts->read_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	454 xchg_rr(code, use_reg, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	455 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	456 add_ir(code, 1, opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	457 call(code, opts->write_8);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	458 //restore reg to normal rotation
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	459 ror_ir(code, 8, use_reg, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	460 cycles(&opts->gen, 2);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	461 }
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	462 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	463 case Z80_EXX:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	464 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	465 mov_rr(code, opts->regs[Z80_BC], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	466 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	467 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_C), opts->regs[Z80_BC], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	468 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_L), opts->regs[Z80_HL], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	469 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_C), SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	470 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, zar_off(Z80_L), SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	471 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	472 mov_rdispr(code, opts->gen.context_reg, zar_off(Z80_E), opts->regs[Z80_DE], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	473 mov_rrdisp(code, opts->gen.scratch1, opts->gen.context_reg, zar_off(Z80_E), SZ_W);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	474 break;
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	475 case Z80_LDI: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	476 cycles(&opts->gen, 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	477 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	478 call(code, opts->read_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	479 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	480 call(code, opts->write_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	481 cycles(&opts->gen, 2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	482 add_ir(code, 1, opts->regs[Z80_DE], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	483 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	484 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	485 //TODO: Implement half-carry
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	486 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	487 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
272 9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	488 break;
9b04b57434b5 Implement LDI Mike Pavone <pavone@retrodev.com> parents: 269 diff changeset	489 }
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	490 case Z80_LDIR: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	491 cycles(&opts->gen, 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	492 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	493 call(code, opts->read_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	494 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	495 call(code, opts->write_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	496 add_ir(code, 1, opts->regs[Z80_DE], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	497 add_ir(code, 1, opts->regs[Z80_HL], SZ_W);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	498
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	499 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	500 uint8_t * cont = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	501 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	502 cycles(&opts->gen, 7);
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	503 //TODO: Figure out what the flag state should be here
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	504 //TODO: Figure out whether an interrupt can interrupt this
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	505 jmp(code, start);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	506 *cont = code->cur - (cont + 1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	507 cycles(&opts->gen, 2);
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	508 //TODO: Implement half-carry
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	509 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	510 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
261 f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	511 break;
f0c53a4bbfa3 Implement LDIR and fix a bug in which context was not restored after a call to z80_handle_code_write Mike Pavone <pavone@retrodev.com> parents: 259 diff changeset	512 }
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	513 case Z80_LDD: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	514 cycles(&opts->gen, 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	515 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	516 call(code, opts->read_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	517 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	518 call(code, opts->write_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	519 cycles(&opts->gen, 2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	520 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	521 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	522 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	523 //TODO: Implement half-carry
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	524 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	525 setcc_rdisp(code, CC_NZ, opts->gen.context_reg, zf_off(ZF_PV));
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	526 break;
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	527 }
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	528 case Z80_LDDR: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	529 cycles(&opts->gen, 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	530 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	531 call(code, opts->read_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	532 mov_rr(code, opts->regs[Z80_DE], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	533 call(code, opts->write_8);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	534 sub_ir(code, 1, opts->regs[Z80_DE], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	535 sub_ir(code, 1, opts->regs[Z80_HL], SZ_W);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	536
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	537 sub_ir(code, 1, opts->regs[Z80_BC], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	538 uint8_t * cont = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	539 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	540 cycles(&opts->gen, 7);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	541 //TODO: Figure out what the flag state should be here
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	542 //TODO: Figure out whether an interrupt can interrupt this
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	543 jmp(code, start);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	544 *cont = code->cur - (cont + 1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	545 cycles(&opts->gen, 2);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	546 //TODO: Implement half-carry
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	547 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	548 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
273 719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	549 break;
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	550 }
719b9fea2fe9 Implement LDD and LDDR Mike Pavone <pavone@retrodev.com> parents: 272 diff changeset	551 /*case Z80_CPI:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	552 case Z80_CPIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	553 case Z80_CPD:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	554 case Z80_CPDR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	555 break;*/
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	556 case Z80_ADD:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	557 num_cycles = 4;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	558 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	559 num_cycles += 12;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	560 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	561 num_cycles += 3;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	562 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	563 num_cycles += 4;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	564 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	565 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	566 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	567 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	568 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	569 add_rr(code, src_op.base, dst_op.base, z80_size(inst));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	570 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	571 add_ir(code, src_op.disp, dst_op.base, z80_size(inst));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	572 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	573 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	574 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	575 //TODO: Implement half-carry flag
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	576 if (z80_size(inst) == SZ_B) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	577 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	578 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	579 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	580 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	581 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	582 z80_save_ea(code, inst, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	583 break;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	584 case Z80_ADC:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	585 num_cycles = 4;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	586 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	587 num_cycles += 12;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	588 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	589 num_cycles += 3;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	590 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	591 num_cycles += 4;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	592 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	593 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	594 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	595 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	596 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	597 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	598 adc_rr(code, src_op.base, dst_op.base, z80_size(inst));
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	599 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	600 adc_ir(code, src_op.disp, dst_op.base, z80_size(inst));
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	601 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	602 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	603 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	604 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	605 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	606 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	607 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	608 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	609 z80_save_ea(code, inst, opts);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	610 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	611 case Z80_SUB:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	612 num_cycles = 4;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	613 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	614 num_cycles += 12;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	615 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	616 num_cycles += 3;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	617 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	618 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	619 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	620 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	621 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	622 sub_rr(code, src_op.base, dst_op.base, z80_size(inst));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	623 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	624 sub_ir(code, src_op.disp, dst_op.base, z80_size(inst));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	625 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	626 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	627 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	628 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	629 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	630 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	631 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	632 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	633 z80_save_ea(code, inst, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	634 break;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	635 case Z80_SBC:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	636 num_cycles = 4;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	637 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	638 num_cycles += 12;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	639 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	640 num_cycles += 3;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	641 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	642 num_cycles += 4;
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	643 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	644 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	645 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	646 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	647 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	648 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	649 sbb_rr(code, src_op.base, dst_op.base, z80_size(inst));
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	650 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	651 sbb_ir(code, src_op.disp, dst_op.base, z80_size(inst));
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	652 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	653 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	654 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	655 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	656 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	657 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	658 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	659 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	660 z80_save_ea(code, inst, opts);
248 9c7a3db7bcd0 Implement ADC and SBC in Z80 core (untested) Mike Pavone <pavone@retrodev.com> parents: 247 diff changeset	661 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	662 case Z80_AND:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	663 num_cycles = 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	664 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	665 num_cycles += 12;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	666 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	667 num_cycles += 3;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	668 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	669 num_cycles += 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	670 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	671 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	672 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	673 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	674 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	675 and_rr(code, src_op.base, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	676 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	677 and_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	678 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	679 //TODO: Cleanup flags
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	680 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	681 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	682 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	683 if (z80_size(inst) == SZ_B) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	684 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	685 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	686 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	687 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	688 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	689 z80_save_ea(code, inst, opts);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	690 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	691 case Z80_OR:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	692 num_cycles = 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	693 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	694 num_cycles += 12;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	695 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	696 num_cycles += 3;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	697 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	698 num_cycles += 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	699 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	700 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	701 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	702 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	703 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	704 or_rr(code, src_op.base, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	705 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	706 or_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	707 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	708 //TODO: Cleanup flags
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	709 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	710 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	711 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	712 if (z80_size(inst) == SZ_B) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	713 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	714 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	715 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	716 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	717 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	718 z80_save_ea(code, inst, opts);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	719 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	720 case Z80_XOR:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	721 num_cycles = 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	722 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	723 num_cycles += 12;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	724 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	725 num_cycles += 3;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	726 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	727 num_cycles += 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	728 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	729 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	730 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	731 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	732 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	733 xor_rr(code, src_op.base, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	734 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	735 xor_ir(code, src_op.disp, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	736 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	737 //TODO: Cleanup flags
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	738 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	739 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	740 //TODO: Implement half-carry flag
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	741 if (z80_size(inst) == SZ_B) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	742 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	743 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	744 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	745 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	746 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	747 z80_save_ea(code, inst, opts);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	748 break;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	749 case Z80_CP:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	750 num_cycles = 4;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	751 if (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	752 num_cycles += 12;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	753 } else if(inst->addr_mode == Z80_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	754 num_cycles += 3;
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	755 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	756 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	757 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	758 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	759 if (src_op.mode == MODE_REG_DIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	760 cmp_rr(code, src_op.base, dst_op.base, z80_size(inst));
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	761 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	762 cmp_ir(code, src_op.disp, dst_op.base, z80_size(inst));
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	763 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	764 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	765 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	766 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	767 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	768 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	769 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	770 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	771 z80_save_ea(code, inst, opts);
242 d3b84b2a4397 Implemente CP (untested) Mike Pavone <pavone@retrodev.com> parents: 241 diff changeset	772 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	773 case Z80_INC:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	774 num_cycles = 4;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	775 if (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	776 num_cycles += 6;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	777 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	778 num_cycles += 2;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	779 } else if(inst->reg == Z80_IXH \|\| inst->reg == Z80_IXL \|\| inst->reg == Z80_IYH \|\| inst->reg == Z80_IYL \|\| inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	780 num_cycles += 4;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	781 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	782 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	783 translate_z80_reg(inst, &dst_op, opts);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	784 if (dst_op.mode == MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	785 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	786 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	787 add_ir(code, 1, dst_op.base, z80_size(inst));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	788 if (z80_size(inst) == SZ_B) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	789 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	790 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	791 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	792 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	793 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	794 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	795 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	796 z80_save_ea(code, inst, opts);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	797 z80_save_result(opts, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	798 break;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	799 case Z80_DEC:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	800 num_cycles = 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	801 if (inst->reg == Z80_IX \|\| inst->reg == Z80_IY) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	802 num_cycles += 6;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	803 } else if(z80_size(inst) == SZ_W) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	804 num_cycles += 2;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	805 } else if(inst->reg == Z80_IXH \|\| inst->reg == Z80_IXL \|\| inst->reg == Z80_IYH \|\| inst->reg == Z80_IYL \|\| inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	806 num_cycles += 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	807 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	808 cycles(&opts->gen, num_cycles);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	809 translate_z80_reg(inst, &dst_op, opts);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	810 if (dst_op.mode == MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	811 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	812 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	813 sub_ir(code, 1, dst_op.base, z80_size(inst));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	814 if (z80_size(inst) == SZ_B) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	815 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	816 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	817 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	818 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	819 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	820 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	821 z80_save_reg(inst, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	822 z80_save_ea(code, inst, opts);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	823 z80_save_result(opts, inst);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	824 break;
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	825 //case Z80_DAA:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	826 case Z80_CPL:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	827 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	828 not_r(code, opts->regs[Z80_A], SZ_B);
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	829 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	830 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	831 break;
be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	832 case Z80_NEG:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	833 cycles(&opts->gen, 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	834 neg_r(code, opts->regs[Z80_A], SZ_B);
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	835 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	836 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	837 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	838 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	839 setcc_rdisp(code, CC_O, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	840 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
274 be2b845d3e94 Implement CPL and NEG (untested) Mike Pavone <pavone@retrodev.com> parents: 273 diff changeset	841 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	842 case Z80_CCF:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	843 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	844 xor_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	845 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
257 4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	846 //TODO: Implement half-carry flag
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	847 break;
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	848 case Z80_SCF:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	849 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	850 mov_irdisp(code, 1, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	851 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
257 4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	852 //TODO: Implement half-carry flag
4c7933444df4 Implement CCF and SCF Mike Pavone <pavone@retrodev.com> parents: 255 diff changeset	853 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	854 case Z80_NOP:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	855 if (inst->immed == 42) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	856 call(code, opts->gen.save_context);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	857 mov_rr(code, opts->gen.context_reg, RDI, SZ_Q);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	858 jmp(code, (uint8_t *)z80_print_regs_exit);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	859 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	860 cycles(&opts->gen, 4 * inst->immed);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	861 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	862 break;
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	863 case Z80_HALT: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	864 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	865 mov_ir(code, address, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	866 uint8_t * call_inst = code->cur;
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	867 mov_rr(code, opts->gen.limit, opts->gen.scratch2, SZ_D);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	868 sub_rr(code, opts->gen.cycles, opts->gen.scratch2, SZ_D);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	869 and_ir(code, 0xFFFFFFFC, opts->gen.scratch2, SZ_D);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	870 add_rr(code, opts->gen.scratch2, opts->gen.cycles, SZ_D);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	871 cmp_rr(code, opts->gen.limit, opts->gen.cycles, SZ_D);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	872 code_ptr skip_last = code->cur+1;
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	873 jcc(code, CC_NB, code->cur+2);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	874 cycles(&opts->gen, 4);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	875 *skip_last = code->cur - (skip_last+1);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	876 call(code, opts->gen.handle_cycle_limit_int);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	877 jmp(code, call_inst);
285 021aeb6df19b Implement HALT (sort of tested) Mike Pavone <pavone@retrodev.com> parents: 284 diff changeset	878 break;
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	879 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	880 case Z80_DI:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	881 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	882 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	883 mov_irdisp(code, 0, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	884 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, sync_cycle), opts->gen.limit, SZ_D);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	885 mov_irdisp(code, 0xFFFFFFFF, opts->gen.context_reg, offsetof(z80_context, int_cycle), SZ_D);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	886 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	887 case Z80_EI:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	888 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	889 mov_rrdisp(code, opts->gen.cycles, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	890 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	891 mov_irdisp(code, 1, opts->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
335 14a937097c2b Some Z80 interrupt fixes Mike Pavone <pavone@retrodev.com> parents: 315 diff changeset	892 //interrupt enable has a one-instruction latency, minimum instruction duration is 4 cycles
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	893 add_irdisp(code, 4, opts->gen.context_reg, offsetof(z80_context, int_enable_cycle), SZ_D);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	894 call(code, opts->do_sync);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	895 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	896 case Z80_IM:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	897 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	898 mov_irdisp(code, inst->immed, opts->gen.context_reg, offsetof(z80_context, im), SZ_B);
243 2f069a0b487e Implement EI, DI and IM in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 242 diff changeset	899 break;
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	900 case Z80_RLC:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	901 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	902 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	903 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	904 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	905 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	906 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	907 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	908 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	909 translate_z80_reg(inst, &dst_op, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	910 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	911 rol_ir(code, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	912 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	913 mov_rr(code, dst_op.base, src_op.base, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	914 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	915 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	916 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	917 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	918 cmp_ir(code, 0, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	919 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	920 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	921 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	922 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	923 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	924 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	925 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	926 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	927 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	928 z80_save_reg(inst, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	929 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	930 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	931 case Z80_RL:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	932 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	933 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	934 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	935 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	936 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	937 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	938 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	939 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	940 translate_z80_reg(inst, &dst_op, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	941 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	942 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	943 rcl_ir(code, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	944 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	945 mov_rr(code, dst_op.base, src_op.base, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	946 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	947 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	948 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	949 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	950 cmp_ir(code, 0, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	951 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	952 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	953 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	954 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	955 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	956 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	957 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	958 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	959 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	960 z80_save_reg(inst, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	961 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	962 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	963 case Z80_RRC:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	964 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	965 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	966 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	967 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	968 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	969 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	970 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	971 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	972 translate_z80_reg(inst, &dst_op, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	973 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	974 ror_ir(code, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	975 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	976 mov_rr(code, dst_op.base, src_op.base, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	977 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	978 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	979 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	980 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	981 cmp_ir(code, 0, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	982 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	983 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	984 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	985 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	986 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	987 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	988 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	989 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	990 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	991 z80_save_reg(inst, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	992 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	993 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	994 case Z80_RR:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	995 num_cycles = inst->immed == 0 ? 4 : (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	996 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	997 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	998 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	999 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1000 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1001 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1002 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1003 translate_z80_reg(inst, &dst_op, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1004 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1005 bt_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1006 rcr_ir(code, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	1007 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1008 mov_rr(code, dst_op.base, src_op.base, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1009 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1010 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1011 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1012 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1013 cmp_ir(code, 0, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1014 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1015 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1016 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1017 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1018 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1019 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1020 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1021 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1022 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1023 z80_save_reg(inst, opts);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1024 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1025 break;
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1026 case Z80_SLA:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1027 case Z80_SLL:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1028 num_cycles = inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1029 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1030 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1031 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1032 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1033 cycles(&opts->gen, 1);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1034 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1035 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1036 translate_z80_reg(inst, &dst_op, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1037 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1038 shl_ir(code, 1, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1039 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1040 if (inst->op == Z80_SLL) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1041 or_ir(code, 1, dst_op.base, SZ_B);
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1042 }
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	1043 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1044 mov_rr(code, dst_op.base, src_op.base, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1045 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1046 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1047 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1048 cmp_ir(code, 0, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1049 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1050 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1051 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1052 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1053 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1054 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1055 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1056 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1057 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1058 z80_save_reg(inst, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1059 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1060 break;
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1061 case Z80_SRA:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1062 num_cycles = inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1063 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1064 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1065 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1066 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1067 cycles(&opts->gen, 1);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1068 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1069 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1070 translate_z80_reg(inst, &dst_op, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1071 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1072 sar_ir(code, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	1073 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1074 mov_rr(code, dst_op.base, src_op.base, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1075 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1076 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1077 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1078 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1079 cmp_ir(code, 0, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1080 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1081 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1082 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1083 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1084 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1085 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1086 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1087 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1088 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1089 z80_save_reg(inst, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1090 }
1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1091 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1092 case Z80_SRL:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1093 num_cycles = inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE ? 16 : 8;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1094 cycles(&opts->gen, num_cycles);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1095 if (inst->addr_mode != Z80_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1096 translate_z80_ea(inst, &dst_op, opts, READ, MODIFY);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1097 translate_z80_reg(inst, &src_op, opts); //For IX/IY variants that also write to a register
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1098 cycles(&opts->gen, 1);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1099 } else {
302 3b831fe32c15 More fixes for confusion between Z80_UNUSED and MODE_UNUSED Mike Pavone <pavone@retrodev.com> parents: 301 diff changeset	1100 src_op.mode = MODE_UNUSED;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1101 translate_z80_reg(inst, &dst_op, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1102 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1103 shr_ir(code, 1, dst_op.base, SZ_B);
301 6e15509a1257 Compare src_op.mode with the correct constant in shift/rotate instructions Mike Pavone <pavone@retrodev.com> parents: 300 diff changeset	1104 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1105 mov_rr(code, dst_op.base, src_op.base, SZ_B);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1106 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1107 setcc_rdisp(code, CC_C, opts->gen.context_reg, zf_off(ZF_C));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1108 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1109 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1110 cmp_ir(code, 0, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1111 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1112 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1113 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1114 if (inst->addr_mode != Z80_UNUSED) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1115 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1116 if (src_op.mode != MODE_UNUSED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1117 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1118 }
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1119 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1120 z80_save_reg(inst, opts);
275 1a7d0a964ad2 Implement shift instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 274 diff changeset	1121 }
310 bf440db64086 Implement carry flag for shift instructions. Implement weird behavior for bit 0 of SLL. Fix missing break statement in SRL. Mike Pavone <pavone@retrodev.com> parents: 309 diff changeset	1122 break;
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1123 case Z80_RLD:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1124 cycles(&opts->gen, 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1125 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1126 call(code, opts->read_8);
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1127 //Before: (HL) = 0x12, A = 0x34
872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1128 //After: (HL) = 0x24, A = 0x31
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1129 mov_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1130 shl_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1131 and_ir(code, 0xF, opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1132 and_ir(code, 0xFFF, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1133 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1134 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1135 //opts->gen.scratch1 = 0x0124
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1136 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1137 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1138 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1139 //set flags
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1140 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1141 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1142 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1143 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1144 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1145
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1146 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1147 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1148 call(code, opts->write_8);
286 872a8911e0f4 Implemente RLD Mike Pavone <pavone@retrodev.com> parents: 285 diff changeset	1149 break;
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1150 case Z80_RRD:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1151 cycles(&opts->gen, 8);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1152 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1153 call(code, opts->read_8);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1154 //Before: (HL) = 0x12, A = 0x34
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1155 //After: (HL) = 0x41, A = 0x32
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1156 movzx_rr(code, opts->regs[Z80_A], opts->gen.scratch2, SZ_B, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1157 ror_ir(code, 4, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1158 shl_ir(code, 4, opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1159 and_ir(code, 0xF00F, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1160 and_ir(code, 0xF0, opts->regs[Z80_A], SZ_B);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1161 //opts->gen.scratch1 = 0x2001
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1162 //opts->gen.scratch2 = 0x0040
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1163 or_rr(code, opts->gen.scratch2, opts->gen.scratch1, SZ_W);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1164 //opts->gen.scratch1 = 0x2041
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1165 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1166 cycles(&opts->gen, 4);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1167 shr_ir(code, 4, opts->gen.scratch1, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1168 or_rr(code, opts->gen.scratch1, opts->regs[Z80_A], SZ_B);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1169 //set flags
fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1170 //TODO: Implement half-carry flag
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1171 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1172 setcc_rdisp(code, CC_P, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1173 setcc_rdisp(code, CC_Z, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1174 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1175
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1176 mov_rr(code, opts->regs[Z80_HL], opts->gen.scratch2, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1177 ror_ir(code, 8, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1178 call(code, opts->write_8);
287 fb840e0a48cd Implement RRD and implement flags on RLD Mike Pavone <pavone@retrodev.com> parents: 286 diff changeset	1179 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1180 case Z80_BIT: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1181 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1182 cycles(&opts->gen, num_cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1183 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1184 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1185 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1186 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1187 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1188 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1189 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1190 bit = inst->immed;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1191 translate_z80_ea(inst, &src_op, opts, READ, DONT_MODIFY);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1192 }
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1193 if (inst->addr_mode != Z80_REG) {
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1194 //Reads normally take 3 cycles, but the read at the end of a bit instruction takes 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1195 cycles(&opts->gen, 1);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1196 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1197 bt_ir(code, bit, src_op.base, size);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1198 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_Z));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1199 setcc_rdisp(code, CC_NC, opts->gen.context_reg, zf_off(ZF_PV));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1200 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_N), SZ_B);
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1201 if (inst->immed == 7) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1202 cmp_ir(code, 0, src_op.base, size);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1203 setcc_rdisp(code, CC_S, opts->gen.context_reg, zf_off(ZF_S));
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1204 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1205 mov_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
307 b6393b89a7e4 Complete flag behavior for Z80 BIT instruction Mike Pavone <pavone@retrodev.com> parents: 306 diff changeset	1206 }
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1207 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1208 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1209 case Z80_SET: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1210 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1211 cycles(&opts->gen, num_cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1212 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1213 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1214 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1215 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1216 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1217 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1218 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1219 bit = inst->immed;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1220 translate_z80_ea(inst, &src_op, opts, READ, MODIFY);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1221 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1222 if (inst->reg != Z80_USE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1223 translate_z80_reg(inst, &dst_op, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1224 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1225 if (inst->addr_mode != Z80_REG) {
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1226 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1227 cycles(&opts->gen, 1);
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1228 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1229 bts_ir(code, bit, src_op.base, size);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1230 if (inst->reg != Z80_USE_IMMED) {
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1231 if (size == SZ_W) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1232 if (dst_op.base >= R8) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1233 ror_ir(code, 8, src_op.base, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1234 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1235 ror_ir(code, 8, src_op.base, SZ_W);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1236 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1237 mov_rr(code, opts->regs[inst->ea_reg], dst_op.base, SZ_B);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1238 }
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1239 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1240 mov_rr(code, src_op.base, dst_op.base, SZ_B);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1241 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1242 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1243 if ((inst->addr_mode & 0x1F) != Z80_REG) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1244 z80_save_result(opts, inst);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1245 if (inst->reg != Z80_USE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1246 z80_save_reg(inst, opts);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1247 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1248 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1249 break;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1250 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1251 case Z80_RES: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1252 num_cycles = (inst->addr_mode == Z80_IX_DISPLACE \|\| inst->addr_mode == Z80_IY_DISPLACE) ? 8 : 16;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1253 cycles(&opts->gen, num_cycles);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1254 uint8_t bit;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1255 if ((inst->addr_mode & 0x1F) == Z80_REG && opts->regs[inst->ea_reg] >= AH && opts->regs[inst->ea_reg] <= BH) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1256 src_op.base = opts->regs[z80_word_reg(inst->ea_reg)];
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1257 size = SZ_W;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1258 bit = inst->immed + 8;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1259 } else {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1260 size = SZ_B;
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1261 bit = inst->immed;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1262 translate_z80_ea(inst, &src_op, opts, READ, MODIFY);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1263 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1264 if (inst->reg != Z80_USE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1265 translate_z80_reg(inst, &dst_op, opts);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1266 }
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1267 if (inst->addr_mode != Z80_REG) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1268 //Reads normally take 3 cycles, but the read in the middle of a set instruction takes 4
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1269 cycles(&opts->gen, 1);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1270 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1271 btr_ir(code, bit, src_op.base, size);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1272 if (inst->reg != Z80_USE_IMMED) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1273 if (size == SZ_W) {
e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1274 if (dst_op.base >= R8) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1275 ror_ir(code, 8, src_op.base, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1276 mov_rr(code, opts->regs[z80_low_reg(inst->ea_reg)], dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1277 ror_ir(code, 8, src_op.base, SZ_W);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1278 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1279 mov_rr(code, opts->regs[inst->ea_reg], dst_op.base, SZ_B);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1280 }
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1281 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1282 mov_rr(code, src_op.base, dst_op.base, SZ_B);
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1283 }
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1284 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1285 if (inst->addr_mode != Z80_REG) {
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1286 z80_save_result(opts, inst);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1287 if (inst->reg != Z80_USE_IMMED) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1288 z80_save_reg(inst, opts);
299 42e1a986f2d0 Fix calcuation of IX/IY dipslacements. Fix a bunch of stuff related to the IX/IY bit/shift/rotate instructions. Mike Pavone <pavone@retrodev.com> parents: 295 diff changeset	1289 }
247 682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1290 }
682e505f5757 Implement rotation and bit set/reset instructions (untested). Mike Pavone <pavone@retrodev.com> parents: 246 diff changeset	1291 break;
308 e0e81551fd7e Deal with the fact that there's no 8-bit version of the BT family of instructions on x86 Mike Pavone <pavone@retrodev.com> parents: 307 diff changeset	1292 }
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1293 case Z80_JP: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1294 num_cycles = 4;
506 a3b48a57e847 Fix timing of certain ld and jp instructions in the Z80 core Michael Pavone <pavone@retrodev.com> parents: 505 diff changeset	1295 if (inst->addr_mode != Z80_REG_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1296 num_cycles += 6;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1297 } else if(inst->ea_reg == Z80_IX \|\| inst->ea_reg == Z80_IY) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1298 num_cycles += 4;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1299 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1300 cycles(&opts->gen, num_cycles);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1301 if (inst->addr_mode != Z80_REG_INDIRECT && inst->immed < 0x4000) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1302 code_ptr call_dst = z80_get_native_address(context, inst->immed);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1303 if (!call_dst) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1304 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1305 //fake address to force large displacement
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1306 call_dst = code->cur + 256;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1307 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1308 jmp(code, call_dst);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1309 } else {
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1310 if (inst->addr_mode == Z80_REG_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1311 mov_rr(code, opts->regs[inst->ea_reg], opts->gen.scratch1, SZ_W);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1312 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1313 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_W);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1314 }
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1315 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1316 jmp_r(code, opts->gen.scratch1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1317 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1318 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1319 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1320 case Z80_JPCC: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1321 cycles(&opts->gen, 7);//T States: 4,3
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1322 uint8_t cond = CC_Z;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1323 switch (inst->reg)
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1324 {
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1325 case Z80_CC_NZ:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1326 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1327 case Z80_CC_Z:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1328 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1329 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1330 case Z80_CC_NC:
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1331 cond = CC_NZ;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1332 case Z80_CC_C:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1333 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1334 break;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1335 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1336 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1337 case Z80_CC_PE:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1338 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1339 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1340 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	1341 cond = CC_NZ;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1342 case Z80_CC_M:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1343 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1344 break;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1345 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1346 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1347 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1348 cycles(&opts->gen, 5);//T States: 5
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1349 uint16_t dest_addr = inst->immed;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1350 if (dest_addr < 0x4000) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1351 code_ptr call_dst = z80_get_native_address(context, dest_addr);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1352 if (!call_dst) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1353 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1354 //fake address to force large displacement
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1355 call_dst = code->cur + 256;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1356 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1357 jmp(code, call_dst);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1358 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1359 mov_ir(code, dest_addr, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1360 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1361 jmp_r(code, opts->gen.scratch1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1362 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1363 *no_jump_off = code->cur - (no_jump_off+1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1364 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1365 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1366 case Z80_JR: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1367 cycles(&opts->gen, 12);//T States: 4,3,5
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1368 uint16_t dest_addr = address + inst->immed + 2;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1369 if (dest_addr < 0x4000) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1370 code_ptr call_dst = z80_get_native_address(context, dest_addr);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1371 if (!call_dst) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1372 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1373 //fake address to force large displacement
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1374 call_dst = code->cur + 256;
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1375 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1376 jmp(code, call_dst);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1377 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1378 mov_ir(code, dest_addr, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1379 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1380 jmp_r(code, opts->gen.scratch1);
236 19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1381 }
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1382 break;
19fb3523a9e5 Implement more Z80 instructions (untested) Mike Pavone <pavone@retrodev.com> parents: 235 diff changeset	1383 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1384 case Z80_JRCC: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1385 cycles(&opts->gen, 7);//T States: 4,3
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1386 uint8_t cond = CC_Z;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1387 switch (inst->reg)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1388 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1389 case Z80_CC_NZ:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1390 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1391 case Z80_CC_Z:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1392 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1393 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1394 case Z80_CC_NC:
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1395 cond = CC_NZ;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1396 case Z80_CC_C:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1397 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1398 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1399 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1400 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1401 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1402 cycles(&opts->gen, 5);//T States: 5
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1403 uint16_t dest_addr = address + inst->immed + 2;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1404 if (dest_addr < 0x4000) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1405 code_ptr call_dst = z80_get_native_address(context, dest_addr);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1406 if (!call_dst) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1407 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1408 //fake address to force large displacement
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1409 call_dst = code->cur + 256;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1410 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1411 jmp(code, call_dst);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1412 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1413 mov_ir(code, dest_addr, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1414 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1415 jmp_r(code, opts->gen.scratch1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1416 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1417 *no_jump_off = code->cur - (no_jump_off+1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1418 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1419 }
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1420 case Z80_DJNZ:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1421 cycles(&opts->gen, 8);//T States: 5,3
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1422 sub_ir(code, 1, opts->regs[Z80_B], SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1423 uint8_t *no_jump_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1424 jcc(code, CC_Z, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1425 cycles(&opts->gen, 5);//T States: 5
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1426 uint16_t dest_addr = address + inst->immed + 2;
a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1427 if (dest_addr < 0x4000) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1428 code_ptr call_dst = z80_get_native_address(context, dest_addr);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1429 if (!call_dst) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1430 opts->gen.deferred = defer_address(opts->gen.deferred, dest_addr, code->cur + 1);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1431 //fake address to force large displacement
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1432 call_dst = code->cur + 256;
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1433 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1434 jmp(code, call_dst);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1435 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1436 mov_ir(code, dest_addr, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1437 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1438 jmp_r(code, opts->gen.scratch1);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1439 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1440 *no_jump_off = code->cur - (no_jump_off+1);
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1441 break;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1442 case Z80_CALL: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1443 cycles(&opts->gen, 11);//T States: 4,3,4
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1444 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1445 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1446 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1447 call(code, opts->write_16_highfirst);//T States: 3, 3
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1448 if (inst->immed < 0x4000) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1449 code_ptr call_dst = z80_get_native_address(context, inst->immed);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1450 if (!call_dst) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1451 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1452 //fake address to force large displacement
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1453 call_dst = code->cur + 256;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1454 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1455 jmp(code, call_dst);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1456 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1457 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1458 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1459 jmp_r(code, opts->gen.scratch1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1460 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1461 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1462 }
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1463 case Z80_CALLCC:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1464 cycles(&opts->gen, 10);//T States: 4,3,3 (false case)
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1465 uint8_t cond = CC_Z;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1466 switch (inst->reg)
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1467 {
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1468 case Z80_CC_NZ:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1469 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1470 case Z80_CC_Z:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1471 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1472 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1473 case Z80_CC_NC:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1474 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1475 case Z80_CC_C:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1476 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1477 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1478 case Z80_CC_PO:
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1479 cond = CC_NZ;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1480 case Z80_CC_PE:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1481 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1482 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1483 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	1484 cond = CC_NZ;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1485 case Z80_CC_M:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1486 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1487 break;
827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1488 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1489 uint8_t *no_call_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1490 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1491 cycles(&opts->gen, 1);//Last of the above T states takes an extra cycle in the true case
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1492 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1493 mov_ir(code, address + 3, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1494 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1495 call(code, opts->write_16_highfirst);//T States: 3, 3
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1496 if (inst->immed < 0x4000) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1497 code_ptr call_dst = z80_get_native_address(context, inst->immed);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1498 if (!call_dst) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1499 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1500 //fake address to force large displacement
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1501 call_dst = code->cur + 256;
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1502 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1503 jmp(code, call_dst);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1504 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1505 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1506 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1507 jmp_r(code, opts->gen.scratch1);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1508 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1509 *no_call_off = code->cur - (no_call_off+1);
238 827ebce557bf Added the rest of the conditions to JPCC, implemented CALLCC (untested) Mike Pavone <pavone@retrodev.com> parents: 236 diff changeset	1510 break;
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1511 case Z80_RET:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1512 cycles(&opts->gen, 4);//T States: 4
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1513 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1514 call(code, opts->read_16);//T STates: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1515 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1516 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1517 jmp_r(code, opts->gen.scratch1);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1518 break;
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1519 case Z80_RETCC: {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1520 cycles(&opts->gen, 5);//T States: 5
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1521 uint8_t cond = CC_Z;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1522 switch (inst->reg)
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1523 {
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1524 case Z80_CC_NZ:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1525 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1526 case Z80_CC_Z:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1527 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_Z), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1528 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1529 case Z80_CC_NC:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1530 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1531 case Z80_CC_C:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1532 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_C), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1533 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1534 case Z80_CC_PO:
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1535 cond = CC_NZ;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1536 case Z80_CC_PE:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1537 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_PV), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1538 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1539 case Z80_CC_P:
367 f20562f2a570 Fix P condition in Z80 core Mike Pavone <pavone@retrodev.com> parents: 366 diff changeset	1540 cond = CC_NZ;
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1541 case Z80_CC_M:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1542 cmp_irdisp(code, 0, opts->gen.context_reg, zf_off(ZF_S), SZ_B);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1543 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1544 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1545 uint8_t *no_call_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1546 jcc(code, cond, code->cur+2);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1547 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1548 call(code, opts->read_16);//T STates: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1549 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1550 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1551 jmp_r(code, opts->gen.scratch1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1552 *no_call_off = code->cur - (no_call_off+1);
246 ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1553 break;
ed548c77b598 Implement RETCC in Z80 core. Mike Pavone <pavone@retrodev.com> parents: 243 diff changeset	1554 }
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1555 case Z80_RETI:
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1556 //For some systems, this may need a callback for signalling interrupt routine completion
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1557 cycles(&opts->gen, 8);//T States: 4, 4
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1558 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1559 call(code, opts->read_16);//T STates: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1560 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1561 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1562 jmp_r(code, opts->gen.scratch1);
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1563 break;
61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1564 case Z80_RETN:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1565 cycles(&opts->gen, 8);//T States: 4, 4
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1566 mov_rdispr(code, opts->gen.context_reg, offsetof(z80_context, iff2), opts->gen.scratch2, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1567 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1568 mov_rrdisp(code, opts->gen.scratch2, opts->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1569 call(code, opts->read_16);//T STates: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1570 add_ir(code, 2, opts->regs[Z80_SP], SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1571 call(code, opts->native_addr);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1572 jmp_r(code, opts->gen.scratch1);
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1573 break;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1574 case Z80_RST: {
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1575 //RST is basically CALL to an address in page 0
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1576 cycles(&opts->gen, 5);//T States: 5
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1577 sub_ir(code, 2, opts->regs[Z80_SP], SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1578 mov_ir(code, address + 1, opts->gen.scratch1, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1579 mov_rr(code, opts->regs[Z80_SP], opts->gen.scratch2, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1580 call(code, opts->write_16_highfirst);//T States: 3, 3
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1581 code_ptr call_dst = z80_get_native_address(context, inst->immed);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1582 if (!call_dst) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1583 opts->gen.deferred = defer_address(opts->gen.deferred, inst->immed, code->cur + 1);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1584 //fake address to force large displacement
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1585 call_dst = code->cur + 256;
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1586 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1587 jmp(code, call_dst);
241 2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1588 break;
2586d49ddd46 Implement EX, EXX and RST in Z80 core Mike Pavone <pavone@retrodev.com> parents: 239 diff changeset	1589 }
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1590 case Z80_IN:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1591 cycles(&opts->gen, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1592 if (inst->addr_mode == Z80_IMMED_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1593 mov_ir(code, inst->immed, opts->gen.scratch1, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1594 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1595 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch1, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1596 }
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1597 call(code, opts->read_io);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1598 translate_z80_reg(inst, &dst_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1599 mov_rr(code, opts->gen.scratch1, dst_op.base, SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1600 z80_save_reg(inst, opts);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1601 break;
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1602 /*case Z80_INI:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1603 case Z80_INIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1604 case Z80_IND:
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1605 case Z80_INDR:*/
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1606 case Z80_OUT:
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1607 cycles(&opts->gen, inst->reg == Z80_A ? 7 : 8);//T States: 4 3/4
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1608 if ((inst->addr_mode & 0x1F) == Z80_IMMED_INDIRECT) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1609 mov_ir(code, inst->immed, opts->gen.scratch2, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1610 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1611 mov_rr(code, opts->regs[Z80_C], opts->gen.scratch2, SZ_B);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1612 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1613 translate_z80_reg(inst, &src_op, opts);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1614 mov_rr(code, dst_op.base, opts->gen.scratch1, SZ_B);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1615 call(code, opts->write_io);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1616 z80_save_reg(inst, opts);
284 ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1617 break;
ed7098f717d7 Implement IN and OUT (untested) Mike Pavone <pavone@retrodev.com> parents: 283 diff changeset	1618 /*case Z80_OUTI:
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1619 case Z80_OTIR:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1620 case Z80_OUTD:
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1621 case Z80_OTDR:*/
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1622 default: {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1623 char disbuf[80];
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	1624 z80_disasm(inst, disbuf, address);
424 7e8e179116af Add support for loading GST format savestates Mike Pavone <pavone@retrodev.com> parents: 420 diff changeset	1625 fprintf(stderr, "unimplemented instruction: %s at %X\n", disbuf, address);
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1626 FILE * f = fopen("zram.bin", "wb");
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1627 fwrite(context->mem_pointers[0], 1, 8 * 1024, f);
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	1628 fclose(f);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1629 exit(1);
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1630 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1631 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1632 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1633
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1634 uint8_t * z80_get_native_address(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1635 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1636 native_map_slot *map;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1637 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1638 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1639 map = context->static_code_map;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1640 } else if (address >= 0x8000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1641 address &= 0x7FFF;
279 6be6056735a9 Fix native address lookup in bannked memory area Mike Pavone <pavone@retrodev.com> parents: 277 diff changeset	1642 map = context->banked_code_map + context->bank_reg;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1643 } else {
313 a13329645ea3 Fix terminal instruction detection in disassembler Mike Pavone <pavone@retrodev.com> parents: 312 diff changeset	1644 //dprintf("z80_get_native_address: %X NULL\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1645 return NULL;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1646 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1647 if (!map->base \|\| !map->offsets \|\| map->offsets[address] == INVALID_OFFSET \|\| map->offsets[address] == EXTENSION_WORD) {
313 a13329645ea3 Fix terminal instruction detection in disassembler Mike Pavone <pavone@retrodev.com> parents: 312 diff changeset	1648 //dprintf("z80_get_native_address: %X NULL\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1649 return NULL;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1650 }
313 a13329645ea3 Fix terminal instruction detection in disassembler Mike Pavone <pavone@retrodev.com> parents: 312 diff changeset	1651 //dprintf("z80_get_native_address: %X %p\n", address, map->base + map->offsets[address]);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1652 return map->base + map->offsets[address];
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1653 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1654
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1655 uint8_t z80_get_native_inst_size(z80_options * opts, uint32_t address)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1656 {
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1657 if (address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1658 return 0;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1659 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1660 return opts->gen.ram_inst_sizes[0][address & 0x1FFF];
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1661 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1662
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1663 void z80_map_native_address(z80_context * context, uint32_t address, uint8_t * native_address, uint8_t size, uint8_t native_size)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1664 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1665 uint32_t orig_address = address;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1666 native_map_slot *map;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1667 z80_options * opts = context->options;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1668 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1669 address &= 0x1FFF;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1670 map = context->static_code_map;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1671 opts->gen.ram_inst_sizes[0][address] = native_size;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1672 context->ram_code_flags[(address & 0x1C00) >> 10] \|= 1 << ((address & 0x380) >> 7);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1673 context->ram_code_flags[((address + size) & 0x1C00) >> 10] \|= 1 << (((address + size) & 0x380) >> 7);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1674 } else if (address >= 0x8000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1675 address &= 0x7FFF;
279 6be6056735a9 Fix native address lookup in bannked memory area Mike Pavone <pavone@retrodev.com> parents: 277 diff changeset	1676 map = context->banked_code_map + context->bank_reg;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1677 if (!map->offsets) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1678 map->offsets = malloc(sizeof(int32_t) * 0x8000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1679 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1680 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1681 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1682 return;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1683 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1684 if (!map->base) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1685 map->base = native_address;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1686 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1687 map->offsets[address] = native_address - map->base;
253 3b34deba4ca0 Squashing some bugs introduced when I switched the register assignments for z80_write_byte around. Mike Pavone <pavone@retrodev.com> parents: 252 diff changeset	1688 for(--size, orig_address++; size; --size, orig_address++) {
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1689 address = orig_address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1690 if (address < 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1691 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1692 map = context->static_code_map;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1693 } else if (address >= 0x8000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1694 address &= 0x7FFF;
279 6be6056735a9 Fix native address lookup in bannked memory area Mike Pavone <pavone@retrodev.com> parents: 277 diff changeset	1695 map = context->banked_code_map + context->bank_reg;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1696 } else {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1697 return;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1698 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1699 if (!map->offsets) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1700 map->offsets = malloc(sizeof(int32_t) * 0x8000);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1701 memset(map->offsets, 0xFF, sizeof(int32_t) * 0x8000);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1702 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1703 map->offsets[address] = EXTENSION_WORD;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1704 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1705 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1706
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1707 #define INVALID_INSTRUCTION_START 0xFEEDFEED
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1708
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1709 uint32_t z80_get_instruction_start(native_map_slot * static_code_map, uint32_t address)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1710 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1711 if (!static_code_map->base \|\| address >= 0x4000) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1712 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1713 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1714 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1715 if (static_code_map->offsets[address] == INVALID_OFFSET) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1716 return INVALID_INSTRUCTION_START;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1717 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1718 while (static_code_map->offsets[address] == EXTENSION_WORD) {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1719 --address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1720 address &= 0x1FFF;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1721 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1722 return address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1723 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1724
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1725 z80_context * z80_handle_code_write(uint32_t address, z80_context * context)
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1726 {
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1727 uint32_t inst_start = z80_get_instruction_start(context->static_code_map, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1728 if (inst_start != INVALID_INSTRUCTION_START) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1729 code_ptr dst = z80_get_native_address(context, inst_start);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1730 code_info code = {dst, dst+16};
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1731 z80_options * opts = context->options;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1732 dprintf("patching code at %p for Z80 instruction at %X due to write to %X\n", code, inst_start, address);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1733 mov_ir(&code, inst_start, opts->gen.scratch1, SZ_D);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1734 call(&code, opts->retrans_stub);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1735 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1736 return context;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1737 }
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1738
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1739 uint8_t * z80_get_native_address_trans(z80_context * context, uint32_t address)
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1740 {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1741 uint8_t * addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1742 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1743 translate_z80_stream(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1744 addr = z80_get_native_address(context, address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1745 if (!addr) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1746 printf("Failed to translate %X to native code\n", address);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1747 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1748 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1749 return addr;
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1750 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1751
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1752 void z80_handle_deferred(z80_context * context)
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1753 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1754 z80_options * opts = context->options;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1755 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1756 if (opts->gen.deferred) {
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1757 translate_z80_stream(context, opts->gen.deferred->address);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1758 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1759 }
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1760
390 561fe3ea3fc8 Use a call instruction to figure out the original native address when retranslating so that it does not get lost when the byte transforms from a instruction word to extension word Mike Pavone <pavone@retrodev.com> parents: 389 diff changeset	1761 void * z80_retranslate_inst(uint32_t address, z80_context * context, uint8_t * orig_start)
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1762 {
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1763 char disbuf[80];
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1764 z80_options * opts = context->options;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1765 uint8_t orig_size = z80_get_native_inst_size(opts, address);
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1766 uint32_t orig = address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1767 address &= 0x1FFF;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1768 code_info *code = &opts->gen.code;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1769 uint8_t after, inst = context->mem_pointers[0] + address;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1770 z80inst instbuf;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1771 dprintf("Retranslating code at Z80 address %X, native address %p\n", address, orig_start);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1772 after = z80_decode(inst, &instbuf);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1773 #ifdef DO_DEBUG_PRINT
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	1774 z80_disasm(&instbuf, disbuf, address);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1775 if (instbuf.op == Z80_NOP) {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1776 printf("%X\t%s(%d)\n", address, disbuf, instbuf.immed);
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1777 } else {
376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1778 printf("%X\t%s\n", address, disbuf);
267 1788e3f29c28 Don't mix H regs with the REX prefix Mike Pavone <pavone@retrodev.com>* parents: 266 diff changeset	1779 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1780 #endif
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1781 if (orig_size != ZMAX_NATIVE_SIZE) {
597 8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place Michael Pavone <pavone@retrodev.com> parents: 594 diff changeset	1782 check_alloc_code(code, ZMAX_NATIVE_SIZE);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1783 code_ptr start = code->cur;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1784 deferred_addr * orig_deferred = opts->gen.deferred;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1785 translate_z80inst(&instbuf, context, address);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1786 /*
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1787 if ((native_end - dst) <= orig_size) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1788 uint8_t * native_next = z80_get_native_address(context, address + after-inst);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1789 if (native_next && ((native_next == orig_start + orig_size) \|\| (orig_size - (native_end - dst)) > 5)) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1790 remove_deferred_until(&opts->gen.deferred, orig_deferred);
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1791 native_end = translate_z80inst(&instbuf, orig_start, context, address);
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1792 if (native_next == orig_start + orig_size && (native_next-native_end) < 2) {
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1793 while (native_end < orig_start + orig_size) {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1794 *(native_end++) = 0x90; //NOP
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1795 }
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1796 } else {
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1797 jmp(native_end, native_next);
8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1798 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1799 z80_handle_deferred(context);
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1800 return orig_start;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1801 }
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1802 }*/
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1803 z80_map_native_address(context, address, start, after-inst, ZMAX_NATIVE_SIZE);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1804 code_info tmp_code = {orig_start, orig_start + 16};
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1805 jmp(&tmp_code, start);
597 8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place Michael Pavone <pavone@retrodev.com> parents: 594 diff changeset	1806 tmp_code = *code;
8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place Michael Pavone <pavone@retrodev.com> parents: 594 diff changeset	1807 code->cur = start + ZMAX_NATIVE_SIZE;
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1808 if (!z80_is_terminal(&instbuf)) {
597 8d6ae5b3b87b Update code->cur before calling z80_get_address_trans in z80_retranslate_inst to avoid any newly translated instructions from being placed in the "buffer zone". Save the current value of the code_info struct for placing the final jmp instruction in the correct place Michael Pavone <pavone@retrodev.com> parents: 594 diff changeset	1809 jmp(&tmp_code, z80_get_native_address_trans(context, address + after-inst));
264 8fd6652e56f8 Fix a crash bug in instruction retranslation Mike Pavone <pavone@retrodev.com> parents: 262 diff changeset	1810 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1811 z80_handle_deferred(context);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1812 return start;
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1813 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1814 code_info tmp_code = *code;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1815 code->cur = orig_start;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1816 code->last = orig_start + ZMAX_NATIVE_SIZE;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1817 translate_z80inst(&instbuf, context, address);
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1818 code_info tmp2 = *code;
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1819 *code = tmp_code;
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1820 if (!z80_is_terminal(&instbuf)) {
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1821
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1822 jmp(&tmp2, z80_get_native_address_trans(context, address + after-inst));
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1823 }
266 376df762ddf5 Fix some more retranslation bugs in the Z80 core Mike Pavone <pavone@retrodev.com> parents: 264 diff changeset	1824 z80_handle_deferred(context);
252 63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1825 return orig_start;
63b9a500a00b Implement retranslating code when written to. Possibly broken, need to fix some other bugs before a proper test. Mike Pavone <pavone@retrodev.com> parents: 250 diff changeset	1826 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1827 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1828
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1829 void translate_z80_stream(z80_context * context, uint32_t address)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1830 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1831 char disbuf[80];
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1832 if (z80_get_native_address(context, address)) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1833 return;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1834 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1835 z80_options * opts = context->options;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1836 uint32_t start_address = address;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1837 uint8_t * encoded = NULL, *next;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1838 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1839 encoded = context->mem_pointers[0] + (address & 0x1FFF);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1840 } else if(address >= 0x8000 && context->mem_pointers[1]) {
394 d5f1840273b5 Bail out on attempt to run code from bank area until it is properly supported Mike Pavone <pavone@retrodev.com> parents: 390 diff changeset	1841 printf("attempt to translate Z80 code from banked area at address %X\n", address);
d5f1840273b5 Bail out on attempt to run code from bank area until it is properly supported Mike Pavone <pavone@retrodev.com> parents: 390 diff changeset	1842 exit(1);
d5f1840273b5 Bail out on attempt to run code from bank area until it is properly supported Mike Pavone <pavone@retrodev.com> parents: 390 diff changeset	1843 //encoded = context->mem_pointers[1] + (address & 0x7FFF);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1844 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1845 while (encoded != NULL)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1846 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1847 z80inst inst;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1848 dprintf("translating Z80 code at address %X\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1849 do {
255 572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1850 if (address > 0x4000 && address < 0x8000) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1851 xor_rr(&opts->gen.code, RDI, RDI, SZ_D);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1852 call(&opts->gen.code, (uint8_t *)exit);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1853 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1854 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1855 uint8_t * existing = z80_get_native_address(context, address);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1856 if (existing) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1857 jmp(&opts->gen.code, existing);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1858 break;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1859 }
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1860 //make sure prologue is in a contiguous chunk of code
f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	1861 check_code_prologue(&opts->gen.code);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1862 next = z80_decode(encoded, &inst);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1863 #ifdef DO_DEBUG_PRINT
314 54c0e5f22198 Show absolute addresses for JR, JRCC and DJNZ in Z80 disassembler Mike Pavone <pavone@retrodev.com> parents: 313 diff changeset	1864 z80_disasm(&inst, disbuf, address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1865 if (inst.op == Z80_NOP) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1866 printf("%X\t%s(%d)\n", address, disbuf, inst.immed);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1867 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1868 printf("%X\t%s\n", address, disbuf);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1869 }
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1870 #endif
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1871 code_ptr start = opts->gen.code.cur;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1872 translate_z80inst(&inst, context, address);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1873 z80_map_native_address(context, address, start, next-encoded, opts->gen.code.cur - start);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1874 address += next-encoded;
255 572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1875 if (address > 0xFFFF) {
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1876 address &= 0xFFFF;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	1877
255 572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1878 } else {
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1879 encoded = next;
572b935dd030 Properly handle wrapping around to 0 in translate_z80_stream Mike Pavone <pavone@retrodev.com> parents: 254 diff changeset	1880 }
283 61f5d88ea01a Implement RETI and RETN (untested). Cleanup tests for "terminal" instructions. Mike Pavone <pavone@retrodev.com> parents: 282 diff changeset	1881 } while (!z80_is_terminal(&inst));
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1882 process_deferred(&opts->gen.deferred, context, (native_addr_func)z80_get_native_address);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1883 if (opts->gen.deferred) {
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1884 address = opts->gen.deferred->address;
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	1885 dprintf("defferred address: %X\n", address);
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1886 if (address < 0x4000) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1887 encoded = context->mem_pointers[0] + (address & 0x1FFF);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1888 } else if (address > 0x8000 && context->mem_pointers[1]) {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1889 encoded = context->mem_pointers[1] + (address & 0x7FFF);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1890 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1891 printf("attempt to translate non-memory address: %X\n", address);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1892 exit(1);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1893 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1894 } else {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1895 encoded = NULL;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1896 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1897 }
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1898 }
4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1899
592 4ff7bbb3943b Get rest of emulator compiling again with Z80 core enabled Michael Pavone <pavone@retrodev.com> parents: 591 diff changeset	1900 void init_x86_z80_opts(z80_options * options, memmap_chunk const * chunks, uint32_t num_chunks)
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	1901 {
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1902 memset(options, 0, sizeof(*options));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1903
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1904 options->gen.address_size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1905 options->gen.address_mask = 0xFFFF;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1906 options->gen.max_address = 0x10000;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1907 options->gen.bus_cycles = 3;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1908 options->gen.mem_ptr_off = offsetof(z80_context, mem_pointers);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1909 options->gen.ram_flags_off = offsetof(z80_context, ram_code_flags);
620 9d6fed6501ba Fix handling of code writes for Z80 core. This seems to get things close to being back to where they were before the big refactor that broke the Z80 core. Some problems remain. Notably the sound driver in Sonic 2 is still quite broken. Michael Pavone <pavone@retrodev.com> parents: 601 diff changeset	1910 options->gen.ram_flags_shift = 7;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1911
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1912 options->flags = 0;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1913 options->regs[Z80_B] = BH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1914 options->regs[Z80_C] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1915 options->regs[Z80_D] = CH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1916 options->regs[Z80_E] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1917 options->regs[Z80_H] = AH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1918 options->regs[Z80_L] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1919 options->regs[Z80_IXH] = DH;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1920 options->regs[Z80_IXL] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1921 options->regs[Z80_IYH] = -1;
239 a5bea9711a46 Implement BIT and DJNZ (tested). Fix register mapping for IYL. Mike Pavone <pavone@retrodev.com> parents: 238 diff changeset	1922 options->regs[Z80_IYL] = R8;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1923 options->regs[Z80_I] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1924 options->regs[Z80_R] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1925 options->regs[Z80_A] = R10;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1926 options->regs[Z80_BC] = RBX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1927 options->regs[Z80_DE] = RCX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1928 options->regs[Z80_HL] = RAX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1929 options->regs[Z80_SP] = R9;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1930 options->regs[Z80_AF] = -1;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1931 options->regs[Z80_IX] = RDX;
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	1932 options->regs[Z80_IY] = R8;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1933
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1934 options->bank_reg = R15;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1935 options->bank_pointer = R12;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1936
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1937 options->gen.context_reg = RSI;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1938 options->gen.cycles = RBP;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1939 options->gen.limit = RDI;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1940 options->gen.scratch1 = R13;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1941 options->gen.scratch2 = R14;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1942
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1943 options->gen.native_code_map = malloc(sizeof(native_map_slot));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1944 memset(options->gen.native_code_map, 0, sizeof(native_map_slot));
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1945 options->gen.deferred = NULL;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1946 options->gen.ram_inst_sizes = malloc(sizeof(uint8_t) * 0x2000 + sizeof(uint8_t *));
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1947 options->gen.ram_inst_sizes[0] = (uint8_t *)(options->gen.ram_inst_sizes + 1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	1948 memset(options->gen.ram_inst_sizes[0], 0, sizeof(uint8_t) * 0x2000);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1949
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1950 code_info *code = &options->gen.code;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1951 init_code_info(code);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1952
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1953 options->save_context_scratch = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1954 mov_rrdisp(code, options->gen.scratch1, options->gen.context_reg, offsetof(z80_context, scratch1), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1955 mov_rrdisp(code, options->gen.scratch2, options->gen.context_reg, offsetof(z80_context, scratch2), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1956
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1957 options->gen.save_context = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1958 for (int i = 0; i <= Z80_A; i++)
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1959 {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1960 int reg;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1961 uint8_t size;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1962 if (i < Z80_I) {
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	1963 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1964 size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1965 } else {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1966 reg = i;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1967 size = SZ_B;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1968 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1969 if (options->regs[reg] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1970 mov_rrdisp(code, options->regs[reg], options->gen.context_reg, offsetof(z80_context, regs) + i, size);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1971 }
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	1972 if (size == SZ_W) {
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	1973 i++;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	1974 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1975 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1976 if (options->regs[Z80_SP] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1977 mov_rrdisp(code, options->regs[Z80_SP], options->gen.context_reg, offsetof(z80_context, sp), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1978 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1979 mov_rrdisp(code, options->gen.limit, options->gen.context_reg, offsetof(z80_context, target_cycle), SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1980 mov_rrdisp(code, options->gen.cycles, options->gen.context_reg, offsetof(z80_context, current_cycle), SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1981 mov_rrdisp(code, options->bank_reg, options->gen.context_reg, offsetof(z80_context, bank_reg), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1982 mov_rrdisp(code, options->bank_pointer, options->gen.context_reg, offsetof(z80_context, mem_pointers) + sizeof(uint8_t ) 1, SZ_PTR);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	1983 retn(code);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1984
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1985 options->load_context_scratch = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1986 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch1), options->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1987 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, scratch2), options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1988 options->gen.load_context = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1989 for (int i = 0; i <= Z80_A; i++)
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1990 {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1991 int reg;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1992 uint8_t size;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1993 if (i < Z80_I) {
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	1994 reg = i /2 + Z80_BC + (i > Z80_H ? 2 : 0);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1995 size = SZ_W;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1996 } else {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1997 reg = i;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1998 size = SZ_B;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	1999 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2000 if (options->regs[reg] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2001 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, regs) + i, options->regs[reg], size);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2002 }
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2003 if (size == SZ_W) {
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2004 i++;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2005 }
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2006 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2007 if (options->regs[Z80_SP] >= 0) {
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2008 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sp), options->regs[Z80_SP], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2009 }
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2010 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, target_cycle), options->gen.limit, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2011 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, current_cycle), options->gen.cycles, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2012 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, bank_reg), options->bank_reg, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2013 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, mem_pointers) + sizeof(uint8_t ) 1, options->bank_pointer, SZ_PTR);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2014 retn(code);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2015
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2016 options->native_addr = code->cur;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2017 call(code, options->gen.save_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2018 push_r(code, options->gen.context_reg);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2019 mov_rr(code, options->gen.context_reg, RDI, SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2020 movzx_rr(code, options->gen.scratch1, RSI, SZ_W, SZ_D);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2021 call(code, (code_ptr)z80_get_native_address_trans);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2022 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2023 pop_r(code, options->gen.context_reg);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2024 call(code, options->gen.load_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2025 retn(code);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2026
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2027 options->gen.handle_cycle_limit = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2028 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2029 code_ptr no_sync = code->cur+1;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2030 jcc(code, CC_B, no_sync);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2031 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, pc), SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2032 call(code, options->save_context_scratch);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2033 pop_r(code, RAX); //return address in read/write func
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2034 pop_r(code, RBX); //return address in translated code
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2035 sub_ir(code, 5, RAX, SZ_PTR); //adjust return address to point to the call that got us here
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2036 mov_rrdisp(code, RBX, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2037 mov_rrind(code, RAX, options->gen.context_reg, SZ_PTR);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2038 //restore callee saved registers
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2039 pop_r(code, R15);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2040 pop_r(code, R14);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2041 pop_r(code, R13);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2042 pop_r(code, R12);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2043 pop_r(code, RBP);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2044 pop_r(code, RBX);
598 faad1927d836 Fix an off-by-one error in a branch destination in the generation of handle_cycle_limit for the Z80 Michael Pavone <pavone@retrodev.com> parents: 597 diff changeset	2045 *no_sync = code->cur - (no_sync + 1);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2046 //return to caller of z80_run
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2047 retn(code);
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2048
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2049 options->gen.handle_code_write = (code_ptr)z80_handle_code_write;
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2050
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2051 options->read_8 = gen_mem_fun(&options->gen, chunks, num_chunks, READ_8, &options->read_8_noinc);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2052 options->write_8 = gen_mem_fun(&options->gen, chunks, num_chunks, WRITE_8, &options->write_8_noinc);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2053
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2054 options->gen.handle_cycle_limit_int = code->cur;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2055 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, int_cycle), options->gen.cycles, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2056 code_ptr skip_int = code->cur+1;
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2057 jcc(code, CC_B, skip_int);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2058 //set limit to the cycle limit
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2059 mov_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.limit, SZ_D);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2060 //disable interrupts
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2061 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff1), SZ_B);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2062 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, iff2), SZ_B);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2063 cycles(&options->gen, 7);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2064 //save return address (in scratch1) to Z80 stack
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2065 sub_ir(code, 2, options->regs[Z80_SP], SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2066 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2067 //we need to do check_cycles and cycles outside of the write_8 call
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2068 //so that the stack has the correct depth if we need to return to C
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2069 //for a synchronization
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2070 check_cycles(&options->gen);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2071 cycles(&options->gen, 3);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2072 //save word to write before call to write_8_noinc
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2073 push_r(code, options->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2074 call(code, options->write_8_noinc);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2075 //restore word to write
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2076 pop_r(code, options->gen.scratch1);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2077 //write high byte to SP+1
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2078 mov_rr(code, options->regs[Z80_SP], options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2079 add_ir(code, 1, options->gen.scratch2, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2080 shr_ir(code, 8, options->gen.scratch1, SZ_W);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2081 check_cycles(&options->gen);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2082 cycles(&options->gen, 3);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2083 call(code, options->write_8_noinc);
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2084 //dispose of return address as we'll be jumping somewhere else
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2085 pop_r(code, options->gen.scratch2);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2086 //TODO: Support interrupt mode 0 and 2
ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2087 mov_ir(code, 0x38, options->gen.scratch1, SZ_W);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2088 call(code, options->native_addr);
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2089 jmp_r(code, options->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2090 *skip_int = code->cur - (skip_int+1);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2091 cmp_rdispr(code, options->gen.context_reg, offsetof(z80_context, sync_cycle), options->gen.cycles, SZ_D);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2092 code_ptr skip_sync = code->cur + 1;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2093 jcc(code, CC_B, skip_sync);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2094 options->do_sync = code->cur;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2095 call(code, options->gen.save_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2096 pop_rind(code, options->gen.context_reg);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2097 //restore callee saved registers
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2098 pop_r(code, R15);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2099 pop_r(code, R14);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2100 pop_r(code, R13);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2101 pop_r(code, R12);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2102 pop_r(code, RBP);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2103 pop_r(code, RBX);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2104 //return to caller of z80_run
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2105 *skip_sync = code->cur - (skip_sync+1);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2106 retn(code);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2107
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2108 options->read_io = code->cur;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2109 check_cycles(&options->gen);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2110 cycles(&options->gen, 4);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2111 //Genesis has no IO hardware and always returns FF
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2112 //eventually this should use a second memory map array
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2113 mov_ir(code, 0xFF, options->gen.scratch1, SZ_B);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2114 retn(code);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2115
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2116 options->write_io = code->cur;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2117 check_cycles(&options->gen);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2118 cycles(&options->gen, 4);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2119 retn(code);
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2120
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2121 options->read_16 = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2122 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2123 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2124 //TODO: figure out how to handle the extra wait state for word reads to bank area
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2125 //may also need special handling to avoid too much stack depth when acces is blocked
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2126 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2127 call(code, options->read_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2128 mov_rr(code, options->gen.scratch1, options->gen.scratch2, SZ_B);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2129 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2130 add_ir(code, 1, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2131 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2132 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2133 call(code, options->read_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2134 shl_ir(code, 8, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2135 mov_rr(code, options->gen.scratch2, options->gen.scratch1, SZ_B);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2136 retn(code);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2137
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2138 options->write_16_highfirst = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2139 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2140 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2141 push_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2142 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2143 add_ir(code, 1, options->gen.scratch2, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2144 shr_ir(code, 8, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2145 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2146 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2147 pop_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2148 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2149 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2150 //TODO: Check if we can get away with TCO here
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2151 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2152 retn(code);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2153
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2154 options->write_16_lowfirst = code->cur;
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2155 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2156 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2157 push_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2158 push_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2159 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2160 pop_r(code, options->gen.scratch1);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2161 pop_r(code, options->gen.scratch2);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2162 add_ir(code, 1, options->gen.scratch2, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2163 shr_ir(code, 8, options->gen.scratch1, SZ_W);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2164 cycles(&options->gen, 3);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2165 check_cycles(&options->gen);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2166 //TODO: Check if we can get away with TCO here
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2167 call(code, options->write_8_noinc);
086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2168 retn(code);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2169
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2170 options->retrans_stub = code->cur;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2171 //pop return address
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2172 pop_r(code, options->gen.scratch2);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2173 call(code, options->gen.save_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2174 //adjust pointer before move and call instructions that got us here
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2175 sub_ir(code, 11, options->gen.scratch2, SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2176 mov_rr(code, options->gen.scratch1, RDI, SZ_D);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2177 mov_rr(code, options->gen.scratch2, RDX, SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2178 push_r(code, options->gen.context_reg);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2179 call(code, (code_ptr)z80_retranslate_inst);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2180 pop_r(code, options->gen.context_reg);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2181 mov_rr(code, RAX, options->gen.scratch1, SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2182 call(code, options->gen.load_context);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2183 jmp_r(code, options->gen.scratch1);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2184
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2185 options->run = (z80_run_fun)code->cur;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2186 //save callee save registers
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2187 push_r(code, RBX);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2188 push_r(code, RBP);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2189 push_r(code, R12);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2190 push_r(code, R13);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2191 push_r(code, R14);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2192 push_r(code, R15);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2193 mov_rr(code, RDI, options->gen.context_reg, SZ_PTR);
594 086de8692932 Add in missing generated Z80 helper functions. Fix a small bug in Z80_HALT. Fix generation of save and load context for Z80 Michael Pavone <pavone@retrodev.com> parents: 593 diff changeset	2194 call(code, options->load_context_scratch);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2195 cmp_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2196 code_ptr no_extra = code->cur+1;
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2197 jcc(code, CC_Z, no_extra);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2198 push_rdisp(code, options->gen.context_reg, offsetof(z80_context, extra_pc));
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2199 mov_irdisp(code, 0, options->gen.context_reg, offsetof(z80_context, extra_pc), SZ_PTR);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2200 *no_extra = code->cur - (no_extra + 1);
5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2201 jmp_rind(code, options->gen.context_reg);
213 4d4559b04c59 Make reset trigger debug exit to make it easier to test the same cases in blastem and musashi. Fix asl #1 overflow flag. Mike Pavone <pavone@retrodev.com> parents: diff changeset	2202 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2203
592 4ff7bbb3943b Get rest of emulator compiling again with Z80 core enabled Michael Pavone <pavone@retrodev.com> parents: 591 diff changeset	2204 void * z80_gen_bank_write(uint32_t start_address, void * voptions)
4ff7bbb3943b Get rest of emulator compiling again with Z80 core enabled Michael Pavone <pavone@retrodev.com> parents: 591 diff changeset	2205 {
4ff7bbb3943b Get rest of emulator compiling again with Z80 core enabled Michael Pavone <pavone@retrodev.com> parents: 591 diff changeset	2206 z80_options * options = voptions;
4ff7bbb3943b Get rest of emulator compiling again with Z80 core enabled Michael Pavone <pavone@retrodev.com> parents: 591 diff changeset	2207 //TODO: Handle writes to bank register
4ff7bbb3943b Get rest of emulator compiling again with Z80 core enabled Michael Pavone <pavone@retrodev.com> parents: 591 diff changeset	2208 return options;
4ff7bbb3943b Get rest of emulator compiling again with Z80 core enabled Michael Pavone <pavone@retrodev.com> parents: 591 diff changeset	2209 }
4ff7bbb3943b Get rest of emulator compiling again with Z80 core enabled Michael Pavone <pavone@retrodev.com> parents: 591 diff changeset	2210
590 ea80559c67cb WIP effort to update z80 core for code gen changes Michael Pavone <pavone@retrodev.com> parents: 506 diff changeset	2211 void init_z80_context(z80_context * context, z80_options * options)
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2212 {
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2213 memset(context, 0, sizeof(*context));
360 c42fae88d346 Fix sizeof expression passed to malloc in z80_init to avoid a minor memory error Mike Pavone <pavone@retrodev.com> parents: 335 diff changeset	2214 context->static_code_map = malloc(sizeof(*context->static_code_map));
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	2215 context->static_code_map->base = NULL;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2216 context->static_code_map->offsets = malloc(sizeof(int32_t) * 0x2000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2217 memset(context->static_code_map->offsets, 0xFF, sizeof(int32_t) * 0x2000);
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2218 context->banked_code_map = malloc(sizeof(native_map_slot) * (1 << 9));
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	2219 memset(context->banked_code_map, 0, sizeof(native_map_slot) * (1 << 9));
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2220 context->options = options;
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2221 context->run = options->run;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2222 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2223
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2224 void z80_reset(z80_context * context)
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2225 {
259 d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	2226 context->im = 0;
d9417261366f Fix a remaining z80_write reg swap bug. Properly initialize the native map slots. Reset appropriate regs when z80_reset is called. Mike Pavone <pavone@retrodev.com> parents: 257 diff changeset	2227 context->iff1 = context->iff2 = 0;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2228 context->native_pc = z80_get_native_address_trans(context, 0);
268 6c2d7e003a55 Sync Z80 on writes to busreq/reset ports. NULL out extra_pc on z80 reset Mike Pavone <pavone@retrodev.com> parents: 267 diff changeset	2229 context->extra_pc = NULL;
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2230 }
d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2231
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2232 void zinsert_breakpoint(z80_context * context, uint16_t address, uint8_t * bp_handler)
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2233 {
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2234 static uint8_t * bp_stub = NULL;
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2235 z80_options * opts = context->options;
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	2236 code_ptr native = z80_get_native_address_trans(context, address);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2237 code_info tmp_code = {native, native+16};
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2238 mov_ir(&tmp_code, address, opts->gen.scratch1, SZ_W);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2239 if (!bp_stub) {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2240 code_info *code = &opts->gen.code;
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	2241 check_code_prologue(code);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2242 bp_stub = code->cur;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2243 call(&tmp_code, bp_stub);
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	2244
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2245 //Calculate length of prologue
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2246 check_cycles_int(&opts->gen, address);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2247 int check_int_size = code->cur-bp_stub;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2248 code->cur = bp_stub;
505 b7b7a1cab44a The local clone on my laptop got messed up and some changes had not been pushed. This commit represents the status of the working copy from that clone. It unfortunately contains some changes that I did not intend to commit yet, but this seems like the best option at the moment. Michael Pavone <pavone@retrodev.com> parents: 467 diff changeset	2249
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2250 //Save context and call breakpoint handler
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2251 call(code, opts->gen.save_context);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2252 push_r(code, opts->gen.scratch1);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2253 mov_rr(code, opts->gen.context_reg, RDI, SZ_Q);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2254 mov_rr(code, opts->gen.scratch1, RSI, SZ_W);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2255 call(code, bp_handler);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2256 mov_rr(code, RAX, opts->gen.context_reg, SZ_Q);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2257 //Restore context
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2258 call(code, opts->gen.load_context);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2259 pop_r(code, opts->gen.scratch1);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2260 //do prologue stuff
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2261 cmp_rr(code, opts->gen.cycles, opts->gen.limit, SZ_D);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2262 uint8_t * jmp_off = code->cur+1;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2263 jcc(code, CC_NC, code->cur + 7);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2264 pop_r(code, opts->gen.scratch1);
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	2265 add_ir(code, check_int_size - (tmp_code.cur-native), opts->gen.scratch1, SZ_Q);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2266 push_r(code, opts->gen.scratch1);
593 5ef3fe516da9 Z80 core is sort of working again Michael Pavone <pavone@retrodev.com> parents: 592 diff changeset	2267 jmp(code, opts->gen.handle_cycle_limit_int);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2268 *jmp_off = code->cur - (jmp_off+1);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2269 //jump back to body of translated instruction
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2270 pop_r(code, opts->gen.scratch1);
601 f0061e3d2ad9 Fix a few bugs introduced in the Z80 core from the adjustments to fit with the code gen refactor Michael Pavone <pavone@retrodev.com> parents: 598 diff changeset	2271 add_ir(code, check_int_size - (tmp_code.cur-native), opts->gen.scratch1, SZ_Q);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2272 jmp_r(code, opts->gen.scratch1);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2273 } else {
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2274 call(&tmp_code, bp_stub);
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2275 }
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2276 }
235 d9bf8e61c33c Get Z80 core working for simple programs Mike Pavone <pavone@retrodev.com> parents: 213 diff changeset	2277
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2278 void zremove_breakpoint(z80_context * context, uint16_t address)
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2279 {
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2280 uint8_t * native = z80_get_native_address(context, address);
591 966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2281 z80_options * opts = context->options;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2282 code_info tmp_code = opts->gen.code;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2283 opts->gen.code.cur = native;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2284 opts->gen.code.last = native + 16;
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2285 check_cycles_int(&opts->gen, address);
966b46c68942 Get Z80 core back into compileable state Michael Pavone <pavone@retrodev.com> parents: 590 diff changeset	2286 opts->gen.code = tmp_code;
366 836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2287 }
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2288
836585d389b8 Partial implementation of Z80 debugger Mike Pavone <pavone@retrodev.com> parents: 363 diff changeset	2289

Mercurial > repos > blastem

annotate z80_to_x86.c @ 620:9d6fed6501ba